Switching modeling systems for power semiconductor devices and related methods

Abstract

Particular implementations of a product system model file generation system may include one or more hardware processors and a first interface generated using a computing device to receive from a user a selection of a product SPICE model of a product including at least one switch; receiving, using a second interface, a selection of at least a portion of a soft handover process condition from the user; receiving, using a third interface, a selection of one or more system characteristics and one or more operating characteristics from the user; receiving, using a fourth interface, a selection of one or more circuit parameters from the user, the one or more circuit parameters comprising an analog circuit, the analog circuit comprising at least two switches; generating a SPICE model output using a SPICE model simulation module; and formatting the SPICE model output into a product system model file using a formatting module.

Description

Technical Field

[0001] Aspects of this document generally relate to electronic system simulation. More specific implementations relate to systems and methods for simulating systems including semiconductor dies. Background Art

[0002] The semiconductor die is incorporated into a larger electronic system such as a motherboard or circuit board by direct attachment or via a packaging system attached to the semiconductor die. The motherboard or circuit board is designed to supply / receive certain electronic signals from the semiconductor die during operation. Summary of the invention

[0003] A specific implementation of the method for generating a product system model file may include: using a processor and a first interface generated by a computing device to select a product SPICE model for a product including at least one switch; and using a processor and a second interface generated by a computing device to select at least a portion of a soft switching process condition. The method may also include: using a third interface generated by a computing device to receive one or more system characteristics and one or more operating characteristics from a user; and using a fourth interface generated by a computing device to receive one or more circuit parameters from a user, the one or more circuit parameters including a simulated circuit, the simulated circuit including at least one switch. The method also includes: using a processor and a SPICE model simulation module to generate a SPICE model output using the product SPICE model, at least a portion of the soft switching process conditions, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters; and using a processor and a formatting module to format the SPICE model output into a product system model file.

[0004] A specific implementation of the method for generating a product system model file may include one, all, or any of the following:

[0005] The product system model file may be configured for use in performing a system-level simulation of a system including a product.

[0006] The analog circuit may also include a resonant inductor coupled to the at least one switch.

[0007] The analog circuit may also include a shunt resistor coupled to the at least one switch.

[0008] The one or more circuit parameters may also include one of gate resistance, gate inductance, gate loop inductance, source inductance, loop inductance, diode voltage, and any combination thereof.

[0009] The one or more circuit parameters may also include one of a shunt resistance, a printed circuit board leakage inductance, a decoupling capacitor series resistance, one or more parasitic effects in a switching loop, and any combination thereof.

[0010] The one or more system characteristics may include an output capacitance of an output capacitor of the at least one switch.

[0011] The one or more operating characteristics may include bus voltage.

[0012] The one or more system characteristics may include an inductance value of the resonant inductor.

[0013] The one or more operating characteristics may include a maximum transition time for switching of the at least one switch.

[0014] Generating the SPICE model output may also include using a current in the resonant inductor prior to a switching event of the at least one switch and using a rate of change of the current in the resonant inductor prior to the switching event of the at least one switch.

[0015] A specific implementation of the product system model file generation system may include: one or more hardware processors configured by machine-readable instructions to: use a first interface generated by a computing device to receive a selection of a product SPICE model for a product including at least one switch from a user; and use a second interface generated by a computing device to receive a selection of at least part of a soft switching process condition from a user. The system may also include: use a third interface generated by a computing device to receive a selection of one or more system characteristics and one or more operating characteristics from a user; and use a fourth interface generated by a computing device to receive a selection of one or more circuit parameters from a user, the one or more circuit parameters including a simulated circuit, the simulated circuit including at least two switches. The system may also include: using a SPICE model simulation module to generate a SPICE model output using a product SPICE model, at least part of a soft switching process condition, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters; and use a formatting module to format the SPICE model output into a product system model file.

[0016] The specific implementation of the product system model file generation system may include one, all or any of the following:

[0017] The product system model file may be configured for use in performing a system-level simulation of a system including a product.

[0018] The analog circuit may also include a resonant inductor coupled to the at least one switch.

[0019] The analog circuit may also include a shunt resistor coupled to the at least one switch.

[0020] The one or more circuit parameters may also include one of a shunt resistance, a printed circuit board leakage inductance, a decoupling capacitor series resistance, one or more parasitic effects in a switching loop, and any combination thereof.

[0021] The one or more system characteristics may include an output capacitance of an output capacitor of the at least one switch.

[0022] The one or more system characteristics may include an inductance value of the resonant inductor.

[0023] The one or more operating characteristics may include a maximum transition time for switching of the at least one switch and a bus voltage.

[0024] Using the SPICE model simulation module, generating the SPICE model output using the product SPICE model may also include using a current in the resonant inductor prior to a switching event of the at least one switch and using a rate of change of the current in the resonant inductor prior to a switching event of the at least one switch.

[0025] A specific implementation of a method for generating a product system model file may include using one or more processors and one or more interfaces generated by a computing device associated with a user. The method may include selecting a product SPICE model for a product including at least one switch; selecting a partial soft switching process condition; and receiving one or more system characteristics and one or more operating characteristics. The method may include: receiving one or more circuit parameters, the one or more circuit parameters including a simulated circuit, the simulated circuit including at least one switch; and using a SPICE model simulation module, using the product SPICE model, the partial soft switching process condition, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters to generate a SPICE model output. The method may include using a formatting module to format the SPICE model output into a product system model file.

[0026] The foregoing and other aspects, features and advantages will be apparent to those skilled in the art from the detailed description and accompanying drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Specific implementations will be described below in conjunction with the accompanying drawings, in which like reference numerals represent like elements, and:

[0028] Figure 1 is a schematic diagram of an RLC equivalent circuit for a circuit comprising at least two semiconductor switches;

[0029] Figure 2 is a graph of the current through the resonant inductor and shows the Figure 1 A graph showing the rate of change of the voltage VSwt at the position indicated in FIG.

[0030] Figure 3 is a schematic diagram and timing diagram of a specific implementation of a half-bridge circuit operating in a boost mode during a double pulse test hard switching operation;

[0031] Figure 4 is a schematic diagram and timing diagram of a specific implementation of a half-bridge circuit operating in buck mode during a double pulse test hard switching operation;

[0032] Figure 5 is a schematic diagram and timing diagram of a specific implementation of a half-bridge circuit operating in a boost mode during soft switching operation;

[0033] Figure 6 is a schematic diagram and timing diagram of a specific implementation of a half-bridge circuit operating in a buck mode during soft switching operation;

[0034] Figure 7 During hard switching and soft switching operations Figures 3 to 6 A diagram of the four quadrants of operation of a half-bridge circuit;

[0035] Figure 8 is a schematic diagram of an analog circuit for two semiconductor switches;

[0036] Fig. 9 is a block diagram of a specific implementation of a switching modeling system; and

[0037] Fig.10 It is a flowchart of a specific implementation of the method for generating a product system model file. DETAILED DESCRIPTION

[0038] The present disclosure, its aspects, and specific implementations are not limited to the specific components, assembly processes, or method elements disclosed herein. Many additional components, assembly processes, and / or method elements known in the art that are consistent with the intended switching modeling system and related methods will obviously be used with specific specific implementations of the present disclosure. Thus, for example, although the present invention discloses a specific specific implementation, such specific implementations and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and / or the like known in the art for such switching modeling systems and implementation components and methods that are consistent with the intended operation and method.

[0039] Various specific implementations of systems and methods for creating product system model files are disclosed in U.S. patent application serial number 18 / 058,382, filed by Xiao et al. on November 23, 2022, entitled "Automated Power Discrete and Module Model Generation for System Level Simulators," the disclosure of which is incorporated herein by reference in its entirety (the '382 application). The product system model files are then used by various system-level simulators used by circuit designers during circuit design. The product SPICE models of semiconductor products disclosed herein (such as the product SPICE models disclosed in the '382 application) are obtained by modeling using either or both of the modeling processes disclosed in the following U.S. patents: U.S. Patent No. 11,481,532, “Systems and Methods for Designing a Discrete Device Product” issued on October 25, 2022 to Victory et al. (the '522 patent) and U.S. Patent No. 11,481,533, “Systems and Methods for Designing a Module Semiconductor Product” issued on October 25, 2022 to Victory et al. (the '533 patent), the disclosure of each of which is incorporated herein by reference in its entirety. Therefore, the term "product SPICE model" as used herein means the same as the corresponding "product SPICE model" as used in each of the '532 patent and the '533 patent. These product SPICE models are the result of significant simulations that take into account the electrical / thermal characteristics of one or more semiconductor dies and the electrical / thermal characteristics of the corresponding packages to which the one or more semiconductor dies are coupled and are used to provide electrical / thermal connections to a circuit or motherboard to which the semiconductor product is coupled. Various system and method implementations disclosed herein utilize product SPICE models (such as the product SPICE models disclosed in the '532 patent and the '533 patent) to create product system model files that can be used by various system-level simulators used by circuit designers during circuit design. In various implementations, these product system model files can be in the format of structured text files, plain text files, or delimited text files.In some implementations, the product system model file may be a structured text file in xml format that is structured for use in a piecewise linear electrical circuit simulation (PLECS) system-level simulator (PLECS model) sold by Plexim of Zurich, Switzerland. In other implementations, the product system file may be a structured text file, a plain text file, or a delimited text file that can be utilized in another system-level simulator type, such as a system-level simulator sold under the trade name PSIM by Powersim, Inc. of Rockville, MD, or any other system-level simulator.

[0040] In the case of semiconductor packages and modules that include switching semiconductor devices (switches), various system simulators (such as those disclosed herein and in the '382 application) utilize hard-switched double-pulse testing to model energy losses and behavior. In hard switching, the energy stored in the output capacitor of the switch is primarily lost in the switch during the on period of the test, so that during the off portion of the test, the output capacitor must be refilled to allow the switch transition to occur. However, under certain operating conditions, the semiconductor switch can use soft switching / operate in soft switching operation. In soft switching, some or all of the energy stored in the output capacitor of the switch is recycled back to the output capacitor with the help of a resonant tank created by an inductor coupled to the switch. The ability to recycle some or all of the energy in the output capacitor of the switch helps to reduce switching power losses and can increase the overall power efficiency of the switching semiconductor package / system.

[0041] Double pulse testing is a good help in developing product system model files for semiconductor packages that include semiconductor switches that operate in hard switching mode / operation. However, double pulse testing cannot help accurately predict / measure the lower losses experienced by semiconductor switches that use soft switching / operate in soft switching mode. This is partly because the soft switching mode operates continuously from some soft switching to all soft switching. Moreover, double pulse testing ignores the impact of the circuit that creates the resonant loop. This may lead to large errors in the simulation performed by the system-level simulator using the resulting product system model file during circuit design. The ability to accurately develop a product system model file that understands the operation of a given semiconductor package that includes a switch may be particularly important for a circuit design that operates in at least part of a soft switching mode or can operate in at least part of a soft switching mode. Non-limiting examples of such applications and circuit designs in which at least part of soft switching may occur include a resonant half-bridge converter, a DC-DC LLC design, a CLLC resonant design, a dual active bridge design, and a phase-shifted full-bridge design.

[0042] Soft switching or partial zero volt transition (ZVT) or partial zero volt switching (ZVS) occurs when the resonant inductor and output capacitor of the semiconductor switch resonate to swing the voltage from one rail to the other during the delay between the turn-off event and the turn-on event. During the delay period of the transition, both switches (in the case of a half-bridge device) are turned off during the transition. At the end of the transition, electrical conduction begins at the body diode of the switch, and Eon is negative. Moreover, the voltage reaches the other rail at the turn-on time or during the delayed period, resulting in a partial transition with switching losses, where Eon is positive but less than Eon in a hard switching system. In order to initiate a soft switching transition, the resonant inductor current in the inductor electrically coupled to the semiconductor switch moves in the opposite direction to the energy transfer or the turn-off body diode forward current. The total amount of energy in the resonant tank formed by the inductor is important in determining whether a soft switching transition can occur. By way of non-limiting example, this total energy in the resonant tank is proportional to the current in the inductor (resonant inductor), the rate of change of the current in the resonant inductor, the voltage storage in the output capacitor of the semiconductor switch, the bus voltage, and the load reflected voltage of the isolation transformer. By way of non-limiting example, the energy in the resonant tank may also depend on the structure of the inductor-capacitor-resistor network in the particular semiconductor switch / semiconductor package and the delay between the timing when each of the two switches changes state. For example, the amount of delay between the high-side switch turning off and the low-side switch turning on may affect whether the two switches are partially or completely operated in a soft switching mode.

[0043] refer to Figure 1 , illustrates an equivalent circuit 2 for a semiconductor package including a semiconductor switch for simulation. Here, the voltage monitored during the switching transition is the VSwt point 4 adjacent to the capacitor Cr 6. Figure 2 A graph of the current through the resonant inductor Lr 8 adjacent to the shunt resistor Rs 10 and the rate of change of the voltage Vswt for a set of delay values ​​between when the switch is turned off and when the other switches are turned on is illustrated (x-axis of the voltage graph). The shaded area 12 in the voltage graph shows the maximum likelihood region where partial soft switching of the semiconductor package is observed at lower energy in the resonant tank formed by the resonant inductor Lr 8. The shaded area 12 corresponds to a delay value of about 250 to 300 nanoseconds (ns). Figure 2 The simulation is illustrated in which the bus voltage VBus is set to 400V, I0 is -1A, the shunt resistor (Rs) is 1 megohm, the inductance of Lr is 10 microhenry, and the capacitance of Cr is 1 nanofarad. When the di / dt variable is varied by stepping dt from 10ns, 20ns, 23ns, 25ns, 27ns, 50ns, and 100ns and Figure 2The simulation was performed while plotting the resulting current and voltage values ​​in . These graphs show the influence of the rate of change of the current in the resonant inductor Lr 8. Figure 1 and Figure 2 It is illustrated that for a given semiconductor switching system, the system may be operated at least partially in a soft switching mode under certain operating conditions.

[0044] exist Figures 3 to 6 The behavior of a half-bridge circuit with two semiconductor switches during hard switching operation and soft switching operation during a double pulse test is illustrated in FIG. Figure 3 , a half-bridge circuit 14 having a low-side switch 16 and a high-side switch 18 is shown coupled with an inductor 22. Here, during the double pulse test, the driving of the switches 16, 18 occurs from the low side as in boost mode. When the high-side switch 18 is turned off, current continues to flow in the body diode represented by diode 24, thereby allowing the output capacitor of the high-side switch 18 represented by capacitor 26 to discharge through the inductor 22 into the low-side switch, resulting in a loss of charge. In a similar manner, reference is made to Figure 4 , when the half-bridge circuit 14 is driven by the high-side switch 18 as in buck mode, when the low-side switch 16 is off, current continues to flow in the body diode of the low-side switch (represented by diode 28). This similarly allows the charge in the output capacitor of the low-side switch 16, represented by capacitor 30, to flow and be lost to the high-side switch 18. Therefore, the double pulse test of the half-bridge circuit relies on / assumes that the charge of the output capacitors of the low-side switch 16 and the high-side switch 18 is completely lost because the inductor 22 does not store any energy in the capacitor.

[0045] However, there are different operating conditions in the soft switching operating condition, where reference Figure 5 , illustrates a half-bridge circuit 14 that is turned off on the low side during boost mode. Here, as illustrated, due to the energy stored in inductor 22, current cannot flow through the body diode represented by diode 28, which prevents the discharge of the charge in the output capacitor of the low-side switch 16 represented by capacitor 30. This means that during buck mode, when the low-side switch is turned on, at least some of the initial charge of the output capacitor of the low-side switch 16 still exists in the output capacitor. Figure 6 Similar behavior is observed in the illustrated soft switching operation during buck mode operation, where when the high side switch 18 is turned off, the energy stored in the inductor 22 again prevents current flow in the body diode represented by diode 24. This prevents at least some of the charge in the output capacitor of the high side switch 28 represented by capacitor 26 from discharging, thereby keeping the charge present for recycling when the high side switch 18 is turned on again. Because the energy is stored in the inductor 22 instantaneously with the appropriate energy and delay timing, this soft switching behavior exists with the appropriate energy value and current change rate.

[0046] In soft switching, the energy depends on the current and also on the rate of change of current (di / dt) to complete the soft transition. In the case of double pulse testing, di / dt always increases, but in soft switching, di / dt can be reduced, which reduces the amount of resonant energy available for transition. In soft switching, the goal is to keep the current in the opposite direction of the forward direction of the body diode of the off switch (high side or low side) for all transitions. This allows the recycling of the charge in the output capacitor of the switch. Because reaching and measuring the soft switching behavior of a given circuit involves changing the rate of change of current (di / dt), a more complex test setup is required than for the double pulse (buck or boost) test setup. This is because the double pulse test is actually a specific switching case of di / dt=0. Achieving partial ZVT depends on the resonant energy (energy in the resonant tank), which involves the current, di / dt and voltage bus values ​​and the maximum delay between the high-side switching event and the low-side switching event.

[0047] Available Figure 7 The preceding process is summarized in the diagram, which shows Figures 3 to 6 4 quadrants of operation of each of the switches in the half-bridge circuit 14. Hard switching operation is illustrated in the upper left quadrant 32 and lower right quadrant 34 during turn-on operation and turn-off operation, respectively. In the upper left quadrant 32, current from the output capacitor is illustrated as flowing from the drain to the source, and in the lower right quadrant 34, current is illustrated as flowing from the source to the drain of the output capacitor. Soft switching operation is illustrated in the upper right quadrant 36 and lower left quadrant 38. In the upper right quadrant 36, current would flow from the drain to the source, but would be blocked by the body diode. In the lower left quadrant 38, current would flow from the source to the drain, but would again be blocked from doing so by the body diode. Figure 7 It illustrates how the use of hard switching only and double pulse testing enables the tester to characterize only half of the possible operating states of a given circuit including semiconductor switches.

[0048] Although the foregoing principles have been discussed in the context of a half-bridge circuit involving two switches, the principles disclosed herein may also be applied to the process of testing a semiconductor package in which only one semiconductor switch is included. A person of ordinary skill in the art will understand how to achieve this by using an inductor coupled to a single switch to achieve a soft switching condition under appropriate operating conditions.

[0049] refer to Figure 8, illustrates a specific implementation of a test setup 40 for a half-bridge circuit, which shows a low-side switch 42 and a high-side switch 44 coupled to an inductor 44. During operation of the test simulation, components in the first measurement module 46 and the second measurement module 48 are used to measure those circuit components required to calculate Eon and Eoff as various operating and system parameters of the half-bridge circuit are varied, including (by way of non-limiting example) bus voltage, current in the resonant inductor 44 before a switching event; di / dt in the resonant inductor 44 before a switching event; output capacitor capacitance of each switch 42, 44; transition / delay time between switching events, and any parasitic effects in the switching loop, including (by way of non-limiting example) shunt resistance, printed circuit board leakage inductance, decoupling capacitor series resistance, one or more parasitic effects in the switching loop, and any combination thereof; any combination thereof, or any other operating or system parameter of the circuit. The measurements during the simulation using the test setup 40 are then used in a product system model file generation system, such as the product system model file generation system disclosed herein, to generate a product system model file for use in a system level simulator, such as the system level simulator disclosed herein. A specific implementation of the product system model file may include various model parameters, such as (by way of non-limiting example) bus voltage, current in the resonant inductor prior to a switching event, rate of change of current (di / dt) in the resonant inductor prior to a switching event, resonant inductor value, or other parameters that enable the product system model file to allow soft switching mode modeling by the system level simulator.

[0050] refer to Fig. 9 , a block diagram of a specific implementation of a system 100 for generating a product system model file for use in a system-level simulation is illustrated. In some specific implementations, the system 100 may include one or more computing platforms 102. The computing platform 102 may be configured to communicate with one or more remote platforms 104 according to a client / server architecture, a peer-to-peer architecture, and / or other architectures. The remote platform 104 may be configured to communicate with other remote platforms via the computing platform 102 and / or according to a client / server architecture, a peer-to-peer architecture, and / or other architectures. A user may access the system 100 via the remote platform 104. Examples of remote platforms 104 available to users include (as non-inhabited examples) a desktop computer, a server computer, a laptop computer, a smart phone, a tablet computer, or any other portable electronic device.

[0051] The computing platform 102 may be configured by machine readable instructions 106. The machine readable instructions 106 may include one or more instruction modules. The instruction modules may include computer program modules. The instruction modules may include one or more of an interface generation module 108, a SPICE model simulation module 110, and a formatting module 112. The interface generation module 108 facilitates the generation of the '382 application. Figures 1 to 4 The various computing interfaces illustrated. SPICE model simulation module 110 performs a series of simulations using a product SPICE model selected by a user, the product SPICE model being stored in a database 114 that includes a set of product SPICE models, such as those disclosed in the '382 application and the '532 and '533 patents. The results of those simulations, including processing of soft switching operating conditions, such as those disclosed herein, are then processed by formatting module 112 to form a product system model file. In various specific implementations, the product system model file may be stored in database 114 for retrieval by a user or others who wish to access the file.

[0052] In some implementations, computing platform 102, remote platform 104, and / or external resource 118 may be operatively linked via one or more electronic communication links. For example, such electronic communication links may be established at least in part via a network (such as the Internet) and / or other networks. It should be understood that this is not intended to be limiting, and the scope of the present disclosure includes implementations in which computing platform 102, remote platform 104, and / or external resource 130 may be operatively linked via some other communication medium.

[0053] A given remote platform 104 may include one or more processors configured to execute computer program modules. The computer program modules may be configured to enable an expert or user associated with a given remote platform 104 to interface with the system 100 and / or external resources 118 and / or to provide other functionality attributed herein to the remote platform 104. As non-limiting examples, a given remote platform 104 and / or a given computing platform 102 may include one or more of a server, a desktop computer, a laptop computer, a handheld computer, a tablet computing platform, a netbook, a smart phone, a game console, and / or other computing platforms.

[0054] External resources 118 may include information sources external to system 100, external entities participating with system 100, and / or other resources. In some implementations, some or all of the functionality attributed herein to external resources 130 may be provided by resources included in system 100. Fig. 9As illustrated, computing platform 102 may include electronic storage / database 114, one or more processors 116, and / or other components. Computing platform 102 may include communication links or ports to enable information to be exchanged with a network and / or other computing platforms. Fig. 9 The illustration of computing platform 102 in is not intended to be limiting. Computing platform 102 may include multiple hardware components, software components, and / or firmware components that operate together to provide the functionality attributed herein to computing platform 102. For example, computing platform 102 may be implemented by a cloud of computing platforms that are computing platforms operating together with computing platform 102.

[0055] Processor 116 may be configured to provide information processing capabilities in computing platform 102. Thus, processor 116 may include one or more of a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and / or other mechanisms for electronically processing information. Fig. 9 108, 110, and / or 112, and / or other modules. Processor 116 may be configured to execute modules 108, 110, and / or 112, and / or other modules by: software; hardware; firmware; some combination of software, hardware, and / or firmware; and / or other mechanisms for configuring processing capabilities on processor 116. As used herein, the term "module" may refer to any component or set of components that perform functionality attributed to the module. This may include one or more physical processors, processor-readable instructions, circuit systems, hardware, storage media, or any other components during the execution of processor-readable instructions.

[0056] It should be understood that although modules 108, 110 and / or 112 are Fig. 9108, 110, and / or 112 may be implemented remotely from the other modules. As any of the modules 108, 110, and / or 112 may provide more or less functionality than described, the description of the functionality provided by the different modules 108, 110, and / or 112 described below is for illustrative purposes and is not intended to be limiting. For example, one or more of the modules 108, 110, and / or 112 may be eliminated, and some or all of its functionality may be provided by other modules in the modules 108, 110, and / or 112. As another example, the processor 116 may be configured to execute one or more additional modules that may perform some or all of the functionality attributed to one of the modules 108, 110, and / or 112 below.

[0057] refer to Fig.10 , illustrates a flow chart of a specific implementation of a method for generating a product system file 50. Various method implementations may be performed using any of the system implementations disclosed herein. As illustrated, the method includes using a first interface generated by a computing device to receive from a user a selection of a product SPICE model for a product including at least one switch (a semiconductor switch, step 52). In various implementations, the product may be any product disclosed in this document or the '382 application. In various implementations, the first interface may be a user interface having a design (such as the '382 application) of the product SPICE model. Figure 1 The method also includes using a second interface generated by the computing device to receive from a user a selection of at least some soft switching process conditions / modes, which conditions / modes may be any of the conditions / modes disclosed herein (step 54). In the '382 application, various selections of process conditions are illustrated, and in various method implementations, any of the process conditions disclosed herein may also be selected. In some method implementations, the process conditions themselves may actually include at least some of the soft switching process conditions / modes within a range of process parameters that are varied / tested for a particular selected process condition. In other implementations, the selection of soft switching may be explicit. The second interface may have a design (such as the '382 application's Figure 2 Design shown).

[0058] The method also includes receiving one or more system characteristics and one or more operating characteristics from a user using a third interface generated by the computing device (step 56). In various implementations, the third interface may have a design (such as the '382 application Figure 3illustrative design). In various system and method implementations, the one or more system characteristics and the one or more operating characteristics can be any of the characteristics disclosed in the '382 application. In various implementations, the one or more system characteristics and the one or more operating characteristics include any of the system characteristics and operating characteristics identified herein that affect soft switching (delay, bus voltage, etc.). The method also includes receiving one or more circuit parameters from a user using a fourth interface generated by the computing device, wherein the one or more circuit parameters include a simulated circuit that includes at least one switch (step 58). In some implementations, the simulated circuit can be a circuit (e.g., Figure 8 Various analog circuit implementations include a schematic design of the internal electrical connections of a semiconductor package including a switch component for identifying to a user a specific circuit parameter of a component of the circuit to be changed / tested. In various implementations, the fourth interface may be an interface design (such as the '382 application Figure 4 Specific circuit parameters of the circuit including at least one switch include any of those identified component values ​​(inductance, capacitance, etc.) that affect the soft switching disclosed herein.

[0059] The method also includes using a SPICE simulation module to generate a SPICE model output using the product SPICE model, at least a portion of the soft switching process conditions, one or more system characteristics, one or more operating characteristics, and one or more circuit parameters (step 60). The method also includes using a formatting module to format the SPICE model output into a product system model file, which can be formatted in any format disclosed in this document or the '382 application (step 62). Here, the method takes this information and uses the product SPICE model (which can be any model disclosed in this document or the '382 application) to model at least a portion of the soft switching operation of the circuit being simulated, and then generates a corresponding product system model file. The resulting product system model file can then be used with a system-level simulator to generate a system simulation that fully understands the impact of soft switching on performance characteristics (such as energy consumption, switching timing, or any other desired system characteristics). Because the soft switching behavior is now understood, the system simulation can be more accurate than if only double pulse and / or hard switching analysis were used in the same circuit design.

[0060] In various method and system implementations, the analog circuit may include a resonant inductor coupled to at least one switch, which may be an inductor type disclosed herein. The method may also include a shunt resistor coupled to at least one switch. In various method implementations, one or more circuit characteristics may also include (by way of non-limiting example) gate resistance, gate loop resistance, source inductance, loop inductance, diode voltage, any combination thereof, or any other circuit or device parameter. The method may also include where one or more circuit characteristics include (by way of non-limiting example) shunt resistance, printed circuit board leakage inductance, decoupling capacitor series resistance, one or more parasitic effects in the switching loop, any combination thereof, or any other circuit or device parameter that affects the soft switching behavior of the product. The method may also include where one or more system characteristics include an output capacitance of an output capacitor of at least one switch. In various method implementations, one or more operating characteristics may include an inductance value of the resonant inductor. In various method implementations, one or more operating characteristics may include a maximum transition time for switching of at least one switch (or a delay between switching of two or more switches). The method may further include using a current in the resonant inductor prior to a switching event of the at least one switch and / or using a rate of change of the current in the resonant inductor prior to a switching event of the at least one switch when generating the SPICE model output.

[0061] Where the above description mentions specific specific implementations of product system model file generation systems and implementation components, sub-components, methods and sub-methods, it should be readily apparent that various modifications may be made without departing from the essence thereof, and that these specific implementations, implementation components, sub-components, methods and sub-methods may be applied to other product system model file generation systems and related methods.

Claims

1. A method for generating a product system model file, the method comprising: selecting, using a processor and a first interface generated by a computing device, a product SPICE model for a product including at least one switch; selecting, using a processor and a second interface generated by the computing device, at least a portion of soft handoff process conditions; receiving, using a third interface generated by the computing device, one or more system characteristics and one or more operational characteristics from a user; receiving, from the user using a fourth interface generated by the computing device, one or more circuit parameters, the one or more circuit parameters comprising a simulated circuit, the simulated circuit comprising at least one switch; generating a SPICE model output using the processor and the SPICE model simulation module using the product SPICE model, the at least a portion of the soft switching process conditions, the one or more system characteristics, the one or more operating characteristics, and the one or more circuit parameters; as well as The SPICE model output is formatted into a product system model file using the processor and formatting module. 2 . The method of claim 1 , wherein the product system model file is configured to be used to perform a system-level simulation of a system including the product. 3 . The method of claim 1 , wherein the analog circuit further comprises a resonant inductor coupled to the at least one switch. 4 . The method of claim 1 , wherein the analog circuit further comprises a shunt resistor coupled to the at least one switch.

5. The method of claim 1, wherein the one or more circuit parameters further comprise one of a shunt resistance, a printed circuit board leakage inductance, a decoupling capacitor series resistance, one or more parasitic effects in a switching loop, and any combination thereof. 6 . The method of claim 1 , wherein the one or more system characteristics include an output capacitance of an output capacitor of the at least one switch. The method of claim 1 , wherein the one or more operating characteristics include a bus voltage.

8. The method of claim 3, wherein the one or more system characteristics include an inductance value of the resonant inductor.

9. The method of claim 1, wherein the one or more operating characteristics include a maximum transition time for switching of the at least one switch.

10. The method of claim 3, wherein generating the SPICE model output further comprises: A current in the resonant inductor is used prior to a switching event of the at least one switch, and a rate of change of the current in the resonant inductor is used prior to the switching event of the at least one switch.

11. A method for generating a product system model file, the method comprising: Using one or more processors and one or more interfaces generated by a computing device associated with a user: selecting a product SPICE model for a product including at least one switch; Selecting some soft switching process conditions; receiving one or more system characteristics and one or more operational characteristics; receiving one or more circuit parameters, the one or more circuit parameters comprising an analog circuit, the analog circuit comprising at least one switch; Using a SPICE model simulation module, generating a SPICE model output using the product SPICE model, the portion of the soft switching process conditions, the one or more system characteristics, the one or more operating characteristics, and the one or more circuit parameters; as well as The SPICE model output is formatted into a product system model file using a formatting module.

12. A product system model file generation system, the product system model file generation system comprising: One or more hardware processors configured by machine-readable instructions to: receiving, using a first interface generated by a computing device, a selection from a user of a product SPICE model for a product including at least one switch; receiving, using a second interface generated by the computing device, a selection of at least a portion of the soft handoff process conditions from a user; receiving, using a third interface generated by the computing device, a selection of one or more system characteristics and one or more operating characteristics from a user; receiving, from the user, a selection of one or more circuit parameters using a fourth interface generated by the computing device, the one or more circuit parameters comprising an analog circuit, the analog circuit comprising at least two switches; generating a SPICE model output using the product SPICE model, the at least a portion of the soft switching process conditions, the one or more system characteristics, the one or more operating characteristics, and the one or more circuit parameters using a SPICE model simulation module; and A formatting module is used to format the SPICE model output into a product system model file.

13. The system of claim 12, wherein the product system model file is configured for use in performing a system-level simulation of a system including the product.

14. The system of claim 12, wherein the analog circuit further comprises a resonant inductor coupled to the at least one switch.

15. The system of claim 12, wherein the analog circuit further comprises a shunt resistor coupled to the at least one switch.

16. The system of claim 12, wherein the one or more circuit parameters further comprise one of a shunt resistance, a printed circuit board leakage inductance, a decoupling capacitor series resistance, one or more parasitic effects in a switching loop, and any combination thereof.

17. The system of claim 12, wherein the one or more system characteristics include an output capacitance of an output capacitor of the at least one switch.

18. The system of claim 14, wherein the one or more system characteristics include an inductance value of the resonant inductor.

19. The system of claim 12, wherein the one or more operating characteristics include a maximum transition time of switching of the at least one switch and a bus voltage.

20. The system of claim 14, wherein using the SPICE model simulation module to generate a SPICE model output using the product SPICE model further comprises: A current in the resonant inductor is used prior to a switching event of the at least one switch, and a rate of change of the current in the resonant inductor is used prior to the switching event of the at least one switch.

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