Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The driving circuit comprises a driving control signal generation circuit and a multi-path output circuit; the multi-path output circuit comprises N stages of output sub-circuits; n is an integer greater than 1; the nth output sub-circuit is electrically connected with a driving control signal output end, a control voltage line, an nth control node, an nth output clock signal line and an nth driving signal output end, the nth output sub-circuit controls the potential of the nth control node according to a driving control signal under the control of the control voltage, and the nth output sub-circuit controls the nth control node according to the driving control signal under the control of the potential of the nth control node. Controlling an nth output clock signal line to provide an nth output clock signal to an nth driving signal output end; n is a positive integer smaller than or equal to N. The purpose that one driving circuit drives multiple rows of grid lines can be achieved, the number of transistors adopted by the driving circuit is effectively reduced, and a narrow frame can be achieved.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Related TDDI (Touch and Display Driver Integration) products have a large number of S-ICs (source drivers), and the price of S-ICs is high, resulting in a high cost for current TDDI products. To address this issue, a three-gate pixel structure design for TDDI display products can be adopted. In this pixel structure, the pixel electrodes are horizontally arranged, the number of gate lines is three times that of normal display products, and the number of data lines is one-third of that of normal display products. This ensures that the number of data lines used is greatly reduced while maintaining the resolution of the display product. At the same time, due to the increase in the number of gate lines, the use of a GOA (Gate On Array, a gate drive circuit provided on an array substrate) architecture that drives a row of pixels will increase the left and right borders of the display product.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising a driving control signal generating circuit and a multi-channel output circuit; the multi-channel output circuit comprises N-stage output sub-circuits; N is an integer greater than 1;

[0005] The drive control signal generating circuit is used to generate a drive control signal, and the drive control signal is output through the drive control signal output terminal;

[0006] The nth output sub-circuit is electrically connected to the drive control signal output terminal, the control voltage line, the nth control node, the nth output clock signal line and the nth drive signal output terminal, respectively. The nth output sub-circuit is used to control the potential of the nth control node according to the drive control signal under the control of the control voltage provided by the control voltage line, and to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output terminal under the control of the potential of the nth control node; n is a positive integer less than or equal to N.

[0007] Optionally, the nth output subcircuit includes an nth control unit and an nth output unit;

[0008] The nth control unit is electrically connected to the drive control signal output terminal, the control voltage line and the nth control node respectively, and is used to control the potential of the nth control node according to the drive control signal under the control of the control voltage;

[0009] The nth output unit is electrically connected to the nth control node, the nth output clock signal line and the nth drive signal output end, respectively, and is used to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output end under the control of the potential of the nth control node.

[0010] Optionally, the nth control unit includes an nth first control transistor; a gate of the nth first control transistor is electrically connected to the control voltage line, a first electrode of the nth first control transistor is electrically connected to the drive control signal output terminal, and a second electrode of the nth first control transistor is electrically connected to the nth control node; or,

[0011] The control voltage line includes a first control voltage line and a second control voltage line, and the nth control unit includes an nth first control transistor and an nth second control transistor; the gate of the nth first control transistor is electrically connected to the first control voltage line, the first electrode of the nth first control transistor is electrically connected to the drive control signal output end, and the second electrode of the nth first control transistor is electrically connected to the nth control node; the gate of the nth second control transistor is electrically connected to the second control voltage line, the first electrode of the nth second control transistor is electrically connected to the drive control signal output end, and the second electrode of the nth second control transistor is electrically connected to the nth control node.

[0012] Optionally, the nth output unit includes an nth output transistor;

[0013] The gate of the nth output transistor is electrically connected to the nth control node, the first electrode of the nth output transistor is electrically connected to the nth output clock signal line, and the second electrode of the nth output transistor is electrically connected to the nth drive signal output terminal.

[0014] Optionally, the nth output subcircuit further includes an nth shutdown reset unit;

[0015] The nth shutdown reset unit is electrically connected to the first voltage line and the nth drive signal output end respectively, and is used to control the connection or disconnection between the nth drive signal output end and the first voltage line under the control of the first voltage signal provided by the first voltage line.

[0016] Optionally, the nth shutdown reset unit includes an nth shutdown reset transistor;

[0017] The gate electrode of the nth shutdown reset transistor and the second electrode of the nth shutdown reset transistor are both electrically connected to the first voltage line, and the first electrode of the nth shutdown reset transistor is electrically connected to the nth driving signal output terminal.

[0018] Optionally, the nth output sub-circuit further includes an nth output capacitor;

[0019] A first end of the nth output capacitor is electrically connected to the nth control node, and a second end of the nth output capacitor is electrically connected to the nth driving signal output end.

[0020] Optionally, the nth output sub-circuit further includes an nth output pull-down unit;

[0021] The nth output pull-down unit is electrically connected to the pull-down node, the nth drive signal output terminal and the first voltage line respectively, and is used to control the connection or disconnection between the nth drive signal output terminal and the first voltage line under the control of the potential of the pull-down node.

[0022] Optionally, the nth output pull-down unit includes an nth first output pull-down transistor; a gate of the nth first output pull-down transistor is electrically connected to the pull-down node, a first electrode of the nth first output pull-down transistor is electrically connected to the nth drive signal output terminal, and a second electrode of the nth first output pull-down transistor is electrically connected to the first voltage line; or,

[0023] The pull-down node includes a first pull-down node and a second pull-down node; the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor; the gate of the nth first output pull-down transistor is electrically connected to the first pull-down node, the first electrode of the nth first output pull-down transistor is electrically connected to the nth drive signal output end, and the second electrode of the nth first output pull-down transistor is electrically connected to the first voltage line; the gate of the nth second output pull-down transistor is electrically connected to the second pull-down node, the first electrode of the nth second output pull-down transistor is electrically connected to the nth drive signal output end, and the second electrode of the nth second output pull-down transistor is electrically connected to the first voltage line.

[0024] Optionally, the pull-down node includes a first pull-down node and a second pull-down node; the drive control signal generating circuit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit and a drive control output circuit;

[0025] The pull-up node control circuit is used to control the potential of the pull-up node;

[0026] The first pull-down node control circuit is used to control the potential of the first pull-down node under the control of the potential of the pull-up node;

[0027] The second pull-down node control circuit is used to control the potential of the second pull-down node under the control of the potential of the pull-up node;

[0028] The drive control output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the drive control signal output end, the drive control clock signal line and the first voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the drive control signal output end under the control of the potential of the pull-up node, control the drive control signal output end to be connected to the first voltage line under the control of the potential of the first pull-down node, and control the drive control signal output end to be connected to the first voltage line under the control of the potential of the second pull-down node.

[0029] Optionally, the drive control signal generating circuit further includes a carry output circuit;

[0030] The carry output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the carry output terminal, the drive control clock signal line and the second voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the carry output terminal under the control of the potential of the pull-up node, control the carry output terminal to be connected to the second voltage line under the control of the potential of the first pull-down node, and control the carry output terminal to be connected to the second voltage line under the control of the potential of the second pull-down node.

[0031] Optionally, the pull-up node control circuit is electrically connected to the input terminal, the frame reset line, the first pull-down node, the second pull-down node, the first reset terminal, the pull-up node, and the second voltage line, respectively, and is configured to control the potential of the pull-up node under the control of an input signal provided by the input terminal, and control the connection between the pull-up node and the second voltage line under the control of a frame reset signal provided by the frame reset line, control the connection between the pull-up node and the second voltage line under the control of the potential of the first pull-down node, control the connection between the pull-up node and the second voltage line under the control of the potential of the second pull-down node, and control the connection between the pull-up node and the second voltage line under the control of a first reset signal provided by the first reset terminal;

[0032] The first pull-down node control circuit is electrically connected to a first control voltage line, a first pull-down node, a pull-up node, and a second voltage line, respectively, and is configured to control the potential of the first pull-down node under the control of a first control voltage provided by the first control voltage line and the potential of the pull-up node;

[0033] The second pull-down node control circuit is electrically connected to the second control voltage line, the second pull-down node, the pull-up node, and the second voltage line, respectively, and is configured to control the potential of the second pull-down node under the control of a second control voltage provided by the second control voltage line and the potential of the pull-up node;

[0034] The drive control output circuit is also electrically connected to a second reset terminal, and is used to control the connection between the drive control signal output terminal and the first voltage line under the control of a second reset signal provided by the second reset terminal.

[0035] Optionally, the pull-up node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor;

[0036] The gate of the first transistor and the first electrode of the first transistor are electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the pull-up node;

[0037] The gate of the second transistor is electrically connected to the first reset terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the second voltage line;

[0038] The gate of the third transistor is electrically connected to the frame reset line, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the second voltage line;

[0039] The gate of the fourth transistor is electrically connected to the first pull-down node, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the second voltage line;

[0040] The gate of the fifth transistor is electrically connected to the second pull-down node, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the second voltage line;

[0041] The first pull-down node control circuit includes a sixth transistor and a seventh transistor;

[0042] The gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the first control voltage line, and the second electrode of the sixth transistor is electrically connected to the first pull-down node;

[0043] The gate of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the second voltage line;

[0044] The second pull-down node control circuit includes an eighth transistor and a ninth transistor;

[0045] The gate of the eighth transistor and the first electrode of the eighth transistor are electrically connected to the second control voltage line, and the second electrode of the eighth transistor is electrically connected to the second pull-down node;

[0046] A gate of the ninth transistor is electrically connected to the pull-up node, a first electrode of the ninth transistor is electrically connected to the second pull-down node, and a second electrode of the ninth transistor is electrically connected to the second voltage line.

[0047] Optionally, the first pull-down node control circuit further includes a tenth transistor, and the second pull-down node control circuit further includes an eleventh transistor;

[0048] The gate of the tenth transistor is electrically connected to the input terminal, the first electrode of the tenth transistor is electrically connected to the first pull-down node, and the second electrode of the tenth transistor is electrically connected to the second voltage line;

[0049] The gate of the eleventh transistor is electrically connected to the input terminal, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line;

[0050] The carry output circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor;

[0051] The gate of the twelfth transistor is electrically connected to the pull-up node, the first electrode of the twelfth transistor is electrically connected to the drive control clock signal line, and the second electrode of the twelfth transistor is electrically connected to the carry output terminal;

[0052] The gate of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry output terminal, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line;

[0053] The gate of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the carry output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage line;

[0054] The drive control output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a first capacitor;

[0055] The gate of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the drive control clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the drive control signal output terminal;

[0056] The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the first voltage line;

[0057] The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the first voltage line;

[0058] The gate of the eighteenth transistor is electrically connected to the second reset terminal, the first electrode of the eighteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first voltage line;

[0059] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the drive control signal output terminal.

[0060] In a second aspect, an embodiment of the present disclosure provides a display substrate, comprising a base substrate and a plurality of stages of the above-mentioned driving circuits disposed on the base substrate.

[0061] Optionally, the display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit;

[0062] The multi-channel output circuit and the drive control signal generating circuit are arranged in the peripheral area;

[0063] The multi-channel output circuit is arranged on a side of the driving control signal generating circuit close to the display area.

[0064] Optionally, the multi-channel output circuit includes N output sub-circuits and N output clock signal lines; N is an integer greater than 1;

[0065] The output clock signal line is arranged on a side of the output sub-circuit close to the display area, and the output clock signal line extends along a first direction.

[0066] Optionally, the nth output subcircuit includes an nth control unit and an nth output unit; n is a positive integer less than or equal to N;

[0067] The nth control unit is disposed on a side of the nth output unit away from the display area.

[0068] Optionally, the active pattern of the transistor included in the nth control unit includes at least one active portion independent of each other, and the active pattern of the transistor included in the nth output unit includes at least one active portion independent of each other.

[0069] Optionally, the nth output sub-circuit includes an nth shutdown reset unit, an nth output capacitor and an nth output pull-down unit;

[0070] The nth output pull-down unit is provided between the nth shutdown reset unit and the nth output capacitor;

[0071] The nth output capacitor is provided between the nth output unit and the nth output pull-down unit;

[0072] The output capacitors respectively included in the N output sub-circuits are arranged along a first direction;

[0073] Active layer patterns of transistors in the shutdown reset units included in the N output sub-circuits are arranged along a first direction;

[0074] Active layer patterns of transistors in output pull-down units included in the N output sub-circuits are arranged along a first direction.

[0075] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a driving control clock signal line, a frame reset line, a first voltage line, a second voltage line, a first control voltage line, and a second control voltage line;

[0076] The driving control clock signal line, the frame reset line, the first voltage line, the second voltage line, the first control voltage line and the second control voltage line are arranged on a side of the driving control signal generating circuit away from the display area.

[0077] Optionally, a channel width-to-length ratio of a transistor included in the nth control unit is greater than or equal to 40 and less than or equal to 80;

[0078] The channel width-to-length ratio of the transistor included in the n-th output unit is greater than or equal to 100 and less than or equal to 200.

[0079] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a plurality of rows of gate lines, a plurality of columns of data lines, and a plurality of pixels arranged in the display area;

[0080] The pixel includes M sub-pixels with different colors; M is an integer greater than or equal to 3;

[0081] The sub-pixel includes a switching transistor and a pixel electrode; the pixel electrode includes at least one pixel electrode portion electrically connected to each other;

[0082] The pixel electrode portion extends along the second direction, the gate line extends along the third direction, and the data line extends along the first direction;

[0083] The second direction is substantially the same as the third direction, the first direction intersects the second direction, and the first direction intersects the third direction;

[0084] A row of gate lines is provided between two adjacent rows of sub-pixels, and a column of data lines is provided between two adjacent columns of sub-pixels;

[0085] The gate of the switch transistor is electrically connected to the corresponding gate line, the first electrode of the switch transistor is electrically connected to the pixel electrode, and the second electrode of the switch transistor is electrically connected to the corresponding data line.

[0086] Optionally, the gate line includes a first end and a second end;

[0087] The driving circuit is electrically connected to the signal input end of the gate line, and is used to provide a driving signal to the gate line through the signal input end; the signal input end is the first end or the second end;

[0088] The display substrate further comprises a plurality of electrostatic discharge blocks provided on the base substrate; the electrostatic discharge blocks are conductive blocks;

[0089] The electrostatic discharge block is electrically connected to an end portion of the gate line except the signal input end portion.

[0090] Optionally, the electrostatic discharge block and the gate line are provided in the same layer and the same material.

[0091] Optionally, a length of the electrostatic discharge block along the first direction is greater than a line width of the gate line.

[0092] Optionally, the side length of the orthographic projection of the electrostatic discharge block on the base substrate is greater than or equal to 12 μm and less than or equal to 30 μm, and the line width of the gate line is greater than or equal to 3 μm and less than or equal to 4 μm.

[0093] Optionally, a channel width-to-length ratio of the switching transistor is greater than or equal to 0.8 and less than or equal to 2, and a channel length of the switching transistor is greater than or equal to 3 μm and less than or equal to 6 μm.

[0094] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a plurality of columns of touch signal lines;

[0095] The touch signal line is arranged between two columns of sub-pixels, and the touch signal line is arranged adjacent to the data line;

[0096] The display substrate further includes a common electrode, and the common electrode includes a plurality of independent common electrode blocks; the pixel electrode is arranged on a side of the common electrode away from the base substrate;

[0097] The touch signal line is electrically connected to the common electrode block through a first via hole.

[0098] Optionally, the touch signal line and the data line are provided in the same layer; the display substrate further comprises a conductive pattern provided in the same layer as the pixel electrode;

[0099] The conductive pattern is electrically connected to the touch signal line and the common electrode block respectively through the first via hole, so that the touch signal line is electrically connected to the common electrode block; the pixel electrode includes a plurality of pixel electrode parts;

[0100] The pixel electrode comprises at least one pixel electrode portion and the conductive pattern arranged along a fourth direction;

[0101] A length of the at least one pixel electrode portion along the fourth direction is smaller than a length of pixel electrode portions of the pixel electrode other than the at least one pixel electrode portion along the fourth direction.

[0102] Optionally, the first via hole includes a first via hole portion and a second via hole portion, and the touch signal line, the common electrode block and the conductive pattern are arranged in sequence along a direction away from the base substrate;

[0103] The conductive pattern is electrically connected to the touch signal line through the first via portion, and the conductive pattern is electrically connected to the common electrode block through the second via portion.

[0104] Optionally, the touch signal line is formed in a source-drain metal layer, the common electrode block is formed in a first conductive layer, and the pixel electrode is formed in a second conductive layer;

[0105] The source / drain metal layer, the first conductive layer, and the second conductive layer are sequentially arranged along a side away from the display substrate.

[0106] Optionally, the display substrate described in at least one embodiment of the present disclosure further includes a virtual sub-pixel;

[0107] The virtual sub-pixel is arranged in the peripheral area, and the virtual sub-pixel is arranged adjacent to the display area;

[0108] The length of the virtual sub-pixel along the fourth direction is smaller than the length of the sub-pixel along the fourth direction.

[0109] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0110] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0111] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0112] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0113] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0114] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0115] FIG6 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0116] FIG7 is a timing diagram of at least one embodiment of the driving circuit shown in FIG6 of the present disclosure during operation;

[0117] 8 is a timing diagram of the drive control signal provided by G01, the potential of NC1, and the first drive signal output by GO1 during operation of at least one embodiment of the drive circuit shown in FIG6 ;

[0118] FIG9 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0119] FIG10 is an operation timing diagram of the driving circuit according to at least one embodiment of the present disclosure shown in FIG9 ;

[0120] 11A and 11B are layout diagrams of at least one embodiment of the driving circuit shown in FIG. 9 ;

[0121] FIG12 is a layout diagram of the gate metal layer in FIG11A;

[0122] FIG13A is a layout diagram of the semiconductor layer in FIG11A;

[0123] FIG13B is a layout diagram of the source / drain metal layer in FIG11A ;

[0124] FIG14 is a layout diagram of some sub-pixels in the display area of ​​the display panel;

[0125] FIG15 is a layout diagram of the gate metal layer in FIG14;

[0126] FIG16 is a layout diagram of the semiconductor layer in FIG14;

[0127] FIG17 is a layout diagram of the source / drain metal layer in FIG14 ;

[0128] FIG18 is a layout diagram of the first conductive layer in FIG14;

[0129] FIG19 is a layout diagram of the second conductive layer in FIG14;

[0130] FIG20 is a layout diagram of the connection between the GOA (Gate On Array, a gate driving circuit provided on an array substrate) region and the display region in at least one embodiment of the present disclosure;

[0131] FIG21 is a layout diagram of the gate metal layer in FIG20;

[0132] FIG22 is a layout diagram of the semiconductor layer in FIG20;

[0133] FIG23 is a layout diagram of the source / drain metal layer in FIG20 ;

[0134] FIG24 is a layout diagram of the first conductive layer in FIG20;

[0135] FIG25 is a layout diagram of the second conductive layer in FIG20;

[0136] FIG26 is a layout diagram of a partial area in the display area of ​​the display panel;

[0137] FIG27 is a layout diagram of the gate metal layer in FIG26;

[0138] FIG28 is a layout diagram of the semiconductor layer in FIG26;

[0139] FIG29 is a layout diagram of the source / drain metal layer in FIG26 ;

[0140] FIG30 is a layout diagram of the first conductive layer in FIG26;

[0141] FIG31 is a layout diagram of the second conductive layer in FIG26;

[0142] FIG32 is an enlarged schematic diagram of the first via hole in FIG26;

[0143] FIG33 is a cross-sectional view of AA′ in FIG32 ;

[0144] FIG34 is a waveform diagram of various signals in a driving module in at least one embodiment of the present disclosure;

[0145] FIG. 35 is a waveform diagram of various signals in a driving module in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0146] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0147] As used in this disclosure, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 10% of either one.

[0148] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0149] The present disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0150] In the present disclosure, circles, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0151] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0152] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0153] The driving circuit of the embodiment of the present disclosure includes a driving control signal generating circuit and a multi-channel output circuit; the multi-channel output circuit includes N-level output sub-circuits; N is an integer greater than 1;

[0154] The drive control signal generating circuit is used to generate a drive control signal, and the drive control signal is output through the drive control signal output terminal;

[0155] The nth output sub-circuit is electrically connected to the drive control signal output terminal, the control voltage line, the nth control node, the nth output clock signal line and the nth drive signal output terminal, respectively. The nth output sub-circuit is used to control the potential of the nth control node according to the drive control signal under the control of the control voltage provided by the control voltage line, and to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output terminal under the control of the potential of the nth control node; n is a positive integer less than or equal to N.

[0156] Existing TDDI (Touch and Display Driver Integration) products have a large number of S-ICs (source drivers), and the price of S-ICs is high, resulting in a high cost of current TDDI products. To address this problem, at least one embodiment of the present disclosure adopts a pixel structure design for a three-gate TDDI display product. In this pixel structure, the pixel electrodes are horizontally arranged, the number of gate lines is three times that of a normal display product, and the number of data lines is one-third of that of a normal display product. This greatly reduces the number of data lines used while ensuring that the resolution of the display product remains unchanged. At the same time, due to the increase in the number of gate lines, using a gate drive architecture that drives a row of pixels using a displayed row of GOA architecture will increase the left and right borders of the display product. Based on this, the present disclosure proposes a multiplexed gate drive architecture. To further achieve a narrow border and reduce costs, when the drive circuit described in the embodiment of the present disclosure is in operation, the drive control signal generation circuit outputs a drive control signal, and the N-level output sub-circuits respectively output N-level drive signals under the control of the drive control signal. This can achieve the purpose of one drive circuit driving multiple rows of gate lines, effectively reducing the number of transistors used in the drive circuit, which is conducive to achieving a narrow border.

[0157] In at least one embodiment of the present disclosure, N is taken as 4 as an example for illustration.

[0158] As shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure includes a driving control signal generating circuit 10 , a first output sub-circuit 11 , a second output sub-circuit 12 , a third output sub-circuit 13 , and a fourth output sub-circuit 14 ;

[0159] The driving control signal generating circuit 10 is used to generate a driving control signal, and the driving control signal is output through the driving control signal output terminal G01;

[0160] The first output sub-circuit 11 is electrically connected to the drive control signal output terminal G01, the control voltage line VDDC, the first control node NC1, the first output clock signal line HC1, and the first drive signal output terminal GO1, respectively. The first output sub-circuit 11 is configured to control the potential of the first control node NC1 according to the drive control signal under the control of the control voltage provided by the control voltage line VDDC, and control the first output clock signal line HC1 to provide a first output clock signal to the first drive signal output terminal GO1 under the control of the potential of the first control node NC1.

[0161] The second output sub-circuit 12 is electrically connected to the drive control signal output terminal GO1, the control voltage line VDDC, the second control node NC2, the second output clock signal line HC2, and the second drive signal output terminal GO2, respectively. The second output sub-circuit 12 is configured to control the potential of the second control node NC2 according to the drive control signal under the control of the control voltage provided by the control voltage line VDDC, and control the second output clock signal line HC2 to provide a second output clock signal to the second drive signal output terminal GO2 under the control of the potential of the second control node NC2;

[0162] The third output sub-circuit 13 is electrically connected to the drive control signal output terminal GO1, the control voltage line VDDC, the third control node NC3, the third output clock signal line HC3, and the third drive signal output terminal GO3, respectively. The three output sub-circuit 13 is used to control the potential of the third control node NC3 according to the drive control signal under the control of the control voltage provided by the control voltage line VDDC, and to control the third output clock signal line HC3 to provide a third output clock signal to the third drive signal output terminal GO3 under the control of the potential of the third control node NC3;

[0163] The fourth output sub-circuit 14 is electrically connected to the drive control signal output terminal GO1, the control voltage line VDDC, the fourth control node NC4, the fourth output clock signal line HC4 and the fourth drive signal output terminal GO4, respectively. The fourth output sub-circuit 14 is used to control the potential of the fourth control node NC4 according to the drive control signal under the control of the control voltage provided by the control voltage line VDDC, and to control the fourth output clock signal line HC4 to provide a fourth output clock signal to the fourth drive signal output terminal GO4 under the control of the potential of the fourth control node NC4.

[0164] In at least one embodiment of the present disclosure, the nth output subcircuit includes an nth control unit and an nth output unit;

[0165] The nth control unit is electrically connected to the drive control signal output terminal, the control voltage line and the nth control node respectively, and is used to control the potential of the nth control node according to the drive control signal under the control of the control voltage;

[0166] The nth output unit is electrically connected to the nth control node, the nth output clock signal line and the nth drive signal output end, respectively, and is used to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output end under the control of the potential of the nth control node.

[0167] In a specific implementation, the nth output subcircuit includes an nth control unit and an nth output unit. The nth control unit controls the potential of the nth control node according to the drive control signal under the control of the control voltage. The nth output unit controls the provision of the nth output clock signal to the nth drive signal output terminal under the control of the potential of the nth control node.

[0168] As shown in FIG2 , based on at least one embodiment of the driving circuit shown in FIG1 , the first output subcircuit includes a first control unit 211 and a first output unit 212 ;

[0169] The first control unit 211 is electrically connected to the drive control signal output terminal G01, the control voltage line VDDC and the first control node NC1 respectively, and is used to control the potential of the first control node NC1 according to the drive control signal under the control of the control voltage;

[0170] The first output unit 212 is electrically connected to the first control node NC1, the first output clock signal line HC1 and the first drive signal output terminal GO1, respectively, and is configured to control the first output clock signal line HC1 to provide a first output clock signal to the first drive signal output terminal GO1 under the control of the potential of the first control node NC1;

[0171] The second output subcircuit includes a second control unit 221 and a second output unit 222;

[0172] The second control unit 221 is electrically connected to the drive control signal output terminal G01, the control voltage line VDDC and the second control node NC2 respectively, and is used to control the potential of the second control node NC2 according to the drive control signal under the control of the control voltage;

[0173] The second output unit 222 is electrically connected to the second control node NC2, the second output clock signal line HC2, and the second drive signal output terminal GO2, respectively, and is configured to control the second output clock signal line HC2 to provide a second output clock signal to the second drive signal output terminal GO2 under the control of the potential of the second control node NC2;

[0174] The third output sub-circuit includes a third control unit 231 and a third output unit 232;

[0175] The third control unit 231 is electrically connected to the drive control signal output terminal G01, the control voltage line VDDC and the third control node NC3, respectively, and is used to control the potential of the third control node NC3 according to the drive control signal under the control of the control voltage;

[0176] The third output unit 232 is electrically connected to the third control node NC3, the third output clock signal line HC3 and the third drive signal output terminal GO3, respectively, and is configured to control the third output clock signal line HC3 to provide a third output clock signal to the third drive signal output terminal GO3 under the control of the potential of the third control node NC3;

[0177] The fourth output subcircuit includes a fourth control unit 241 and a fourth output unit 242;

[0178] The fourth control unit 241 is electrically connected to the drive control signal output terminal G01, the control voltage line VDDC and the fourth control node NC4, respectively, and is configured to control the potential of the fourth control node NC4 according to the drive control signal under the control of the control voltage;

[0179] The fourth output unit 242 is electrically connected to the fourth control node NC4, the fourth output clock signal line HC4 and the fourth drive signal output terminal GO4, respectively, and is used to control the fourth output clock signal line HC4 to provide a fourth output clock signal to the fourth drive signal output terminal GO4 under the control of the potential of the fourth control node NC4.

[0180] Optionally, the nth control unit includes an nth first control transistor; a gate of the nth first control transistor is electrically connected to the control voltage line, a first electrode of the nth first control transistor is electrically connected to the drive control signal output terminal, and a second electrode of the nth first control transistor is electrically connected to the nth control node; or,

[0181] The control voltage line includes a first control voltage line and a second control voltage line, and the nth control unit includes an nth first control transistor and an nth second control transistor; the gate of the nth first control transistor is electrically connected to the first control voltage line, the first electrode of the nth first control transistor is electrically connected to the drive control signal output end, and the second electrode of the nth first control transistor is electrically connected to the nth control node; the gate of the nth second control transistor is electrically connected to the second control voltage line, the first electrode of the nth second control transistor is electrically connected to the drive control signal output end, and the second electrode of the nth second control transistor is electrically connected to the nth control node.

[0182] In a specific implementation, when the nth control unit includes only one control transistor, and the gate of the control transistor is electrically connected to the control voltage line, after long-term use, the threshold voltage of the control transistor drifts, resulting in a weakened charge on the gate of the output transistor. In addition, among the four rows of pixels controlled by G01, the pre-charge time of the first row of pixels is the shortest, and the pre-charge time increases successively from the first row of pixels to the fourth row of pixels, resulting in differences in the gate voltages of the output transistors in the four output sub-circuits, thereby resulting in differences in the waveforms of the drive signals provided by the four output sub-circuits. The high level of the drive signal provided by the first output sub-circuit is the lowest, and the high level of the drive signal provided by the fourth output sub-circuit is the highest, resulting in differences in the brightness of the circuits of the four adjacent rows of pixels, thereby causing horizontal stripes to appear. Based on this, at least one embodiment of the present disclosure uses two control voltage lines and two control transistors. The two control voltage lines respectively control the two control transistors to work alternately, and the charging difference between different rows can reach 6mV (the corresponding brightness difference is less than 1 grayscale).

[0183] In a specific implementation, the nth control unit may include one control transistor, or the nth control unit may include two control transistors. In at least one embodiment of the present disclosure, the nth control unit includes two control transistors as an example.

[0184] In a specific implementation, the control voltage line may include a first control voltage line and a second control voltage line; the first control voltage line is used to provide a first control voltage, and the second control voltage line is used to provide a second control voltage. The first control voltage and the second control voltage may be square wave voltages, and the first control voltage may be inversely phase with the second control voltage.

[0185] Optionally, the nth output unit includes an nth output transistor;

[0186] The gate of the nth output transistor is electrically connected to the nth control node, the first electrode of the nth output transistor is electrically connected to the nth output clock signal line, and the second electrode of the nth output transistor is electrically connected to the nth drive signal output terminal.

[0187] In at least one embodiment of the present disclosure, the nth output sub-circuit further includes an nth shutdown reset unit;

[0188] The nth shutdown reset unit is electrically connected to the first voltage line and the nth drive signal output end respectively, and is used to control the connection or disconnection between the nth drive signal output end and the first voltage line under the control of the first voltage signal provided by the first voltage line.

[0189] In a specific implementation, the nth output sub-circuit may further include an nth shutdown reset unit, which controls the connection or disconnection between the nth drive signal output terminal and the first voltage line under the control of the first voltage signal;

[0190] When the power is turned off, the first voltage line provides a high voltage signal to connect the nth drive signal output terminal to the first voltage line, and the nth drive signal output terminal outputs a high voltage signal to turn on the transistor whose gate in the pixel circuit in the display area is electrically connected to the nth drive signal output terminal, so as to release the residual charge in the pixel and improve the shutdown ghosting phenomenon.

[0191] In existing oxide display products, when shutting down, the control voltages provided by the two control voltage lines are pulled up to a high voltage. The first pull-down node controls the corresponding output pull-down transistor to turn on, and the second pull-down node controls the corresponding output pull-down transistor to turn on. The potential of the voltage signal provided by the low-voltage line is also pulled up to a high voltage, which then charges the drive signal output terminal. After the drive signal output terminal is charged with high voltage, the pixel is discharged, thereby achieving the purpose of shutdown discharge. However, the gate-source voltage of the output pull-down transistor is at a high level for a long time, the threshold voltage of the output pull-down transistor drifts significantly, and the drain-source current of the output pull-down transistor is significantly reduced. The drive signal output terminal is insufficiently charged, and the pixel cannot be fully discharged. To improve this problem, at least one embodiment of the present disclosure adds a shutdown reset unit including a shutdown reset transistor. The gate of the shutdown reset transistor is electrically connected to the low-voltage line, and the source and drain are respectively connected to the drive signal output terminal and the low-voltage line. For the shutdown reset transistor, its gate-source voltage is 0V for a long time, and there is no problem of threshold voltage drift. When shutting down, the low voltage line provides a high voltage signal, the drive signal output terminal outputs a low voltage signal, the shutdown reset transistor is turned on, and the drive signal output terminal is charged with a high voltage, thereby achieving the purpose of shutdown discharge.

[0192] Optionally, the nth shutdown reset unit includes an nth shutdown reset transistor;

[0193] The gate electrode of the nth shutdown reset transistor and the second electrode of the nth shutdown reset transistor are both electrically connected to the first voltage line, and the first electrode of the nth shutdown reset transistor is electrically connected to the nth driving signal output terminal.

[0194] Optionally, the nth output sub-circuit further includes an nth output capacitor;

[0195] A first end of the nth output capacitor is electrically connected to the nth control node, and a second end of the nth output capacitor is electrically connected to the nth driving signal output end.

[0196] In at least one embodiment of the present disclosure, the nth output sub-circuit further includes an nth output pull-down unit;

[0197] The nth output pull-down unit is electrically connected to the pull-down node, the nth drive signal output terminal and the first voltage line respectively, and is used to control the connection or disconnection between the nth drive signal output terminal and the first voltage line under the control of the potential of the pull-down node.

[0198] Optionally, the nth output pull-down unit includes an nth first output pull-down transistor; a gate of the nth first output pull-down transistor is electrically connected to the pull-down node, a first electrode of the nth first output pull-down transistor is electrically connected to the nth drive signal output terminal, and a second electrode of the nth first output pull-down transistor is electrically connected to the first voltage line; or,

[0199] The pull-down node includes a first pull-down node and a second pull-down node; the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor; the gate of the nth first output pull-down transistor is electrically connected to the first pull-down node, the first electrode of the nth first output pull-down transistor is electrically connected to the nth drive signal output end, and the second electrode of the nth first output pull-down transistor is electrically connected to the first voltage line; the gate of the nth second output pull-down transistor is electrically connected to the second pull-down node, the first electrode of the nth second output pull-down transistor is electrically connected to the nth drive signal output end, and the second electrode of the nth second output pull-down transistor is electrically connected to the first voltage line.

[0200] In a specific implementation, the pull-down node may include a first pull-down node and a second pull-down node, and the nth output pull-down unit may include two output pull-down transistors. In at least one embodiment of the present disclosure, the nth output pull-down unit includes two output pull-down transistors as an example for description.

[0201] Optionally, the first voltage line may be a first low voltage line, but is not limited thereto.

[0202] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 ,

[0203] The first output sub-circuit further includes a first shutdown reset unit 311, a first output capacitor CO1 and a first output pull-down unit 312;

[0204] The first shutdown reset unit 311 is electrically connected to the first voltage line V1 and the first drive signal output terminal GO1, respectively, and is used to control the connection or disconnection between the first drive signal output terminal GO1 and the first voltage line V1 under the control of the first voltage signal provided by the first voltage line V1;

[0205] A first end of the first output capacitor CO1 is electrically connected to the first control node NC1, and a second end of the first output capacitor CO1 is electrically connected to the first drive signal output terminal GO1;

[0206] The first output pull-down unit 312 is electrically connected to the pull-down node PD, the first drive signal output terminal GO1, and the first voltage line V1 (VGL), respectively, and is used to control the connection or disconnection between the first drive signal output terminal GO1 and the first voltage line V1 under the control of the potential of the pull-down node PD;

[0207] The second output sub-circuit further includes a second shutdown reset unit 321, a second output capacitor CO2 and a second output pull-down unit 322;

[0208] The second shutdown reset unit 321 is electrically connected to the first voltage line V1 and the second drive signal output terminal GO2, respectively, and is used to control the connection or disconnection between the second drive signal output terminal GO1 and the first voltage line V1 under the control of the first voltage signal provided by the first voltage line V1;

[0209] A first end of the second output capacitor CO2 is electrically connected to the second control node NC2, and a second end of the second output capacitor CO2 is electrically connected to the second drive signal output terminal GO2;

[0210] The second output pull-down unit 322 is electrically connected to the pull-down node PD, the second drive signal output terminal GO2, and the first voltage line V1 (VGL), respectively, and is used to control the connection or disconnection between the second drive signal output terminal GO2 and the first voltage line V1 under the control of the potential of the pull-down node PD;

[0211] The third output sub-circuit further includes a third shutdown reset unit 331, a third output capacitor CO3 and a third output pull-down unit 332;

[0212] The third shutdown reset unit 331 is electrically connected to the first voltage line V1 and the third drive signal output terminal GO3, respectively, and is used to control the connection or disconnection between the third drive signal output terminal GO3 and the first voltage line V1 under the control of the first voltage signal provided by the first voltage line V1;

[0213] A first end of the third output capacitor CO3 is electrically connected to the third control node NC3, and a second end of the third output capacitor CO3 is electrically connected to the third drive signal output terminal GO3;

[0214] The third output pull-down unit 332 is electrically connected to the pull-down node PD, the third drive signal output terminal GO3, and the first voltage line V1, respectively, and is used to control the connection or disconnection between the third drive signal output terminal GO3 and the first voltage line V1 under the control of the potential of the pull-down node PD;

[0215] The fourth output sub-circuit further includes a fourth shutdown reset unit 341, a fourth output capacitor CO4 and a fourth output pull-down unit 342;

[0216] The fourth shutdown reset unit 341 is electrically connected to the first voltage line V1 and the fourth drive signal output terminal GO4, respectively, and is used to control the connection or disconnection between the fourth drive signal output terminal GO4 and the first voltage line V1 under the control of the first voltage signal provided by the first voltage line V1;

[0217] A first end of the fourth output capacitor CO4 is electrically connected to the fourth control node NC4, and a second end of the fourth output capacitor CO4 is electrically connected to the fourth drive signal output terminal GO4;

[0218] The fourth output pull-down unit 342 is electrically connected to the pull-down node PD, the fourth drive signal output terminal GO4 and the first voltage line V1 respectively, and is used to control the connection or disconnection between the fourth drive signal output terminal GO4 and the first voltage line V1 under the control of the potential of the pull-down node PD.

[0219] In a specific implementation, the control voltage line may include two control voltage lines, and the pull-down node may include two pull-down nodes.

[0220] As shown in FIG4, based on at least one embodiment of the driving circuit shown in FIG3,

[0221] The control voltage lines include a first control voltage line VDDo and a second control voltage line VDDe, and the pull-down nodes include a first pull-down node PDo and a second pull-down node PDe;

[0222] The first control unit 211 is electrically connected to the drive control signal output terminal G01, the first control voltage line VDDo, the second control voltage line VDDe, and the first control node NC1, respectively, and is configured to control the potential of the first control node NC1 according to the drive control signal under the control of a first control voltage provided by the first control voltage line VDDo, and to control the potential of the first control node NC1 according to the drive control signal under the control of a second control voltage provided by the second control voltage line VDDe;

[0223] The second control unit 221 is electrically connected to the drive control signal output terminal G01, the first control voltage line VDDo, the second control voltage line VDDe, and the second control node NC2, respectively, and is configured to control the potential of the second control node NC2 according to the drive control signal under the control of a first control voltage provided by the first control voltage line VDDo, and to control the potential of the second control node NC2 according to the drive control signal under the control of a second control voltage provided by the second control voltage line VDDe;

[0224] The third control unit 231 is electrically connected to the drive control signal output terminal G01, the first control voltage line VDDo, the second control voltage line VDDe, and the third control node NC3, respectively, and is configured to control the potential of the third control node NC3 according to the drive control signal under the control of a first control voltage provided by the first control voltage line VDDo, and to control the potential of the third control node NC3 according to the drive control signal under the control of a second control voltage provided by the second control voltage line VDDe;

[0225] The fourth control unit 241 is electrically connected to the drive control signal output terminal G01, the first control voltage line VDDo, the second control voltage line VDDe, and the fourth control node NC4, respectively, and is configured to control the potential of the fourth control node NC4 according to the drive control signal under the control of the first control voltage provided by the first control voltage line VDDo, and to control the potential of the fourth control node NC4 according to the drive control signal under the control of the second control voltage provided by the second control voltage line VDDe;

[0226] The first output pull-down unit 312 is electrically connected to the first pull-down node PDo, the second pull-down node PDe, the first drive signal output terminal GO1, and the first voltage line V1, respectively, and is configured to control the connection or disconnection between the first drive signal output terminal GO1 and the first voltage line V1 under the control of the potential of the first pull-down node PDo, and to control the connection or disconnection between the first drive signal output terminal GO1 and the first voltage line V1 under the control of the potential of the second pull-down node PDe;

[0227] The second output pull-down unit 322 is electrically connected to the first pull-down node PDo, the second pull-down node PDe, the second drive signal output terminal GO2 and the first voltage line V1, respectively, and is used to control the connection or disconnection between the second drive signal output terminal GO2 and the first voltage line V1 under the control of the potential of the first pull-down node PDo, and is used to control the connection or disconnection between the second drive signal output terminal GO2 and the first voltage line V1 under the control of the potential of the second pull-down node PDe;

[0228] The third output pull-down unit 332 is electrically connected to the first pull-down node PDo, the second pull-down node PDe, the third drive signal output terminal GO3 and the first voltage line V1, respectively, and is used to control the connection or disconnection between the third drive signal output terminal GO3 and the first voltage line V1 under the control of the potential of the first pull-down node PDo, and is used to control the connection or disconnection between the third drive signal output terminal GO3 and the first voltage line V1 under the control of the potential of the second pull-down node PDe;

[0229] The fourth output pull-down unit 342 is electrically connected to the first pull-down node PDo, the second pull-down node PDe, the fourth drive signal output terminal GO4 and the first voltage line V1, respectively, and is used to control the connection or disconnection between the fourth drive signal output terminal GO4 and the first voltage line V1 under the control of the potential of the first pull-down node PDo, and to control the connection or disconnection between the fourth drive signal output terminal GO4 and the first voltage line V1 under the control of the potential of the second pull-down node PDe.

[0230] In at least one embodiment of the present disclosure, the pull-down node includes a first pull-down node and a second pull-down node; the drive control signal generating circuit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit, and a drive control output circuit;

[0231] The pull-up node control circuit is used to control the potential of the pull-up node;

[0232] The first pull-down node control circuit is used to control the potential of the first pull-down node under the control of the potential of the pull-up node;

[0233] The second pull-down node control circuit is used to control the potential of the second pull-down node under the control of the potential of the pull-up node;

[0234] The drive control output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the drive control signal output end, the drive control clock signal line and the first voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the drive control signal output end under the control of the potential of the pull-up node, control the drive control signal output end to be connected to the first voltage line under the control of the potential of the first pull-down node, and control the drive control signal output end to be connected to the first voltage line under the control of the potential of the second pull-down node.

[0235] In a specific implementation, the driving control clock signal line is used to provide a driving control clock signal.

[0236] In a specific implementation, the drive control signal generating circuit may include a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit and a drive control output circuit. The pull-up node control circuit controls the potential of the pull-up node, the first pull-down node control circuit controls the potential of the first pull-down node, and the second pull-down node control circuit controls the potential of the second pull-down node. The drive control output circuit controls the drive control signal output end to provide a corresponding drive control signal under the control of the potential of the pull-up node, the potential of the first pull-down node and the potential of the second pull-down node.

[0237] In at least one embodiment of the present disclosure, the drive control signal generating circuit further includes a carry output circuit;

[0238] The carry output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the carry output terminal, the drive control clock signal line and the second voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the carry output terminal under the control of the potential of the pull-up node, control the carry output terminal to be connected to the second voltage line under the control of the potential of the first pull-down node, and control the carry output terminal to be connected to the second voltage line under the control of the potential of the second pull-down node.

[0239] In a specific implementation, the drive control signal generating circuit may further include a carry output circuit, which controls the carry output terminal to provide a corresponding carry signal under the control of the potential of the pull-up node, the potential of the first pull-down node and the potential of the second pull-down node. The carry signal can be used for cascading.

[0240] In at least one embodiment of the present disclosure, the pull-up node control circuit is electrically connected to the input terminal, the frame reset line, the first pull-down node, the second pull-down node, the first reset terminal, the pull-up node, and the second voltage line, respectively, and is configured to control the potential of the pull-up node under the control of an input signal provided by the input terminal, and control the connection between the pull-up node and the second voltage line under the control of a frame reset signal provided by the frame reset line, control the connection between the pull-up node and the second voltage line under the control of the potential of the first pull-down node, control the connection between the pull-up node and the second voltage line under the control of the potential of the second pull-down node, and control the connection between the pull-up node and the second voltage line under the control of a first reset signal provided by the first reset terminal;

[0241] The first pull-down node control circuit is electrically connected to a first control voltage line, a first pull-down node, a pull-up node, and a second voltage line, respectively, and is configured to control the potential of the first pull-down node under the control of a first control voltage provided by the first control voltage line and the potential of the pull-up node;

[0242] The second pull-down node control circuit is electrically connected to the second control voltage line, the second pull-down node, the pull-up node, and the second voltage line, respectively, and is configured to control the potential of the second pull-down node under the control of a second control voltage provided by the second control voltage line and the potential of the pull-up node;

[0243] The drive control output circuit is also electrically connected to a second reset terminal, and is used to control the connection between the drive control signal output terminal and the first voltage line under the control of a second reset signal provided by the second reset terminal.

[0244] Optionally, the second voltage line may be the first low voltage line, but is not limited thereto.

[0245] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG4 ,

[0246] The driving control signal generating circuit may include a pull-up node control circuit 31, a first pull-down node control circuit 32, a second pull-down node control circuit 33, a driving control output circuit 34 and a carry output circuit 35;

[0247] The pull-up node control circuit 31 is electrically connected to the input terminal I1, the frame reset line TRST, the first pull-down node PD1, the second pull-down node PD2, the first reset terminal RST1, the pull-up node PU, and the second low-voltage line LVGL, respectively, and is configured to control the potential of the pull-up node PU under the control of the input signal provided by the input terminal I1, and control the connection between the pull-up node PU and the second low-voltage line LVGL under the control of the frame reset signal provided by the frame reset line TRST, control the connection between the pull-up node PU and the second low-voltage line LVGL under the control of the potential of the first pull-down node PD1, control the connection between the pull-up node PU and the second low-voltage line LVGL under the control of the potential of the second pull-down node PD2, and control the connection between the pull-up node PU and the second low-voltage line LVGL under the control of the first reset signal provided by the first reset terminal RST1;

[0248] The first pull-down node control circuit 32 is electrically connected to the first control voltage line VDDo, the first pull-down node PD1, the pull-up node PU, and the second low voltage line LVGL, respectively, and is configured to control the potential of the first pull-down node PD1 under the control of the first control voltage provided by the first control voltage line VDDo and the potential of the pull-up node PU;

[0249] The second pull-down node control circuit 33 is electrically connected to the second control voltage line VDDe, the second pull-down node PD2, the pull-up node PU, and the second low voltage line LVGL, respectively, and is used to control the potential of the second pull-down node PD2 under the control of the second control voltage provided by the second control voltage line VDDe and the potential of the pull-up node PU;

[0250] The drive control output circuit 34 is electrically connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the drive control signal output terminal G01, the drive control clock signal line CLK, and the first low-voltage line VGL, respectively, and is configured to control the drive control clock signal line CLK to be electrically connected to the drive control signal output terminal G01 under the control of the potential of the pull-up node PU, control the drive control signal output terminal G01 to be connected to the first low-voltage line VGL under the control of the potential of the first pull-down node PD1, and control the drive control signal output terminal G01 to be connected to the first low-voltage line VGL under the control of the potential of the second pull-down node PD2;

[0251] The drive control output circuit 34 is also electrically connected to the second reset terminal RST2, and is used to control the connection between the drive control signal output terminal G01 and the first low voltage line VGL under the control of the second reset signal provided by the second reset terminal RST2;

[0252] The carry output circuit 35 is electrically connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the carry output terminal CR, the drive control clock signal line CLK and the second low voltage line LVGL, respectively, and is used to control the drive control clock signal line CLK to be electrically connected to the carry output terminal CR under the control of the potential of the pull-up node PU, control the carry output terminal CR to be connected to the second low voltage line under the control of the potential of the first pull-down node PD1, and control the carry output terminal CR to be connected to the second low voltage line LVGL under the control of the potential of the second pull-down node PD3.

[0253] As shown in FIG6 , in at least one embodiment of the driving circuit shown in FIG5 , the first output sub-circuit may include a first first control transistor MC11, a first second control transistor MC12, a first output transistor MO1, a first shutdown reset transistor MF1, a first output capacitor CO1, a first first output pull-down transistor MX11, and a first second output pull-down transistor MX12;

[0254] The gate of MC11 is electrically connected to the first control voltage line VDDo, the source of MC11 is electrically connected to the drive control signal output terminal G01, and the drain of MC11 is electrically connected to the first control node NC1;

[0255] The gate of MC12 is electrically connected to the second control voltage line VDDe, the source of MC12 is electrically connected to the drive control signal output terminal G01, and the drain of MC12 is electrically connected to the first control node NC1;

[0256] The gate of MO1 is electrically connected to the first control node NC1, the source of MO1 is electrically connected to the first output clock signal line HC1, and the drain of MO1 is electrically connected to the nth drive signal output terminal GO1;

[0257] The gate electrode of MF1 and the drain electrode of MF1 are both electrically connected to the first low voltage line VGL, and the source electrode of MF1 is electrically connected to the first driving signal output terminal GO1;

[0258] A first end of the first output capacitor CO1 is electrically connected to the first control node NC1, and a second end of the first output capacitor CO1 is electrically connected to the first drive signal output terminal GO1;

[0259] The gate of MX11 is electrically connected to the first pull-down node PD1, the source of MX11 is electrically connected to the first drive signal output terminal GO1, and the drain of MX11 is electrically connected to the first low voltage line VGL;

[0260] The gate of MX12 is electrically connected to the second pull-down node PD2, the source of MX12 is electrically connected to the first drive signal output terminal GO1, and the drain of MX12 is electrically connected to the first low voltage line VGL;

[0261] The second output sub-circuit may include a second first control transistor MC21, a second second control transistor MC22, a second output transistor MO2, a second shutdown reset transistor MF2, a second output capacitor CO2, a second first output pull-down transistor MX21 and a second second output pull-down transistor MX22;

[0262] The gate of MC21 is electrically connected to the first control voltage line VDDo, the source of MC21 is electrically connected to the drive control signal output terminal G01, and the drain of MC21 is electrically connected to the second control node NC2;

[0263] The gate of MC22 is electrically connected to the second control voltage line VDDe, the source of MC22 is electrically connected to the drive control signal output terminal G01, and the drain of MC22 is electrically connected to the second control node NC2;

[0264] The gate of MO2 is electrically connected to the second control node NC2, the source of MO2 is electrically connected to the second output clock signal line HC2, and the drain of MO2 is electrically connected to the second drive signal output terminal GO2;

[0265] The gate electrode of MF2 and the drain electrode of MF2 are both electrically connected to the first low voltage line VGL, and the source electrode of MF2 is electrically connected to the second drive signal output terminal GO2;

[0266] a first end of the second output capacitor CO2 is electrically connected to the second control node NC2, and a second end of the second output capacitor CO2 is electrically connected to the second drive signal output terminal GO2;

[0267] The gate of MX21 is electrically connected to the first pull-down node PD1, the source of MX21 is electrically connected to the second drive signal output terminal GO2, and the drain of MX21 is electrically connected to the first low voltage line VGL;

[0268] The gate of MX22 is electrically connected to the second pull-down node PD2, the source of MX22 is electrically connected to the second drive signal output terminal GO2, and the drain of MX22 is electrically connected to the first low voltage line VGL;

[0269] The third output sub-circuit may include a third first control transistor MC31, a third second control transistor MC32, a third output transistor MO3, a third shutdown reset transistor MF3, a third output capacitor CO3, a third first output pull-down transistor MX31 and a third second output pull-down transistor MX32;

[0270] The gate of MC31 is electrically connected to the first control voltage line VDDo, the source of MC31 is electrically connected to the drive control signal output terminal G01, and the drain of MC31 is electrically connected to the third control node NC3;

[0271] The gate of MC32 is electrically connected to the second control voltage line VDDe, the source of MC32 is electrically connected to the drive control signal output terminal G01, and the drain of MC32 is electrically connected to the third control node NC3;

[0272] The gate of MO3 is electrically connected to the third control node NC3, the source of MO3 is electrically connected to the third output clock signal line HC3, and the drain of MO3 is electrically connected to the third drive signal output terminal GO3;

[0273] The gate electrode of MF3 and the drain electrode of MF3 are both electrically connected to the first low voltage line VGL, and the source electrode of MF3 is electrically connected to the third driving signal output terminal GO3;

[0274] A first end of the third output capacitor CO3 is electrically connected to the third control node NC3, and a second end of the third output capacitor CO3 is electrically connected to the third drive signal output terminal GO3;

[0275] The gate of MX31 is electrically connected to the first pull-down node PD1, the source of MX31 is electrically connected to the third drive signal output terminal GO3, and the drain of MX31 is electrically connected to the first low voltage line VGL;

[0276] The gate of MX32 is electrically connected to the second pull-down node PD2, the source of MX32 is electrically connected to the third drive signal output terminal GO3, and the drain of MX32 is electrically connected to the first low voltage line VGL;

[0277] The fourth output sub-circuit may include a fourth first control transistor MC41, a fourth second control transistor MC42, a fourth output transistor MO4, a fourth shutdown reset transistor MF4, a fourth output capacitor CO4, a fourth first output pull-down transistor MX41, and a fourth second output pull-down transistor MX42;

[0278] The gate of MC41 is electrically connected to the first control voltage line VDDo, the source of MC41 is electrically connected to the drive control signal output terminal G01, and the drain of MC41 is electrically connected to the fourth control node NC4;

[0279] The gate of MC42 is electrically connected to the second control voltage line VDDe, the source of MC42 is electrically connected to the drive control signal output terminal G01, and the drain of MC42 is electrically connected to the fourth control node NC4;

[0280] The gate of MO4 is electrically connected to the fourth control node NC4, the source of MO4 is electrically connected to the fourth output clock signal line HC4, and the drain of MO4 is electrically connected to the fourth drive signal output terminal GO4;

[0281] The gate electrode and the drain electrode of MF4 are both electrically connected to the first low voltage line VGL, and the source electrode of MF4 is electrically connected to the fourth drive signal output terminal GO4;

[0282] A first end of the fourth output capacitor CO4 is electrically connected to the fourth control node NC4, and a second end of the fourth output capacitor CO4 is electrically connected to the fourth drive signal output terminal GO4;

[0283] The gate of MX41 is electrically connected to the first pull-down node PD1, the source of MX41 is electrically connected to the fourth drive signal output terminal GO4, and the drain of MX41 is electrically connected to the first low voltage line VGL;

[0284] The gate of MX42 is electrically connected to the second pull-down node PD2 , the source of MX42 is electrically connected to the fourth driving signal output terminal GO4 , and the drain of MX42 is electrically connected to the first low voltage line VGL.

[0285] In at least one embodiment shown in FIG. 6 , all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto.

[0286] As shown in FIG7 , when at least one embodiment of the present disclosure as shown in FIG6 is working, when VDDo provides a high voltage signal and VDDe provides a low voltage signal,

[0287] In the first stage t1, when G01 outputs a high voltage signal, MC11 turns on and charges NC1;

[0288] In the second stage t2, MO1 is turned on, HC1 provides a high voltage signal to charge GO1, and at the same time, the potential of NC1 is further increased by the bootstrap effect of CO1 to ensure sufficient charging of GO1. It should be noted that MC11 is turned off at this time to prevent the potential of NC1 from failing to bootstrap.

[0289] In the third stage t3, MO1 is still in the open state, and HC1 provides a low voltage signal to discharge GO1;

[0290] In the period after this, the potential of PDo and the potential of PDe are high voltages; MX11 and MX12 are turned on to continuously discharge G01.

[0291] At least one embodiment of the driving circuit shown in FIG6 of the present disclosure is in operation.

[0292] When G01 outputs a high voltage signal and HC2 outputs a high voltage signal, GO2 outputs a high voltage signal;

[0293] When G01 outputs a high voltage signal and HC3 outputs a low voltage signal, GO2 outputs a low voltage signal;

[0294] When G01 outputs a high voltage signal and HC3 outputs a high voltage signal, GO3 outputs a high voltage signal;

[0295] When G01 outputs a high voltage signal and HC3 outputs a low voltage signal, GO3 outputs a low voltage signal;

[0296] When G01 outputs a high voltage signal and HC4 outputs a high voltage signal, GO4 outputs a high voltage signal;

[0297] When G01 outputs a high voltage signal and HC4 outputs a low voltage signal, GO4 outputs a low voltage signal.

[0298] In at least one embodiment of the driving circuit shown in FIG6 of the present disclosure, the functions of each control transistor are described as follows: when VDDo provides a high voltage signal and VDDe provides a low voltage signal,

[0299] At the beginning of the first stage t1, the potential of NC1 is low. For MC11, the gate-source voltage of MC11 is greater than the threshold voltage of MC11. The drive control signal output by G01 charges NC1. During the bootstrap process of NC1, the voltage of NC1 is greater than the high voltage value VGH. The gate-source voltage of MC11 is 0V, and both MC11 and MC12 are in the off state.

[0300] Without MC11 and MC12, the potential of NC1 cannot be self-bootstrapping. The reason is that the transistor whose gate is electrically connected to the pull-up node PU included in the drive control output circuit on the left is in the open state, and the drive control clock signal line outputs a high voltage signal, which is an active signal. The bootstrapped charge will flow through the transistor to the drive control clock signal line, thereby failing to complete the bootstrapping of NC1.

[0301] FIG8 is a timing diagram of the driving control signal provided by G01, the potential of NC1, and the first driving signal output by GO1 during operation of at least one embodiment of the driving circuit shown in FIG6.

[0302] Optionally, the pull-up node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor;

[0303] The gate of the first transistor and the first electrode of the first transistor are electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the pull-up node;

[0304] The gate of the second transistor is electrically connected to the first reset terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the second voltage line;

[0305] The gate of the third transistor is electrically connected to the frame reset line, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the second voltage line;

[0306] The gate of the fourth transistor is electrically connected to the first pull-down node, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the second voltage line;

[0307] The gate of the fifth transistor is electrically connected to the second pull-down node, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the second voltage line;

[0308] The first pull-down node control circuit includes a sixth transistor and a seventh transistor;

[0309] The gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the first control voltage line, and the second electrode of the sixth transistor is electrically connected to the first pull-down node;

[0310] The gate of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the second voltage line;

[0311] The second pull-down node control circuit includes an eighth transistor and a ninth transistor;

[0312] The gate of the eighth transistor and the first electrode of the eighth transistor are electrically connected to the second control voltage line, and the second electrode of the eighth transistor is electrically connected to the second pull-down node;

[0313] A gate of the ninth transistor is electrically connected to the pull-up node, a first electrode of the ninth transistor is electrically connected to the second pull-down node, and a second electrode of the ninth transistor is electrically connected to the second voltage line.

[0314] Optionally, the first pull-down node control circuit further includes a tenth transistor, and the second pull-down node control circuit further includes an eleventh transistor;

[0315] The gate of the tenth transistor is electrically connected to the input terminal, the first electrode of the tenth transistor is electrically connected to the first pull-down node, and the second electrode of the tenth transistor is electrically connected to the second voltage line;

[0316] The gate of the eleventh transistor is electrically connected to the input terminal, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line;

[0317] The carry output circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor;

[0318] The gate of the twelfth transistor is electrically connected to the pull-up node, the first electrode of the twelfth transistor is electrically connected to the drive control clock signal line, and the second electrode of the twelfth transistor is electrically connected to the carry output terminal;

[0319] The gate of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry output terminal, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line;

[0320] The gate of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the carry output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage line;

[0321] The drive control output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a first capacitor;

[0322] The gate of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the drive control clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the drive control signal output terminal;

[0323] The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the first voltage line;

[0324] The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the first voltage line;

[0325] The gate of the eighteenth transistor is electrically connected to the second reset terminal, the first electrode of the eighteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first voltage line;

[0326] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the drive control signal output terminal.

[0327] As shown in FIG9 , based on at least one embodiment of the driving circuit shown in FIG6 ,

[0328] The pull-up node control circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5;

[0329] The gate of the first transistor M1 and the drain of the first transistor M1 are electrically connected to the input terminal I1, and the source of the first transistor M1 is electrically connected to the pull-up node PU;

[0330] The source of the second transistor M2 is electrically connected to the first reset terminal RST1, the drain of the second transistor M2 is electrically connected to the pull-up node PU, and the source of the second transistor M2 is electrically connected to the second low voltage line LVGL;

[0331] The gate of the third transistor M3 is electrically connected to the frame reset terminal TRST, the drain of the third transistor M3 is electrically connected to the pull-up node PU, and the source of the third transistor M3 is electrically connected to the second low voltage line LVGL;

[0332] The gate of the fourth transistor M4 is electrically connected to the first pull-down node PD1, the drain of the fourth transistor M4 is electrically connected to the pull-up node PU, and the source of the fourth transistor M4 is electrically connected to the second low voltage line LVGL;

[0333] The gate of the fifth transistor M5 is electrically connected to the second pull-down node PD2, the drain of the fifth transistor M5 is electrically connected to the pull-up node PU, and the source of the fifth transistor M5 is electrically connected to the second low voltage line LVGL;

[0334] The first pull-down node control circuit includes a sixth transistor M6 and a seventh transistor M7;

[0335] The gate of the sixth transistor M6 and the drain of the sixth transistor M6 are electrically connected to the first control voltage line VDDo, and the source of the sixth transistor M6 is electrically connected to the first pull-down node PD1;

[0336] The gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the drain of the seventh transistor M7 is electrically connected to the first pull-down node PD1, and the source of the seventh transistor M7 is electrically connected to the second low voltage line LVGL;

[0337] The second pull-down node control circuit includes an eighth transistor M8 and a ninth transistor M9;

[0338] The gate of the eighth transistor M8 and the drain of the eighth transistor M8 are electrically connected to the second control voltage line VDDe, and the source of the eighth transistor M8 is electrically connected to the second pull-down node PD2;

[0339] The gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the drain of the ninth transistor M9 is electrically connected to the second pull-down node PD2, and the source of the ninth transistor M9 is electrically connected to the second low voltage line LVGL;

[0340] The first pull-down node control circuit further includes a tenth transistor M10, and the second pull-down node control circuit 33 further includes an eleventh transistor M11;

[0341] The gate of the tenth transistor M10 is electrically connected to the input terminal I1, the drain of the tenth transistor M10 is electrically connected to the first pull-down node PD1, and the source of the tenth transistor M10 is electrically connected to the second low voltage line LVGL;

[0342] The gate of the eleventh transistor M11 is electrically connected to the input terminal I1, the drain of the eleventh transistor M11 is electrically connected to the second pull-down node PD2, and the source of the eleventh transistor M11 is electrically connected to the second voltage line LVGL;

[0343] The carry output circuit 35 includes a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14;

[0344] The gate of the twelfth transistor M12 is electrically connected to the pull-up node PU, the drain of the twelfth transistor M12 is electrically connected to the drive control clock signal line CLK, and the source of the twelfth transistor M12 is electrically connected to the carry output terminal CR;

[0345] The gate of the thirteenth transistor M13 is electrically connected to the first pull-down node PD1, the drain of the thirteenth transistor M13 is electrically connected to the carry output terminal CR, and the source of the thirteenth transistor M13 is electrically connected to the second low voltage line LVGL;

[0346] The gate of the fourteenth transistor M14 is electrically connected to the second pull-down node PD2, the drain of the fourteenth transistor M14 is electrically connected to the carry output terminal CR, and the source of the fourteenth transistor M14 is electrically connected to the second low voltage line LVGL;

[0347] The driving control output circuit includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18 and a first capacitor C1;

[0348] The gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the drain of the fifteenth transistor M15 is electrically connected to the drive control clock signal line CLK, and the source of the fifteenth transistor M15 is electrically connected to the drive control signal output terminal G01;

[0349] The gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, the drain of the sixteenth transistor M16 is electrically connected to the driving control signal output terminal G01, and the source of the sixteenth transistor M16 is electrically connected to the first low voltage line VGL;

[0350] The gate of the seventeenth transistor M17 is electrically connected to the second pull-down node PD2, the drain of the seventeenth transistor M17 is electrically connected to the driving control signal output terminal G01, and the source of the seventeenth transistor M17 is electrically connected to the first low voltage line VGL;

[0351] The gate of the eighteenth transistor M18 is electrically connected to the second reset terminal RST2, the drain of the eighteenth transistor M18 is electrically connected to the driving control signal output terminal G01, and the source of the eighteenth transistor M18 is electrically connected to the first low voltage line VGL;

[0352] The first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the driving control signal output terminal G01.

[0353] In at least one embodiment of the driving circuit shown in FIG. 9 , all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto.

[0354] In at least one embodiment of the driving circuit shown in FIG9 , the width-to-length ratio of M1 may be greater than or equal to 12 and less than or equal to 15, the width-to-length ratio of M2 may be greater than or equal to 2 and less than or equal to 5, the width-to-length ratio of M15 may be greater than or equal to 100 and less than or equal to 300, the width-to-length ratio of M18 may be greater than or equal to 4 and less than or equal to 6, the width-to-length ratio of M6 and the width-to-length ratio of M8 may be greater than or equal to 0.8 and less than or equal to 1.2, the width-to-length ratio of M7 and the width-to-length ratio of M9 may be greater than or equal to 4 and less than or equal to 4.8, the width-to-length ratio of M10 and the width-to-length ratio of M11 may be greater than or equal to 3 and less than or equal to 5, the width-to-length ratio of M4 and the width-to-length ratio of M5 may be greater than or equal to 13 and less than or equal to 15, and the width-to-length ratio of M12 may be greater than or equal to 1. The aspect ratio of M13 and M14 may be greater than or equal to 1 and less than or equal to 3, the aspect ratio of M16 and M17 may be greater than or equal to 7 and less than or equal to 9, the aspect ratio of M3 may be greater than or equal to 0.8 and less than or equal to 1.2, the aspect ratio of each control transistor may be greater than or equal to 40 and less than or equal to 80, the aspect ratio of each output transistor may be greater than or equal to 100 and less than or equal to 200, the aspect ratio of each output pull-down transistor may be greater than or equal to 7 and less than or equal to 9, the capacitance value of the first capacitor may be greater than or equal to 1 pF and less than or equal to 3 pF, and the capacitance value of each output capacitor may be greater than or equal to 1 pF and less than or equal to 3 pF.

[0355] As shown in FIG10 , when at least one embodiment of the driving circuit shown in FIG9 of the present disclosure is in operation, a display cycle may include a first display stage S1 , a second display stage S2 , a third display stage S3 , a fourth display stage S4 and a fifth display stage S5 ;

[0356] In the first display phase S1, TRST provides a high voltage signal, M3 is turned on, and other transistors are turned off. A low voltage signal is written to the pull-up nodes in all row driver circuits. TRST connects all row driver circuits and reduces noise for all rows before the frame. The frame reset signal provided by TRST prevents abnormal signals at the front end of the gate driver architecture (such as the timing control chip) from causing noise to be transferred to the next frame.

[0357] In the second display stage S2, STV1 is a high voltage signal (the input terminal I1 in Figure 9 is connected to the first start signal STV1), M1 is turned on, M10 and M11 are turned on, and other transistors are turned off. M1 writes a high voltage signal to the PU, M10 writes a low voltage signal to PD1, and M11 writes a low voltage signal to PD2. This design can reduce the discharge current through M10 and M11 when charging the PU. When the PU is charged to a certain level (usually when the potential of the PU rises to above 2V), M15 is turned on, G01 outputs a low voltage signal, and M7 and M9 are turned on to write low voltage signals to PD1 and PD2.

[0358] In the third display stage S3, M15 is turned on, CLK outputs a high voltage signal, M15 is turned on, M7 and M9 remain on, G01 outputs a high voltage signal, and the potential of PU is further increased under the bootstrap effect of C1;

[0359] In the fourth display stage S4, RST1 provides a high voltage signal, M2 is turned on, a low voltage signal is written to PU, M7 and M9 are turned off, VDDo writes a high voltage to PD1 through M6, VDDe writes a high voltage to PD2 through M8, M4, M5, M13, M14, M16 and M17 are all turned on to continuously reduce noise for PU, CR and G01, the potential of PU is low voltage, and CR and G01 both output low voltage signals;

[0360] In the period after the fourth display stage S4, the potentials of PD1 and PD2 are both high voltages, and M4, M5, M13, M14, M16 and M17 are continuously controlled to be turned on, and noise reduction is continuously performed for PU, CR and G01 until the end of this frame.

[0361] In FIG10 , the second drive control clock signal is labeled CK2, the third drive control clock signal is labeled CK3, and the fourth drive control clock signal is labeled CK4;

[0362] In a specific implementation, when the first-stage driving circuit is electrically connected to CLK in FIG10 , the second-stage driving circuit can be connected to CK2 , the third-stage driving circuit can be connected to CK3 , and the fourth-stage driving circuit can be connected to CK4 ; A is a positive integer;

[0363] The input terminal of the first stage driving circuit is connected to the first starting signal STV1, and the input terminal of the second stage driving circuit is connected to the second starting signal STV2 (STV2 is shown in FIG10 );

[0364] The input terminal of the third-stage driving circuit can be electrically connected to the driving control signal output terminal of the first-stage driving circuit, and the input terminal of the fourth-stage driving circuit can be electrically connected to the driving control signal output terminal of the second-stage driving circuit;

[0365] The first reset terminal of the first stage driving circuit can be electrically connected to the driving control signal output terminal of the third stage driving circuit, and the first reset terminal of the second stage driving circuit can be electrically connected to the driving control signal output terminal of the fourth stage driving circuit.

[0366] In actual operation, the driving module can be electrically connected to eight output clock signal lines, and the odd-level driving circuits included in the driving module are electrically connected to the first output clock signal line, the second output clock signal line, the third output clock signal line and the fourth output clock signal line, respectively, and the even-level driving circuits included in the driving module are electrically connected to the fifth output clock signal line, the sixth output clock signal line, the seventh output clock signal line and the eighth output clock signal line, respectively.

[0367] In at least one embodiment of the present disclosure, the driving circuit includes an input terminal and a driving control signal output terminal;

[0368] The input terminal of the B-th level driving circuit is electrically connected to the driving control signal output terminal of the B-2-th level driving circuit, and the reset terminal of the A-th level driving circuit is electrically connected to the driving control signal output terminal of the A+2-th level driving circuit.

[0369] A is a positive integer, B is an integer greater than 2;

[0370] The input end of the first-stage driving circuit is connected to the first starting signal, and the input end of the second-stage driving circuit is connected to the second starting signal.

[0371] The display substrate described in the embodiment of the present disclosure includes a base substrate and a plurality of stages of the above-mentioned driving circuits arranged on the base substrate.

[0372] In at least one embodiment of the present disclosure, the display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit;

[0373] The multi-channel output circuit and the drive control signal generating circuit are arranged in the peripheral area;

[0374] The multi-channel output circuit is arranged on a side of the driving control signal generating circuit close to the display area.

[0375] In a specific implementation, the driving circuit can be arranged in the peripheral area, and the multi-channel output circuit is arranged on the side of the driving control signal generating circuit close to the display area, so that the driving signal output ends respectively included in the multi-channel output circuit are electrically connected to each row gate line in the display area.

[0376] Optionally, the multi-channel output circuit includes N output sub-circuits and N output clock signal lines; N is an integer greater than 1;

[0377] The output clock signal line is arranged on a side of the output sub-circuit close to the display area, and the output clock signal line extends along a first direction.

[0378] In a specific implementation, each of the output clock signal lines is arranged on a side of the output sub-circuit close to the display area, which is beneficial to reducing the crossover distance between the output sub-circuit and the output clock signal line, thereby saving space.

[0379] Optionally, the nth output subcircuit includes an nth control unit and an nth output unit; n is a positive integer less than or equal to N;

[0380] The nth control unit is disposed on a side of the nth output unit away from the display area.

[0381] In a specific implementation, the nth output sub-circuit may include an nth control unit and an nth output unit, and the nth control unit may be arranged on a side of the nth output unit away from the display area.

[0382] Optionally, the active pattern of the transistor included in the nth control unit includes at least one active portion independent of each other, and the active pattern of the transistor included in the nth output unit includes at least one active portion independent of each other.

[0383] In at least one embodiment of the present disclosure, the extension direction of part of the active portion and the extension direction of the output clock signal line may both be a first direction. For example, the first direction may be vertical, but is not limited thereto.

[0384] Optionally, the active layer pattern of at least one transistor included in the driving circuit may include at least two active pattern portions extending along the first direction;

[0385] A distance between two adjacent active pattern portions in the fourth direction is greater than a first predetermined distance.

[0386] Optionally, the first direction may be a vertical direction, and the fourth direction may be a horizontal direction.

[0387] For example, the first predetermined distance may be 3 μm, but is not limited thereto.

[0388] In at least one embodiment of the present disclosure, the active layer pattern of the transistor in the driver circuit can be a long, vertically extending strip, facilitating a narrow bezel. If a narrow bezel is not required, the transistor active layer pattern can include at least two vertically extending active pattern portions, with the horizontal distance between each two adjacent active pattern portions being greater than or equal to 3 μm, to facilitate heat dissipation and improve transistor performance.

[0389] Optionally, the nth output sub-circuit includes an nth shutdown reset unit, an nth output capacitor and an nth output pull-down unit;

[0390] The nth output pull-down unit is provided between the nth shutdown reset unit and the nth output capacitor;

[0391] The nth output capacitor is provided between the nth output unit and the nth output pull-down unit;

[0392] The output capacitors respectively included in the N output sub-circuits are arranged along a first direction;

[0393] Active layer patterns of transistors in the shutdown reset units included in the N output sub-circuits are arranged along a first direction;

[0394] Active layer patterns of transistors in output pull-down units included in the N output sub-circuits are arranged along a first direction.

[0395] In a specific implementation, the nth output sub-circuit may include an nth shutdown reset unit, an nth output capacitor and an nth output pull-down unit. The nth output pull-down unit may be arranged between the nth shutdown reset unit and the nth output capacitor. The output capacitors included in the N output sub-circuits may be arranged along a first direction. The active layer patterns of the transistors in the shutdown reset units included in the N output sub-circuits may be arranged along the first direction. The active layer patterns of the transistors in the output pull-down units included in the N output sub-circuits may be arranged along the first direction.

[0396] The display substrate according to at least one embodiment of the present disclosure further includes a driving control clock signal line, a frame reset line, a first voltage line, a second voltage line, a first control voltage line, and a second control voltage line;

[0397] The driving control clock signal line, the frame reset line, the first voltage line, the second voltage line, the first control voltage line and the second control voltage line are arranged on a side of the driving control signal generating circuit away from the display area.

[0398] In a specific implementation, the drive control clock signal line, the frame reset line, the first voltage line, the second voltage line, the first control voltage line and the second control voltage line included in the display substrate can be arranged on a side of the drive control signal generating circuit away from the display area.

[0399] Optionally, a channel width-to-length ratio of a transistor included in the nth control unit is greater than or equal to 40 and less than or equal to 80;

[0400] The channel width-to-length ratio of the transistor included in the nth output unit is greater than or equal to 100 and less than or equal to 200;

[0401] But it is not limited to this.

[0402] In at least one embodiment of the present disclosure, the semiconductor layer includes a conductive region, a transition region and a channel region, wherein the conductive region is connected to the source and drain of the transistor, the channel region refers to the area of ​​the semiconductor layer that overlaps with the gate when viewed from a top-down perspective, and the transition region is located between the conductive region and the channel region.

[0403] The display substrate according to at least one embodiment of the present disclosure further includes a plurality of rows of gate lines, a plurality of columns of data lines, and a plurality of pixels arranged in the display area;

[0404] The pixel includes M sub-pixels with different colors; M is an integer greater than or equal to 3;

[0405] The sub-pixel includes a switching transistor and a pixel electrode; the pixel electrode includes at least one pixel electrode portion electrically connected to each other;

[0406] The pixel electrode portion extends along the second direction, the gate line extends along the third direction, and the data line extends along the first direction;

[0407] The second direction is substantially the same as the third direction, the first direction intersects the second direction, and the first direction intersects the third direction;

[0408] A row of gate lines is provided between two adjacent rows of sub-pixels, and a column of data lines is provided between two adjacent columns of sub-pixels;

[0409] The gate of the switch transistor is electrically connected to the corresponding gate line, the first electrode of the switch transistor is electrically connected to the pixel electrode, and the second electrode of the switch transistor is electrically connected to the corresponding data line.

[0410] In at least one embodiment of the present disclosure, in the display area, a pixel electrode portion of a pixel electrode included in each sub-pixel extends along a second direction, and the extending direction of the pixel electrode portion is substantially the same as the extending direction of the gate line.

[0411] Existing TDDI (Touch and Display Driver Integration) products have a large number of S-ICs (source drivers), and the price of S-ICs is high, resulting in a high cost for current TDDI products. To address this issue, at least one embodiment of the present disclosure adopts a pixel structure design for a three-gate TDDI display product. In this pixel structure, the pixel electrodes are horizontally arranged, the number of gate lines is three times that of a normal display product, and the number of data lines is one-third of that of a normal display product. This ensures that the number of data lines used is greatly reduced while maintaining the resolution of the display product. At the same time, due to the increase in the number of gate lines, using a gate drive architecture that uses a row of GOA architecture to drive a row of pixels will increase the left and right borders of the display product. Based on this, the embodiments of the present disclosure propose a multiplexed gate drive architecture.

[0412] Optionally, the gate line includes a first end and a second end;

[0413] The driving circuit is electrically connected to the signal input end of the gate line, and is used to provide a driving signal to the gate line through the signal input end; the signal input end is the first end or the second end;

[0414] The display substrate further comprises a plurality of electrostatic discharge blocks provided on the base substrate; the electrostatic discharge blocks are conductive blocks;

[0415] The electrostatic discharge block is electrically connected to an end portion of the gate line except the signal input end portion.

[0416] In a specific implementation, a gate line with a blunt end is designed to reduce discharge at the tip of the gate line end, thereby improving ESD (electrostatic discharge).

[0417] In at least one embodiment of the present disclosure, the driving circuit is electrically connected to the signal input end of the gate line, and a driving signal is provided to the gate line through the signal input end. The display panel is provided with an electrostatic discharge block at the end of the gate line other than the signal input end. The electrostatic discharge block is electrically connected to the end of the gate line other than the signal input end to prevent discharge at the tip end of the gate line.

[0418] Optionally, the electrostatic discharge block and the gate line are provided in the same layer and the same material.

[0419] The electrostatic discharge block may be a conductive block, and the electrostatic discharge block may be provided in the same layer and material as the gate line.

[0420] Optionally, the orthographic projection of the electrostatic discharge block on the substrate may be a square or a rectangle, but is not limited thereto.

[0421] In at least one embodiment of the present disclosure, a length of the electrostatic discharge block along the first direction is greater than a line width of the gate line.

[0422] Optionally, the first direction may be a vertical direction.

[0423] In a specific implementation, the width of the electrostatic discharge block is greater than the line width of the gate line. For example, the line width of the gate line can be 3.5μm, and the side length of the positive projection of the electrostatic discharge block on the substrate can be 18μm. The electrostatic discharge block can prevent discharge at the tip end of the gate line.

[0424] Optionally, the side length of the orthographic projection of the electrostatic discharge block on the base substrate is greater than or equal to 12 μm and less than or equal to 30 μm, and the line width of the gate line is greater than or equal to 3 μm and less than or equal to 4 μm.

[0425] Optionally, a channel width-to-length ratio of the switching transistor is greater than or equal to 0.8 and less than or equal to 2, and a channel length of the switching transistor is greater than or equal to 3 μm and less than or equal to 6 μm.

[0426] In at least one embodiment of the present disclosure, an increase in the line width of the gate line will affect the aperture ratio, and a decrease in the line width of the gate line will increase the gate line resistance, affecting pixel charging. Therefore, in at least one embodiment of the present disclosure, the line width of the gate line is set between 3μm and 4μm, and the channel width-to-length ratio of the thin film transistor in the pixel circuit is 5 / 4. An increase in the channel width of the thin film transistor affects the aperture ratio, and an increase in the channel width of the thin film transistor will reduce the charging rate; an increase in the channel length of the thin film transistor affects the aperture ratio and reduces the charging rate at the same time; a decrease in the channel length of the thin film transistor will have the risk of channel short circuit, and the channel length of the thin film transistor is between 3μm and 6μm.

[0427] The display substrate according to at least one embodiment of the present disclosure further includes a plurality of columns of touch signal lines;

[0428] The touch signal line is arranged between two columns of sub-pixels, and the touch signal line is arranged adjacent to the data line;

[0429] The display substrate further includes a common electrode, and the common electrode includes a plurality of independent common electrode blocks; the pixel electrode is arranged on a side of the common electrode away from the base substrate;

[0430] The touch signal line is electrically connected to the common electrode block through a first via hole.

[0431] In a specific implementation, a column of touch signal lines is provided between two columns of sub-pixels. The touch signal lines are provided adjacent to the data lines. The touch signal lines are electrically connected to the common electrode blocks through first vias. The touch signal lines can be made of a source-drain metal layer.

[0432] Optionally, the touch signal line and the data line are provided in the same layer; the display substrate further comprises a conductive pattern provided in the same layer as the pixel electrode;

[0433] The conductive pattern is electrically connected to the touch signal line and the common electrode block respectively through the first via hole, so that the touch signal line is electrically connected to the common electrode block; the pixel electrode includes a plurality of pixel electrode parts;

[0434] The pixel electrode comprises at least one pixel electrode portion and the conductive pattern arranged along a fourth direction;

[0435] A length of the at least one pixel electrode portion along the fourth direction is smaller than a length of pixel electrode portions of the pixel electrode other than the at least one pixel electrode portion along the fourth direction.

[0436] In a specific implementation, since the conductive pattern can be in the same layer as the pixel electrode, in order to set the conductive pattern, the length of at least one pixel electrode portion along the fourth direction can be smaller than the length of the pixel electrode portion other than the at least one pixel electrode portion included in the pixel electrode along the fourth direction, so as to set the conductive pattern around the pixel electrode having a smaller length along the fourth direction.

[0437] Optionally, the fourth direction may be a horizontal direction.

[0438] In at least one embodiment of the present disclosure, the first via hole includes a first via hole portion and a second via hole portion, and the touch signal line, the common electrode block, and the conductive pattern are sequentially arranged in a direction away from the base substrate;

[0439] The conductive pattern is electrically connected to the touch signal line through the first via portion, and the conductive pattern is electrically connected to the common electrode block through the second via portion.

[0440] Optionally, the touch signal line is formed in a source-drain metal layer, the common electrode block is formed in a first conductive layer, and the pixel electrode is formed in a second conductive layer;

[0441] The source / drain metal layer, the first conductive layer, and the second conductive layer are sequentially arranged along a side away from the display substrate.

[0442] The display substrate according to at least one embodiment of the present disclosure further includes a virtual sub-pixel;

[0443] The virtual sub-pixel is arranged in the peripheral area, and the virtual sub-pixel is arranged adjacent to the display area;

[0444] The length of the virtual sub-pixel along the fourth direction is smaller than the length of the sub-pixel along the fourth direction.

[0445] In a specific implementation, virtual sub-pixels are provided around the display area, and the length of the virtual sub-pixels along the third direction may be smaller than the length of the normal sub-pixels along the fourth direction.

[0446] 11A and 11B are layout diagrams of at least one embodiment of the driving circuit shown in FIG. 9 .

[0447] FIG12 is a layout diagram of the gate metal layer in FIG11A , FIG13A is a layout diagram of the semiconductor layer in FIG11A , and FIG13B is a layout diagram of the source / drain metal layer in FIG11A .

[0448] In Figure 11A, CLK1 is the first clock signal line, CLK3 is the third clock signal line, VGL1 is the first first low voltage line, VGL2 is the second first low voltage line, LVGL is the second low voltage line, HC1 is the first output clock signal line, HC2 is the second output clock signal line, HC3 is the third output clock signal line, HC4 is the fourth output clock signal line, VDDo is the first control voltage line, and VDDe is the second control voltage line.

[0449] In FIG12 , the first clock signal line portion included in the first clock signal line is labeled CLK11 , and the first clock signal line portion included in the third clock signal line is labeled CLK31 ;

[0450] In Figure 13B , the second clock signal line portion of the first clock signal line is labeled CLK12, and the second clock signal line portion of the third clock signal line is labeled CLK32. As shown in Figures 11A-13B , the orthographic projections of CLK11 and CLK12 on the substrate at least partially overlap, and the orthographic projections of CLK21 and CLK22 on the substrate at least partially overlap. CLK11, CLK12, CLK21, and CLK22 all extend vertically.

[0451] In FIG12 , the first electrode plate labeled CO11 is CO1, the first electrode plate labeled CO21 is CO2, the first electrode plate labeled CO31 is CO3, and the first electrode plate labeled CO41 is CO4;

[0452] In FIG13B , CO12 is the second electrode plate of CO1 , CO22 is the second electrode plate of CO2 , CO32 is the second electrode plate of CO3 , and CO42 is the second electrode plate of CO4 .

[0453] In Figure 12, the gate labeled G12 is M12, the gate labeled G15 is M15, the gate labeled GC11 is MC11, the gate labeled GC12 is MC12, the gate labeled GC21 is MC21, the gate labeled GC22 is MC12, the gate labeled GC31 is MC31, the gate labeled GC32 is MC32, the gate labeled GC41 is MC41, and the gate labeled GC42 is MC12.

[0454] As shown in Figure 12, a hollow structure is provided on G12, G15, GC11, GC12, GC21, GC22, GC31, GC32, GC41 and GC42 to facilitate heat dissipation. Under the premise that the mobility of the transistor is relatively large, the characteristics of M12, M15, MC11, MC12, MC21, MC22, MC31, MC32, MC41 and MC42 will not produce a large drift, which is beneficial to the output stability of the driving circuit.

[0455] As shown in FIG11A , the capacitors and transistors included in the multi-channel output circuit, and the capacitors and transistors included in the drive control signal generation circuit are all arranged in the peripheral area;

[0456] The capacitors and transistors included in the multi-channel output circuit are arranged on a side of the drive control signal generating circuit close to the display area, that is, on the right side of the drive control signal generating circuit in the display area.

[0457] As shown in FIG11A , the first output clock signal line HC1 , the second output clock signal line HC2 , the third output clock signal line HC3 , and the fourth output clock signal line HC4 may all extend in a vertical direction;

[0458] Each output clock signal line is arranged on a side of the capacitor and transistor included in the output sub-circuit close to the display area.

[0459] As shown in FIG11A , the first output subcircuit includes MO1 , MC11 , MC12 , CO1 , MX11 , MX12 , and MF1 ;

[0460] The second output subcircuit includes MO2, MC21, MC22, CO2, MX21, MX22 and MF2;

[0461] The third output subcircuit includes MO3, MC31, MC32, CO3, MX31, MX32 and MF3;

[0462] The fourth output subcircuit includes MO4, MC41, MC42, CO4, MX41, MX42 and MF4;

[0463] HC1, HC2, HC3 and HC4 are arranged on the side of the first output sub-circuit, the second output sub-circuit, the third output sub-circuit and the fourth output sub-circuit close to the display area, which is beneficial to reducing the crossover distance between the output sub-circuit and the output clock signal line and saving space.

[0464] As shown in FIG11A , MC11 and MC12 are arranged on the side of MO1 away from the display area, MC21 and MC22 are arranged on the side of MO2 away from the display area, MC31 and MC32 are arranged on the side of MO3 away from the display area, and MC41 and MC42 are arranged on the side of MO4 away from the display area.

[0465] As shown in FIG13A , the active pattern of MO1 includes four independent active portions; the active pattern of MO2 includes four independent active portions; the active pattern of MO3 includes four independent active portions; and the active pattern of MO4 includes four independent active portions.

[0466] The first active part of MO1 is labeled PO11, the second active part of MO1 is labeled PO12, the third active part of MO1 is labeled PO13, and the fourth active part of MO1 is labeled PO14; PO11, PO12, PO13 and PO14 are block-shaped active parts;

[0467] The first active part of MO2 is labeled PO21, the second active part of MO2 is labeled PO22, the third active part of MO2 is labeled PO23, and the fourth active part of MO2 is labeled PO24; PO21, PO22, PO23 and PO24 are block-shaped active parts;

[0468] The first active part of MO3 is labeled PO31, the second active part of MO3 is labeled PO32, the third active part of MO3 is labeled PO33, and the fourth active part of MO3 is labeled PO34; PO31, PO32, PO33 and PO34 are block-shaped active parts;

[0469] The first active part of MO4 is labeled PO41, the second active part of MO4 is labeled PO42, the third active part of MO4 is labeled PO43, and the fourth active part of MO4 is labeled PO44; PO41, PO42, PO43 and PO44 are block-shaped active parts;

[0470] The active pattern of MC11 includes four independent active parts, and the active patterns of other control transistors also include four independent active parts;

[0471] The first active portion of MC11 is labeled PC111, the second active portion of MC11 is labeled PC112, the third active portion of MC11 is labeled PC113, and the fourth active portion of MC11 is labeled PC114. PC111, PC112, PC113, and PC114 are block-shaped active portions.

[0472] The active pattern labeled AC12 is MC12, and AC12 includes four independent block-shaped active parts;

[0473] The active pattern of MC21 is labeled AC21, and AC21 includes four independent block-shaped active parts;

[0474] The active pattern of MC22 is labeled AC22, and AC22 includes four independent block-shaped active parts;

[0475] The active pattern labeled AC31 is MC31, and AC31 includes four independent block-shaped active parts;

[0476] The active pattern of MC32 is labeled AC32, and AC32 includes four independent block-shaped active parts;

[0477] The active pattern labeled AC41 is MC41, and AC41 includes four independent block-shaped active parts;

[0478] The active pattern labeled AC42 is MC42, and AC42 includes four independent block-shaped active parts.

[0479] As shown in FIG. 13A , the extension direction of the active portion of each output transistor and the extension direction of each output clock signal line may both be vertical, but the present invention is not limited thereto.

[0480] As shown in FIG. 13A , the distance between adjacent active portions of each output transistor in the horizontal direction may be greater than 3 μm, but is not limited thereto.

[0481] In FIG13A , the active pattern labeled A12 is M12, the active pattern labeled A15 is M15, and A15 includes two strip-shaped active portions extending in the vertical direction;

[0482] The active pattern labeled A1 is M1, and A1 is a strip-shaped active pattern; A1 extends in the vertical direction;

[0483] The active pattern labeled A2 is M2, and A2 is a block active pattern;

[0484] The active pattern labeled A3 is M3, and A3 is a strip-shaped active pattern; A3 extends in the vertical direction;

[0485] The active pattern labeled A4 is M4, and A4 is a strip-shaped active pattern; A4 extends in the vertical direction;

[0486] The active pattern labeled A5 is M5, and A5 is a strip-shaped active pattern; A5 extends in the vertical direction;

[0487] The active pattern labeled A6 is M6, and A6 is a block active pattern;

[0488] The active pattern labeled A7 is M7, and A7 includes two block-shaped independent active parts;

[0489] The active pattern labeled A8 is M8, and A8 is a block active pattern;

[0490] The active pattern labeled A9 is M9, and A9 is a strip-shaped active pattern; A9 extends in the vertical direction;

[0491] The active pattern labeled A10 is M5, and A10 is a strip-shaped active pattern; A10 extends in the vertical direction;

[0492] The active pattern labeled A11 is M11, and A11 is a strip-shaped active pattern; A11 extends in the vertical direction;

[0493] The active pattern labeled A12 is M12, and A12 is a strip-shaped active pattern; A12 extends in the vertical direction;

[0494] The active pattern labeled A13 is M13, and A13 is a strip-shaped active pattern; A13 extends in the vertical direction;

[0495] The active pattern labeled A14 is M14, and A14 is a strip-shaped active pattern; A14 extends in the vertical direction;

[0496] The active pattern labeled A15 is M15, and A15 includes two strip-shaped active portions extending in the vertical direction and being independent of each other;

[0497] The active pattern labeled A16 is M16, and A16 includes two block-shaped independent active parts;

[0498] The active pattern labeled A17 is M17, and A17 includes two block-shaped independent active parts;

[0499] The active pattern labeled A18 is M18, and A18 is a block active pattern;

[0500] AX11 is the active pattern of MX11, AX12 is the active pattern of MX12, AX21 is the active pattern of MX21, AX22 is the active pattern of MX12, AX31 is the active pattern of MX31, AX32 is the active pattern of MX32, AX41 is the active pattern of MX41, AX42 is the active pattern of MX42, and AX11, AX12, AX21, AX22, AX31, AX32, AX41, and AX42 are block active patterns;

[0501] AF1 is an active pattern of MF1, AF2 is an active pattern of MF2, AF3 is an active pattern of MF3, and AF4 is an active pattern of MF4. AF1, AF2, AF3, and AF4 are block active patterns.

[0502] As shown in FIG11A , the first output sub-circuit may include a first shutdown reset transistor MF1 , a first output capacitor CO1 , a first first output pull-down transistor MX11 , a first second output pull-down transistor MX12 , and a first output transistor MO1 ;

[0503] MX11 and MX12 are set between MF1 and CO1; CO1 is set between MO1 and MX11;

[0504] The second output sub-circuit may include a second shutdown reset transistor MF2, a second output capacitor CO2, a second first output pull-down transistor MX21, a second second output pull-down transistor MX22, and a second output transistor MO2;

[0505] MX21 and MX22 are set between MF2 and CO2; CO2 is set between MO2 and MX21;

[0506] The third output sub-circuit may include a third shutdown reset transistor MF3, a third output capacitor CO3, a third first output pull-down transistor MX31, a third second output pull-down transistor MX32 and a third output transistor MO3;

[0507] MX31 and MX32 are set between MF3 and CO3; CO3 is set between MO3 and MX31;

[0508] The fourth output sub-circuit may include a fourth shutdown reset transistor MF4, a fourth output capacitor CO4, a fourth first output pull-down transistor MX41, a fourth second output pull-down transistor MX42, and a fourth output transistor MO4;

[0509] MX41 and MX42 are set between MF4 and CO4; CO4 is set between MO4 and MX41;

[0510] CO1, CO2, CO3 and CO4 are arranged in sequence along the vertical direction;

[0511] The active layer pattern of MF1, the active layer pattern of MF2, the active layer pattern of MF3 and the active layer pattern of MF4 are arranged in sequence along the vertical direction;

[0512] The active layer pattern of MX11, the active layer pattern of MX21, the active layer pattern of MX31, and the active layer pattern of MX41 are arranged in sequence along the vertical direction;

[0513] The active layer pattern of MX12, the active layer pattern of MX22, the active layer pattern of MX32, and the active layer pattern of MX42 are sequentially arranged along the vertical direction.

[0514] In a specific implementation, the output capacitors are arranged in sequence along the vertical direction, the active layer patterns of the shutdown reset transistors are arranged in sequence along the vertical direction, and the active layer patterns of the output pull-down transistors are arranged in sequence along the vertical direction, so as to save horizontal space and achieve a narrow frame.

[0515] As shown in FIG11A and FIG11B , the first clock signal line CLK1, the third clock signal line CLK3, VGL1, TRST, LVGL, VDDo and VDDe are arranged on a side away from the area where the drive control signal generating circuit is located;

[0516] The first clock signal line CLK1 and the third clock signal line CLK3 are driving control clock signal lines.

[0517] In a specific implementation, the odd-numbered driving circuit can be set on the left side of the display area, and the even-numbered driving circuit can be set on the right side of the display area. The driving control clock signal lines of adjacent odd-numbered driving circuits can be the first clock signal line and the third clock signal line, respectively, and the driving control clock signal lines of adjacent even-numbered driving circuits can be the second clock signal line and the fourth clock signal line, respectively.

[0518] In a specific implementation, the channel width-to-length ratio of MC11, the channel width-to-length ratio of MC12, the channel width-to-length ratio of MO21, the channel width-to-length ratio of MO22, the channel width-to-length ratio of MC31, the channel width-to-length ratio of MC32, the channel width-to-length ratio of MO41, and the channel width-to-length ratio of MO42 may all be equal to or equal to 40 and less than or equal to 80;

[0519] The channel width-to-length ratio of MO1, the channel width-to-length ratio of MO2, the channel width-to-length ratio of MO3, and the channel width-to-length ratio of MO4 are all greater than or equal to 100 and less than or equal to 200.

[0520] As shown in FIG14 , the first row of gate lines is labeled G1, the second row of gate lines is labeled G2, the third row of gate lines is labeled G3, the third row of gate lines is labeled G4, and the fourth row of gate lines is labeled G5; the first column of data lines is labeled D1, the second column of data lines is labeled D2, the third column of data lines is labeled D3, and the fourth column of data lines is labeled D4;

[0521] Two adjacent rows of gate lines and two adjacent columns of data lines divide a sub-pixel area, and a sub-pixel is provided in the sub-pixel area;

[0522] In FIG14 , the sub-pixel labeled P0 is a sub-pixel;

[0523] Figure 15 is a layout diagram of the gate metal layer in Figure 14, Figure 16 is a layout diagram of the semiconductor layer in Figure 14, Figure 17 is a layout diagram of the source and drain metal layer in Figure 14, Figure 18 is a layout diagram of the first conductive layer in Figure 14, and Figure 19 is a layout diagram of the second conductive layer in Figure 14.

[0524] In FIG15 , the first row of grid lines is labeled G1, the second row of grid lines is labeled G2, the third row of grid lines is labeled G3, the third row of grid lines is labeled G4, and the fourth row of grid lines is labeled G5;

[0525] In FIG16 , each active pattern is an active layer pattern of each switching transistor.

[0526] As shown in FIG15 , each row of grid lines has a bent structure;

[0527] The first row of gate lines G1, the second row of gate lines G2, the third row of gate lines G3, the fourth row of gate lines G4 and the fifth row of gate lines are in a bent structure;

[0528] Furthermore, each row of gate lines is provided with a protruding block structure for compensation.

[0529] In FIG. 15 , the first protrusion labeled TQ1 is on the first row of gate lines G1 .

[0530] In Figure 17, the data line labeled D1 is the first column, the data line labeled D2 is the second column, the data line labeled D3 is the third column, and the data line labeled D4 is the fourth column; the data line labeled TXL1 is the first touch signal line, the data line labeled TXL2 is the second touch signal line, the data line labeled TXL3 is the third touch signal line, and the data line labeled TXL4 is the fourth touch signal line.

[0531] In FIG18 , the first common electrode block is labeled CM1 , the second common electrode block is labeled CM2 , and each common electrode block is multiplexed as a touch signal line.

[0532] In FIG19 , the pixel electrode is labeled P1 , and the pixel electrode P1 includes five pixel electrode portions electrically connected to each other, and each pixel electrode portion extends along the second direction.

[0533] As shown in Figure 14 , the extension direction of each pixel electrode portion is substantially the same as the extension direction of each gate line. A row of gate lines is provided between two adjacent rows of sub-pixels, and a column of data lines is provided between two adjacent columns of sub-pixels. At least one embodiment of the present disclosure utilizes a triple-gate TDDI display product pixel structure design. In this pixel structure, the pixel electrodes are arranged horizontally, the number of gate lines is tripled, and the number of data lines is one-third of that of a normal display product. This significantly reduces the number of data lines used while maintaining the display product's resolution.

[0534] As shown in FIG17 , in the display area, a first column of data lines D1, a first touch signal line TXL1, a second column of data lines D2, a second touch signal line TXL2, a third column of data lines D3, a third touch signal line TXL3, a fourth column of data lines D4, and a fourth touch signal line TXL4 are provided;

[0535] D1 and TXL1 are adjacent to each other, D2 and TXL2 are adjacent to each other, D3 and TXL3 are adjacent to each other, and D4 and TXL4 are adjacent to each other. D1, TXL1, D2, TXL2, D3, TXL3, D4 and TXL4 all extend in the vertical direction.

[0536] As shown in FIG. 18 , a plurality of openings are provided on the first common electrode block CM1 , and a plurality of openings are provided on the second common electrode block CM2 .

[0537] In FIG. 18 , K1 is the first opening on CM1 .

[0538] As shown in Figure 19, the pixel electrode P1 includes a first pixel electrode portion, a second pixel electrode portion, a third pixel electrode portion, a fourth pixel electrode portion and a fifth pixel electrode portion, which are arranged in sequence from top to bottom and electrically connected to each other and extend in the horizontal direction; the length of the fourth pixel electrode portion along the horizontal direction and the length of the fifth pixel electrode portion along the horizontal direction are shorter to avoid the bending area of ​​the touch signal line.

[0539] FIG. 20 is a layout diagram of the connection between a GOA (Gate On Array, a gate driving circuit disposed on an array substrate) region and a display region in at least one embodiment of the present disclosure.

[0540] In FIG20 , the area labeled A0 is the display area, and the area labeled GA is the GOA area;

[0541] The area labeled DP is where the virtual sub-pixels are set;

[0542] The second row of grid lines is labeled G2, the third row of grid lines is labeled G3, the fourth row of grid lines is labeled G4, the fifth row of grid lines is labeled G5, the sixth row of grid lines is labeled G6, the seventh row of grid lines is labeled G7, the eighth row of grid lines is labeled G8, the ninth row of grid lines is labeled G9, and the tenth row of grid lines is labeled G10;

[0543] Each row of grid lines includes a left end portion and a right end portion;

[0544] The right end of G5, the right end of G6, the right end of G7 and the right end of G8 are signal input ends. The driving circuit is electrically connected to the right end of G5, the right end of G6, the right end of G7 and the right end of G8, and provides a corresponding driving signal to G5 through the right end of G5, provides a corresponding driving signal to G6 through the right end of G6, provides a corresponding driving signal to G7 through the right end of G7, and provides a corresponding driving signal to G8 through the right end of G8;

[0545] The display substrate further includes a first electrostatic discharge block F1, a second electrostatic discharge block F2, a third electrostatic discharge block F3 and a fourth electrostatic discharge block F4 provided on the base substrate;

[0546] F1 is electrically connected to the left end of G5, F2 is electrically connected to the left end of G6, F3 is electrically connected to the left end of G7, and F4 is electrically connected to the left end of G8;

[0547] F1, F2, F3 and F4 can be provided in the same layer and material as the gate line to release static electricity.

[0548] In at least one embodiment shown in FIG. 20 , the left end portion of G2 , the left end portion of G3 , the left end portion of G4 , the left end portion of G9 , and the left end portion of G10 are signal input ends.

[0549] In Figure 20, a square metal block is added to the left end of the fifth row of gate lines G5 to the eighth row of gate lines G8. The longitudinal width of the metal block is greater than the line width of the gate line. The line width of the gate line is 3.5μm. The orthographic projection of the metal block on the substrate is 18μm. The metal block prevents discharge at the tip end of the gate line.

[0550] Figure 21 is a layout diagram of the gate metal layer in Figure 20, Figure 22 is a layout diagram of the semiconductor layer in Figure 20, Figure 23 is a layout diagram of the source and drain metal layer in Figure 20, Figure 24 is a layout diagram of the first conductive layer in Figure 20, and Figure 25 is a layout diagram of the second conductive layer in Figure 20.

[0551] In FIG23 , the line labeled TXL1 is a first touch signal line, the line labeled TXL2 is a second touch signal line, the line labeled D1 is a first column data line, and the line labeled D2 is a second column data line.

[0552] In FIG24 , the common electrode block is labeled CM.

[0553] As shown in FIG25 , the pixel electrode PM in the virtual sub-pixel is labeled, and the pixel electrode P1 in the sub-pixel arranged in the display area A0 is labeled;

[0554] As can be seen from FIG. 25 , the length of the pixel electrode PM in the virtual sub-pixel along the horizontal direction is smaller than the length of the pixel electrode PA in the sub-pixel along the horizontal direction, so as to facilitate the realization of a narrow frame.

[0555] FIG26 is a layout diagram of a partial area in the display area of ​​the display panel;

[0556] Figure 27 is a layout diagram of the gate metal layer in Figure 26, Figure 28 is a layout diagram of the semiconductor layer in Figure 26, Figure 29 is a layout diagram of the source and drain metal layer in Figure 26, Figure 30 is a layout diagram of the first conductive layer in Figure 26, and Figure 31 is a layout diagram of the second conductive layer in Figure 26.

[0557] In FIG26 and FIG27, the first row of gate lines is labeled G1, the second row of gate lines is labeled G2, and the third row of gate lines is labeled G3;

[0558] In FIG29 , the line labeled TXL1 is a first touch signal line, the line labeled TXL2 is a second touch signal line, the line labeled D1 is a first data line, and the line labeled D2 is a second data line;

[0559] In FIG28 , each active pattern is an active layer pattern of each switching transistor.

[0560] In FIG30 , the common electrode block CM is multiplexed as a touch electrode;

[0561] In FIG31 , the pixel electrode is labeled P1, and the conductive pattern is labeled DX;

[0562] The pixel electrode P1 and the conductive pattern DX are provided in the same layer and the same material;

[0563] The pixel electrode P1 includes a first pixel electrode portion B1, a second pixel electrode portion B2, a third pixel electrode portion B3, a fourth pixel electrode portion B4 and a fifth pixel electrode portion B5 which are electrically connected to each other;

[0564] Each pixel electrode portion extends along a second direction, and the extending direction of each pixel electrode portion is substantially the same as the extending direction of each gate line;

[0565] The conductive pattern DX is provided on the right side of B4 and B5;

[0566] The width of B4 in the horizontal direction is smaller than the width of B1 in the horizontal direction, the width of B4 in the horizontal direction is smaller than the width of B2 in the horizontal direction, the width of B4 in the horizontal direction is smaller than the width of B3 in the horizontal direction, the width of B5 in the horizontal direction is smaller than the width of B1 in the horizontal direction, the width of B5 in the horizontal direction is smaller than the width of B2 in the horizontal direction, and the width of B5 in the horizontal direction is smaller than the width of B3 in the horizontal direction; so that the conductive pattern DX can be arranged in the space to the right of B4 and B5;

[0567] As shown in Figure 26, the conductive pattern DX is electrically connected to the first touch signal line TXL1 and the common electrode block CM through the first via hole, so that the first touch signal line TXL1 and the common electrode block CM are electrically connected, so that the touch signal can be provided to the common electrode block CM through the first touch signal line TXL1 during the touch detection time period.

[0568] FIG32 is an enlarged schematic diagram of the first via hole in FIG26 .

[0569] As shown in FIG32 , the conductive pattern includes a first conductive pattern portion DB1 and a second conductive pattern portion DB2 ;

[0570] The first conductive pattern DB1 is electrically connected to the first touch signal line TXL1 through the first via portion disposed on the left side and included in the first via hole;

[0571] The first conductive pattern DB1 is electrically connected to the first touch signal line TXL1 through the first via portion included in the first via hole;

[0572] The second conductive pattern DB2 is electrically connected to the common electrode block CM through the second via portion included in the first via hole;

[0573] The orthographic projection of the conductive pattern DX on the base substrate covers the orthographic projection of the first via hole on the base substrate;

[0574] The first conductive pattern DB1 is formed on the second conductive layer, the first touch signal line TXL1 is formed on the source-drain metal layer, and the common electrode block CM is formed on the first conductive layer; the source-drain metal layer, the first conductive layer, and the second conductive layer are arranged in sequence in a direction away from the base substrate;

[0575] An organic film layer is arranged between the source-drain metal layer and the first conductive layer, and a passivation layer is arranged between the first conductive layer and the second conductive layer.

[0576] In at least one embodiment shown in FIG32 , the first via hole is a half-lapped hole, wherein the first via portion on the left penetrates the passivation layer and the organic film layer to reach the first touch signal line TXL1 on the source / drain metal layer, and the second via portion on the right penetrates the organic film layer to reach the common electrode block CM on the first conductive layer.

[0577] FIG33 is a cross-sectional view taken along line AA′ in FIG32 .

[0578] In a specific implementation, 8Mask can be used to manufacture the display substrate described in at least one embodiment of the present disclosure;

[0579] It can produce a gate metal layer, a semiconductor layer, a gate insulating layer, a source-drain metal layer, a first passivation layer, an organic layer, a first conductive layer, a second passivation layer and a second conductive layer;

[0580] The gate metal layer, the semiconductor layer, the gate insulating layer, the source / drain metal layer, the first passivation layer, the organic layer, the first conductive layer, the second passivation layer, and the second conductive layer may be arranged in sequence in a direction away from the substrate;

[0581] The first passivation layer and the second passivation layer may be formed by etching in one step.

[0582] The semiconductor layer material may include amorphous silicon, polycrystalline silicon, or metal oxide materials. Polycrystalline silicon may include low-temperature polycrystalline silicon (LTPS), and the metal oxide may include one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), and rare earth doped oxide (Ln-OS). The semiconductor layer material may be amorphous, partially crystalline, single crystal, or polycrystalline, and the film layer may be a single layer or multilayer structure.

[0583] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0584] In a specific implementation, in the display device according to at least one embodiment of the present disclosure, the driving module may use a first driving clock signal CK1, a second driving clock signal CK2, a third driving clock signal CK3, a fourth driving clock signal CK4, a fifth driving clock signal CK5, a sixth driving clock signal CK6, a seventh driving clock signal CK7, and an eighth driving clock signal CK8;

[0585] The driving module may be electrically connected to the first output clock signal line HC1, the second output clock signal line HC2, the third output clock signal line HC3, the fourth output clock signal line HC4, the fifth output clock signal line HC5, the sixth output clock signal line HC6, the seventh output clock signal line HC7, the eighth output clock signal line HC8, the ninth output clock signal line HC9, the tenth output clock signal line HC10, the eleventh output clock signal line HC11, and the twelfth output clock signal line HC12;

[0586] Each level of driving circuit can output three levels of driving signals;

[0587] The 6n-5th stage driving circuit is connected to the first driving control clock signal CK1, the 6n-4th stage driving circuit is connected to the second driving control clock signal CK2, the 6n-3th stage driving circuit is connected to the third driving control clock signal CK3, the 6n-2th stage driving circuit is connected to the fourth driving control clock signal CK4, the 6n-1th stage driving circuit is connected to the fifth driving control clock signal CK5, and the 6nth stage driving circuit is connected to the sixth driving control clock signal CK6; n is a positive integer;

[0588] The first-stage driving circuit is electrically connected to HC1, HC2 and HC3 respectively, the second-stage driving circuit is electrically connected to HC4, HC5 and HC6 respectively, the third-stage driving circuit is electrically connected to HC7, HC8 and HC9 respectively, the fourth-stage driving circuit is electrically connected to HC10, HC11 and HC12 respectively, and so on;

[0589] FIG34 is a waveform diagram of CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, a first output clock signal provided by HC1, a second output clock signal provided by HC2, a third output clock signal provided by HC3, a fourth output clock signal provided by HC4, a fifth output clock signal provided by HC5, a sixth output clock signal provided by HC6, a seventh output clock signal provided by HC7, an eighth output clock signal provided by HC8, a ninth output clock signal provided by HC9, a tenth output clock signal provided by HC10, an eleventh output clock signal provided by HC11, and a twelfth output clock signal provided by HC12;

[0590] The odd-numbered driving circuits may be disposed on the left side of the display area, and the even-numbered driving circuits may be disposed on the right side of the display area.

[0591] In a specific implementation, in the display device according to at least one embodiment of the present disclosure, the driving module may use a first driving clock signal CK1, a second driving clock signal CK2, a third driving clock signal CK3, a fourth driving clock signal CK4, a fifth driving clock signal CK5, and a sixth driving clock signal CK6;

[0592] The driving module may be electrically connected to the first output clock signal line HC1, the second output clock signal line HC2, the third output clock signal line HC3, the fourth output clock signal line HC4, the fifth output clock signal line HC5, the sixth output clock signal line HC6, the seventh output clock signal line HC7, the eighth output clock signal line HC8, the ninth output clock signal line HC9, the tenth output clock signal line HC10, the eleventh output clock signal line HC11, and the twelfth output clock signal line HC12;

[0593] Each level of driving circuit can output four levels of driving signals;

[0594] The first-stage driving circuit is electrically connected to HC1, HC2, HC3 and HC4 respectively, the second-stage driving circuit is electrically connected to HC5, HC6, HC7 and HC8 respectively, and the third-stage driving circuit is electrically connected to HC9, HC10, HC11 and HC12 respectively;

[0595] FIG35 is a diagram of CK1, CK2, CK3, CK4, CK5, CK6, a first output clock signal provided by HC1, a second output clock signal provided by HC2, a third output clock signal provided by HC3, a fourth output clock signal provided by HC4, a fifth output clock signal provided by HC5, a sixth output clock signal provided by HC6, a seventh output clock signal provided by HC7, an eighth output clock signal provided by HC8, a ninth output clock signal provided by HC9, a tenth output clock signal provided by HC10, and a fourth output clock signal provided by HC11.

[0596] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A driving circuit, comprising a driving control signal generating circuit and a multi-channel output circuit; the multi-channel output circuit comprises N-level output sub-circuits; N is an integer greater than 1; The drive control signal generating circuit is used to generate a drive control signal, and the drive control signal is output through the drive control signal output terminal; The nth output sub-circuit is electrically connected to the drive control signal output terminal, the control voltage line, the nth control node, the nth output clock signal line and the nth drive signal output terminal respectively. The nth output sub-circuit is used to control the potential of the nth control node according to the drive control signal under the control of the control voltage provided by the control voltage line, and to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output terminal under the control of the potential of the nth control node; n is a positive integer less than or equal to N.

2. The driving circuit according to claim 1, wherein: The nth output subcircuit comprises an nth control unit and an nth output unit; The nth control unit is electrically connected to the drive control signal output terminal, the control voltage line and the nth control node respectively, and is used to control the potential of the nth control node according to the drive control signal under the control of the control voltage; The nth output unit is electrically connected to the nth control node, the nth output clock signal line and the nth drive signal output end respectively, and is used to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output end under the control of the potential of the nth control node.

3. The driving circuit according to claim 2, wherein: The nth control unit comprises an nth first control transistor; a gate of the nth first control transistor is electrically connected to the control voltage line, a first electrode of the nth first control transistor is electrically connected to the drive control signal output terminal, and a second electrode of the nth first control transistor is electrically connected to the nth control node; or, The control voltage line includes a first control voltage line and a second control voltage line, and the nth control unit includes an nth first control transistor and an nth second control transistor; the gate of the nth first control transistor is electrically connected to the first control voltage line, the first electrode of the nth first control transistor is electrically connected to the drive control signal output end, and the second electrode of the nth first control transistor is electrically connected to the nth control node; the gate of the nth second control transistor is electrically connected to the second control voltage line, the first electrode of the nth second control transistor is electrically connected to the drive control signal output end, and the second electrode of the nth second control transistor is electrically connected to the nth control node.

4. The driving circuit according to claim 2, wherein: The nth output unit comprises an nth output transistor; The gate of the nth output transistor is electrically connected to the nth control node, the first electrode of the nth output transistor is electrically connected to the nth output clock signal line, and the second electrode of the nth output transistor is electrically connected to the nth drive signal output terminal.

5. The driving circuit according to claim 2, wherein: The nth output subcircuit further includes an nth shutdown reset unit; The nth shutdown reset unit is electrically connected to the first voltage line and the nth drive signal output terminal respectively, and is used to control the connection or disconnection between the nth drive signal output terminal and the first voltage line under the control of the first voltage signal provided by the first voltage line.

6. The driving circuit according to claim 5, wherein: The nth shutdown reset unit comprises an nth shutdown reset transistor; The gate electrode of the nth shutdown reset transistor and the second electrode of the nth shutdown reset transistor are both electrically connected to the first voltage line, and the first electrode of the nth shutdown reset transistor is electrically connected to the nth driving signal output terminal.

7. The driving circuit according to claim 2, wherein: The nth output subcircuit further includes an nth output capacitor; A first end of the nth output capacitor is electrically connected to the nth control node, and a second end of the nth output capacitor is electrically connected to the nth driving signal output end.

8. The driving circuit according to claim 1, wherein: The nth output subcircuit further includes an nth output pull-down unit; The nth output pull-down unit is electrically connected to the pull-down node, the nth drive signal output terminal and the first voltage line respectively, and is used to control the connection or disconnection between the nth drive signal output terminal and the first voltage line under the control of the potential of the pull-down node.

9. The driving circuit according to claim 8, wherein: The nth output pull-down unit comprises an nth first output pull-down transistor; The gate of the nth first output pull-down transistor is electrically connected to the pull-down node, the first electrode of the nth first output pull-down transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth first output pull-down transistor is electrically connected to the first voltage line; or, The pull-down node includes a first pull-down node and a second pull-down node; the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor; The gate of the nth first output pull-down transistor is electrically connected to the first pull-down node, the first electrode of the nth first output pull-down transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth first output pull-down transistor is electrically connected to the first voltage line; the gate of the nth second output pull-down transistor is electrically connected to the second pull-down node, the first electrode of the nth second output pull-down transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth second output pull-down transistor is electrically connected to the first voltage line.

10. The driving circuit according to any one of claims 1 to 9, wherein: The pull-down node includes a first pull-down node and a second pull-down node; the drive control signal generating circuit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit and a drive control output circuit; The pull-up node control circuit is used to control the potential of the pull-up node; The first pull-down node control circuit is used to control the potential of the first pull-down node under the control of the potential of the pull-up node; The second pull-down node control circuit is used to control the potential of the second pull-down node under the control of the potential of the pull-up node; The drive control output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the drive control signal output terminal, the drive control clock signal line and the first voltage line, respectively, and is used for controlling the drive control clock signal line to be electrically connected to the drive control signal output terminal under the control of the potential of the pull-up node, controlling the drive control signal output terminal to be connected to the first voltage line under the control of the potential of the first pull-down node, and controlling the drive control signal output terminal to be connected to the first voltage line under the control of the potential of the second pull-down node.

11. The driving circuit according to claim 10, wherein: The drive control signal generating circuit further includes a carry output circuit; The carry output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the carry output terminal, the drive control clock signal line and the second voltage line respectively, and is used for controlling the drive control clock signal line to be electrically connected to the carry output terminal under the control of the potential of the pull-up node, controlling the carry output terminal to be connected to the second voltage line under the control of the potential of the first pull-down node, and controlling the carry output terminal to be connected to the second voltage line under the control of the potential of the second pull-down node.

12. The driving circuit according to claim 11, wherein: The pull-up node control circuit is electrically connected to the input terminal, the frame reset line, the first pull-down node, the second pull-down node, the first reset terminal, the pull-up node, and the second voltage line, respectively, and is used to control the potential of the pull-up node under the control of the input signal provided by the input terminal, and control the connection between the pull-up node and the second voltage line under the control of the frame reset signal provided by the frame reset line, control the connection between the pull-up node and the second voltage line under the control of the potential of the first pull-down node, control the connection between the pull-up node and the second voltage line under the control of the potential of the second pull-down node, and control the connection between the pull-up node and the second voltage line under the control of the first reset signal provided by the first reset terminal; The first pull-down node control circuit is electrically connected to the first control voltage line, the first pull-down node, the pull-up node and the second voltage line respectively, and is used to control the potential of the first pull-down node under the control of the first control voltage provided by the first control voltage line and the potential of the pull-up node; The second pull-down node control circuit is electrically connected to the second control voltage line, the second pull-down node, the pull-up node and the second voltage line respectively, and is used to control the potential of the second pull-down node under the control of the second control voltage provided by the second control voltage line and the potential of the pull-up node; The drive control output circuit is also electrically connected to a second reset terminal, and is used to control the connection between the drive control signal output terminal and the first voltage line under the control of a second reset signal provided by the second reset terminal.

13. The driving circuit according to claim 12, wherein: The pull-up node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; The gate of the first transistor and the first electrode of the first transistor are electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the pull-up node; The gate of the second transistor is electrically connected to the first reset terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the second voltage line; The gate of the third transistor is electrically connected to the frame reset line, and the first electrode of the third transistor is electrically connected to the pull-up A node is electrically connected, and a second electrode of the third transistor is electrically connected to the second voltage line; The gate of the fourth transistor is electrically connected to the first pull-down node, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the second voltage line; The gate of the fifth transistor is electrically connected to the second pull-down node, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the second voltage line; The first pull-down node control circuit includes a sixth transistor and a seventh transistor; The gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the first control voltage line, and the second electrode of the sixth transistor is electrically connected to the first pull-down node; The gate of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the second voltage line; The second pull-down node control circuit includes an eighth transistor and a ninth transistor; The gate of the eighth transistor and the first electrode of the eighth transistor are electrically connected to the second control voltage line, and the second electrode of the eighth transistor is electrically connected to the second pull-down node; A gate of the ninth transistor is electrically connected to the pull-up node, a first electrode of the ninth transistor is electrically connected to the second pull-down node, and a second electrode of the ninth transistor is electrically connected to the second voltage line.

14. The driving circuit according to claim 12, wherein: The first pull-down node control circuit further includes a tenth transistor, and the second pull-down node control circuit further includes an eleventh transistor; The gate of the tenth transistor is electrically connected to the input terminal, the first electrode of the tenth transistor is electrically connected to the first pull-down node, and the second electrode of the tenth transistor is electrically connected to the second voltage line; The gate of the eleventh transistor is electrically connected to the input terminal, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line; The carry output circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor; The gate of the twelfth transistor is electrically connected to the pull-up node, the first electrode of the twelfth transistor is electrically connected to the drive control clock signal line, and the second electrode of the twelfth transistor is electrically connected to the carry output terminal; The gate of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry output terminal, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line; The gate of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the carry output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage line; The drive control output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a first capacitor; The gate of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the drive control clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the drive control signal output terminal; The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the first voltage line; The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the first voltage line; The gate of the eighteenth transistor is electrically connected to the second reset terminal, the first electrode of the eighteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first voltage line; The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the drive control signal output terminal.

15. A display substrate, comprising a base substrate and a plurality of driving circuits according to any one of claims 1 to 14 arranged on the base substrate.

16. The display substrate according to claim 15, wherein: The display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit; The multi-channel output circuit and the drive control signal generating circuit are arranged in the peripheral area; The multi-channel output circuit is arranged on a side of the driving control signal generating circuit close to the display area.

17. The display substrate according to claim 16, wherein: The multi-channel output circuit includes N output sub-circuits and N output clock signal lines; N is an integer greater than 1; The output clock signal line is arranged on a side of the output sub-circuit close to the display area, and the output clock signal line extends along a first direction.

18. The display substrate according to claim 17, wherein: The nth output subcircuit comprises an nth control unit and an nth output unit; n is a positive integer less than or equal to N; The nth control unit is disposed on a side of the nth output unit away from the display area.

19. The display substrate according to claim 17, wherein: The active pattern of the transistor included in the n-th control unit includes at least one active portion independent of each other, and the active pattern of the transistor included in the n-th output unit includes at least one active portion independent of each other.

20. The display substrate according to claim 18, wherein: The nth output subcircuit comprises an nth shutdown reset unit, an nth output capacitor and an nth output pull-down unit; The nth output pull-down unit is disposed between the nth shutdown reset unit and the nth output capacitor; The nth output capacitor is disposed between the nth output unit and the nth output pull-down unit; The output capacitors respectively included in the N output sub-circuits are arranged along a first direction; The active layer patterns of transistors in the shutdown reset units included in the N output sub-circuits are arranged along a first direction; Active layer patterns of transistors in output pull-down units included in the N output sub-circuits are arranged along a first direction.

21. The display substrate according to claim 16, wherein: Also includes a drive control clock signal line, a frame reset line, a first voltage line, a second voltage line, a first control voltage line, and a second control voltage line; The driving control clock signal line, the frame reset line, the first voltage line, the second voltage line, the first control voltage line and the second control voltage line are arranged on a side of the driving control signal generating circuit away from a display area.

22. The display substrate according to claim 18, wherein: The channel width-to-length ratio of the transistor included in the nth control unit is greater than or equal to 40 and less than or equal to 80; The channel width-to-length ratio of the transistor included in the nth output unit is greater than or equal to 100 and less than or equal to 200.

23. The display substrate according to any one of claims 16 to 22, wherein: It also includes a plurality of rows of gate lines, a plurality of columns of data lines and a plurality of pixels arranged in the display area; The pixel includes M sub-pixels with different colors; M is an integer greater than or equal to 3; The sub-pixel comprises a switch transistor and a pixel electrode; the pixel electrode comprises at least one pixel electrode portion electrically connected to each other; The pixel electrode portion extends along the second direction, the gate line extends along the third direction, and the data line extends along the first direction; The second direction is substantially the same as the third direction, the first direction intersects the second direction, and the first direction intersects the third direction; A row of gate lines is arranged between two adjacent rows of sub-pixels, and a column of data lines is arranged between two adjacent columns of sub-pixels; The gate of the switch transistor is electrically connected to the corresponding gate line, the first electrode of the switch transistor is electrically connected to the pixel electrode, and the second electrode of the switch transistor is electrically connected to the corresponding data line.

24. The display substrate according to claim 23, wherein: The gate line includes a first end and a second end; The driving circuit is electrically connected to the signal input end of the gate line, and is used to provide a driving signal to the gate line through the signal input end; the signal input end is the first end or the second end; The display substrate further comprises a plurality of electrostatic discharge blocks disposed on the base substrate; the electrostatic discharge blocks are conductive blocks; The electrostatic discharge block is electrically connected to an end portion of the gate line except the signal input end portion.

25. The display substrate according to claim 24, wherein: The electrostatic discharge block and the gate line are arranged in the same layer and made of the same material.

26. The display substrate according to claim 25, wherein: A length of the electrostatic discharge block along the first direction is greater than a line width of the gate line.

27. The display substrate according to claim 26, wherein: The side length of the orthographic projection of the electrostatic discharge block on the base substrate is greater than or equal to 12 μm and less than or equal to 30 μm, and the line width of the gate line is greater than or equal to 3 μm and less than or equal to 4 μm.

28. The display substrate according to claim 23, wherein: A channel width-to-length ratio of the switch transistor is greater than or equal to 0.8 and less than or equal to 2, and a channel length of the switch transistor is greater than or equal to 3 μm and less than or equal to 6 μm.

29. The display substrate according to claim 23, wherein: Also included are multiple columns of touch signal lines; The touch signal line is arranged between two columns of sub-pixels, and the touch signal line is arranged adjacent to the data line; The display substrate further comprises a common electrode, and the common electrode comprises a plurality of common electrode blocks which are independent of each other; the pixel electrode is arranged on a side of the common electrode away from the base substrate; The touch signal line is electrically connected to the common electrode block through a first via hole.

30. The display substrate according to claim 29, wherein: The touch signal line is arranged in the same layer as the data line; the display substrate further comprises a conductive pattern arranged in the same layer as the pixel electrode; The conductive pattern is electrically connected to the touch signal line and the common electrode block respectively through the first via hole, so that the touch signal line is electrically connected to the common electrode block; The pixel electrode includes a plurality of pixel electrode portions; At least one pixel electrode portion included in the pixel electrode is arranged along a fourth direction with the conductive pattern; A length of the at least one pixel electrode portion along the fourth direction is smaller than a length of a pixel electrode portion of the pixel electrode other than the at least one pixel electrode portion along the fourth direction.

31. The display substrate according to claim 30, wherein: The first via hole includes a first via hole portion and a second via hole portion, and the touch signal line, the common electrode block and the conductive pattern are arranged in sequence along a direction away from the base substrate; The conductive pattern is electrically connected to the touch signal line through the first via portion, and the conductive pattern is electrically connected to the common electrode block through the second via portion.

32. The display substrate according to claim 30, wherein: The touch signal line is formed in the source-drain metal layer, the common electrode block is formed in the first conductive layer, and the pixel electrode is formed in the second conductive layer; The source-drain metal layer, the first conductive layer and the second conductive layer are sequentially arranged along a side away from the display substrate.

33. The display substrate according to claim 23, wherein: Also included are virtual sub-pixels; The virtual sub-pixel is arranged in the peripheral area, and the virtual sub-pixel is arranged adjacent to the display area; The length of the virtual sub-pixel along the fourth direction is smaller than the length of the sub-pixel along the fourth direction.

34. A display device comprising the display substrate according to any one of claims 15 to 33.

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