Multilayer ceramic capacitor

Abstract

In order to provide a multilayer ceramic capacitor capable of enlarging the effective area of internal electrodes contributing to capacitance and reducing the manufacturing cost, a first internal electrode layer (16a) and a second internal electrode layer (16b) of the multilayer ceramic capacitor are exposed on a first side surface (12c) and a second side surface (12d) of a multilayer body (12). The first internal electrode layer (16a) has a first region (23a) along the edge of the laminate (12) on the first side surface (12c) side and a second region (25a) along the edge of the laminate (12) on the second side surface (12d) side, the second internal electrode layer (16b) has a third region (23b) along the edge of the laminate (12) on the first side surface (12c) side and a fourth region (25b) along the edge of the laminate (12) on the second side surface (12d) side, and an Ni-Mg-O phase is formed in the first region (23a) to the fourth region (25b).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] In recent years, there is a demand for large-capacitance and small-sized laminated ceramic capacitors. Such laminated ceramic capacitors have, for example, a laminated body formed in a rectangular parallelepiped shape, in which dielectric layers with internal electrodes printed thereon and internal electrodes are alternately laminated, and further, external ceramic layers are laminated on the upper and lower surfaces thereof. Furthermore, the laminated body has external electrodes formed on both end faces.

[0003] Among such laminated ceramic capacitors, there is a laminated ceramic capacitor in which a dielectric layer called a side margin is formed on the side surface in order to prevent the internal electrode from being connected to the external electrode at the side surface of the laminated body.

[0004] Patent Document 1 discloses a method for manufacturing a laminated ceramic capacitor having a side margin as described above. In this manufacturing method, first, ceramic green sheets having conductive films to be internal electrodes formed on their surfaces are stacked to form a mother laminate. Next, the mother laminate is cut so that the conductive films are exposed on the sides where no external electrodes are formed, thereby obtaining laminated small pieces. Then, a ceramic slurry to be the side margin is applied to the internal electrodes exposed on both sides of the cut laminated small pieces.

[0005] Prior Art Literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 61-248413 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] However, in the structure of forming the side margins by applying a ceramic slurry to the internal electrodes exposed on both sides of the cut laminated body small piece as in Patent Document 1, there are the following problems. That is, since the internal electrodes are not arranged in the side margins, the effective area of ​​the internal electrodes is reduced. In addition, the manufacturing cost increases due to the additional process of forming the side margins.

[0010] Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor capable of increasing the effective area of ​​internal electrodes that contribute to the development of electrostatic capacitance and reducing the manufacturing cost.

[0011] Technical solutions to solve problems

[0012] The multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising: a multilayer body including a plurality of stacked dielectric layers, and having a first main surface and a second main surface opposite to each other in a stacking direction of the plurality of dielectric layers, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the stacking direction and the width direction; a first internal electrode layer arranged on the plurality of dielectric layers and exposed at the first end surface; a second internal electrode layer arranged on the plurality of dielectric layers and exposed at the second end surface; a first external electrode including a base electrode layer arranged on the first end surface and a plating layer arranged on the base electrode layer; and a second external electrode including a base electrode layer arranged on the second end surface and a plating layer arranged on the base electrode layer, wherein the first internal electrode layer is exposed at the first side surface and the second side surface, and the second internal electrode layer is exposed at the first side surface and the second side surface.

[0013] According to the multilayer ceramic capacitor of the present invention, the first internal electrode layer is exposed on the first side surface and the second side surface, so that the effective area of ​​the internal electrode layer that contributes to the electrostatic capacitance of the capacitor can be expanded. In addition, since the process of forming the dielectric layer at the end in the width direction can be eliminated, the manufacturing cost of the multilayer ceramic capacitor can be reduced.

[0014] Effects of the Invention

[0015] According to the present invention, in a multilayer ceramic capacitor, it is possible to increase the effective area of ​​the internal electrodes that contribute to the capacitance and reduce the manufacturing cost.

[0016] The above-mentioned object, other objects, features and advantages of the present invention will become more apparent from the following description of the mode for carrying out the invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. 1 is a perspective view showing the appearance of a multilayer ceramic capacitor as an example of the multilayer ceramic capacitor according to the embodiment of the present invention.

[0018] Figure 2 FIG. 1 is a front view showing a multilayer ceramic capacitor as an example of the multilayer ceramic capacitor according to the embodiment of the present invention.

[0019] Figure 3 FIG. 1 is a plan view showing a multilayer ceramic capacitor as an example of the multilayer ceramic capacitor according to the embodiment of the present invention.

[0020] Figure 4 yes Figure 1 Schematic diagram of the cross section at line IV-IV.

[0021] Figure 5 yes Figure 1 Schematic cross-section along the line VV involved.

[0022] Figure 6 yes Figure 4 Schematic cross-sectional view of the line VI-VI involved.

[0023] Figure 7 yes Figure 4 Schematic cross-section at line VII-VII.

[0024] exist Figure 8 (a) shows a structure in which the opposing electrode portion of the internal electrode layer of the multilayer ceramic capacitor according to the embodiment of the present invention is divided into two, Figure 1 (b) is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor according to the present invention, showing a structure in which the opposing electrode portion of the internal electrode layer is divided into three. Figure 1 (c) is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor according to the present invention, showing a structure in which the opposing electrode portion of the internal electrode layer is divided into four. Figure 1 Cross-sectional view at line II-II. DETAILED DESCRIPTION

[0025] Hereinafter, a multilayer ceramic capacitor will be described using this embodiment as an example of the present invention.

[0026] 1. Multilayer ceramic capacitors

[0027] A multilayer ceramic capacitor 10 is described as an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 1 FIG. 1 is a perspective view showing the appearance of a multilayer ceramic capacitor as an example of the multilayer ceramic capacitor according to the embodiment of the present invention. Figure 2 FIG. 1 is a front view showing a multilayer ceramic capacitor as an example of the multilayer ceramic capacitor according to the embodiment of the present invention. Figure 3 FIG. 1 is a plan view showing a multilayer ceramic capacitor as an example of the multilayer ceramic capacitor according to the embodiment of the present invention. Figure 4 yes Figure 1 Schematic diagram of the cross section at line IV-IV. Figure 5 yes Figure 1 Schematic cross-section along the line VV involved. Figure 6 yes Figure 4 Schematic cross-sectional view of the line VI-VI involved. Figure 4 yes Figure 1 Schematic cross-section at line VI-VII.

[0028] The multilayer ceramic capacitor 10 has a laminate 12 and external electrodes 30. The laminate 12 includes an inner layer portion 15a and a first outer layer portion 15b1 and a second outer layer portion 15b2 disposed so as to sandwich the inner layer portion 15a from upper and lower main surfaces. The inner layer portion 15a exhibits capacitance by alternately laminating a plurality of dielectric layers 14 and a plurality of internal electrode layers 16.

[0029] Hereinafter, each structure will be described in the order of the laminated body 12 , the internal electrode layer 16 , and the external electrode 30 .

[0030] (Laminated body)

[0031] The laminate 12 has a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 that are stacked. Furthermore, the laminate 12 includes a first main surface 12a and a second main surface 12b that are opposite to each other in a height direction x that is a stacking direction of the plurality of dielectric layers 14, a first side surface 12c and a second side surface 12d that are opposite to each other in a width direction y that is orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f that are opposite to each other in a length direction z that is orthogonal to the height direction x and the width direction y. In addition, the length direction z may also be defined as an L direction, which is a direction connecting the first end surface 12e and the second end surface 12f. The width direction y may also be defined as a W direction, which is a direction connecting the first side surface 12c and the second side surface 12d. The height direction x may also be defined as a T direction, which is a direction connecting the first main surface 12a and the second main surface 12b.

[0032] The stack 12 is in the shape of a cuboid. The "cuboid" is assumed to include a cuboid with rounded corners and ridges. In addition, the so-called corner is the portion where three adjacent faces of the stack 12 intersect, and the so-called ridge is the portion where two adjacent faces of the stack 12 intersect. That is, the so-called "cuboid" component means all components having a first main face 12a and a second main face 12b, a first side face 12c and a second side face 12d, and a first end face 12e and a second end face 12f.

[0033] Concavities and convexities may be formed partially or entirely on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0034] like Figure 4 as well as Figure 5As shown, the stack 12 has an inner layer portion 15a in which a plurality of internal electrode layers 16 are opposed to each other in the height direction x connecting the first main surface 12a and the second main surface 12b, a first outer layer portion 15b1 formed by a plurality of dielectric layers 14 arranged between the internal electrode layer 16 located closest to the first main surface 12a and the first main surface 12a, and a second outer layer portion 15b2 formed by a plurality of dielectric layers 14 arranged between the internal electrode layer 16 located closest to the second main surface 12b and the second main surface 12b.

[0035] The first outer layer portion 15 b 1 is located on the first principal surface 12 a side of the laminate 12 , and is an aggregate of a plurality of dielectric layers 14 located between the first principal surface 12 a and the internal electrode layer 16 closest to the first principal surface 12 a .

[0036] The second outer layer portion 15 b 2 is located on the second main surface 12 b side of the laminate 12 , and is an aggregate of a plurality of dielectric layers 14 located between the second main surface 12 b and the internal electrode layer 16 closest to the second main surface 12 b .

[0037] Furthermore, a region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the inner layer portion 15a.

[0038] The stack 12 includes an end portion 22 b (L interval) of the stack 12 , which is located between the inner layer portion 15 a and the first end surface 12 e and between the inner layer portion 15 a and the second end surface 12 f and includes an extraction electrode portion of either the first internal electrode layer 16 a or the second internal electrode layer 16 b described below.

[0039] The number of laminated dielectric layers 14 is not particularly limited, but preferably 50 or more and 1000 or less including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of dielectric layer 14 is preferably about 0.5 μm or more and 10 μm or less, for example.

[0040] The dielectric layer 14 can be made of, for example, a dielectric material. For example, a dielectric material containing BaTiO can be used. 3 、CaTiO 3 、SrTiO 3 , or CaZrO 3 In addition, depending on the desired characteristics of the laminate, for example, a material to which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added whose content is less than that of the main component may be used. In particular, in the present embodiment, as an additive to the dielectric layer 14, Mg as a single substance or a compound is preferably included. Here, MgO is used.

[0041] (Internal electrode layer)

[0042] like Figure 4 as well as Figure 5 As shown, the internal electrode layer 16 includes a first internal electrode layer 16 a and a second internal electrode layer 16 b. The first internal electrode layer 16 a and the second internal electrode layer 16 b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0043] The first internal electrode layer 16a is arranged on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a and a first extraction electrode portion 20a. The first opposing electrode portion 18a is opposed to the second internal electrode layer 16b. The first extraction electrode portion 20a is located on one end side of the first internal electrode layer 16a and reaches from the first opposing electrode portion 18a to the first end surface 12e of the laminate 12. The end of the first extraction electrode portion 20a is extracted and exposed to the first end surface 12e. In detail, the end of the first extraction electrode portion 20a is slightly retreated from the second end surface 12f.

[0044] The shape of the first counter electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably a rectangular shape in plan view. However, the corners may be rounded or inclined (tapered) in plan view.

[0045] The shape of the first lead electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but is preferably a rectangular shape in a plan view. However, the corners may be rounded in a plan view or may be formed to be inclined (tapered) in a plan view. In addition, the shape may be a tapered shape that is inclined toward a certain direction in a plan view.

[0046] The second internal electrode layer 16b is arranged on the surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is arranged. The second internal electrode layer 16b has a second opposing electrode portion 18b and a second extraction electrode portion 20b. The second opposing electrode portion 18b is opposed to the first internal electrode layer 16a. The second extraction electrode portion 20b is located on one end side of the second internal electrode layer 16b and reaches from the second opposing electrode portion 18b to the second end face 12f of the laminate 12. The end of the second extraction electrode portion 20b is extracted and exposed to the second end face 12f. Specifically, the end of the second extraction electrode portion 20b is slightly retracted from the first end face 12e.

[0047] The shape of the second counter electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably a rectangular shape in plan view. However, the corners may be rounded or inclined (tapered) in plan view.

[0048] The shape of the second lead electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably a rectangular shape in a plan view. However, the corners may be rounded in a plan view or may be formed to be inclined (tapered) in a plan view. In addition, the shape may be a tapered shape that is inclined toward a certain direction in a plan view.

[0049] In the present embodiment, the first counter electrode portion 18a of the first internal electrode layer 16a and the second counter electrode portion 18b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0050] The number of the stacked internal electrode layers 16 is not particularly limited, but is preferably 50 or more and 1000 or less. The thickness of the internal electrode layer 16 is preferably about 0.2 μm or more and 2.0 μm or less.

[0051] Furthermore, in the present embodiment, the first internal electrode layer 16 a and the second internal electrode layer 16 b of the internal electrode layer 16 are exposed on the first side surface 12 c and the second side surface 12 d of the laminate 12 .

[0052] Specifically, Figure 5 as well as Figure 6 As shown, in the first internal electrode layer 16a, the first edge 16a1, which is one of the two edges along the width direction y, is led out to the first side surface 12c and exposed. In the first internal electrode layer 16a, the second edge 16a2, which is the other of the two edges along the width direction y, is led out to the second side surface 12d and exposed.

[0053] like Figure 5 as well as Figure 7 As shown, in the second internal electrode layer 16b, the third edge 16b1, which is one of the two edges along the width direction y, is led out to the first side surface 12c and exposed. In the second internal electrode layer 16b, the fourth edge 16b2, which is the other of the two edges along the width direction y, is led out to the second side surface 12d and exposed.

[0054] In this way, the first internal electrode layer 16a and the second internal electrode layer 16b are exposed on the first side surface 12c and the second side surface 12d in the laminate 12. Thus, the effective area of ​​the internal electrode that contributes to the capacitance can be expanded. In addition, the step of forming a dielectric layer on the side end side in the width direction y where the first side surface 12c and the second side surface 12d are located can be omitted, and the manufacturing cost can be reduced.

[0055] The internal electrode layer 16 can be made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag-Pd alloy. In particular, in the present embodiment, it is preferred that at least Ni is contained.

[0056] Furthermore, in the present embodiment, it is preferable that an insulating Ni—Mg—O phase is formed in the region of the internal electrode layer 16 along the exposed portion of each of the first side surface 12 c and the second side surface 12 d of the laminate 12 .

[0057] Specifically, in particular, Figure 5 , Figure 6 As shown, the first internal electrode layer 16a has a first region 23a along a first edge 16a1 on the first side surface 12c and a second region 25a along a second edge 16a2 on the second side surface 12d. Ni-Mg-O phases are arranged in the first region 23a and the second region 25a.

[0058] In particular, Figure 5 , Figure 7 As shown, the second internal electrode layer 16b has a third region 23b along the third edge 16b1 on the first side surface 12c and a fourth region 25b along the fourth edge 16b2 on the second side surface 12d. Ni-Mg-O phases are arranged in the third region 23b and the fourth region 25b.

[0059] Thus, the insulation of the exposed portions of the first side surface 12c and the second side surface 12d of the first internal electrode layer 16a can be ensured. In addition, the insulation of the exposed portions of the first side surface 12c and the second side surface 12d of the second internal electrode layer 16b can be ensured.

[0060] In addition, Mg is contained as an additive in the ceramics as the raw material of the dielectric layer 14, and Ni is contained as the raw material of the internal electrode layer 16. Therefore, when the laminated body 12 is fired, in the first region 23a and the second region 25a of the first internal electrode layer 16a, NiO generated on the internal electrode layer 16 side and MgO contained in the dielectric layer 14 are solid-dissolved. Similarly, in the third region 23b and the fourth region 25b of the second internal electrode layer 16b, NiO and MgO are solid-dissolved. As a result, Ni-Mg-O phases are arranged in the first region 23a, the second region 25a, the third region 23b, and the fourth region 25b.

[0061] In addition, although the oxide NiO generated when the stack 12 is fired also has insulating properties, it is advantageous to configure the Ni-Mg-O phase from the following aspects. That is, the Ni-Mg-O phase is a solid solution, and once formed, it cannot be restored to its original state through redox reaction. On the other hand, NiO is restored to a single substance of Ni in a reducing atmosphere. As such, the Ni-Mg-O phase has a high chemical stability compared to NiO, and therefore the insulating properties of the exposed portions of the internal electrode layer 16 in the first side 12c and the second side 12d of the stack 12 can be ensured with high reliability.

[0062] The presence or absence of the Ni-Mg-O phase in the first region 23a, the second region 25a, the third region 23b, and the fourth region 25b can be analyzed by FE-WDX. In general, in SEM observation, it can also be identified from two images, a secondary electron image and a reflected electron image.

[0063] In the first internal electrode layer 16 a , the dimension WE1 of the first region 23 a in the width direction y and the dimension WE2 of the second region 25 a in the width direction y (ie, the dimension in the width direction y) are preferably 5 μm or more and 50 μm or less.

[0064] In the second internal electrode layer 16 b , the dimension WE3 of the third region 23 b in the width direction y and the dimension WE4 of the fourth region 25 b in the width direction y (ie, the dimension in the width direction y) are preferably 5 μm or more and 50 μm or less.

[0065] This is based on the following reasons. That is, if the dimensions WE1 to WE4 in the width direction y are less than 5 μm, the insulation of each region cannot be ensured. On the other hand, if the dimensions WE1 to WE4 in the width direction y become larger than 50 μm, the effective area of ​​the internal electrode that contributes to the appearance of electrostatic capacitance becomes smaller. Specifically, the insulating region (W gap) between the inner layer portion 15a and the first side surface 12c and between the inner layer portion 15a and the second side surface 12d becomes larger.

[0066] The coverage K1 of the first internal electrode layer 16a to the dielectric layer 14 in the first region 23a and the second region 25a is preferably greater than that in the central portion C in the width direction y of the laminate 12. 1 The coverage K2 of the first internal electrode layer 16a to the dielectric layer 14 is low. 1 , refers to a region sandwiched between the first region 23a and the second region 25a in the width direction y of the first internal electrode layer 16a.

[0067] The coverage K3 of the second internal electrode layer 16b to the dielectric layer 14 in the third region 23b and the fourth region 25b is preferably greater than that in the central portion C in the width direction y of the laminate 12. 2 The coverage K4 of the second internal electrode layer 16b to the dielectric layer 14 is low. 2 , refers to a region sandwiched between the third region 23b and the fourth region 25b in the width direction y of the second internal electrode layer 16b.

[0068] Thus, the size of the W spacer is substantially reduced, and the effect of ensuring insulation in each region can be further enhanced.

[0069] Preferably, the coverage K1 is 40% to 70%, and the coverage K3 is 40% to 70%. If the coverage K1 and K3 are less than 40%, microcracks are generated in the laminate 12 due to the volume expansion of the Ni-Mg-O phase, and the defective rate in the moisture resistance test increases. On the other hand, if the coverage K1 and K3 are greater than 70%, the proportion of the Ni-Mg-O phase in each region decreases, the insulation decreases, and the short circuit defect rate increases.

[0070] Here, generally, the coverage of the internal electrode layer 16 in the dielectric layer 14 is measured as follows. That is, the internal electrode layer 16 and the dielectric layer 14 located in the center of the laminate 12 in the T direction are peeled off by electric field peeling or the like. Next, the center (the position of 1 / 2 in the W direction and 1 / 2 in the L direction) of the exposed internal electrode layer 16 is observed at a magnification of about 100 times using a microscope. Then, by analyzing the obtained image, the ratio of the area occupied by the internal electrode layer 16 in the exposed portion is obtained as the coverage.

[0071] in addition, Figure 1 The stacked body 12 shown may also be configured as follows: Figure 8 As shown, in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, a floating internal electrode layer 16c that is not led out to either the first end face 12e or the second end face 12f is provided, and the opposing electrode portion 26c is divided into a plurality of portions by the floating internal electrode layer 16c. Figure 8 The two links shown in (a) Figure 8 The 3-link shown in (b) Figure 8It is self-evident that the 4-connected structure shown in (c) can also be a structure of more than 4 connections. In this way, by setting the structure of dividing the opposing electrode portion 26c into multiple parts, a structure is formed as follows, that is, a plurality of capacitor components are formed between the opposing first internal electrode layer 16a, the second internal electrode layer 16b, and the floating internal electrode layer 16c, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the high withstand voltage of the stacked ceramic capacitor 10 can be sought.

[0072] In addition, the floating internal electrode layer 16c, like the first internal electrode layer 16a and the second internal electrode layer 16b, can be formed of an appropriate conductive material such as metals such as Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals such as Ag-Pd alloy.

[0073] like Figures 1 to 3 As shown in FIG. 1 , external electrodes 30 are arranged on the first end surface 12 e side and the second end surface 12 f side of the stacked body 12 .

[0074] The external electrode 30 includes a base electrode layer 32 and a plating layer 34 disposed on the surface of the base electrode layer 32 , and the base electrode layer 32 includes a metal component and glass.

[0075] The external electrode 30 includes a first external electrode 30 a and a second external electrode 30 b .

[0076] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed at least on the surface of the first end surface 12e. In addition, the first external electrode 30a is also extended from the first end surface 12e of the stacked body 12 and is disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 20a of the first internal electrode layer 16a.

[0077] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed at least on the surface of the second end surface 12f. In addition, the second external electrode 30b is also extended from the second end surface 12f of the stacked body 12 and is disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 20b of the second internal electrode layer 16b.

[0078] In the laminate 12, the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b are opposed to each other via the dielectric layer 14, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, showing the characteristics of a capacitor.

[0079] The foundation electrode layer 32 includes a first foundation electrode layer 32 a and a second foundation electrode layer 32 b .

[0080] The first foundation electrode layer 32a is connected to the first internal electrode layer 16a and is arranged on the surface of the first end surface 12e. In addition, the first foundation electrode layer 32a is also extended from the first end surface 12e and is arranged on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the first foundation electrode layer 32a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0081] The second foundation electrode layer 32b is connected to the second internal electrode layer 16b and is arranged on the surface of the second end surface 12f. In addition, the second foundation electrode layer 32b is also extended from the second end surface 12f and arranged on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the second foundation electrode layer 32b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0082] The base electrode layer 32 includes at least one selected from a sintered layer, a conductive resin layer, a thin film layer, and the like.

[0083] Hereinafter, each structure in the case where the base electrode layer 32 is formed as the above-mentioned sintered layer, conductive resin layer, and thin film layer will be described.

[0084] (Situation of burnt layer)

[0085] The sintered layer contains metal components and glass. As the metal component of the sintered layer, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. is included. The sintered layer is a sintered layer in which a conductive paste containing glass and metal is applied to the stacked body and sintered. The sintered layer is formed by simultaneously sintering a stacked chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the stacked chip, but it can also be sintered after the stacked chip having the internal electrode layer 16 and the dielectric layer 14 is sintered. The sintered layer can also be a plurality of layers.

[0086] The thickness of the first foundation electrode layer 32a located at the center of the first end face 12e in the height direction x in the longitudinal direction z connecting the first end face 12e and the second end face 12f is preferably about 10 μm or more and 150 μm or less, for example.

[0087] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center portion of the second foundation electrode layer 32b located at the second end face 12f in the height direction x is preferably about 10 μm or more and 150 μm or less, for example.

[0088] The thickness of the first base electrode layer 32a located on a portion of the first principal surface 12a and the second principal surface 12b in the height direction x connecting the first principal surface 12a and the second principal surface 12b at the center in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably, for example, greater than 10 μm and less than 100 μm.

[0089] In addition, the thickness of the second base electrode layer 32b located on a portion of the first principal surface 12a and the second principal surface 12b in the height direction x connecting the first principal surface 12a and the second end surface 12f at the central portion in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably greater than 10 μm and less than 100 μm.

[0090] The thickness of the first base electrode layer 32a located on a portion of the first side surface 12c and the second side surface 12d in the width direction y connecting the first side surface 12c and the second side surface 12d at the center in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably, for example, greater than 10 μm and less than 100 μm.

[0091] In addition, the thickness of the second base electrode layer 32b located on a portion of the first side surface 12c and the second side surface 12d in the width direction y connecting the first side surface 12c and the second side surface 12d at the center in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably greater than 10 μm and less than 100 μm.

[0092] (Conductive resin layer)

[0093] The conductive resin layer includes a first conductive resin layer and a second conductive resin layer.

[0094] The first conductive resin layer is preferably arranged as the first foundation electrode layer 32a to further cover other layers such as a sintered layer, and the second conductive resin layer is preferably arranged as the second foundation electrode layer 32b to further cover other layers such as a sintered layer.

[0095] Specifically, the first conductive resin layer and the second conductive resin layer are preferably arranged as the first base electrode layer 32a and the second base electrode layer 32b on other layers such as the sintered layer located on the first end face 12e and the second end face 12f, and also reach other layers such as the sintered layer located on the first main face 12a and the second main face 12b and the first side face 12c and the second side face 12d. However, the first conductive resin layer and the second conductive resin layer may also be arranged only on other layers such as the sintered layer located on the first end face 12e and the second end face 12f.

[0096] The thickness of the first conductive resin layer and the second conductive resin layer is preferably about 10 μm or more and 200 μm or less, for example.

[0097] The first conductive resin layer and the second conductive resin layer contain a thermosetting resin and a metal component.

[0098] The first conductive resin layer and the second conductive resin layer contain a thermosetting resin and are therefore more flexible than the base electrode layer 32 formed of, for example, a plated film or a fired product of a conductive paste. Therefore, even when a physical shock or a shock due to a thermal cycle is applied to the multilayer ceramic capacitor 10, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0099] As specific examples of thermosetting resins, various known thermosetting resins such as epoxy resins, phenolic resins, urethane resins, silicone resins, and polyimide resins can be used. Among them, epoxy resins having excellent heat resistance, moisture resistance, and adhesion are particularly suitable.

[0100] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenols, amines, acid anhydrides, and imidazoles can be used as the curing agent for the epoxy resin.

[0101] As the metal contained in the first conductive resin layer and the second conductive resin layer, Ag, Cu, or an alloy thereof can be used. In addition, a metal powder coated with Ag on the surface of the metal powder can be used. When a metal powder coated with Ag on the surface of the metal powder is used, Cu and Ni are preferably used as the metal powder.

[0102] In addition, metal obtained by subjecting Cu to oxidation prevention treatment can also be used. The reason for using the Ag-coated metal is that the metal of the base material can be made cheap while maintaining the above-mentioned characteristics of Ag.

[0103] The metal contained in the first conductive resin layer and the second conductive resin layer preferably accounts for 35 vol % or more and 75 vol % or less relative to the volume of the entire conductive resin.

[0104] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The conductive filler may be spherical, flat, or the like.

[0105] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0106] The metal contained in the first conductive resin layer and the second conductive resin layer mainly bears the electrical conductivity of the conductive resin layer. Specifically, the conductive fillers are in contact with each other, thereby forming an electrical conduction path inside the conductive resin layer.

[0107] The metal contained in the first conductive resin layer and the second conductive resin layer may be a spherical metal, a flat metal, or the like. However, it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0108] The conductive resin layer may be formed directly on the laminate without forming a sintered layer.

[0109] (Thin film layer)

[0110] When the base electrode layer 32 is formed of a thin film layer, the thin film layer is a layer of 10 μm or less in which metal particles are deposited by a thin film forming method such as sputtering or vapor deposition.

[0111] Next, refer to Figure 2 as well as Figure 3 The first plating layer 34 a and the second plating layer 34 b as the plating layer 34 disposed on the base electrode layer 32 will be described.

[0112] The first plating layer 34 a and the second plating layer 34 b include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0113] The first plating layer 34a is arranged so as to completely cover the first foundation electrode layer 32a.

[0114] The second plating layer 34b is arranged so as to completely cover the second foundation electrode layer 32b.

[0115] The first plating layer 34a and the second plating layer 34b may also be formed of a plurality of layers. In this case, the plating layer 34 is preferably a two-layer structure of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 and composed of a Ni plating layer and an upper plating layer (Sn plating layer) formed on the lower plating layer and composed of a Sn plating layer.

[0116] That is, in this case, the first plating layer 34 a includes a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer.

[0117] Furthermore, the second plating layer 34 b includes a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0118] The lower plating layer composed of Ni plating is used to prevent the base electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer composed of Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting.

[0119] The thickness of each of the lower plating layer and the upper plating layer is preferably 1.0 μm or more and 15.0 μm or less.

[0120] The dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b in the length direction z is set to L dimension, the dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b in the height direction x is set to T dimension, and the dimension of the multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b in the width direction y is set to W dimension.

[0121] Regarding the dimensions of the multilayer ceramic capacitor 10, the L dimension in the length direction z is greater than or equal to 0.2 mm and less than or equal to 10.0 mm, the W dimension in the width direction y is greater than or equal to 0.1 mm and less than or equal to 10.0 mm, and the T dimension in the height direction x is greater than or equal to 0.1 mm and less than or equal to 5.0 mm. In addition, the dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0122] exist Figure 1In the multilayer ceramic capacitor 10 according to the embodiment shown, the first internal electrode layer 16a and the second internal electrode layer 16a of the internal electrode layer 16 are exposed at the first side surface 12c and the second side surface 12d of the laminate 12, respectively. As a result, in the multilayer ceramic capacitor 10, the effective area of ​​the internal electrode that contributes to the capacitance can be increased. In addition, the step of forming a dielectric layer on the side end side in the width direction y where the first side surface 12c and the second side surface 12d are located can be omitted, and the manufacturing cost of the multilayer ceramic capacitor 10 can be reduced.

[0123] Furthermore, in the multilayer ceramic capacitor 10, an insulating Ni-Mg-O phase is preferably formed in the first region 23a of the internal electrode layer 16 along the first edge 16a1 on the first side surface 12c side of the multilayer body 12, the second region 25a along the second edge 16a2 on the second side surface 12d side of the multilayer body 12, the third region 23b along the third edge 16b1 on the first side surface 12c side of the multilayer body 12, and the fourth region 25b along the fourth edge 16b2 on the second side surface 12d side of the multilayer body 12. Thus, the insulation of the exposed portions of the first side surface 12c and the second side surface 12d of the first internal electrode layer 16a and the exposed portions of the first side surface 12c and the second side surface 12d of the second internal electrode layer 16b can be ensured.

[0124] Furthermore, in the first internal electrode layer 16a of the multilayer ceramic capacitor 10, the dimension WE1 of the first region 23a in the width direction y and the dimension WE2 of the second region 25a in the width direction y (i.e., the dimension in the width direction y) are preferably 5 μm or more and 50 μm or less. In addition, in the second internal electrode layer 16b, the dimension WE3 of the third region 23b in the width direction y and the dimension WE4 of the fourth region 25b in the width direction y are preferably 5 μm or more and 50 μm or less.

[0125] Furthermore, in the multilayer ceramic capacitor 10, the coverage K1 of the first internal electrode layer 16a to the dielectric layer 14 in the first region 23a and the second region 25a is preferably greater than that in the central portion C in the width direction y of the multilayer body 12. 1 The coverage K2 of the first internal electrode layer 16a to the dielectric layer 14 is lower in the third region 23b and the fourth region 25b. In addition, the coverage K3 of the second internal electrode layer 16b to the dielectric layer 14 is preferably lower than that of the central portion C in the width direction y of the laminate 12. 2 The coverage K4 of the second internal electrode layer 16b to the dielectric layer 14 is low. As a result, the size of the W interval is substantially reduced, and the effect of ensuring insulation in each region can be further enhanced.

[0126] Furthermore, in the multilayer ceramic capacitor 10 , preferably, the coverage ratio K1 is 40% to 70%, and the coverage ratio K3 is 40% to 70%.

[0127] 2. Manufacturing method of multilayer ceramic capacitor

[0128] Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0129] (1) Preparing a conductive paste for a dielectric sheet and an internal electrode layer The conductive paste for a dielectric sheet and an internal electrode layer contains a binder (eg, a known organic binder) and a solvent (eg, a known organic binder).

[0130] (2) Next, a conductive paste for the internal electrode layer is printed in a strip shape in a given pattern on a dielectric sheet by screen printing, gravure printing, etc., to prepare a dielectric sheet having a first internal electrode pattern corresponding to the first internal electrode layer and a dielectric sheet having a second internal electrode pattern corresponding to the second internal electrode layer. In addition, a dielectric sheet for an outer layer on which the internal electrode pattern is not printed is also prepared.

[0131] (3) A predetermined number of outer layer dielectric sheets on which an internal electrode pattern is not formed are stacked to form a portion to be an outer layer portion, and a dielectric sheet on which a first internal electrode pattern is formed and a dielectric sheet on which a second internal electrode pattern is formed are stacked in sequence with an offset in the width direction (short dimension direction) of the strip-shaped pattern to form a portion to be an inner layer portion.

[0132] (4) Furthermore, a predetermined number of dielectric sheets without internal electrode patterns printed thereon are stacked on the internal electrode patterns corresponding to the internal electrode layers located on the outermost surface of the inner layer portion to form a portion to be the outer layer portion, thereby manufacturing a laminated sheet.

[0133] (5) The laminated sheets are pressed in the lamination direction by isostatic pressing or the like to produce a laminated block.

[0134] (6) Cut the laminated block into a predetermined size to obtain laminated small pieces. At this time, the corners and ridges of the laminated small pieces may be rounded by barrel grinding or the like.

[0135] (7) The stacked small pieces are fired to produce the stacked body 12. The firing temperature depends on the ceramic and the material of the internal electrode layer 16, but is preferably 900° C. or higher and 1400° C. or lower. In particular, by adjusting the oxygen concentration within the range of 900° C. or higher and 1100° C. or lower, a Ni-Mg-O phase can be formed in the regions along the two edges of the internal electrode layer 16 in the width direction y of the stacked body 12 after firing.

[0136] (8) Next, a base electrode layer is formed. The base electrode layer is used as a sintered layer. A conductive paste for the first base electrode layer and a conductive paste for the second base electrode layer, each containing a glass component and a metal component, are prepared.

[0137] (9) For example, a conductive paste is applied to the first end face and the second end face of the laminate 12 by dipping, screen printing, or the like, and then sintered to form the first base electrode layer and the second base electrode layer. The sintering temperature is preferably 700° C. or higher and 900° C. or lower.

[0138] (10) When the base electrode layer is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the calcined layer, or the conductive resin layer may be formed directly on the laminate without forming a calcined layer.

[0139] As a method for forming a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the sintered layer or the laminate 12, and heat-treated at a temperature of 250° C. to 550° C. to heat-cure the resin to form a conductive resin layer. The atmosphere during the heat treatment is preferably N 2 In order to prevent the resin from scattering and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0140] As a method for applying the conductive resin paste, for example, a method of applying the conductive resin paste by squeezing it out from a slit or a roll transfer method can be used.

[0141] (11) Plating is performed on the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surfaces of the first base electrode layer and the second base electrode layer. Specifically, a Ni plating layer is formed on the first base electrode layer and the second base electrode layer, and a Sn plating layer is formed on the Ni plating layer. The Ni plating layer and the Sn plating layer can be formed sequentially by, for example, a barrel plating method.

[0142] As above, make Figure 1 A multilayer ceramic capacitor 10 according to the embodiment shown.

[0143] 3. Experimental Examples

[0144] Next, in order to confirm the effect of the stacked ceramic capacitor involved in the present invention, a stacked ceramic capacitor as a sample was prepared according to the above-mentioned manufacturing method, and an experiment was carried out to confirm the changes in the width direction y from the first region to the fourth region and the changes in insulation and electrostatic capacitance associated with the changes.

[0145] (1) Specifications of samples used in the experiments

[0146] First, according to the manufacturing method of the laminated ceramic capacitor described above, samples of the laminated ceramic capacitors according to Examples 1 to 7 with the following specifications were produced. In addition, regarding the laminated ceramic capacitor according to the comparative example, the laminated ceramic capacitor was fired in the range of 900° C. to 1100° C. in step (7) of the manufacturing method so that the oxygen concentration was lower than that of the experimental example.

[0147] (Specifications of multilayer ceramic capacitors)

[0148] ・Dimensions of multilayer ceramic capacitors (design values): L×W×T=1.17mm×0.68mm×0.68mm

[0149] ·Ceramic material of the main component of the dielectric layer: BaTiO 3

[0150] Capacitance: 22μF

[0151] Internal electrode material: Ni

[0152] · External electrode structure: Conductive metal (Cu) and glass components

[0153] Plating layer

[0154] Forming two layers of Ni plating layer and Sn plating layer

[0155] Ni plating layer thickness: about 3μm

[0156] Sn plating layer thickness: about 5μm

[0157] (2) Evaluation method of insulation properties (IR)

[0158] The insulation properties of the multilayer capacitors were measured using a digital ultra-high resistance / micro-ammeter (5451 manufactured by ADCMT) under the condition of a rated voltage of 6.3V for 1 minute. The criterion for judging the insulation properties (IR) was that Log (IR) was 6.8 or more (150Ω·F), so in consideration of the variation, values ​​below 6.8 were set to ×, values ​​between 6.9 and 7.4 were set to △, and values ​​above 7.5 were set to 0.

[0159] (3) Measurement method of electrostatic capacitance (Cap)

[0160] Regarding the measurement of electrostatic capacitance (Cap), the electrostatic capacitance (C) obtained under the conditions of 120 Hz and 0.5 Vrms was measured using a tester (4278A manufactured by Agilent Technologies). Regarding the judgment criteria of electrostatic capacitance (Cap), 18.7 or more and 25.3 or less was set as 0, 17.6 or more and 18.7 or less was set as △, and 17.6 or less and 25.3 or more was set as ×.

[0161] (4) Results

[0162] Table 1 shows the evaluation and comprehensive evaluation of the insulation properties and electrostatic capacitance of the dielectric layers of the laminated bodies of Examples 1 to 7 and the comparative example.

[0163] [Table 1]

[0164]

[0165] According to Table 1, in each of the samples of Examples 1 to 7, since the internal electrode layer has the first region to the fourth region where the Ni—Mg—O phase is arranged, the samples with ensured insulation properties were obtained.

[0166] In addition, in each sample of Example 2 to Example 5, the length in the width direction y of the first region to the fourth region where the Ni-Mg-O phase is arranged in the internal electrode layer is greater than 5 μm and less than 50 μm, so the measurement result of the insulation property is a better result of greater than 7.5.

[0167] Furthermore, according to each sample of Example 1 to Example 7, it has been confirmed that the smaller the length in the width direction y of the 1st region to the 4th region where the Ni-Mg-O phase is configured in the internal electrode layer, the larger the effective area of ​​the internal electrode layer can be, and the higher the electrostatic capacitance can be.

[0168] On the other hand, in the sample according to the comparative example, although improvement in electrostatic capacitance was observed, insulation properties could not be obtained because the internal electrode layer did not have the first to fourth regions where the Ni—Mg—O phase was arranged.

[0169] According to the above results, in the present invention, if the internal electrode layer has the first to fourth regions in which the Ni-Mg-O phase is arranged, the effective area of ​​the internal electrode contributing to the capacitance can be expanded. In addition, there is the following suggestion, that is, the process of forming the dielectric layer on the side end side in the width direction y where the first side surface and the second side surface are located can be omitted, the manufacturing cost of the laminated ceramic capacitor 10 can be reduced, and the insulation of the exposed portion of the first side surface and the second side surface of the first internal electrode layer and the exposed portion of the first side surface and the second side surface of the second internal electrode layer can be ensured.

[0170] As mentioned above, the embodiments of the present invention are disclosed through the above description, but the present invention is not limited thereto.

[0171] That is, various changes can be added to the above-described embodiments with respect to mechanism, shape, material, number, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these are included in the present invention.

[0172] Description of Reference Numerals

[0173] 10: Multilayer ceramic capacitor;

[0174] 12: laminate;

[0175] 12a: 1st main side;

[0176] 12b: 2nd main side;

[0177] 12c: 1st side;

[0178] 12d: lateral side 2;

[0179] 12e: 1st end surface;

[0180] 12f: 2nd end surface;

[0181] 14: dielectric layer;

[0182] 15a: inner part;

[0183] 15b1: 1st outer part;

[0184] 15b2: 2nd outer part;

[0185] 16: internal electrode layer;

[0186] 16a: first internal electrode layer;

[0187] 16a1: 1st edge;

[0188] 16a2: The second edge;

[0189] 16b: second internal electrode layer;

[0190] 16b1: 3rd edge;

[0191] 16b2: 4th edge;

[0192] 16c: floating internal electrode layer;

[0193] 18a: first opposing electrode portion;

[0194] 18b: second opposing electrode portion;

[0195] 20a: first lead electrode portion;

[0196] 20b: second lead electrode portion;

[0197] 22b: end;

[0198] 23a: Area 1;

[0199] 23b: Area 3;

[0200] 25a: Area 2;

[0201] 25b: Area 4;

[0202] 26c: opposing electrode portion;

[0203] 30: external electrode;

[0204] 30a: 1st external electrode;

[0205] 30b: second external electrode;

[0206] 32: base electrode layer;

[0207] 32a: first base electrode layer;

[0208] 32b: second base electrode layer;

[0209] 34: plating layer;

[0210] 34a: first plating layer;

[0211] 34b: second plating layer;

[0212] x: height direction (stack direction);

[0213] y: width direction;

[0214] z: length direction.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction of the plurality of dielectric layers, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed at the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed at the second end surface; a first external electrode including a base electrode layer disposed on the first end surface and a plating layer disposed on the base electrode layer; and a second external electrode including a base electrode layer disposed on the second end surface and a plating layer disposed on the base electrode layer; in, The first internal electrode layer is exposed on the first side surface and the second side surface, The second internal electrode layer is exposed on the first side surface and the second side surface, The first internal electrode layer has a first region along an edge of the first side surface of the stacked body and a second region along an edge of the second side surface of the stacked body. A Ni-Mg-O phase is formed in the first region and the second region, The second internal electrode layer has a third region along an edge of the stacked body on the first side surface side and a fourth region along an edge of the stacked body on the second side surface side. A Ni—Mg—O phase is formed in the third region and the fourth region.

2. The multilayer ceramic capacitor according to claim 1, wherein The first region and the second region each have a width dimension of 5 μm or more and 50 μm or less. The third region and the fourth region each have a size in the width direction of 5 μm or more and 50 μm or less.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The dielectric layer contains at least Mg.

Images