Display substrate and display device

Abstract

The display substrate comprises a first display area (A1), and the first display area (A1) comprises a plurality of display island areas (A11) and a plurality of light-transmitting areas (A12) which are arranged in an array mode. The first display area (A1) meets at least one of the following conditions: the display island areas (A11) and the light-transmitting areas (A12) are alternately arranged in the row direction, and the display island areas (A11) and the light-transmitting areas (A12) are alternately arranged in the column direction. The display island area (A11) comprises at least one first pixel circuit (11) and at least one first light-emitting element (13), and the at least one first pixel circuit (11) is electrically connected with the at least one first light-emitting element (13) and is configured to drive the at least one first light-emitting element (13) to emit light.

Description

Display substrate and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] In one aspect, this embodiment provides a display substrate comprising a first display area, the first display area comprising a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The first display area satisfies at least one of the following conditions: the display island areas and the light-transmitting areas are alternately arranged in the row direction, and the display island areas and the light-transmitting areas are alternately arranged in the column direction. The display island area comprises at least one first pixel circuit and at least one first light-emitting element, the at least one first pixel circuit being electrically connected to the at least one first light-emitting element and configured to drive the at least one first light-emitting element to emit light.

[0007] In some exemplary embodiments, in the row direction, the display island regions and the light-transmitting regions are alternately arranged and aligned; in the column direction, a plurality of display island regions are continuously and staggeredly arranged, or a plurality of display island regions are continuously and aligned, or the display island regions and the light-transmitting regions are alternately arranged and aligned.

[0008] In some exemplary embodiments, for a column of display islands, the display islands located in odd rows are aligned, and the display islands located in even rows are aligned; adjacent display islands in a column of display islands are staggered.

[0009] In some exemplary embodiments, the display island regions include: a first pixel circuits sequentially arranged along the row direction, where a is an integer greater than 1. A staggered distance between adjacent display island regions in a column of display island regions in the row direction is greater than or equal to a length of one first pixel circuit in the row direction and less than or equal to a-1 first pixel circuits in the row direction.

[0010] In some exemplary embodiments, each display island area located in the jth column has a first edge close to the display island area in the j-1th column and a second edge close to the display island area in the j+1th column in the row direction; the center line of the display island area located in the i-th row and j-th column in the row direction is aligned with the first edge of the display island area located in the i+1-th row and j-th column; the center line of the display island area located in the i+1-th row and j-th column in the row direction is aligned with the second edge of the display island area located in the i-th row and j-th column; wherein i and j are both integers greater than 0.

[0011] In some exemplary embodiments, in the column direction, the light-transmitting region is aligned with a half area of ​​an adjacent display island region.

[0012] In some exemplary embodiments, the multiple display island areas include: multiple first display island areas and multiple second display island areas; the odd-numbered column display island areas include multiple first display island areas arranged in sequence along the column direction, and the even-numbered column display island areas include multiple second display island areas arranged in sequence along the column direction; the arrangement order of the multiple first light-emitting elements included in the first display island areas is different from the arrangement order of the multiple first light-emitting elements included in the second display island areas.

[0013] In some exemplary embodiments, adjacent light-transmitting regions in the column direction are arranged in a staggered manner in the row direction.

[0014] In some exemplary embodiments, a staggered distance between adjacent light-transmitting regions in the column direction in the row direction is greater than or equal to a length of a first pixel circuit in the row direction, and less than or equal to a length of a-1 first pixel circuits in the row direction.

[0015] In some exemplary embodiments, the display island region includes a plurality of first light emitting elements, and the plurality of first light emitting elements in the plurality of display island regions are arranged in the same manner.

[0016] In some exemplary embodiments, the display island regions are arranged alternately with and aligned with the light-transmitting regions in the row direction, and alternately with and aligned with the light-transmitting regions in the column direction. The plurality of display island regions include a plurality of first display island regions and a plurality of second display island regions. The display island regions in odd-numbered columns include a plurality of first display island regions arranged alternately with the light-transmitting regions along the column direction, and the display island regions in even-numbered columns include a plurality of second display island regions arranged alternately with the light-transmitting regions along the column direction. The arrangement order of the plurality of first light-emitting elements included in the first display island regions is different from the arrangement order of the plurality of first light-emitting elements included in the second display island regions.

[0017] In some exemplary embodiments, each display island region includes four first pixel circuits arranged sequentially along a row direction, and four first light-emitting elements electrically connected to the four first pixel circuits in a one-to-one correspondence, wherein the orthographic projection of the first light-emitting element on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit to which it is connected. The four first light-emitting elements include: a first light-emitting element that emits a first color light, a first light-emitting element that emits a second color light, and two first light-emitting elements that emit a third color light. The arrangement order of the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light in the first display island region is opposite to the arrangement order of the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light in the second display island region.

[0018] In some exemplary embodiments, the display islands and the light-transmitting areas are arranged alternately and aligned in the row direction, and alternately and aligned in the column direction. Each display island includes a first pixel circuit and a first light-emitting element. The plurality of display islands include: a plurality of third display islands, a plurality of fourth display islands, and a plurality of fifth display islands. The display islands in odd-numbered rows include: a plurality of third display islands and a plurality of fourth display islands arranged alternately; the display islands in even-numbered rows include: a plurality of fifth display islands. The first light-emitting elements in the third display islands, the fourth display islands, and the fifth display islands emit light of different colors.

[0019] In some exemplary embodiments, the third display island area includes: a first light-emitting element that emits a first color light; the fourth display island area includes: a first light-emitting element that emits a second color light; and the fifth display island area includes: a first light-emitting element that emits a third color light.

[0020] In some exemplary embodiments, the display substrate further includes a second display area located on at least one side of the first display area; wherein the second display area includes at least one second pixel circuit and at least one second light-emitting element, the at least one second pixel circuit being electrically connected to the at least one second light-emitting element and configured to drive the at least one second light-emitting element to emit light. The arrangement density of the first pixel circuits in the first display area is less than the arrangement density of the second pixel circuits in the second display area.

[0021] In some exemplary embodiments, the arrangement density of the first pixel circuits in the first display area in the row direction is 1 / 2 or 1 / 3 of the arrangement density of the second pixel circuits in the second display area in the row direction.

[0022] In some exemplary embodiments, in a direction perpendicular to a display substrate, the display substrate includes: a substrate, and a circuit structure layer and a light-emitting structure layer located on the substrate; the circuit structure layer includes: a plurality of first pixel circuits, each of which includes: at least one first-type transistor, at least one second-type transistor, and a storage capacitor. The circuit structure layer includes at least: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer disposed on the substrate; the first semiconductor layer includes at least: an active layer of the first-type transistor of the first pixel circuit; the first conductive layer includes at least: a gate electrode of the first-type transistor of the first pixel circuit and a first electrode of the storage capacitor; the second conductive layer includes at least: a second electrode of the storage capacitor of the first pixel circuit and a bottom gate of the second-type transistor; the second semiconductor layer includes at least: an active layer of the second-type transistor of the first pixel circuit; the third conductive layer includes at least: a gate electrode of the second-type transistor of the first pixel circuit; and the fourth conductive layer includes at least: a plurality of connection electrodes.

[0023] In some exemplary embodiments, the circuit structure layer further includes: a fifth conductive layer and a sixth conductive layer located on the side of the fourth conductive layer away from the substrate; the fifth conductive layer includes at least: a plurality of data lines; the sixth conductive layer includes at least: a voltage transmission line; or, the fifth conductive layer includes at least: a voltage transmission line, and the sixth conductive layer includes at least: a plurality of data lines.

[0024] In some exemplary embodiments, the circuit structure layer further includes: a shielding layer located on a side of the first semiconductor layer close to the substrate. The shielding layer's orthographic projection on the substrate covers the orthographic projection of the first semiconductor layer on the substrate; alternatively, the shielding layer's orthographic projection on the substrate covers the orthographic projections of the first and second semiconductor layers on the substrate.

[0025] On the other hand, this embodiment provides a display device, comprising the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0026] On the other hand, this embodiment provides a display substrate, comprising: a first display area and a second display area at least located on one side of the first display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area. The first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; the display island areas and the light-transmitting areas are alternately arranged in the row direction, or the display island areas and the light-transmitting areas are alternately arranged in the column direction. The display island areas at least comprise: n first pixel circuits arranged along the row direction, where n is a positive integer greater than 0; the first pixel circuits in adjacent display island areas in the column direction are staggered, and the staggered distance of adjacent display island areas in the row direction is greater than or equal to the length of one first pixel circuit in the row direction and less than or equal to the length of n first pixel circuits in the row direction.

[0027] In some exemplary embodiments, in the column direction, the light-transmitting region is aligned with a half area of ​​an adjacent display island region.

[0028] In some exemplary embodiments, each display island area further includes: n first light-emitting elements electrically connected to the n first pixel circuits in a one-to-one correspondence; the multiple display island areas include: multiple first display island areas and multiple second display island areas; the odd-numbered column display island areas include: multiple first display island areas arranged in sequence along the column direction, and the even-numbered column display island areas include: multiple second display island areas arranged in sequence along the column direction; the arrangement order of the n first light-emitting elements included in the first display island area is different from the arrangement order of the n first light-emitting elements included in the second display island area.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0030] Summary of the Figures

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0032] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0033] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0034] FIG3 is a timing diagram of the operation of the pixel circuit provided in FIG2 ;

[0035] FIG4 is a partial schematic diagram of a second display area according to at least one embodiment of the present disclosure;

[0036] FIG5 is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure;

[0037] FIG6 is a partial schematic diagram of a first pixel circuit and a first light-emitting element in a first display area according to at least one embodiment of the present disclosure;

[0038] FIG7 is a partial top view of the first display area according to at least one embodiment of the present disclosure;

[0039] FIG8A is a schematic diagram of the first display area after the shielding layer is formed in FIG7 ;

[0040] FIG8B is a schematic diagram of a first display island region in FIG8A ;

[0041] FIG9A is a schematic diagram of the first display area after the first semiconductor layer is formed in FIG7 ;

[0042] FIG9B is a schematic diagram of a first display island region in FIG9A ;

[0043] FIG10A is a schematic diagram of the first display area after the first conductive layer is formed in FIG7 ;

[0044] FIG10B is a schematic diagram of the first conductive layer in FIG10A ;

[0045] FIG10C is a schematic diagram of a first display island region in FIG10A;

[0046] FIG11A is a schematic diagram of the first display area after the second conductive layer is formed in FIG7 ;

[0047] FIG11B is a schematic diagram of the second conductive layer in FIG11A ;

[0048] FIG11C is a schematic diagram of a first display island region in FIG11A ;

[0049] FIG12A is a schematic diagram of the first display area after the second semiconductor layer is formed in FIG7;

[0050] FIG12B is a schematic diagram of a first display island region in FIG12A;

[0051] FIG13A is a schematic diagram of the first display area after the third conductive layer is formed in FIG7 ;

[0052] FIG13B is a schematic diagram of the third conductive layer in FIG13A;

[0053] FIG13C is a schematic diagram of a first display island region in FIG13A;

[0054] FIG14 is a schematic diagram of a first display island region after forming a fifth insulating layer in FIG7;

[0055] FIG15A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG7 ;

[0056] FIG15B is a schematic diagram of the fourth conductive layer in FIG15A;

[0057] FIG15C is a schematic diagram of a first display island region in FIG15A;

[0058] FIG16 is a schematic diagram of a first display island region after forming a seventh insulating layer in FIG7;

[0059] FIG17A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG7 ;

[0060] FIG17B is a schematic diagram of the fifth conductive layer in FIG17A;

[0061] FIG17C is a schematic diagram of a first display island region in FIG17A;

[0062] FIG18 is a schematic diagram of a first display island region after the eighth insulating layer is formed in FIG7 ;

[0063] FIG19A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG7 ;

[0064] FIG19B is a schematic diagram of the sixth conductive layer in FIG19A;

[0065] FIG19C is a schematic diagram of a first display island region in FIG19A;

[0066] FIG20 is a schematic diagram of a first display island region after the ninth insulating layer is formed in FIG7 ;

[0067] FIG21 is a schematic diagram of the first display area after the anode layer is formed in FIG7;

[0068] FIG22 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0069] FIG23 is a partial top view of the first display area according to at least one embodiment of the present disclosure;

[0070] FIG24 is a schematic diagram of the first display area after the shielding layer is formed in FIG23;

[0071] FIG25 is a schematic diagram of the first display area after the first semiconductor layer is formed in FIG23;

[0072] FIG26A is a schematic diagram of the first display area after the first conductive layer is formed in FIG23;

[0073] FIG26B is a schematic diagram of the first conductive layer in FIG26A ;

[0074] FIG27A is a schematic diagram of the first display area after the second conductive layer is formed in FIG23;

[0075] FIG27B is a schematic diagram of the second conductive layer in FIG27A;

[0076] FIG28 is a schematic diagram of the first display area after the second semiconductor layer is formed in FIG23;

[0077] FIG29A is a schematic diagram of the first display area after the third conductive layer is formed in FIG23;

[0078] FIG29B is a schematic diagram of the third conductive layer in FIG29A ;

[0079] FIG30A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG23;

[0080] FIG30B is a schematic diagram of the fourth conductive layer in FIG30A ;

[0081] FIG31 is a schematic diagram of the first display area after the seventh insulating layer is formed in FIG23;

[0082] FIG32A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG23;

[0083] FIG32B is a schematic diagram of the fifth conductive layer in FIG32A ;

[0084] FIG33 is a schematic diagram of the first display area after the eighth insulating layer is formed in FIG23;

[0085] FIG34A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG23;

[0086] FIG34B is a schematic diagram of the sixth conductive layer in FIG34A ;

[0087] FIG35 is a schematic diagram of the first display area after the ninth insulating layer is formed in FIG23;

[0088] FIG36 is a schematic diagram of the first display area after the anode layer is formed in FIG23;

[0089] FIG37 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0090] FIG38 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0091] FIG39 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0092] FIG40 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0093] FIG41 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0094] FIG42 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0095] Details

[0096] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0097] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0098] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0099] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0100] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0101] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0102] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0103] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. When using transistors with opposite polarity or when the direction of current changes during circuit operation, the functions of "source" and "drain" are sometimes interchanged. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0104] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0105] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0106] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0107] In this disclosure, the terms "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" can include both completely identical and substantially identical values, and "substantially identical" means values ​​within a 10% difference.

[0108] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0109] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and hollowing out in the screen have appeared one after another. These technologies are achieved by making holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technologies require digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit external method or the pixel circuit internal method is usually adopted in the camera area under the screen.

[0110] The external pixel circuit method involves placing the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area. By separating the light-emitting element and the pixel circuit, the light transmittance of the under-screen camera area is improved. Since the under-screen camera area does not have a pixel circuit, there is no other light-shielding layer in this area except for the anode of the light-emitting element, which can achieve a higher light transmittance. However, under this method, the pixel circuit and the light-emitting element need to be electrically connected via conductive connecting wires. Due to the limited arrangement space of the conductive connecting wires, the size (e.g., aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. Increasing the aperture of the under-screen camera area usually requires increasing the masking process for the conductive connecting wires, resulting in increased costs. Moreover, the conductive connecting wires are usually made of transparent conductive materials, such as indium tin oxide (ITO). Due to the large square resistance of ITO, the conductive connecting wires are loaded heavily, which can easily affect the brightness of the light-emitting element in the under-screen camera area, reducing the brightness of the under-screen camera area, thereby causing poor display in the under-screen camera area, such as vertical display defect (mura). Moreover, the use of conductive connecting wires easily introduces more vias, which in turn reduces the aperture ratio of the under-screen camera area, which is not conducive to optimizing the light transmittance of the under-screen camera area.

[0111] The built-in pixel circuit method involves placing a light-emitting element and the pixel circuit connected to it in the under-screen camera area. Compared to the external pixel circuit method, the built-in method eliminates the need for long conductive wires to connect the pixel circuit and light-emitting element in the under-screen camera area, thus avoiding poor display quality in the under-screen camera area caused by these wires. Furthermore, the built-in method places no restrictions on the size of the under-screen camera area and can support large-aperture under-screen camera areas. However, for complex pixel circuits, due to the numerous wiring patterns, it is difficult to improve the light transmittance of the under-screen camera area by compressing the pixel circuit layout, resulting in an inability to meet the light transmittance requirements for functions such as under-screen video or under-screen facial recognition.

[0112] This embodiment provides a display substrate and a display device, which can improve the light transmittance of the under-screen camera area of ​​a display substrate using a pixel circuit built-in method while meeting the display white balance.

[0113] This embodiment provides a display substrate, comprising: a first display area, the first display area comprising: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The first display area satisfies at least one of the following conditions: the display island areas and the light-transmitting areas are alternately arranged in the row direction, and the display island areas and the light-transmitting areas are alternately arranged in the column direction. The display island area includes at least one first pixel circuit and at least one first light-emitting element, the at least one first pixel circuit being electrically connected to the at least one first light-emitting element and configured to drive the at least one first light-emitting element to emit light.

[0114] In some examples, within the first display area, display island areas and light-transmitting areas may be alternately arranged in the row direction; or, display island areas and light-transmitting areas may be alternately arranged in the column direction; or, display island areas and light-transmitting areas may be alternately arranged in the row direction, and in the column direction, display island areas and light-transmitting areas may be alternately arranged. The row direction may be perpendicular to the column direction.

[0115] In this example, alternating arrangement of A and B in direction C means that A and B are alternately arranged along direction C, that is, they are periodically arranged in AB pattern along direction C. Aligning arrangement of A and B in direction C means that the midlines of A and B in the direction perpendicular to direction C substantially coincide, and the extended edges of A and B substantially coincide. Staggered arrangement of A and B in direction C means that the midlines of A and B in the direction perpendicular to direction C are substantially parallel and do not coincide.

[0116] In some examples, the multiple display island regions in the first display area may have the same shape and size. The multiple light-transmitting regions may have the same shape and size. The light-transmitting regions may be formed by deleting first pixel circuits and first light-emitting elements. The number of first pixel circuits deleted from the light-transmitting regions may be less than or equal to the number of first pixel circuits included in the display island regions.

[0117] In some examples, each display island area may include a first pixel circuit and a first light-emitting element, and the first pixel circuit may be electrically connected to the first light-emitting element to drive the first light-emitting element to emit light. In other examples, each display island area may include multiple first pixel circuits and multiple first light-emitting elements, for example, it may include four first pixel circuits and four first light-emitting elements, or it may include three first pixel circuits and three first light-emitting elements. The multiple first pixel circuits and the multiple first light-emitting elements in each display island area may be electrically connected one-to-one. However, this embodiment is not limited to this. In other examples, in the display island area, the number of first pixel circuits may be less than the number of first light-emitting elements, and at least one first pixel circuit may be electrically connected to multiple first light-emitting elements.

[0118] The display substrate provided in this embodiment adopts a built-in pixel circuit method, and alternately arranges display island areas and light-transmitting areas in the row direction or column direction within the first display area. This can improve the light transmittance of the first display area and realize the under-screen functional requirements while meeting the display white balance. For example, the aperture of the first display area can be expanded and under-screen camera or under-screen face recognition and other functional requirements can be realized simultaneously.

[0119] In some exemplary embodiments, in the row direction, the display island regions and the light-transmitting regions may be arranged alternately and aligned; in the column direction, multiple display island regions may be arranged continuously and staggered, or multiple display island regions may be arranged continuously and aligned, or the display island regions and the light-transmitting regions may be arranged alternately and aligned. The arrangement of the display island regions and the light-transmitting regions in the first display region of this example can help improve the light transmittance of the first display region.

[0120] In some exemplary embodiments, within a column of display islands, the display islands located in odd-numbered rows can be aligned, and the display islands located in even-numbered rows can be aligned. Adjacent display islands within a column can be staggered. In this example, the display islands of the first display area can be arranged continuously in the column direction, with adjacent display islands staggered. This can improve light transmittance in the first display area while ensuring display white balance.

[0121] In this example, odd rows refer to rows with odd row numbers, even rows refer to rows with even row numbers, odd columns refer to columns with odd column numbers, and even columns refer to columns with even column numbers.

[0122] In some exemplary embodiments, the display island area may include: a first pixel circuits arranged in sequence along the row direction, where a is an integer greater than 1. The staggered distance in the row direction between adjacent display island areas in a column of display island areas may be greater than or equal to the length of one first pixel circuit in the row direction and less than or equal to the length of a-1 first pixel circuits in the row direction. For example, the display island area may include: four first pixel circuits arranged in sequence along the row direction. The staggered distance in the row direction between adjacent display island areas in a column of display island areas may be approximately the length of two first pixel circuits in the row direction. The staggered arrangement of the display island areas in this example is conducive to ensuring display white balance.

[0123] In some exemplary embodiments, each display island located in the jth column may have a first edge in the row direction proximate to the display island located in the j-1th column and a second edge in the row direction proximate to the display island located in the j+1th column. The row centerline of the display island located in the i-th row, j-th column may be aligned with the first edge of the display island located in the i+1th row, j-th column; and the row centerline of the display island located in the i+1th row, j-th column may be aligned with the second edge of the display island located in the i-th row, j-th column; where i and j are both integers greater than 0. The staggered arrangement of the display islands in this example facilitates ensuring display white balance.

[0124] In some exemplary embodiments, the display substrate may further include: a second display area located on at least one side of the first display area; wherein the second display area includes: at least one second pixel circuit and at least one second light-emitting element, the at least one second pixel circuit being electrically connected to the at least one second light-emitting element and configured to drive the at least one second light-emitting element to emit light. The arrangement density of the first pixel circuits in the first display area may be less than the arrangement density of the second pixel circuits in the second display area. In some examples, the arrangement density of the first pixel circuits in the row direction in the first display area may be 1 / 2 or 1 / 3 of the arrangement density of the second pixel circuits in the row direction in the second display area. In this example, by deleting the pixel circuits in the first display area, the light transmittance of the first display area can be improved while ensuring the display white balance.

[0125] The solution of this embodiment is illustrated below through some examples.

[0126] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the display substrate may include a display area AA and a peripheral area BB located outside the display area AA. The display area AA of the display substrate may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this.

[0127] In some examples, as shown in Figure 1, the first display area A1 may be a light-transmitting display area, and may also be referred to as an under-screen camera (FDC, Full Display With Camera) area. The second display area A2 may also be referred to as a normal display area. The light transmittance of the first display area A1 is greater than the light transmittance of the second display area A2. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0128] In some examples, as shown in FIG1 , the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other locations, such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0129] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0130] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0131] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0132] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight transistors (i.e., a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data write transistor, the fifth transistor T5 may also be referred to as a first light-emitting control transistor, the sixth transistor T6 may also be referred to as a second light-emitting control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0133] In some examples, the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0134] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0135] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0136] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0137] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0138] FIG3 is an operating timing diagram of the pixel circuit shown in FIG2. The operating process of the pixel circuit shown in FIG2 will be described below with reference to FIG3. In the pixel circuit, the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0139] In some examples, as shown in FIG. 2 and FIG. 3 , during a frame display period, the operation process of the pixel circuit may include at least: a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 .

[0140] The first stage S1 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The eighth transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be supplied to the second node N2. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0141] The second stage S2 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The first transistor T1 and the second transistor T2 are turned on, causing the first initial signal line provided by the first initial signal line INIT1 to be supplied to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0142] The third stage S3 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0143] In the fourth stage S4, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light-emitting element EL to emit light.

[0144] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata]2 ;

[0145] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0146] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0147] FIG4 is a partial schematic diagram of the second display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG1 and FIG4 , the second display area A2 may include: a plurality of second sub-pixels arranged in an array. The plurality of second sub-pixels of the second display area A2 may include: a plurality of second sub-pixels 2a emitting a first color light, a plurality of second sub-pixels 2c emitting a second color light, and a plurality of second sub-pixels 2b and 2d emitting a third color light. In some examples, the first color light may be red light (R), the second color light may be blue light (B), and the third color light may be green light (G). This embodiment is not limited to this.

[0148] In some examples, the plurality of second sub-pixels in the second display area A2 may be arranged in an array along a first direction X and a second direction Y. The plurality of second sub-pixels continuously arranged along the first direction X may be referred to as a row of second sub-pixels, where the first direction X may be parallel to the row direction; the plurality of second sub-pixels continuously arranged along the second direction Y may be referred to as a column of second sub-pixels, where the second direction Y may be parallel to the column direction.

[0149] In some examples, each second sub-pixel may include a second pixel circuit 12 and a second light-emitting element 14 electrically connected to the second pixel circuit 12. The second pixel circuit 12 may be configured to drive the connected second light-emitting element 14 to emit light. The orthographic projection of the second light-emitting element 14 on the substrate may at least partially overlap with the orthographic projection of the connected second pixel circuit 12 on the substrate.

[0150] In some examples, a pixel unit in the second display area A2 may include four second sub-pixels, namely, one second sub-pixel 2a that emits light of the first color, one second sub-pixel 2c that emits light of the second color, and two second sub-pixels 2b and 2d that emit light of the third color. For example, within a single pixel unit, the second sub-pixels 2a, 2b, 2c, and 2d may be arranged sequentially along the first direction X, or the second sub-pixels 2c, 2d, 2a, and 2b may be arranged sequentially along the first direction X.

[0151] In some examples, a plurality of second sub-pixels 2a emitting first color light and a plurality of second sub-pixels 2c emitting second color light can be arranged in a column and alternately arranged along the second direction Y. A plurality of second sub-pixels 2b and 2d emitting third color light can be arranged in a column and alternately arranged along the second direction Y. The plurality of second pixel circuits within the second display area can be arranged continuously in the row direction and the column direction. The second display area is not provided with a light-transmitting area. The light transmittance of the second display area is lower than the light transmittance of the first display area.

[0152] Figure 5 is a partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 6 is a partial schematic diagram of the first pixel circuit and first light-emitting element of the first display area of ​​at least one embodiment of the present disclosure. Figures 5 and 6 illustrate six rows (e.g., rows i through i+5) and three columns (e.g., columns j through j+2) of the display island area. Where i and j are both integers greater than 0.

[0153] In some examples, as shown in Figures 1, 5 and 6, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The display island areas A11 and the light-transmitting areas A12 may be alternately arranged in a first direction X (parallel to the row direction). In the second direction Y (parallel to the column direction), a plurality of display island areas A11 may be arranged continuously. For a column of display island areas, the display island areas A11 located in odd rows may be aligned, the display island areas A11 located in even rows may be aligned, and adjacent display island areas A11 in a column of display island areas may be staggered. The shapes and sizes of the plurality of light-transmitting areas A12 may be substantially the same. The shapes and sizes of the plurality of display island areas A11 may be substantially the same.

[0154] In some examples, the multiple display island areas A11 of the first display area A1 may include: multiple first display island areas A11a and multiple second display island areas A11b. In the first direction X, they may be periodically arranged in the order of the first display island area A11a, the light-transmitting area A12, the second display island area A11b, and the light-transmitting area A12. In each row of display island areas, the first display island areas A11a and the second display island areas A11b may be alternately arranged, and the light-transmitting area A12 is arranged between adjacent display island areas. The display island areas of odd columns (for example, the jth column, the j+2th column) may include multiple first display island areas A11a arranged in sequence along the second direction Y, and the display island areas of even columns (for example, the j+1th column) may include multiple second display island areas A11b arranged in sequence along the second direction Y. However, this embodiment is not limited to this. For example, odd columns may include multiple first display island areas, and even columns may include multiple second display island areas.

[0155] In some examples, as shown in FIG5 , taking the display island area in the jth column as an example, the first display island area A11a located in the i-th row and j-th column and the first display island area A11a located in the i+2-th row and j-th column can be aligned in the second direction Y, the first display island area A11a located in the i+1-th row and j-th column and the first display island area A11a located in the i+3-th row and j-th column can be aligned in the second direction Y, and the display island area located in the i-th row and j-th column and the display island area located in the i+1-th row and j-th column can be staggered. Each first display island area A11a located in the jth column can have a first edge F1 proximate to the display island area in the j-1th column and a second edge F2 proximate to the display island area in the j+1th column in the first direction X. The center line F3 of the first display island area A11a located in the i-th row and j-th column in the first direction X is aligned with the first edge F1 of the first display island area A11a located in the i+1-th row and j-th column; the center line F3 of the first display island area A11a located in the i+1-th row and j-th column in the first direction X is aligned with the second edge F2 of the first display island area A11a located in the i-th row and j-th column.

[0156] In some examples, for a column of display islands, the second edge of a display island located in an odd row may overlap with an extension of the row centerline of an adjacent display island located in an even row, and the extension of the row centerline of a display island located in an odd row may overlap with the first edge of an adjacent display island located in an even row. An extension of the second edge of a display island located in an even row in a column of display islands may overlap with an extension of the first edge of a display island located in an odd row in a display island adjacent to the right. Alternatively, for a column of display islands, the second edge of a display island located in an even row may overlap with an extension of the row centerline of an adjacent display island located in an odd row, and the extension of the row centerline of an even row may overlap with the first edge of an adjacent display island located in an odd row. An extension of the second edge of a display island located in an odd row in a column of display islands may overlap with an extension of the first edge of a display island located in an odd row in a display island adjacent to the right.

[0157] In some examples, the light-transmitting area A12 is aligned with half of the adjacent display island area A11 in the second direction Y. The midline of the light-transmitting area A12 in the first direction X may coincide with the midline of half of the adjacent display island area A11 in the second direction Y (i.e., a quarter bisector of the display island area A11).

[0158] In some examples, the first display island A11a and the second display island A11b may each include four first sub-pixels sequentially arranged along the first direction X. The first display island A11a may include a first sub-pixel 1a emitting first color light, a first sub-pixel 1b emitting third color light, a first sub-pixel 1c emitting second color light, and a first sub-pixel 1d emitting third color light, sequentially arranged along the first direction X. The second display island A11b may include a first sub-pixel 1c emitting second color light, a first sub-pixel 1d emitting third color light, a first sub-pixel 1a emitting first color light, and a first sub-pixel 1b emitting third color light, sequentially arranged along the first direction X. The first sub-pixels in the first display island A11a and the second display island A12 are arranged in a different order.

[0159] In some examples, each first sub-pixel may include: a first pixel circuit and a first light-emitting element electrically connected to the first pixel circuit. Each display island area in this example may include: four first pixel circuits and four first light-emitting elements. As shown in Figure 6, the four first pixel circuits in each display island area may be arranged in sequence along the first direction X. The four first light-emitting elements in each display island area may include: a first light-emitting element 13a emitting a first color light, a first light-emitting element 13c emitting a second color light, and first light-emitting elements 13b and 13d emitting a third color light. The first sub-pixel 1a may include: a first pixel circuit 11a and a first light-emitting element 13a connected to each other, the first sub-pixel 1b may include: a first pixel circuit 11b and a first light-emitting element 13b connected to each other, the first sub-pixel 1c may include: a first pixel circuit 11c and a first light-emitting element 13c connected to each other, and the first sub-pixel 1d may include: a first pixel circuit 11d and a first light-emitting element 13d connected to each other. In the first display island area A11a, the four first pixel circuits 11a, 11b, 11c, and 11d can be arranged sequentially along the first direction X; in the second display island area A11b, the four first pixel circuits 11c, 11d, 11a, and 11b can be arranged sequentially along the first direction X. In each display island area, the first light-emitting elements 13a and 13c can be arranged in the same row, the first light-emitting elements 13b and 13d can be arranged in the same row, the first light-emitting elements 13a and 13b can be arranged in different rows, and the first light-emitting elements 13a, 13b, 13c, and 13d can be arranged in different columns. In the first display island area A11a, the first light-emitting elements 13a, 13b, 13c, and 13d are arranged sequentially along the first direction X; in the second display island area A11b, the first light-emitting elements 13c, 13d, 13a, and 13b are arranged sequentially along the first direction X. The arrangement order of the four first light-emitting elements in the first display island area A11 a is different from the arrangement order of the four first light-emitting elements in the second display island area A11 b .

[0160] In some examples, the staggered distances between adjacent display islands A11 in each column of display islands may be the same, for example, they may be approximately the length of the light-transmitting area A12 along the first direction X. For example, the staggered distance L1 between adjacent first display islands A11a in the j-th column of display islands may be equal to the staggered distance L5 between adjacent second display islands A11b in the j+1-th column of display islands. The lengths of the four first pixel circuits in each display island along the first direction X may be the same. The staggered distance in the first direction of adjacent display islands in a column of display islands may be greater than or equal to the length of one first sub-pixel along the first direction, and less than or equal to the length of three first sub-pixels along the first direction. As shown in FIG6 , the staggered distance in the first direction X of adjacent display islands in a column of display islands (for example, the staggered distance L1 shown in FIG5 ) may be approximately the length of two first pixel circuits in the first direction X. The length of the light-transmitting area A12 along the first direction X may be less than or equal to the length of two first pixel circuits in the first direction X.

[0161] In some examples, as shown in Figures 4 and 5, the pixel density (PPI, Pixels Per Inch) of the first display area can be less than the pixel density of the second display area. The arrangement density of the first pixel circuit in the first display area can be less than the arrangement density of the second pixel circuit in the second display area. For example, the arrangement density of the first pixel circuit in the first direction in the first display area can be 1 / 3 of the arrangement density of the second pixel circuit in the second display area in the first direction. Compared with the second display area, the odd-numbered column display island area of ​​the first display area of ​​this example uses RGBG as a repeating unit, and the even-numbered column display island area uses BGRG as a repeating unit, and the RG unit or BG unit between adjacent columns is deleted at intervals, so that the number of deleted first sub-pixels in the first display area accounts for one-third of the total number of first sub-pixels, and a light-transmitting area is formed at the position where the first sub-pixel is deleted, thereby improving the light transmittance of the first display area on the basis of satisfying the display white balance.

[0162] Figure 7 is a partial top view of the first display area of ​​at least one embodiment of the present disclosure. Figure 7 illustrates a partial top view of three rows (e.g., rows i+1 through i+3) and two columns (e.g., columns j and j+1) of display islands. In some examples, as shown in Figure 7, the first display area may include: multiple display islands and multiple light-transmitting areas A12. The light-transmitting areas A12 may be surrounded by the display islands in the first direction X and the second direction Y.

[0163] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, and a circuit structure layer and a light-emitting structure layer disposed on the substrate. The light-emitting structure layer may be located on a side of the circuit structure layer away from the substrate. The circuit structure layer of the first display area may include: a plurality of first pixel circuits, and the light-emitting structure layer of the first display area may include: a plurality of first light-emitting elements.

[0164] In some examples, the circuit structure layer may include: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A first insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, a third insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer may be disposed on the side of the sixth conductive layer facing away from the substrate. In some examples, the first to sixth insulating layers may be inorganic insulating layers, and the seventh to ninth insulating layers may be organic insulating layers. This embodiment is not limited thereto. In other examples, a single insulating layer may be disposed between the fourth and fifth conductive layers. In other examples, two insulating layers may be disposed on the side of the sixth conductive layer facing away from the substrate to enhance the planarization of the anode layer.

[0165] In some examples, the light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer, which are sequentially arranged on the circuit structure layer. The anode layer may be electrically connected to the pixel circuit of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, and the cathode layer may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light of a corresponding color when driven by the anode layer and the cathode layer.

[0166] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate as an example. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0167] The “A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. The “thickness” of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The “shape of A” mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0168] The following takes the four first pixel circuits (e.g., first pixel circuits 11a, 11b, 11c, and 11d) of the first display island area of ​​the first display area (e.g., the first display island area located in the i+1th row and jth column) as an example to describe the film layer of the circuit structure layer. The film layer of the second display island area is similar to the film layer structure of the first display island area, so it will not be repeated here. This example is described by taking the first pixel circuit as the aforementioned 8T1C structure as an example. Among them, the first pixel circuit 11a may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, and a storage capacitor; the first pixel circuit 11b may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b, and a storage capacitor. The connection relationship between the eight transistors and the storage capacitor in each first pixel circuit can be referred to the equivalent circuit diagram shown in Figure 2.

[0169] In some examples, the preparation process of the display substrate may include the following operations.

[0170] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The material of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0171] (2) Forming a shielding layer. In some examples, a shielding film is deposited on a substrate and patterned through a patterning process to form a shielding layer disposed on the substrate. In some examples, the shielding layer may also be referred to as a bottom shielding metal (BSM).

[0172] FIG8A is a schematic diagram of the first display area after the shielding layer is formed in FIG7 . FIG8B is a schematic diagram of a first display island area in FIG8A . In some examples, as shown in FIG8A and FIG8B , the shielding layer of the first display area may include at least: a shielding block 300 located in the display island area. One shielding block 300 may be provided for each display island area. The shielding blocks 300 of adjacent display island areas in a column of display island areas may be interconnected as an integrated structure. The shielding blocks 300 of adjacent display island areas in adjacent rows of display island areas in adjacent columns of display island areas may be interconnected as an integrated structure. The multiple shielding blocks 300 of the first display area may be interconnected as an integrated structure.

[0173] In some examples, as shown in FIG8B , the obstructing block 300 located within the first display island area may include two first hollow portions 301, two second hollow portions 302, two third hollow portions 303, and two fourth hollow portions 304. The obstructing block 300 may be substantially symmetrical about the second centerline O2. The two first hollow portions 301 may be substantially symmetrical about the second centerline O2, and the single first hollow portion 301 may be substantially symmetrical about the first centerline O1 or the third centerline O3. The second hollow portion 302, the third hollow portion 303, and the fourth hollow portion 304 may be located on one side of the first hollow portion 301 opposite to the second direction Y. The fourth hollow portion 304 may be located between the second hollow portion 302 and the third hollow portion 303 in the first direction X. One second hollow portion 302 and one third hollow portion 303 may be substantially symmetrical about the first centerline O1, and another second hollow portion 302 and another third hollow portion 303 may be substantially symmetrical about the third centerline O3. One fourth hollow portion 304 can be substantially symmetrical about the first center line O1, and another fourth hollow portion 304 can be substantially symmetrical about the third center line O3. In this example, providing a light shielding block in the display island region can provide a light shielding effect for the transistors of the first pixel circuit in the display island region. Furthermore, providing a hollow portion in the light shielding block can avoid the use of large areas of metal, which could cause parasitic capacitance between the metal film layers and affect the display effect.

[0174] In some examples, the shielding layer can extend to the peripheral area and be electrically connected to the first power line in the peripheral area to receive the first voltage signal to avoid affecting other signal lines.

[0175] (3) Forming a first semiconductor layer. In some examples, a first semiconductor film is deposited on the substrate having the aforementioned pattern, and the first semiconductor film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0176] Fig. 9A is a schematic diagram of the first display region after the first semiconductor layer is formed in Fig. 7. Fig. 9B is a schematic diagram of a first display island region in Fig. 9A. In some examples, as shown in Figures 9A and 9B, the first semiconductor layer of the first display area may include at least: active layers of multiple first-type transistors of multiple first pixel circuits (for example, including: the first active layer 310a of the first transistor of the first pixel circuit 11a, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor; the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor).

[0177] In some examples, as shown in FIG9B , the first semiconductor layer patterns of the first pixel circuits 11a and 11b within a first display island region can be substantially symmetrical about a first centerline O1, the first semiconductor layer patterns of the first pixel circuits 11b and 11c can be substantially symmetrical about a second centerline O2, and the first semiconductor layer patterns of the first pixel circuits 11c and 11d can be substantially symmetrical about a third centerline O3. The first semiconductor layer patterns of the first pixel circuits 11a and 11b and the first semiconductor layer patterns of the first pixel circuits 11c and 11d can be substantially symmetrical about the second centerline O2. As shown in FIG9A , the first semiconductor layer patterns of different display island regions can be independent of each other.

[0178] In some examples, as shown in FIG9B , the third active layer, fourth active layer, fifth active layer, sixth active layer, and seventh active layer of the four first pixel circuits within the first display island region may be interconnected as an integrated structure. Specifically, the seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b may be directly connected, the fifth active layer 350b of the first pixel circuit 11b and the fifth active layer of the first pixel circuit 11c may be directly connected, and the seventh active layer of the first pixel circuit 11c and the seventh active layer of the first pixel circuit 11d may be directly connected.

[0179] In some examples, as shown in FIG9B , the first semiconductor layer pattern of the first pixel circuit 11 a is used as an example for description. The first active layer 310 a and the fourth active layer 340 a of the first pixel circuit 11 a may be located on one side of the third active layer 330 a along the second direction Y, and the fifth active layer 350 a, the sixth active layer 360 a, the seventh active layer 370 a, and the eighth active layer 380 a may be located on a side of the third active layer 330 a opposite to the second direction Y. The first active layer 310 a, the sixth active layer 360 a, and the seventh active layer 370 a may be aligned in the second direction Y.

[0180] In some examples, the third active layer 330a may be approximately U-shaped, the fourth active layer 340a may be approximately I-shaped, and the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a may be approximately L-shaped. However, this embodiment is not limited to this. The arrangement and shape of the first semiconductor layer pattern of the first pixel circuits 11b, 11c, and 11d are similar to those of the first pixel circuit 11a, and are therefore not further described herein.

[0181] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0182] In some examples, as shown in Figure 9A , the orthographic projection of the shielding layer of the first display area onto the substrate can cover the orthographic projection of the first semiconductor layer onto the substrate. As shown in Figure 9B , the orthographic projection of the shielding block 300 of the first display island onto the substrate can cover the orthographic projection of the first semiconductor layer of the four first pixel circuits of the first display island onto the substrate. In this example, by providing a shielding layer to shield the first semiconductor layer, external light can be prevented from affecting the transistors of the pixel circuits, thereby ensuring transistor performance.

[0183] (4) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the first insulating layer may also be referred to as a first gate insulating layer.

[0184] FIG10A is a schematic diagram of the first display area after the first conductive layer is formed in FIG7 . FIG10B is a schematic diagram of the first conductive layer in FIG10A . FIG10C is a schematic diagram of a first display island in FIG10A . In some examples, as shown in FIG10A to FIG10C , the first conductive layer in the first display area may include at least: a plurality of first scan lines (e.g., first scan lines GL1(i+1), GL1(i+2), and GL(i+3)), a plurality of emission control lines (e.g., emission control lines EML(i+1), EML(i+2), and EML(i+3)), a plurality of first reset control lines (e.g., first reset control lines RST1(i+1), RST1(i+2), and RST1(i+3)), a plurality of second reset control lines (e.g., second reset control lines RST2(i+1), RST2(i+2), and RST2(i+3)), and first electrodes of storage capacitors of a plurality of first pixel circuits (e.g., first electrodes 391 a and 391 b).

[0185] In some examples, the first scan line GL1(i+1) can be located on one side of the first electrode (e.g., first electrodes 391a, 391b) of the storage capacitor of the first pixel circuit in the second direction Y, and the first reset control line RST1(i+1) can be located on one side of the first scan line GL1(i+1) in the second direction Y. The emission control line EML(i+1) can be located on the side of the first electrode (e.g., first electrodes 391a, 391b) of the storage capacitor of the first pixel circuit in the opposite direction of the second direction Y, and the second reset control line RST2(i+1) can be located on the side of the emission control line EML(i+1) in the opposite direction of the second direction Y.

[0186] In some examples, the first reset control line RST1(i+1), the first scan line GL1(i+1), the second reset control line RST2(i+1), and the emission control line EML(i+1) can bend around the light-transmitting area. For example, the first reset control line RST1(i+1) and the first scan line GL1(i+1) can bend around the light-transmitting area along the second direction Y, and the second reset control line RST2(i+1) and the emission control line EML(i) can bend around the light-transmitting area in the opposite direction of the second direction Y. In this example, by arranging the routing of the first conductive layer to bend around the light-transmitting area, the area of ​​the light-transmitting area is increased, thereby improving the light transmittance of the first display area.

[0187] In some examples, the shape of the first reset control line RST1(i+1) can be substantially a zigzag line extending along the first direction X. In the first display island area, the overlapping region of the first reset control line RST1(i+1) and the first active layers of the four first pixel circuits can serve as the gates of the first transistors of the four first pixel circuits (e.g., including the gate of the first transistor 31 a and the gate of the first transistor 31 b ).

[0188] In some examples, the shape of the first scan line GL1(i+1) can be substantially a zigzag line extending along the first direction X. In the first display island area, the overlapping region of the first scan line GL1(i+1) and the fourth active layer of the four first pixel circuits can serve as the gates of the fourth transistors of the four first pixel circuits (for example, including the gate of the fourth transistor 34 a and the gate of the fourth transistor 34 b ).

[0189] In some examples, the shape of the light-emitting control line EML(i+1) can be substantially a zigzag line extending along the first direction X. In the first display island area, the overlapping region of the light-emitting control line EML(i+1) and the fifth active layer of the four first pixel circuits can serve as the gates of the fifth transistors of the four first pixel circuits (for example, including the gates of the fifth transistors 35 a and 35 b ), and the overlapping region of the light-emitting control line EML(i+1) and the sixth active layer of the four first pixel circuits can serve as the gates of the sixth transistors of the four first pixel circuits (for example, including the gates of the sixth transistors 36 a and 36 b ).

[0190] In some examples, the shape of the second reset control line RST2(i+1) can be substantially a zigzag line extending along the first direction X. In the first display island area, the overlapping region of the second reset control line RST2(i+1) and the seventh active layer of the four first pixel circuits can serve as the gates of the seventh transistors of the four first pixel circuits (for example, including the gates of the seventh transistors 37a and 37b), and the overlapping region of the second reset control line RST2(i+1) and the eighth active layer of the four first pixel circuits can serve as the gates of the eighth transistors of the four first pixel circuits (for example, including the gates of the eighth transistors 38a and 38b).

[0191] In some examples, the first electrode 391a of the storage capacitor of the first pixel circuit 11a can also serve as the gate of the third transistor 33a, and the first electrode 391b of the storage capacitor of the first pixel circuit 11b can also serve as the gate of the third transistor 33b. The orthographic projections of the first electrodes 391a and 391b on the substrate can be approximately rectangular. This embodiment is not limited to this.

[0192] (5) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the second insulating layer may also be referred to as a second gate insulating layer.

[0193] Figure 11A is a schematic diagram of the first display area after the second conductive layer is formed in Figure 7. Figure 11B is a schematic diagram of the second conductive layer in Figure 11A. Figure 11C is a schematic diagram of a first display island area in Figure 11A. In some examples, as shown in Figures 11A to 11C, the second conductive layer of the first display area may include at least: a plurality of second auxiliary scanning lines (for example, including second auxiliary scanning lines GL2b(i+1), GL2b(i+2), and GL2b(i+3)), and a plurality of second electrodes of storage capacitors of first pixel circuits (for example, including second electrodes 392a and 392b).

[0194] In some examples, the shape of the second scan auxiliary line GL2b(i+1) can be substantially a zigzag line extending along the first direction X. Within the first display island area, the second scan auxiliary line GL2b(i+1) can be located on one side of the second electrode (e.g., second electrodes 392a and 392b) of the storage capacitor of the first pixel circuit in the second direction Y. The second scan auxiliary line GL2b(i+1) can bypass the light-transmitting area from one side in the second direction Y and be located on a side opposite to the first scan line GL1(i+1) in the second direction Y.

[0195] In some examples, within the first display island region, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit on the substrate can be approximately a rectangular structure having a hollow region, and the orthographic projection of the hollow region on the substrate can be approximately a rectangle, and the rectangle can have rounded or chamfered corners. The second electrode 392a of the storage capacitor of the first pixel circuit 11a and the second electrode 392b of the storage capacitor of the first pixel circuit 11b can be electrically connected via a first plate connection block 392-1, the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode of the storage capacitor of the first pixel circuit 11c can be electrically connected via a second plate connection block 392-2, and the second electrode of the storage capacitor of the first pixel circuit 11c and the second electrode of the storage capacitor of the first pixel circuit 11d can be electrically connected via another first plate connection block 392-1. The side of the second electrode 392a of the storage capacitor of the first pixel circuit 11a away from the first pixel circuit 11b can be connected to a second plate connecting block 392-2, and the side of the second electrode of the storage capacitor of the first pixel circuit 11d away from the first pixel circuit 11c can be electrically connected to another second plate connecting block 392-2. The length H1 of the first plate connecting block 392-1 along the second direction Y can be less than the length H2 of the second plate connecting block 392-2 along the second direction Y. The second electrode of the storage capacitor can subsequently be electrically connected to the first power line through the second plate connecting block. In this example, the second electrodes of the storage capacitors of the four first pixel circuits in the first display island area can be an integrated structure that is interconnected, which is conducive to ensuring uniform transmission of the first voltage signal along the first direction X.

[0196] (6) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the third insulating layer may also be referred to as a third gate insulating layer.

[0197] Figure 12A is a schematic diagram of the first display area after the second semiconductor layer is formed in Figure 7. Figure 12B is a schematic diagram of a first display island area in Figure 12A. In some examples, as shown in Figures 12A and 12B, the second semiconductor layer of the first display area may include at least: active layers of the second type transistors of multiple first pixel circuits (for example, including: second active layer 320a of second transistor 32a of first pixel circuit 11a, second active layer 320b of second transistor 32b of first pixel circuit 11b).

[0198] In some examples, within the first display island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be approximately symmetrical about the first center line O1, the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be approximately symmetrical about the second center line O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be approximately symmetrical about the third center line O3. The second semiconductor layer patterns of the first pixel circuits 11a and 11b and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be approximately symmetrical about the second center line O2.

[0199] In some examples, the second active layers 320a and 320b may be shaped approximately like an inverted L. The overlapping region between the second scanning auxiliary line GL2b(i+1) and the second active layer 320a may serve as the bottom gate of the second transistor 32a, and the overlapping region between the second scanning auxiliary line GL2b(i+1) and the second active layer 320b may serve as the bottom gate of the second transistor 32b.

[0200] In some examples, the orthographic projection of the second semiconductor layer on the substrate may not overlap with the orthographic projection of the shielding layer on the substrate. For example, the orthographic projections of the second active layers 320a and 320b on the substrate may be within the orthographic projection range of the first hollow region 301 on the substrate.

[0201] (7) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer, and the fourth insulating layer may also be referred to as a fourth gate insulating layer.

[0202] FIG13A is a schematic diagram of the first display area after the third conductive layer is formed in FIG7 . FIG13B is a schematic diagram of the third conductive layer in FIG13A . FIG13C is a schematic diagram of a first display island area in FIG13A . In some examples, the third conductive layer in the first display area may include at least: a plurality of second scan lines (e.g., second scan lines GL2(i+1), GL2(i+2), and GL2(i+3)), a plurality of first initial signal lines (e.g., first initial signal lines INIT1(i+1), INIT1(i+2), and INIT1(i+3)), a plurality of second initial signal lines (e.g., second initial signal lines INIT2(i+1), INIT2(i+2), and INIT2(i+3)), and a plurality of third initial signal lines (e.g., third initial signal lines INIT3(i+1), INIT3(i+2), and INIT3(i+3)). The first initial signal lines, the second scan lines, the second initial signal lines, and the third initial signal lines may each be substantially zigzag lines extending along the first direction X.

[0203] In some examples, within the first display island area, the first initial signal line INIT1(i+1) and the second scan line GL2(i+1) may be located on one side of the storage capacitor along the second direction Y, and the second initial signal line INIT2(i+1) and the third initial signal line INIT3(i+1) may be located on the side of the storage capacitor in the opposite direction to the second direction Y. The first initial signal line INIT1(i+1) may be located on one side of the second scan line GL2(i+1) in the second direction Y, the third initial signal line INIT3(i+1) and the second initial signal line INIT2(i+1) may be located on the side of the second scan line GL2(i+1) in the opposite direction to the second direction Y, and the second initial signal line INIT2(i+1) may be located on the side of the third initial signal line INIT3(i+1) in the opposite direction to the second direction Y.

[0204] In some examples, the first initial signal line INIT1(i+1), the second scan line GL2(i+1), the second initial signal line INIT2(i+1), and the third initial signal line INIT3(i+1) can bypass the light-transmitting area by bending. For example, the first initial signal line INIT1(i+1) and the second scan line GL2(i+1) can bypass the light-transmitting area from one side along the second direction Y, and the second initial signal line INIT2(i+1) and the third initial signal line INIT3(i+1) can bypass the light-transmitting area from the side opposite to the second direction Y. In this example, by setting the routing of the third conductive layer to bend around the light-transmitting area, the area of ​​the light-transmitting area can be increased, which helps to improve the light transmittance of the first display area.

[0205] In some examples, the orthographic projection of the first initial signal line INIT1(i+1) on the substrate may at least partially overlap with the orthographic projection of the first reset control line RST1(i+1) on the substrate. For example, the orthographic projection of the first initial signal line INIT1(i+1) on the substrate may include the orthographic projection of the first reset control line RST1(i+1) on the substrate. The orthographic projection of the second scan line GL2(i+1) on the substrate may at least partially overlap with the orthographic projection of the second scan auxiliary line GL2b(i+1) on the substrate. For example, the orthographic projection of the second scan line GL2(i+1) on the substrate may include the orthographic projection of the second scan auxiliary line GL2b(i+1) on the substrate. The orthographic projection of the third initial signal line INIT3(i+1) on the substrate may at least partially overlap with the orthographic projection of the emission control line EML(i+1) on the substrate. For example, the orthographic projection of the third initial signal line INIT3(i+1) on the substrate may include the orthographic projection of the emission control line EML(i+1) on the substrate. The orthographic projection of the second initial signal line INIT2(i) on the substrate may at least partially overlap with the orthographic projection of the second reset control line RST2(i+1) on the substrate. For example, the orthographic projection of the second initial signal line INIT2(i+1) on the substrate may include the orthographic projection of the second reset control line RST2(i+1) on the substrate. This example avoids occupying excessive routing space by stacking the routing of different conductive layers (e.g., the first conductive layer, the second conductive layer, and the third conductive layer), which helps save wiring space and thereby improves the light transmittance of the first display area.

[0206] (8) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate having the aforementioned pattern, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer.

[0207] FIG14 is a schematic diagram of a first display island region after the fifth insulating layer is formed in FIG7. In some examples, as shown in FIG14, the fifth insulating layer in the first display region may have a plurality of vias, such as first to nineteenth vias V1 to V19, twenty-first to twenty-second vias V21 to V22, twenty-third to twenty-fourth vias V23 to V24, twenty-fifth to twenty-ninth vias V25 to V29, and thirty-first to thirty-fourth vias V31 to V34.

[0208] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first via hole V1 to the nineteenth via hole V19 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twenty-first via hole V21 and the twenty-second via hole V22 can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in the twenty-third via hole V23 and the twenty-fourth via hole V24 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in the twenty-fifth via hole V25 to the twenty-ninth via hole V29 can be removed to expose a portion of the surface of the third conductive layer. The fifth insulating layer and the fourth insulating layer in the thirty-first via hole V31 to the thirty-fourth via hole V34 can be removed to expose the surface of the second semiconductor layer.

[0209] (9) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0210] Figure 15A is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 7. Figure 15B is a schematic diagram of the fourth conductive layer in Figure 15A. Figure 15C is a schematic diagram of a first display island region in Figure 15A. In some examples, as shown in Figures 15A to 15C, the fourth conductive layer in the first display area may include at least a plurality of connecting electrodes (for example, including first to ninth connecting electrodes 401 to 409, and eleventh to seventeenth connecting electrodes 411 to 417).

[0211] In some examples, the shape of the first connection electrode 401 may be substantially rectangular.The first connection electrode 401 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the third via hole V3.

[0212] In some examples, the second connection electrode 402 can be shaped substantially like a strip extending along the second direction Y. One end of the second connection electrode 402 can be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a through a thirty-first via hole V31, and the other end can be electrically connected to the first electrode 391a of the storage capacitor through a twenty-first via hole V21. The second connection electrode 402 is electrically connected to the gate of the third transistor 33a, the first electrode 391a of the storage capacitor, and the first electrode of the second transistor 32a. The second connection electrode 402 can serve as the first node of the first pixel circuit 11a.

[0213] In some examples, the third connection electrode 403 can be shaped substantially like a strip extending along the second direction Y. One end of the third connection electrode 403 can be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a through the second via V2, and the other end can be electrically connected to the second active layer 320a of the second transistor 32a through the thirty-second via V32. The third connection electrode 403 can also be electrically connected to the third active layer of the third transistor 33a through the sixth via V6. The third connection electrode 403 can serve as a third node of the first pixel circuit 11a.

[0214] In some examples, the fourth connection electrode 404 may be shaped substantially like a zigzag line extending along the second direction Y. The fourth connection electrode 404 may be electrically connected to the fourth active layer 340 a of the fourth transistor 34 a of the first pixel circuit 11 a through a fourth via hole V4, and may also be electrically connected to the eighth active layer 380 a of the eighth transistor 38 a through an eighth via hole V8.

[0215] In some examples, the fifth connection electrode 405 may be shaped substantially like a strip extending along the second direction Y. The fifth connection electrode 405 may be electrically connected to the fifth active layer 350 a of the fifth transistor 35 a of the first pixel circuit 11 a through a fifth via hole V5, and may also be electrically connected to the second plate connection block 392 - 2 through a twenty-third via hole V23, thereby achieving electrical connection to the second electrode 392 a of the storage capacitor.

[0216] In some examples, the shape of the sixth connection electrode 406 may be substantially rectangular.The sixth connection electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through a seventh via hole V7.

[0217] In some examples, the shape of the seventh connection electrode 407 can be substantially L-shaped. The seventh connection electrode 407 can be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a through a ninth via hole V9, and can also be electrically connected to the third initial signal line INIT3(i) through a twenty-sixth via hole V26.

[0218] In some examples, the eighth connection electrode 408 may be shaped substantially like a strip extending along the second direction Y. The eighth connection electrode 408 may be electrically connected to the seventh active layer 370 a of the seventh transistor 37 a of the first pixel circuit 11 a through a tenth via hole V10, and may also be electrically connected to the second initial signal line INIT2(i) through a twenty-seventh via hole V27.

[0219] In some examples, the shape of the ninth connection electrode 409 can be substantially an arch extending along the second direction Y. One end of the ninth connection electrode 409 can be electrically connected to the first active layer 310 a of the first transistor 31 a of the first pixel circuit 11 a through the first via hole V1, and can also be electrically connected to the first initial signal line INIT1(i) through the twenty-fifth via hole V25, and the other end can be electrically connected to the first active layer 310 b of the first transistor 31 b of the first pixel circuit 11 b through the eleventh via hole V11, and can also be electrically connected to the first initial signal line INIT1(i) through the twenty-eighth via hole V28.

[0220] In some examples, the eleventh connection electrode 411 may be substantially rectangular in shape. The eleventh connection electrode 411 may be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the thirteenth via hole V13.

[0221] In some examples, the twelfth connection electrode 412 can be shaped substantially like a strip extending along the second direction Y. One end of the twelfth connection electrode 412 can be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via a thirty-third via hole V31, and the other end can be electrically connected to the first electrode 391b of the storage capacitor via a twenty-second via hole V22. The twelfth connection electrode 412 is electrically connected to the gate of the third transistor 33b, the first electrode 391b of the storage capacitor, and the first electrode of the second transistor 32b. The twelfth connection electrode 412 can serve as the first node of the first pixel circuit 11b.

[0222] In some examples, the thirteenth connection electrode 413 can be shaped substantially like a strip extending along the second direction Y. One end of the thirteenth connection electrode 413 can be electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b through the twelfth via hole V12, and the other end can be electrically connected to the second active layer 320b of the second transistor 32b through the thirty-fourth via hole V34. The thirteenth connection electrode 413 can also be electrically connected to the third active layer 330b of the third transistor 33b through the sixteenth via hole V16. The thirteenth connection electrode 413 can serve as a third node of the first pixel circuit 11b.

[0223] In some examples, the shape of the fourteenth connection electrode 414 can be substantially a zigzag shape extending along the second direction Y. The fourteenth connection electrode 414 can be electrically connected to the fourth active layer 340 b of the fourth transistor 34 b of the first pixel circuit 11 b through the fourteenth via hole V14, and can also be electrically connected to the eighth active layer 380 b of the eighth transistor 38 b through the eighteenth via hole V18.

[0224] In some examples, the shape of the fifteenth connection electrode 415 can be substantially a strip extending along the second direction Y. The fifteenth connection electrode 415 can be electrically connected to the fifth active layer 350 b of the fifth transistor 35 b of the first pixel circuit 11 b through the fifteenth via hole V15, and can also be electrically connected to another second plate connection block 392 - 2 through the twenty-fourth via hole V24, thereby achieving electrical connection with the second electrode 392 b of the storage capacitor.

[0225] In some examples, the shape of the sixteenth connection electrode 416 may be substantially rectangular. The sixteenth connection electrode 416 may be electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b through the seventeenth via hole V17.

[0226] In some examples, the shape of the seventeenth connection electrode 417 can be substantially L-shaped. The seventeenth connection electrode 417 can be electrically connected to the eighth active layer 380b of the eighth transistor 38b of the first pixel circuit 11b through a nineteenth via hole V19, and can also be electrically connected to the third initial signal line INIT3(i) through a twenty-ninth via hole V29.

[0227] In some examples, within the first display island area, the first pixel circuits 11a and 11b can be roughly symmetrical about the second center line O2, the first pixel circuits 11c and 11d can be roughly symmetrical about the third center line O3, and the first pixel circuits 11a and 11b, the first pixel circuits 11c and 11d can be roughly symmetrical about the first center line O1.

[0228] (10) Forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a seventh insulating film is coated. The seventh insulating film and the sixth insulating film are patterned by a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

[0229] Figure 16 is a schematic diagram of a first display island region after the seventh insulating layer is formed in Figure 7. In some examples, as shown in Figure 16, the seventh insulating layer in the first display region can be provided with a plurality of vias, such as vias 41 to 46 (V41 to V46). The seventh and sixth insulating layers within vias 41 to 46 (V41 to V46) can be removed to expose a portion of the surface of the fourth conductive layer.

[0230] (11) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source / drain metal layer.

[0231] Figure 17A is a schematic diagram of the first display area after the fifth conductive layer is formed in Figure 7. Figure 17B is a schematic diagram of the fifth conductive layer in Figure 17A. Figure 17C is a schematic diagram of a first display island area in Figure 17A. In some examples, as shown in Figures 17A to 17C, the fifth conductive layer in the first display area may include at least: a plurality of data lines (e.g., data lines DL(k-2), DL(k-1), DL(k), DL(k+1), DL(k+2), DL(k+3), DL(k+4), DL(k+5), DL(k+6), DL(k+7)), a plurality of first anode connection electrodes (e.g., first anode connection electrodes 422a, 422b, 422c, and 422d), a plurality of first power connection electrodes (e.g., first power connection electrodes 423a, 423b, and 423c), and a plurality of first shield electrodes (e.g., first shield electrodes 421a and 421b). Where k is an integer greater than 0.

[0232] In some examples, the plurality of data lines may be roughly in the shape of a zigzag line extending along the second direction Y. The four first pixel circuits in each first display island area are electrically connected to the four data lines in a one-to-one correspondence. The data line DL(k) may be electrically connected to the first connection electrode 401 through the forty-first via V41, thereby being electrically connected to the fourth transistor of the first pixel circuit 11a. The data line DL(k+1) may be electrically connected to the eleventh connection electrode 411 through the forty-fifth via V45, thereby being electrically connected to the fourth transistor of the first pixel circuit 11b. The data line DL(k+2) may be electrically connected to the fourth transistor of the first pixel circuit 11c. The data line DL(k+3) may be electrically connected to the fourth transistor of the first pixel circuit 11d. In some examples, the data lines DL(k-1), DL(k+2), DL(k+3), and DL(k+5) may provide data signals to the first pixel circuits arranged in alternate rows.

[0233] In some examples, the four data lines electrically connected to the four first pixel circuits in the first display island area can be divided into two groups to bypass the light-transmitting area adjacent to the first display island area in the second direction Y. For example, the data line DL(k) connected to the first pixel circuit 11a, the data line DL(k+1) connected to the first pixel circuit 11b, and the data line DL(k+2) connected to the first pixel circuit 11c can bypass the light-transmitting area from the side opposite to the first direction X, and the data line DL(k+3) connected to the first pixel circuit 11d can bypass the light-transmitting area from the side of the first direction X. In this example, by setting the data lines to bend around the light-transmitting area, it is beneficial to reduce the space occupied by the wiring, thereby improving the light transmittance of the first display area.

[0234] In some examples, the shape of the first anode connection electrodes 422a, 422b, 422c, and 422d can be substantially rectangular. The first anode connection electrodes 422a and 422b can be located between the data lines DL(k) and DL(k+1), and the first anode connection electrodes 422c and 422d can be located between the data lines DL(k+2) and DL(k+3).

[0235] In some examples, the first anode connection electrode 422a can be electrically connected to the sixth connection electrode 406 through the forty-third via hole V43, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 422b can be electrically connected to the sixteenth connection electrode 416 through the forty-sixth via hole V46, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 422c can be electrically connected to the sixth transistor of the first pixel circuit 11c. The first anode connection electrode 422d can be electrically connected to the sixth transistor of the first pixel circuit 11d.

[0236] In some examples, the shapes of the first power connection electrodes 423a, 423b, and 423c can be substantially rectangular. The first power connection electrode 423a can be located between the data lines DL(k) and DL(k-1), the first power connection electrode 423b can be located between the data lines DL(k+1) and DL(k+2), and the first power connection electrode 423c can be located between the data lines DL(k+3) and DL(k+3).

[0237] In some examples, the first power connection electrode 423a can be electrically connected to the fifth connection electrode 405 through the forty-second via hole V42, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuit 11a. The second power connection electrode 423b can be electrically connected to the fifteenth connection electrode 415 through the forty-fourth via hole V44, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuits 11b and 11c. The third power connection electrode 423c can be electrically connected to the fifth transistor and storage capacitor of the first pixel circuit 11d.

[0238] In some examples, the shape of the first shielding electrodes 421a and 421b can be roughly n-shaped. The first shielding electrode 421a can be located between the data lines DL(k) and DL(k+1), and the first shielding electrode 421b can be located between the data lines DL(k+2) and DL(k+3). The orthographic projection of the first shielding electrode 421a on the substrate can cover the orthographic projection of the second connecting electrode 402 and the twelfth connecting electrode 412 on the substrate, which can block the first node of the first pixel circuit 11a and the first node of the first pixel circuit 11b, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11a and 11b. The second shielding electrode 421b can block the first node of the first pixel circuit 11c and the first node of the first pixel circuit 11d, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11c and 11d.

[0239] (12) Forming an eighth insulating layer. In some examples, an eighth insulating layer is coated on the substrate having the aforementioned pattern, and the eighth insulating layer is patterned by a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as a second planar layer.

[0240] FIG18 is a schematic diagram of a first display island region after the eighth insulating layer is formed in FIG7 . In some examples, as shown in FIG18 , the eighth insulating layer in the first display region may be provided with a plurality of vias, such as vias V51 through V59. The eighth insulating layer within vias V51 through V59 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0241] (13) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate having the aforementioned pattern, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source / drain metal layer.

[0242] FIG19A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG7 . FIG19B is a schematic diagram of the sixth conductive layer in FIG19A . FIG19C is a schematic diagram of a first display island in FIG19A . In some examples, as shown in FIG19A to FIG19C , the sixth conductive layer in the first display area may include at least: a plurality of second anode connection electrodes (e.g., including second anode connection electrodes 432a, 432b, 432c, and 432d), a plurality of second power connection electrodes 433, a plurality of power connection bars 451, a plurality of first voltage transmission lines (e.g., including first voltage transmission lines 441a, 441b, and 441c), and a plurality of second voltage transmission lines 442.

[0243] In some examples, the second anode connection electrode 432a can be located between the first voltage transmission line 441a and the second voltage transmission line 442, the second anode connection electrode 432b can be located between the second voltage transmission line 442 and the first voltage transmission line 441b, the second anode connection electrode 432c can be located between the first voltage transmission line 441b and the second power connection electrode 433, and the second anode connection electrode 432d can be located between the second power connection electrode 433 and the first voltage transmission line 441c.

[0244] In some examples, the shape of the second anode connection electrode 432a can be approximately a zigzag structure extending along the second direction Y. The second anode connection electrode 432a can be electrically connected to the first anode connection electrode 422a through the fifty-sixth via V56. The shape of the second anode connection electrode 432b can be approximately rectangular. The second anode connection electrode 432b can be electrically connected to the first anode connection electrode 422b through the fifty-seventh via V57. The shape of the second anode connection electrode 432c can be approximately a strip structure extending along the second direction Y. The second anode connection electrode 432c can be electrically connected to the first anode connection electrode 422c through the fifty-eighth via V58. The shape of the second anode connection electrode 432d can be approximately a strip structure extending in a direction intersecting both the first direction X and the second direction Y. The second anode connection electrode 432d can be electrically connected to the first anode connection electrode 422d through the fifty-ninth via V59.

[0245] In some examples, the first voltage transmission lines 441a, 441b, and 441c and the second voltage transmission line 442 may be in the shape of a broken line extending along the second direction Y. The line width of the second voltage transmission line 442 (i.e., the length along the first direction X) may be greater than the line width of the first voltage transmission line 441a. The line widths of the first voltage transmission lines 441a, 441b, and 441c may be substantially the same. The first voltage transmission line 441a may be electrically connected to the first power connection electrode 423a through the fifty-third via V53, the first voltage transmission line 441b may be electrically connected to the first power connection electrode 423b through the fifty-fourth via V54, and the first voltage transmission line 441c may be electrically connected to the first power connection electrode 423c through the fifty-fifth via V55. The second voltage transmission line 442 may be electrically connected to the first shielding electrode 421a through the fifty-first via V51. The first voltage transmission lines 441a, 441b, 441c, and the second voltage transmission line 442 may receive the first voltage signal. For example, the first voltage transmission lines 441a, 441b, and 441c and the second voltage transmission line 442 may extend to the peripheral area and be electrically connected to the first power line in the peripheral area to access the first voltage signal.

[0246] In some examples, the second power connection electrode 433 may be a strip-shaped structure extending along the second direction Y. The second power connection electrode 433 may be electrically connected to the first shielding electrode 421 b through a fifty-second via hole V52 .

[0247] In some examples, the power connection bar 451 can be shaped substantially like a strip extending along the first direction X. The power connection line 451 can connect adjacent voltage transmission lines. The power connection line 451, the first voltage transmission lines 441a, 441b, and 441c, the second voltage transmission line 442, and the second power connection electrode 433 can be interconnected as an integrated structure, thereby forming a mesh connection structure for transmitting the first voltage signal to ensure uniform transmission of the first voltage signal.

[0248] In this example, the fifth and sixth conductive layers are used to arrange the voltage transmission lines and data lines, which can avoid the problem of arranging too many lines in the conductive layer close to the anode layer and affecting the flatness of the anode layer. In addition, the voltage transmission lines (including the first and second voltage transmission lines) are arranged in the sixth conductive layer, and the data lines are arranged in the fifth conductive layer. This can increase the distance between the data lines and the anode layer, thereby preventing the data line transmission signals from affecting the anode layer.

[0249] (14) Forming a ninth insulating layer. In some examples, a ninth insulating layer is coated on the substrate having the aforementioned pattern, and the ninth insulating layer is patterned by a patterning process to form the ninth insulating layer. In some examples, the ninth insulating layer may also be referred to as a third planar layer.

[0250] FIG20 is a schematic diagram of a first display island region after the ninth insulating layer is formed in FIG7 . In some examples, as shown in FIG20 , the ninth insulating layer in the first display region may have multiple vias, such as vias 61 to 64. The ninth insulating layer within vias 61 to 64 may be removed to expose a portion of the surface of the sixth conductive layer.

[0251] At this point, the circuit structure layer can be prepared. The film structure of the circuit structure layer in the second display area is similar to that of the first display area, so it will not be described in detail here.

[0252] (15) Forming a light-emitting structure layer. In some examples, an anode film is deposited on the substrate having the aforementioned pattern, and the anode film is patterned by a patterning process to form an anode layer.

[0253] FIG21 is a schematic diagram of the first display area after the anode layer is formed in FIG7 . In some examples, as shown in FIG21 , the anode layer of the first display area may include at least: anodes of a plurality of first light-emitting elements (e.g., anode 131 a of first light-emitting element 13 a , anode 131 b of first light-emitting element 13 b , anode 131 c of first light-emitting element 13 c , and anode 131 d of first light-emitting element 13 d ), and a plurality of third anode connecting electrodes (e.g., third anode connecting electrodes 132 a , 132 b , 132 c , and 132 d ).

[0254] In some examples, the shapes of the anodes 131a, 131b, 131c, and 131d can be approximately circular or elliptical. The shapes of the third anode connection electrodes 132a, 132b, 132c, and 132d can be approximately rectangular. The anode 131a and the third anode connection electrode 132a can be interconnected as a single unit. The third anode connection electrode 132a can be electrically connected to the second anode connection electrode 432a via a sixty-first via hole V61 to achieve electrical connection with the first pixel circuit 11a. The anode 131b and the third anode connection electrode 132b can be interconnected as a single unit. The third anode connection electrode 132b can be electrically connected to the second anode connection electrode 432b via a sixty-second via hole V62 to achieve electrical connection with the first pixel circuit 11b. The anode 131c and the third anode connection electrode 132c can be interconnected as a single unit. The third anode connection electrode 132c can be electrically connected to the second anode connection electrode 432c via a sixty-third via hole V63 to achieve electrical connection with the first pixel circuit 11c. The anode 131d and the third anode connection electrode 132d may be an integral structure connected to each other. The third anode connection electrode 132d may be electrically connected to the second anode connection electrode 432d through the sixty-fourth via hole V64.

[0255] In some examples, a pixel definition film is coated on a substrate having the aforementioned pattern, and a pixel definition layer is formed by masking, exposure, and development processes. As shown in FIG7 , the pixel definition layer of the first display area can form a plurality of first pixel openings (e.g., first pixel openings 130a, 130b, 130c, and 130d). The shape of the plurality of first pixel openings can be roughly circular. The first pixel opening 130a of the first light-emitting element 13b and the first pixel opening 130d of the first light-emitting element 13d can be roughly the same size, the first pixel opening 130a of the first light-emitting element 13a can be larger than the first pixel opening 130b of the first light-emitting element 13b, and the first pixel circuit 130c of the first light-emitting element 13c can be larger than the first pixel opening 130a of the first light-emitting element 13a.

[0256] In some examples, an organic light-emitting layer is formed within the pixel opening formed above, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode film is deposited and patterned through a patterning process to form a cathode pattern, and the cathode is connected to the organic light-emitting layer.

[0257] In some examples, the light-emitting area of ​​a light-emitting element may be the portion of the light-emitting element located within the pixel opening of the pixel definition layer. The light-emitting area of ​​first light-emitting element 13a may be larger than the light-emitting area of ​​first light-emitting element 13b, the light-emitting area of ​​first light-emitting element 13c may be larger than the light-emitting area of ​​first light-emitting element 13a, and the light-emitting areas of first light-emitting element 13b and first light-emitting element 13d may be approximately the same size.

[0258] In some examples, after preparing the light-emitting structure layer, an encapsulation structure layer can be formed on the cathode. In some examples, the encapsulation structure layer can include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer can be arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementations, the display substrate can also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0259] In some examples, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The seventh insulating layer, the eighth insulating layer, and the ninth insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material. However, this embodiment is not limited thereto.

[0260] The structure of the display substrate and its preparation process in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or removed as needed. The preparation process of this exemplary embodiment can be implemented using currently available manufacturing equipment and is well compatible with existing manufacturing processes. The process is simple to implement, easy to implement, and has high production efficiency, low production costs, and a high yield rate.

[0261] Compared with the second display area, the display substrate of this example forms a light-transmitting area by deleting the first pixel circuit and the first light-emitting element in the first display area, and performs a routing design that avoids the light-transmitting area in the light-transmitting area. Therefore, on the basis of ensuring the white balance of the light emission in the first display area, the light transmittance of the first display area is improved to meet the size and light transmittance requirements of the under-screen function.

[0262] Figure 22 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 22 illustrates six rows (e.g., rows i through i+5) and five columns (e.g., columns j through j+4) of display islands. In some examples, as shown in Figure 22, the first display area A1 may include: a plurality of display islands A11 and a plurality of light-transmitting areas A12 arranged in an array. In a first direction X, the display islands A11 and the light-transmitting areas A12 may be arranged alternately and aligned; in a second direction Y, the display islands A11 and the light-transmitting areas A12 may be arranged alternately and aligned.

[0263] In some examples, as shown in FIG22 , the plurality of display islands A11 may include a plurality of first display islands A11a and a plurality of second display islands A11b. The plurality of light-transmitting areas A12 may include a plurality of first light-transmitting areas A12a and a plurality of second light-transmitting areas A12b. The display islands in odd-numbered rows (e.g., row i, row i+2, and row i+4) may include a plurality of first display islands A11a alternating with the first light-transmitting areas A12a; and the display islands in even-numbered rows (e.g., row i+1, row i+3, and row i+5) may include a plurality of second display islands A11b alternating with the second light-transmitting areas A12b. The display islands in odd columns (e.g., column j, column j+2, and column j+4) may include: a plurality of first display islands A11a arranged alternately with the second light-transmitting areas A12b; the display islands in even columns (e.g., column j+1 and column j+3) may include: a plurality of second display islands A11b arranged alternately with the first light-transmitting areas A12a. This embodiment is not limited to this. In other examples, the display islands in odd and even rows may be swapped, and the display islands in odd and even columns may be swapped.

[0264] In some examples, as shown in FIG22 , the shapes and sizes of the plurality of display islands A11 can be substantially the same. The shapes and sizes of the plurality of light-transmitting areas A12 can be substantially the same. The length of the display islands A11 along the first direction X can be greater than or equal to the length of the light-transmitting areas A12 along the first direction X.

[0265] Figure 23 is a schematic top view of a portion of the first display area of ​​at least one embodiment of the present disclosure. Figure 23 illustrates a schematic top view of four rows (e.g., rows i through i+3) and two columns (e.g., columns j and j+1). The following describes the film structure using the first display island located in row i and column j as an example.

[0266] FIG24 is a schematic diagram of the first display area after the shielding layer is formed in FIG23 . In some examples, as shown in FIG24 , the shielding layer of the first display area may include at least: a shielding block 300 located in the display island area. One shielding block 300 may be provided for each display island area. The shielding block 300 may not have a hollow portion. The multiple shielding blocks 300 in the first display area may be an interconnected integral structure. In this example, the provision of a light shielding block in the display island area can provide a light shielding effect for the transistor of the first pixel circuit in the display island area, thereby ensuring the performance of the transistor.

[0267] FIG25 is a schematic diagram of the first display area after the first semiconductor layer is formed in FIG23. In some examples, as shown in FIG25, the first semiconductor layer of the first display area may include at least: active layers of multiple first-type transistors of multiple first pixel circuits (for example, including: the first active layer 310a of the first transistor, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor of the first pixel circuit 11a; the first active layer 310b of the first transistor, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor of the first pixel circuit 11b). The orthographic projection of the blocking layer on the substrate may cover the orthographic projection of the first semiconductor layer on the substrate.

[0268] Fig. 26A is a schematic diagram of the first display area after the first conductive layer is formed in Fig. 23. Fig. 26B is a schematic diagram of the first conductive layer in Fig. 26A. In some examples, as shown in Figures 26A and 26B, the first conductive layer of the first display area may include at least: a plurality of first scan lines (for example, first scan lines GL1(i), GL1(i+1), GL1(i+2), and GL1(i+3)), a plurality of emission control lines (for example, emission control lines EML(i), EML(i+1), EML(i+2), and EML(i+3)), a plurality of first reset control lines (for example, first reset control lines RST1(i), RST1(i+1), RST1(i+2), and RST1(i+3)), a plurality of second reset control lines (for example, second reset control lines RST2(i), RST2(i+1), RST2(i+2), and RST2(i+3)), and a plurality of first electrodes of storage capacitors of first pixel circuits (for example, first electrodes 391a and 391b). The first scan lines, emission control lines, first reset control lines, and second reset control lines may each be substantially zigzag lines extending along the first direction X.

[0269] FIG27A is a schematic diagram of the first display area after the second conductive layer is formed in FIG23 . FIG27B is a schematic diagram of the second conductive layer in FIG27A . In some examples, as shown in FIG27A and FIG27B , the second conductive layer of the first display area may include at least: a plurality of second auxiliary scan lines (e.g., including second auxiliary scan lines GL2b(i), GL2b(i+1), GL2b(i+2), and GL2b(i+3)), and second electrodes of storage capacitors of a plurality of first pixel circuits (e.g., including second electrodes 392a and 392b). The shape of the second auxiliary scan lines may be roughly a zigzag line extending along the first direction X. In the display island area, the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode of the storage capacitor of the first pixel circuit 11c can be electrically connected through a second plate connecting block 392-2, the side of the second electrode 392a of the storage capacitor of the first pixel circuit 11a away from the first pixel circuit 11b can be connected to another second plate connecting block 392-a, and the side of the second electrode of the storage capacitor of the first pixel circuit 11d away from the first pixel circuit 11c can be electrically connected to another second plate connecting block 392-2.

[0270] Figure 28 is a schematic diagram of the first display area after the second semiconductor layer is formed in Figure 23. In some examples, as shown in Figure 28, the second semiconductor layer of the first display area may include at least: the active layer of the second type transistor of multiple first pixel circuits (for example, including: the second active layer 320a of the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b). In some examples, the positive projection of the blocking layer on the substrate may cover the positive projection of the second semiconductor layer on the substrate. This embodiment is not limited to this. In other examples, the blocking block of the blocking layer can be set to cover the hollow area of ​​the second semiconductor layer, and the active layer of the second transistor is blocked by the second scanning auxiliary line located in the second conductive layer.

[0271] FIG29A is a schematic diagram of the first display area after the third conductive layer is formed in FIG23 . FIG29B is a schematic diagram of the third conductive layer in FIG29A . In some examples, as shown in FIG29A and FIG29B , the third conductive layer in the first display area may include at least: a plurality of second scan lines (e.g., second scan lines GL2(i), GL2(i+1), GL2(i+2), and GL2(i+3)), a plurality of first initial signal lines (e.g., first initial signal lines INIT1(i), INIT1(i+1), INIT1(i+2), and INIT1(i+3)), a plurality of second initial signal lines (e.g., second initial signal lines INIT2(i), INIT2(i+1), INIT2(i+2), and INIT2(i+3)), and a plurality of third initial signal lines (e.g., third initial signal lines INIT3(i), INIT3(i+1), INIT3(i+2), and INIT3(i+3)). The first preliminary signal line, the second scan line, the second preliminary signal line, and the third preliminary signal line may each be substantially in the shape of a zigzag line extending along the first direction X.

[0272] FIG30A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG23 . FIG30B is a schematic diagram of the fourth conductive layer in FIG30A . In some examples, as shown in FIG30A and FIG30B , the fourth conductive layer in the first display area may include at least: a plurality of connecting electrodes (e.g., including first to ninth connecting electrodes 401 to 409, and eleventh to seventeenth connecting electrodes 411 to 417). The plurality of connecting electrodes may be electrically connected to the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer, respectively, through vias extending from the fifth insulating layer to the first insulating layer.

[0273] FIG31 is a schematic diagram of the first display area after the seventh insulating layer is formed in FIG23 . In some examples, as shown in FIG31 , the seventh insulating layer in the first display area may be provided with a plurality of vias, such as vias 41 to 46 (V41 to V46). The seventh and sixth insulating layers within vias 41 to 46 (V41 to V46) may be removed to expose a portion of the surface of the fourth conductive layer.

[0274] FIG32A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG23 . FIG32B is a schematic diagram of the fifth conductive layer in FIG32A . In some examples, as shown in FIG32A and FIG32B , the fifth conductive layer in the first display area may include at least: a plurality of first anode connection electrodes (e.g., first anode connection electrodes 422a, 422b, 422c, and 422d), a plurality of first power connection electrodes (e.g., first power connection electrodes 423a, 423b, and 423c), a plurality of first shielding electrodes (e.g., first shielding electrodes 421a and 421b), a plurality of first data connection electrodes (e.g., first data connection electrodes 424a, 424b, 424c, and 424d), and a plurality of third voltage transmission lines (e.g., third voltage transmission lines 443a and 443b).

[0275] In some examples, the third voltage transmission lines 443a and 443b may be straight lines extending along the second direction Y. The two first shielding electrodes 421a and 421b, the three first power connection electrodes 423a, 423b, and 423c, the four first anode connection electrodes 422a, 422b, 422c, and 422d, and the four first data connection electrodes 424a, 424b, 424c, and 424d may be located between the first voltage transmission lines 443a and 443b. The two first shielding electrodes 421a and 421b, and the three first power connection electrodes 423a, 423b, and 423c may be an integrated structure connected to each other with the third voltage transmission lines 443a and 443b. In this example, the first shielding electrode and the first power connection electrode are connected to each other to realize the transmission of the first voltage signal in the first direction X within the display island area. The third voltage transmission line can be used to realize the transmission of the first voltage signal in the second direction Y within the display island area, thereby forming a mesh structure for transmitting the first voltage signal in the first display area, which can ensure the transmission uniformity of the first voltage signal.

[0276] In some examples, the first power connection electrode 423a can be electrically connected to the fifth connection electrode 405 through the forty-second via V42 to achieve electrical connection with the storage capacitor and the fifth transistor of the first pixel circuit 11a; the first power connection electrode 423b can be electrically connected to the fifteenth connection electrode through the forty-fourth via V44 to achieve electrical connection with the storage capacitor and the fifth transistor of the first pixel circuits 11b and 11c; the first power connection electrode 423c can be electrically connected to the storage capacitor and the fifth transistor of the first pixel circuit 11d.

[0277] In some examples, the first data connection electrodes 424a, 424b, 424c, and 424d can be shaped approximately like a figure 8. The first data connection electrode 424a can be electrically connected to the first connection electrode 401 through a forty-first via hole V41, thereby being electrically connected to the fourth transistor of the first pixel circuit 11a. The first data connection electrode 424b can be electrically connected to the eleventh connection electrode 411 through a forty-fifth via hole V45, thereby being electrically connected to the fourth transistor of the first pixel circuit 11b. The first data connection electrode 424c can be electrically connected to the fourth transistor of the first pixel circuit 11c. The first data connection electrode 424d can be electrically connected to the fourth transistor of the first pixel circuit 11d.

[0278] FIG33 is a schematic diagram of the first display area after the eighth insulating layer is formed in FIG23 . In some examples, as shown in FIG33 , the eighth insulating layer in the first display area may have multiple vias, such as vias 47 through 59 (V47 through V59). The eighth insulating layer within vias 47 through V59 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0279] FIG34A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG23 . FIG34B is a schematic diagram of the sixth conductive layer in FIG34A . In some examples, as shown in FIG34A and FIG34B , the sixth conductive layer in the first display area may include at least: a plurality of data lines (e.g., data lines DL(k-1) to DL(k+7)), a plurality of second anode connection electrodes (e.g., second anode connection electrodes 432a, 432b, 432c, and 432d), a plurality of fourth voltage transmission lines (e.g., fourth voltage transmission lines 444a and 444b), a plurality of first auxiliary electrodes (e.g., first auxiliary electrodes 434a and 434b), and a plurality of second auxiliary electrodes 435.

[0280] In some examples, the shape of the plurality of data lines can be substantially a zigzag line extending along the second direction Y. The data line DL(k) can be electrically connected to the first data connection electrode 424a through the forty-seventh via hole V47 to achieve electrical connection with the first first pixel circuit. The data line DL(k+1) can be electrically connected to the first data connection electrode 424b through the forty-eighth via hole V48 to achieve electrical connection with the second first pixel circuit. The data line DL(k+2) can be electrically connected to the first data connection electrode 424c through the forty-ninth via hole V48 to achieve electrical connection with the third first pixel circuit. The data line DL(k+3) can be electrically connected to the first data connection electrode 424d through the fiftieth via hole V50 to achieve electrical connection with the fourth first pixel circuit.

[0281] In some examples, the fourth voltage transmission lines 444a and 444b may be shaped approximately like a zigzag line extending along the second direction Y. The fourth voltage transmission line 444a may be located between the data lines DL(k-1) and DL(k), and the fourth voltage transmission line 444b may be located between the data lines DL(k+3) and DL(k+4). The fourth voltage transmission line 444a may be electrically connected to the first power connection electrode 423a through a fifty-third via hole V53. The fourth voltage transmission line 444b may be electrically connected to the first power connection electrode 423c through a fifty-fifth via hole V55.

[0282] In some examples, the first auxiliary electrode 434a can be located between the data line DL(k) and the data line DL(k+1), and the first auxiliary electrode 434b can be located between the data line DL(k+2) and the data line DL(k+3). The first auxiliary electrodes 434a and 434b can be shaped substantially like strips extending along the second direction Y. The first auxiliary electrode 434a can be electrically connected to the first shielding electrode 421a through a fifty-first via hole V51, and the first auxiliary electrode 434b can be electrically connected to the first shielding electrode 421b through a fifty-second via hole V52.

[0283] In some examples, the second auxiliary electrode 435 may be located between the data line DL(k+1) and the data line DL(k+2). The shape of the second auxiliary electrode 435 may be substantially a strip structure extending along the second direction Y. The length of the second auxiliary electrode 435 along the first direction X may be less than the length of the first auxiliary electrode 434a along the first direction X. The first auxiliary electrodes 434a and 434b may be substantially symmetrical about the second auxiliary electrode 435. The second auxiliary electrode 435 may be electrically connected to the first power connection electrode 423b through the fifty-fourth via hole V54.

[0284] In this example, by electrically connecting the first auxiliary electrode, the second auxiliary electrode, and the fourth voltage transmission line to the mesh structure transmitting the first voltage signal on the fifth conductive layer, this can help reduce the resistance of the wiring that transmits the first voltage signal, thereby helping to improve the transmission uniformity of the first voltage signal. In this example, the fifth and sixth conductive layers are used to arrange the voltage transmission lines and data lines, which can avoid the problem of having too many wiring lines in the conductive layer close to the anode layer, which would affect the flatness of the anode layer.

[0285] FIG35 is a schematic diagram of the first display area after the ninth insulating layer is formed in FIG23 . In some examples, as shown in FIG35 , the ninth insulating layer in the first display area may have multiple vias, such as vias V61 through V64. The ninth insulating layer within vias V61 through V64 may be removed to expose a portion of the surface of the sixth conductive layer.

[0286] FIG36 is a schematic diagram of the first display area after the anode layer is formed in FIG23 . In some examples, as shown in FIG36 , the anode layer of the first display area may include at least: anodes of multiple first light-emitting elements (e.g., anode 131a of first light-emitting element 13a, anode 131b of first light-emitting element 13b, anode 131c of first light-emitting element 13c, and anode 131d of first light-emitting element 13d), and multiple third anode connecting electrodes (e.g., third anode connecting electrodes 132a, 132b, 132c, and 132d). The remaining structures of the circuit structure layer and the light-emitting structure layer of this example can be referred to the description of the aforementioned embodiments, and therefore will not be repeated here.

[0287] Compared to the second display area, the display substrate of this example uses RGBG as a repeating unit in odd rows and removes RGBG units in even columns at intervals; and uses BGRG as a repeating unit in even rows and removes BGRG units in odd columns at intervals. In this example, the number of first sub-pixels deleted in the first display area accounts for half of the total number of first sub-pixels, and a light-transmitting area is formed at the location where the first sub-pixels are deleted. The wiring between adjacent display islands can be directly connected by metal wires, and the light-transmitting area is designed to avoid the light-transmitting area. This example can improve the light transmittance of the first display area while ensuring the white balance of the light emission of the first display area, so as to meet the size and light transmittance requirements of the under-screen function. For example, taking the pixel density of the second display area as 426 as an example, by deleting the first sub-pixel, the pixel density of the first display area can be reduced to 302, and the aperture ratio of the light-transmitting area can be 31.62%. The aperture ratio of the light-transmitting area refers to the ratio of the area of ​​the light-transmitting area in the first display area to the total area of ​​the first display area. This example can achieve a light transmittance of 16.2% for 550nm light and 19.1% for 940nm light, which can meet the needs of under-screen shooting and under-screen face recognition.

[0288] Figure 37 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 37 illustrates six rows (e.g., rows i to i+5) and three columns (e.g., columns j to j+2) of display islands. In some examples, as shown in Figure 37, the first display area A1 may include: a plurality of display islands A11 and a plurality of light-transmitting areas A12 arranged in an array. The display islands A11 and the light-transmitting areas A12 are arranged alternately in the first direction X, and the plurality of display islands A11 may be arranged continuously and staggered in the second direction Y. The arrangement order of the first light-emitting elements in the plurality of display islands A11 is the same. For a column of display islands, the display islands A11 located in odd rows (e.g., rows i, i+2, and rows i+4) are aligned, and the display islands A11 located in even rows (e.g., rows i+1, i+3, and rows i+5) are aligned. Adjacent display islands A11 in a column of display islands may be staggered.

[0289] In some examples, each display island A11 may include four first sub-pixels, i.e., four first pixel circuits and four first light-emitting elements electrically connected to each other. The offset distance between adjacent display islands in a column of display islands in the first direction X may be greater than or equal to the length of one first pixel circuit in the first direction X and less than or equal to the length of three first pixel circuits in the first direction X. For example, the offset distance L2 between adjacent display islands in a column of display islands in the first direction X may be approximately equal to the length of two first pixel circuits in the first direction X.

[0290] In some examples, adjacent light-transmitting areas A12 in the second direction Y may be staggered in the first direction X. The staggered distance L3 between adjacent light-transmitting areas A12 in the second direction X in the first direction X may be substantially the same as the staggered distance L2, for example, equal to the length of two first pixel circuits in the first direction X. However, this embodiment is not limited thereto.

[0291] Compared with the second display area, the display substrate of this example uses RGBG as a repeating unit in each row, deletes RGBG units at intervals, and staggers the repeating units in adjacent rows. The number of first sub-pixels deleted in the first display area of ​​this example accounts for one-half of the total number of first sub-pixels, and a light-transmitting area is formed at the location where the first sub-pixels are deleted. This example can improve the light transmittance of the first display area while ensuring the white balance of the light emission in the first display area, so as to meet the size and light transmittance requirements of the under-screen function. The rest of the description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0292] Figure 38 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 38 illustrates six rows (e.g., row i to row i+5) and three columns (e.g., column j to column j+2) of display island areas. In some examples, as shown in Figure 38, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The display island areas A11 and the light-transmitting areas A12 are alternately arranged in the first direction X, and the plurality of display island areas A11 are continuously arranged in the second direction Y. The plurality of display island areas A11 within each column of display island areas A11 are aligned. Adjacent light-transmitting areas A12 in the second direction Y may be separated by lateral metal traces.

[0293] In some examples, as shown in Figure 38, the plurality of display islands A11 may include a plurality of first display islands A11a and a plurality of second display islands A11b. In each column of display islands, the first display islands A11a and the second display islands A11b may be arranged alternately.

[0294] Compared to the second display area, the display substrate of this example uses RGBG as a repeating unit in odd-numbered rows, with RGBG units removed at intervals. In even-numbered rows, BGRG is used as a repeating unit, with BGRG units removed at intervals. The data of the first subpixels deleted in the first display area accounts for half of the total number of first subpixels. A light-transmitting area is formed at the location where the first subpixels are deleted. This improves the light transmittance of the first display area while maintaining the white balance of the light emitted by the first display area, thereby meeting the size and light transmittance requirements of the under-screen function. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and is not repeated here.

[0295] Figure 39 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 38 illustrates six rows (e.g., rows i through i+5) and multiple columns of display islands. In some examples, as shown in Figure 38, the first display area A1 may include: a plurality of display islands A11 and a plurality of light-transmitting areas A12 arranged in an array. In the first direction X, the display islands A11 and the light-transmitting areas A12 are alternately arranged and aligned. In the second direction Y, the display islands A11 and the light-transmitting areas A12 are alternately arranged and aligned.

[0296] In some examples, each display island area A11 can include a first sub-pixel, for example, including a first pixel circuit and a first light-emitting element. The multiple display island areas A11 can include: multiple third display island areas A11c, multiple fourth display island areas A11d, and multiple fifth display island areas A11e. The first sub-pixels in the third display island area A11c, the fourth display island area A11d, and the fifth display island area A11e can emit light of different colors. For example, the third display island area A11e can include a first sub-pixel 1a that emits light of the first color, the fourth display island area A11d can include a first sub-pixel 1c that emits light of the second color, and the fifth display island area A11e can include a first sub-pixel 1b or 1d that emits light of the third color.

[0297] In some examples, within the display islands of odd-numbered rows (e.g., row i, row i+2, and row i+4), the third display islands A11c and the fourth display islands A11d may be arranged alternately. Within the display islands of even-numbered rows (e.g., row i+1, row i+3, and row i+5), a plurality of fifth display islands A11e may be arranged. A column of display islands may include: a plurality of third display islands A11c, or a plurality of fourth display islands A11d, or a plurality of fifth display islands A11e. For example, the jth column of display islands includes third display islands A11c arranged alternately with the light-transmitting areas A12, the j+1th column of display islands includes fifth display islands A11e arranged alternately with the light-transmitting areas A12, the j+2th column of display islands includes fourth display islands A11d arranged alternately with the light-transmitting areas A12, and the j+3th column of display islands includes fifth display islands A11e arranged alternately with the light-transmitting areas A12. Multiple columns of display islands are periodically arranged in the order of a column of third display islands, a column of fifth display islands, a column of fourth display islands, and a column of fifth display islands.

[0298] Compared to the second display area, the display substrate of this example uses R and B as a repeating unit in odd-numbered rows, with G units removed at intervals. In even-numbered rows, G is used as a repeating unit, with R and B units removed at intervals. The data of the first subpixels deleted in the first display area accounts for half of the total number of first subpixels. A light-transmitting area is formed at the location where the first subpixels are deleted. This improves the light transmittance of the first display area while maintaining the white balance of the light emitted by the first display area, thereby meeting the size and light transmittance requirements of the under-screen function. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and is not repeated here.

[0299] Figure 40 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 40 illustrates six rows (e.g., row i to row i+5) and three columns (e.g., column j to column j+2) of display islands. In some examples, as shown in Figure 40, the first display area A1 may include: a plurality of display islands A11 and a plurality of light-transmitting areas A12 arranged in an array. The display islands A11 and the light-transmitting areas A12 are alternately arranged in the first direction X, and the plurality of display islands A11 may be arranged continuously in the second direction Y. For a column of display islands, the display islands A11 located in odd rows (e.g., row i, row i+2, and row i+4) are aligned, and the display islands A11 located in even rows (e.g., row i+1, row i+3, and row i+5) are aligned, and adjacent display islands A11 in a column of display islands may be staggered.

[0300] In some examples, the plurality of display islands A11 may include a plurality of first display islands A11a and a plurality of second display islands A11b. In the first direction X, the display islands A11a, the light-transmitting areas A12, the second display islands A11b, and the light-transmitting areas A12 may be periodically arranged in the order of the first display islands A11a, the light-transmitting areas A12, the second display islands A11b, and the light-transmitting areas A12. In each row of display islands, the first display islands A11a and the second display islands A11b may be alternately arranged, and the light-transmitting areas A12 may be arranged between adjacent display islands. The display islands in odd columns (e.g., the jth column, the j+2th column) may include a plurality of first display islands A11a sequentially arranged along the second direction Y, and the display islands in even columns (e.g., the j+1th column) may include a plurality of second display islands A11b sequentially arranged along the second direction Y.

[0301] In some examples, each display island A11 may include three first sub-pixels, i.e., three correspondingly electrically connected first pixel circuits and three first light-emitting elements. The first display island A11a may include: a first sub-pixel 1a emitting first color light, a first sub-pixel 1b emitting third color light, and a first sub-pixel 1c emitting second color light, arranged sequentially along the first direction X. The second display island A11b may include: a first sub-pixel 1c emitting second color light, a first sub-pixel 1d emitting third color light, and a first sub-pixel 1a emitting first color light, arranged sequentially along the first direction X. The first sub-pixels in the first display island A11a and the second display island A12 are arranged in a different order.

[0302] In some examples, the offset distance L4 between adjacent display islands in a column of display islands in the first direction X may be greater than or equal to the length of one first pixel circuit in the first direction X and less than or equal to the length of three first pixel circuits in the first direction X. For example, the offset distance L4 between adjacent display islands in a column of display islands in the first direction X may be substantially equal to the length of two first pixel circuits in the first direction X.

[0303] Compared to the second display area, the display substrate of this example uses RGB as a repeating unit in the odd-numbered column display islands and BGR as a repeating unit in the even-numbered column display islands. GRG units or GBG units are removed between adjacent columns, and light-transmitting areas are formed at the locations where the first sub-pixels are removed. This improves the light transmittance of the first display area while maintaining display white balance. The remaining description of the display substrate of this example can be found in the description of the previous embodiment and is not repeated here.

[0304] FIG41 is another partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. FIG41 illustrates two rows (e.g., row i to row i+1) and five columns (e.g., column j to column j+4) of display islands. In some examples, as shown in FIG41 , the first display area A1 may include: a plurality of display islands A11 and a plurality of light-transmitting areas A12 arranged in an array. The display islands A11 and the light-transmitting areas A12 are arranged alternately in the second direction Y, and the plurality of display islands A11 may be continuously arranged and aligned in the first direction X. Adjacent light-transmitting areas A12 in the first direction X may be separated by longitudinal metal traces.

[0305] In some examples, as shown in FIG41 , the plurality of display islands A11 may include a plurality of first display islands A11a and a plurality of second display islands A11b. The i-th row may include a plurality of first display islands A11a, and the i+1-th row may include a plurality of second display islands A11b. The first display island A11a may include eight first sub-pixels, and the second display island A11b may include eight first sub-pixels. The arrangement order of the first sub-pixels in the first display island A11a may be different from the arrangement order of the first sub-pixels in the second display island A11b. For example, in the first display island A11a, the first sub-pixels 1a, 1b, 1c, and 1d may be arranged in the first row, and the first sub-pixels 1c, 1d, 1a, and 1b may be arranged in the second row; in the second display island A11b, the first sub-pixels 1c, 1d, 1a, and 1b may be arranged in the first row, and the first sub-pixels 1a, 1b, 1c, and 1d may be arranged in the second row.

[0306] Compared to the second display area, the display substrate of this example removes the RGRB repeating unit in every other row, forming a light-transmitting area at the location where the first sub-pixel is removed. This improves the light transmittance of the first display area while maintaining the white balance of the light emission in the first display area, thus meeting the size and light transmittance requirements of the under-display function. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and is not repeated here.

[0307] This embodiment also provides a display substrate, comprising: a first display area and a second display area at least located on one side of the first display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area. The first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; the display island areas and the light-transmitting areas are alternately arranged in the row direction, or the display island areas and the light-transmitting areas are alternately arranged in the column direction. The display island area comprises at least: n first pixel circuits arranged along the row direction, where n is a positive integer greater than 0; the first pixel circuits in adjacent display island areas in the column direction are staggered, and the staggered distance between adjacent display island areas in the row direction is greater than or equal to the length of one first pixel circuit in the row direction and less than or equal to the length of n first pixel circuits in the row direction. In some examples, n can be 1, or n can be 3, or n can be 4.

[0308] The display substrate provided in this embodiment adopts a built-in pixel circuit method, and alternately arranges display island areas and light-transmitting areas in the row direction or column direction within the first display area. This can improve the light transmittance of the first display area and realize the under-screen functional requirements while meeting the display white balance. For example, the aperture of the first display area can be expanded and under-screen camera or under-screen face recognition and other functional requirements can be realized simultaneously.

[0309] In some exemplary embodiments, in the column direction, the light-transmitting region is aligned with half of the area of ​​the adjacent display island region. This example can refer to the description of the embodiment shown in FIG5 .

[0310] In some examples, each display island region may further include: n first light-emitting elements electrically connected to the n first pixel circuits in a one-to-one correspondence. The multiple display island regions include: multiple first display island regions and multiple second display island regions; the odd-numbered column display island regions include: multiple first display island regions arranged sequentially along the column direction, and the even-numbered column display island regions include: multiple second display island regions arranged sequentially along the column direction; the arrangement order of the n first light-emitting elements included in the first display island regions is different from the arrangement order of the n first light-emitting elements included in the second display island regions. The display substrate of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0311] Figure 42 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 42, this embodiment provides a display device comprising: a display substrate 91; and a sensor 92 located on the light-emitting side of the light-emitting structure layer, away from the display substrate 91. Sensor 92 may be located on the non-display surface of the display substrate 91. The orthographic projection of sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0312] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0313] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: A first display area, the first display area comprising: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; the first display area satisfies at least one of the following conditions: the display island areas and the light-transmitting areas are alternately arranged in a row direction, and the display island areas and the light-transmitting areas are alternately arranged in a column direction; The display island region includes: at least one first pixel circuit and at least one first light-emitting element. The at least one first pixel circuit is electrically connected to the at least one first light-emitting element and is configured to drive the at least one first light-emitting element to emit light.

2. The display substrate according to claim 1, wherein: In the row direction, the display island areas and the light-transmitting areas are alternately arranged and aligned; in the column direction, the multiple display island areas are continuously and staggeredly arranged, or the multiple display island areas are continuously and aligned, or the display island areas and the light-transmitting areas are alternately arranged and aligned.

3. The display substrate according to claim 2, wherein: For a column of display islands, the display islands located in odd-numbered rows are aligned, and the display islands located in even-numbered rows are aligned; adjacent display islands in a column of display islands are staggered.

4. The display substrate according to claim 3, wherein: The display island area comprises: a first pixel circuits arranged in sequence along the row direction, where a is an integer greater than 1; The offset distance between adjacent display islands in a column of display islands in the row direction is greater than or equal to the length of one first pixel circuit in the row direction and less than or equal to the length of a-1 first pixel circuits in the row direction.

5. The display substrate according to claim 3, wherein: Each display island region located in the jth column has a first edge close to the display island region in the j-1th column and a second edge close to the display island region in the j+1th column in the row direction; A midline of the display island area located at the i-th row and the j-th column in the row direction is aligned with a first edge of the display island area located at the i+1-th row and the j-th column; The center line of the display island area located at the i+1th row and jth column in the row direction is aligned with the second edge of the display island area located at the ith row and jth column; wherein i and j are both integers greater than 0.

6. The display substrate according to claim 3, wherein: In the column direction, the light-transmitting area is aligned with a half area of ​​an adjacent display island area.

7. The display substrate according to any one of claims 3 to 6, wherein: The plurality of display island regions include: a plurality of first display island regions and a plurality of second display island regions; The odd-numbered column display island regions include a plurality of first display island regions sequentially arranged along the column direction, and the even-numbered column display island regions include a plurality of second display island regions sequentially arranged along the column direction; An arrangement order of the plurality of first light emitting elements included in the first display island region is different from an arrangement order of the plurality of first light emitting elements included in the second display island region.

8. The display substrate according to claim 4, wherein: The light-transmitting regions adjacent to each other in the column direction are arranged in a staggered manner in the row direction.

9. The display substrate according to claim 8, wherein: The offset distance between adjacent light-transmitting areas in the column direction in the row direction is greater than or equal to the length of a first pixel circuit in the row direction, and less than or equal to the length of a-1 first pixel circuits in the row direction.

10. The display substrate according to claim 8 or 9, wherein: The display island region includes a plurality of first light emitting elements, and the plurality of first light emitting elements in the plurality of display island regions are arranged in the same manner.

11. The display substrate according to claim 2, wherein: In the row direction, the display island regions and the light-transmitting regions are alternately arranged and aligned, and in the column direction, the display island regions and the light-transmitting regions are alternately arranged and aligned; The plurality of display island regions include: a plurality of first display island regions and a plurality of second display island regions; The odd-numbered columns of display island regions include: a plurality of first display island regions alternately arranged with the light-transmitting regions along the column direction; the even-numbered columns include: a plurality of second display island regions alternately arranged with the light-transmitting regions along the column direction; An arrangement order of the plurality of first light emitting elements included in the first display island region is different from an arrangement order of the plurality of first light emitting elements included in the second display island region.

12. The display substrate according to claim 7 or 11, wherein: Each display island region comprises four first pixel circuits sequentially arranged along a row direction, and four first light-emitting elements electrically connected to the four first pixel circuits in a one-to-one correspondence, wherein the orthographic projection of the first light-emitting element on the substrate at least partially overlaps with the orthographic projection of the connected first pixel circuit on the substrate; The four first light-emitting elements include: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and two first light-emitting elements emitting a third color light; The arrangement order of the first light emitting elements emitting the first color light and the first light emitting elements emitting the second color light in the first display island area is opposite to the arrangement order of the first light emitting elements emitting the first color light and the first light emitting elements emitting the second color light in the second display island area.

13. The display substrate according to claim 2, wherein: In the row direction, the display island regions and the light-transmitting regions are alternately arranged and aligned, and in the column direction, the display island regions and the light-transmitting regions are alternately arranged and aligned; each display island region includes a first pixel circuit and a first light-emitting element; The multiple display island areas include: multiple third display island areas, multiple fourth display island areas and multiple fifth display island areas; the odd-numbered row display island areas include: multiple third display island areas and multiple fourth display island areas arranged alternately; the even-numbered row display island areas include: multiple fifth display island areas; the first light-emitting elements in the third display island areas, the fourth display island areas and the fifth display island areas emit light of different colors.

14. The display substrate according to claim 13, wherein: The third display island area includes: a first light emitting element emitting a first color light; the fourth display island area includes: a first light emitting element emitting a second color light; the fifth display island area includes: a first light emitting element emitting a third color light.

15. The display substrate according to any one of claims 1 to 14, further comprising: A second display area located on at least one side of the first display area; wherein the second display area includes: at least one second pixel circuit and at least one second light-emitting element, the at least one second pixel circuit is electrically connected to the at least one second light-emitting element and configured to drive the at least one second light-emitting element to emit light; the arrangement density of the first pixel circuits in the first display area is less than the arrangement density of the second pixel circuits in the second display area.

16. The display substrate according to claim 15, wherein: The arrangement density of the first pixel circuits in the first display area in the row direction is 1 / 2 or 1 / 3 of the arrangement density of the second pixel circuits in the second display area in the row direction.

17. The display substrate according to any one of claims 1 to 16, wherein: In a direction perpendicular to the display substrate, the display substrate comprises: a substrate, and a circuit structure layer and a light emitting structure layer located on the substrate; the circuit structure layer comprises: a plurality of first pixel circuits, the first pixel circuits comprising: at least one first type transistor, at least one second type transistor and a storage capacitor; The circuit structure layer at least includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer arranged on the substrate; The first semiconductor layer includes at least: an active layer of a first type transistor of the first pixel circuit; The first conductive layer at least includes: a gate of a first type transistor of the first pixel circuit and a first electrode of a storage capacitor; The second conductive layer at least includes: a second electrode of the storage capacitor of the first pixel circuit and a bottom gate of the second type transistor; The second semiconductor layer at least includes: an active layer of a second type transistor of the first pixel circuit; The third conductive layer at least includes: a gate of the second type transistor of the first pixel circuit; The fourth conductive layer at least includes: a plurality of connecting electrodes.

18. The display substrate according to claim 17, wherein: The circuit structure layer further includes: a fifth conductive layer and a sixth conductive layer located on a side of the fourth conductive layer away from the substrate; The fifth conductive layer at least includes: a plurality of data lines; the sixth conductive layer at least includes: a voltage transmission line; or the fifth conductive layer at least includes: a voltage transmission line, and the sixth conductive layer at least includes: a plurality of data lines.

19. The display substrate according to claim 17, wherein: The circuit structure layer further includes: a shielding layer located on a side of the first semiconductor layer close to the substrate; The orthographic projection of the shielding layer on the substrate covers the orthographic projection of the first semiconductor layer on the substrate; or, the orthographic projection of the shielding layer on the substrate covers the orthographic projections of the first semiconductor layer and the second semiconductor layer on the substrate.

20. A display device, comprising a display substrate as claimed in any one of claims 1 to 19, and a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate at least partially overlaps with a first display area of ​​the display substrate.

21. A display substrate, comprising: a first display area and a second display area at least located on one side of the first display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area, and the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; the display island areas and the light-transmitting areas are alternately arranged in a row direction, or the display island areas and the light-transmitting areas are alternately arranged in a column direction; The display island area at least includes: n first pixel circuits arranged along the row direction, where n is a positive integer greater than 0; The first pixel circuits in adjacent display islands in the column direction are staggered, and the staggered distance of the adjacent display islands in the row direction is greater than or equal to the length of one first pixel circuit in the row direction and less than or equal to the length of n first pixel circuits in the row direction.

22. The display substrate according to claim 21, wherein: In the column direction, the light-transmitting area is aligned with a half area of ​​an adjacent display island area.

23. The display substrate according to claim 21, wherein: Each display island area further includes: n first light emitting elements electrically connected to the n first pixel circuits in a one-to-one correspondence; The plurality of display island regions include: a plurality of first display island regions and a plurality of second display island regions; The odd-numbered column display islands include: a plurality of first display islands arranged in sequence along the column direction; the even-numbered column display islands include: a plurality of second display islands arranged in sequence along the column direction; An arrangement order of the n first light emitting elements included in the first display island area is different from an arrangement order of the n first light emitting elements included in the second display island area.

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