Ultrasonic detection device

Abstract

The present invention relates to an ultrasonic detection device, which is built inside a set of neck card bodies and includes a drive signal forming unit for receiving externally input control information and forming and outputting an ultrasonic signal matching the control information according to the control information; a control signal forming circuit for receiving the control information and forming and outputting a transmission timing control signal matching the control information according to the control information; a drive signal forming circuit for receiving the transmission timing control signal and forming a drive logic signal according to the transmission timing control signal; a high-voltage pulse forming circuit for receiving the drive logic signal and forming and outputting a high-voltage drive signal; and collecting a feedback signal formed based on the ultrasonic signal and forming and outputting a display signal matching the feedback signal according to the feedback signal.

Description

Technical Field

[0001] The present invention relates to the medical field, and particularly to an ultrasonic detection device. Background Art

[0002] Tracheotomy is a surgical operation that creates a stoma in the anterior wall of the trachea in the neck through surgery and inserts a tracheal cannula to establish a temporary or long-term artificial airway. It is mainly used to solve patients with upper airway obstruction or those who require long-term mechanical ventilation to ensure unobstructed gas exchange. There are mainly two types: traditional surgical tracheotomy and percutaneous tracheotomy. Percutaneous tracheotomy is increasingly widely used clinically due to its advantages such as small trauma, fast recovery, convenient operation, and short operation time. However, due to individual differences, the operator needs to use ultrasonic positioning before the operation and then perform blind puncture, or the operator holds an ultrasonic detection device in one hand and a puncture needle in the other hand to puncture into the trachea. Such an operation lacks stability and has relatively large potential safety hazards. Summary of the Invention

[0003] In view of the deficiencies of the prior art, the present invention provides an ultrasonic detection device that is convenient to use and improves the stability and safety of the operation. Specifically:

[0004] An ultrasonic detection device, which is built inside a neck card body and includes:

[0005] A drive signal forming unit, which is used to receive externally input control information and form and output an ultrasonic signal that matches the control information; specifically includes:

[0006] A control signal forming circuit, which is used to receive the control information and form and output a transmission timing control signal that matches the control information;

[0007] A drive signal forming circuit, which is used to receive the transmission timing control signal and form the drive logic signal according to the transmission timing control signal;

[0008] A high-voltage pulse forming circuit, which is used to receive the drive logic signal and form and output a high-voltage drive signal according to the drive logic signal; the high-voltage drive signal includes a first high-voltage drive sub-signal and a second high-voltage drive sub-signal.

[0009] A first energy conversion circuit, which is used to receive the high-voltage drive signal and form and output the ultrasonic signal that matches the control information according to the high-voltage drive signal.

[0010] A receiving unit, which collects a feedback signal formed based on the ultrasonic signal and forms and outputs a display signal that matches the feedback signal.

[0011] Preferably, for an ultrasonic detection device as described above, the drive signal forming circuit includes: a first operational amplifier U3, the non-inverting input terminal of the first operational amplifier U3 is connected to the first output terminal EPT50+ of the drive signal forming unit, and the inverting input terminal of the first operational amplifier U3 is grounded through a first resistor R11 and connected to a first power supply +5V through a second resistor R12; the output terminal of the first operational amplifier U3 forms an output of a first emission timing control sub-signal; wherein the first operational amplifier U3 amplifies the first output terminal EPT50+ of the drive signal forming unit to form a first emission timing control sub-signal;

[0012] a second operational amplifier U2, the non-inverting input terminal of the second operational amplifier U2 is connected to the second output terminal EPT50- of the drive signal forming unit, and the inverting input terminal of the second operational amplifier U2 is connected to the first power supply +5V through a third resistor R8 and grounded through a fourth resistor R9; the output terminal of the second operational amplifier U2 forms an output of a second emission timing control sub-signal; wherein the second operational amplifier U2 amplifies the second output terminal EPT50- of the drive signal forming unit to form a second emission timing control sub-signal.

[0013] Preferably, for an ultrasonic detection device as described above, the non-inverting input terminal of the first operational amplifier U3 is connected to the first output terminal EPT50+ of the drive signal forming unit through a first capacitor C16, and at the same time, the first output terminal EPT50+ of the drive signal forming unit is grounded through a fifth resistor R13;

[0014] the non-inverting input terminal of the second operational amplifier U2 is connected to the second output terminal EPT50- of the drive signal forming unit through a second capacitor C11, and at the same time, the second output terminal EPT50- of the drive signal forming unit is connected to the first power supply +5V through a sixth resistor R10, and the second capacitor C11 and the sixth resistor R10 also form a low-pass filter RC circuit.

[0015] Preferably, for an ultrasonic detection device as described above, a first decoupling circuit is connected between the power supply terminal and the ground terminal of the first operational amplifier U3, the power supply terminal of the first operational amplifier U3 is connected to the first power supply +5V, the ground terminal of the first operational amplifier U3 is connected to the common ground, and the first decoupling circuit is formed by the parallel connection of a third capacitor C14 and a fourth capacitor C15,

[0016] a second decoupling circuit is connected between the power supply terminal and the ground terminal of the second operational amplifier U2, the power supply terminal of the second operational amplifier U2 is connected to the first power supply +5V, the ground terminal of the second operational amplifier U2 is connected to the common ground, and the second decoupling circuit is formed by the parallel connection of a fifth capacitor C12 and a sixth capacitor C13.

[0017] Preferably, in an ultrasonic detection device as described above, the high-voltage pulse forming circuit includes a third integrated circuit U4 and a fourth integrated circuit U5.

[0018] The input terminal IN pin of the third integrated circuit U4 receives the first emission timing control sub-signal. The OE pin of the third integrated circuit U4 is connected to the second power supply of 10V through a seventh resistor R14. The VS + pins of the third integrated circuit U4 are respectively connected to the second power supply of 10V and grounded through a fifth capacitor C17. The GND pin of the third integrated circuit U4 is respectively connected to the VS - pin, the VL pin of the third integrated circuit U4 and grounded. The OUT pin of the third integrated circuit U4 forms the output terminal of the third integrated circuit U4 to output a first high-voltage drive sub-signal.

[0019] The input terminal of the fourth integrated circuit U5 receives the second emission timing control sub-signal. The OE pin of the fourth integrated circuit U5 is connected to the second power supply of 10V through an eighth resistor R15. The VS + pins of the fourth integrated circuit U5 are respectively connected to the second power supply of 10V, the VH pin, and grounded through a sixth capacitor C19. The GND pin of the fourth integrated circuit U5 is respectively connected to the VS - pin, the VL pin of the fourth integrated circuit U5 and grounded. The OUT pin of the fourth integrated circuit U5 forms the output terminal of the fourth integrated circuit U5 to output a second high-voltage drive sub-signal.

[0020] Preferably, in an ultrasonic detection device as described above, the first energy conversion circuit includes:

[0021] A first energy conversion sub-circuit, the first energy conversion sub-circuit includes a first PMOS transistor. The gate of the first PMOS transistor is connected to the OUT pin of the third integrated circuit U4 through a seventh capacitor C18, and a first current-limiting resistor R16 is connected to the source of the first PMOS transistor. The source of the first PMOS transistor is connected to the +10V pin through a tenth resistor R17, connected to the common ground through a first emission filtering circuit, and connected to the common ground through a first DC voltage stabilizing circuit. The drain of the first PMOS transistor is connected to the input terminal of the ultrasonic output device through a first diode D3. Wherein the first emission filtering circuit is formed by the parallel connection of a ninth capacitor C21 and a tenth capacitor TC2.

[0022] The second energy conversion sub-circuit, the second energy conversion sub-circuit includes a second NMOS transistor, the gate of the second NMOS transistor is connected to the OUT pin of the fourth integrated circuit U5 through the eighth capacitor C20, the second current-limiting resistor R19 is connected to the source of the second NMOS transistor, the source of the second NMOS transistor is connected to the -10V pin through the eleventh resistor R18, connected to the common ground through the second emission filtering circuit, connected to the common ground through the second DC voltage regulation circuit, the drain of the second NMOS transistor is connected to the input end of the ultrasonic output device through the second diode D4; wherein the second emission filtering circuit is formed by the parallel connection of the eleventh capacitor C22 and the twelfth capacitor TC3.

[0023] Preferably, in the above ultrasonic detection device, the driving signal forming unit further includes: a first suppression circuit, connected to the energy conversion unit, specifically including:

[0024] The first inverter U6A, the input end of the first inverter U6A is connected to the RTZ signal output from the 56th pin of the STM32F405RGT6 chip, and the output end is connected to the input end of the fifth integrated circuit U7.

[0025] The second inverter U6B, the input end of the second inverter U6B is connected to the output end of the first inverter U6A, and the output end of the second inverter U6B is connected to the input end of the sixth integrated circuit U8.

[0026] The OE pin of the fifth integrated circuit U7 is connected to the second power supply 10V through the twelfth resistor R21, the VS+ pin of the fifth integrated circuit U7 is respectively connected to the VH pin of the fifth integrated circuit U7 and the second power supply 10V, and the connection point formed by the VS+ pin and the VH pin of the fifth integrated circuit U7 is grounded through the filtering capacitor C24; the VL pin, the VS- pin and the GND pin of the fifth integrated circuit U7 are all grounded, and the OE pin OUT pin of the fifth integrated circuit U7 is connected to the gate of the third MOS transistor Q3.

[0027] The OE pin of the sixth integrated circuit U8 is connected to the second power supply 10V through the thirteenth resistor R22, the VS+ pin of the sixth integrated circuit U8 is respectively connected to the VH pin of the sixth integrated circuit U8 and the second power supply 10V, and the connection point formed by the VS+ pin and the VH pin of the sixth integrated circuit U8 is grounded through the filtering capacitor C24; the VL pin, the VS- pin and the GND pin of the sixth integrated circuit U8 are all grounded, the OE pin OUT pin of the sixth integrated circuit U8 is connected to the gate of the fourth MOS transistor Q4, and the drain of the fourth MOS transistor Q4 is connected to the drain of the third MOS transistor Q3.

[0028] Preferably, in the above ultrasonic detection device, the receiving unit specifically includes:

[0029] A preamplifier, which includes three - stage amplification by the first triode Q5, the second triode Q6, and the third triode Q7, and is used to amplify the weak feedback signal to form an amplified echo signal for output. Specifically, it includes:

[0030] The first triode Q5, the acquisition unit is connected to the base of the first triode. The collector of the first triode is respectively connected to the base of the second triode and connected to the third voltage 15V through the echo first resistor R28. The emitter of the first triode is connected to the fourth power supply - 5V through the echo second resistor R25 and the echo third resistor R26;

[0031] The collector of the second triode Q6 is connected to the third voltage 15V through the echo fourth resistor R29. The emitter of the second triode is grounded through the echo fifth resistor R30, and the emitter of the second triode is connected to the base of the third triode through the echo sixth resistor R31;

[0032] The collector of the third triode Q7 is connected to the third voltage 15V. The emitter of the third triode Q7 is grounded through the echo sixth resistor R32 and connected to the connection point of the echo second resistor R25 and the echo third resistor R26 through the echo seventh resistor R27. The echo seventh resistor R27 is equivalent to a feedback resistor, and the emitter of the third triode Q7 forms the output end of the preamplifier.

[0033] Preferably, in the above ultrasonic detection device, it further includes:

[0034] A detection circuit, including a detection coupling capacitor C31, which is used to receive the amplified echo signal,

[0035] A detection filtering circuit, formed by a detection inductor L1 and a free - wheeling diode D18,

[0036] A detection comparator U9. The inverting terminal of the detection comparator U9 is connected to the output end of the detection filtering circuit through the fourteenth resistor R36. The non - inverting terminal of the detection comparator U9 is connected to the output end of the detection filtering circuit through the fifteenth resistor R38 and the sixteenth resistor R37. The output end of the detection comparator U9 is connected to the inverting terminal of the detection comparator U9 through a detection feedback circuit to form a negative feedback network.

[0037] Preferably, in the above ultrasonic detection device, a second conversion circuit is further included. The second conversion circuit includes a second conversion comparator U10. The inverting terminal of the second conversion comparator U10 is connected to the output terminal of the detection comparator U9. The non-inverting terminal of the second conversion comparator U10 is connected to the REFL pin of the seventh integrated circuit U11 through a first conversion resistor R42. The output terminal of the second conversion comparator is connected to the input pin of the seventh integrated circuit U11.

[0038] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0039] In the above ultrasonic detection device, since it is built inside a neck card body, during the operation, the neck card body is fixed to the target area of the patient's neck, and the image of the subcutaneous detection area is obtained through the real-time detection of the ultrasonic detection device. Specifically, the drive signal forming unit is used to receive the externally input control information and form and output an ultrasonic signal matching the control information according to the control information. Specifically, it includes a control signal forming circuit for receiving the control information and forming and outputting a transmission timing control signal matching the control information according to the control information; a drive signal forming circuit for receiving the transmission timing control signal and forming the drive logic signal according to the transmission timing control signal. A high-voltage pulse forming circuit is used to receive the drive logic signal and form and output a high-voltage drive signal according to the drive logic signal; a first energy conversion circuit is used to receive the high-voltage drive signal and form and output the ultrasonic signal matching the control information according to the high-voltage drive signal; the ultrasonic signal acts on the patient's neck to form a feedback signal, and the receiving unit collects the feedback signal formed based on the ultrasonic signal and forms and outputs a display signal matching the feedback signal; the surgical operator performs the surgical operation according to the display signal. This method greatly improves the safety and stability of the operation. Description of the Drawings

[0040] Figure 1 It is the circuit diagram of the drive signal forming circuit in an ultrasonic detection device provided by an embodiment of the present invention;

[0041] Figure 2 It is the circuit diagram of the high-voltage pulse forming circuit in an ultrasonic detection device provided by an embodiment of the present invention;

[0042] Figure 3 It is the circuit diagram of the first energy conversion circuit in an ultrasonic detection device provided by an embodiment of the present invention;

[0043] Figure 4 It is the circuit diagram of the first suppression circuit in an ultrasonic detection device provided by an embodiment of the present invention;

[0044] Figure 5 The circuit diagram of the preamplifier in an ultrasonic detection device provided by an embodiment of the present invention;

[0045] Figure 6 The circuit diagram of the detection circuit in an ultrasonic detection device provided by an embodiment of the present invention;

[0046] Figure 7 The circuit diagram of the second conversion comparator in an ultrasonic detection device provided by an embodiment of the present invention. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0048] An ultrasonic detection device, which is built inside a set of neck card bodies and includes

[0049] A driving signal forming unit for receiving externally input control information and forming and outputting an ultrasonic signal matching the control information; specifically including

[0050] A control signal forming circuit for receiving the control information and forming and outputting a transmission timing control signal matching the control information; where the externally input control information at least includes preset imaging parameter signals, such as frequency signals and pulse signals, and the control signal forming circuit forms a transmission timing control signal according to the preset imaging parameter signals. Schematically, the control signal forming circuit can be formed by an STM32F405RGT6 chip. The 58th pin of the STM32F405RGT6 chip outputs the EPT50+ signal, and the 57th pin outputs the EPT50- signal. The EPT50+ signal and the EPT50- signal are the transmission timing control signals. Among them, the EPT50+ forms the first output end of the driving signal forming unit, and the EPT50- forms the second output end of the driving signal forming unit.

[0051] A driving signal forming circuit for receiving the transmission timing control signal and forming the driving logic signal according to the transmission timing control signal. The driving signal forming circuit specifically includes:

[0052] Such as Figure 1As shown, there is a first operational amplifier U3. The positive input terminal of the first operational amplifier U3 is connected to the first output terminal EPT50+ of the drive signal forming unit. The negative input terminal of the first operational amplifier U3 is grounded through a first resistor R11 and connected to a first power supply +5V through a second resistor R12. The output terminal of the first operational amplifier U3 forms an output of a first emission timing control sub-signal. Among them, the first operational amplifier U3 amplifies the first output terminal EPT50+ of the drive signal forming unit to form a first emission timing control sub-signal.

[0053] There is a second operational amplifier U2. The positive input terminal of the second operational amplifier U2 is connected to the second output terminal EPT50- of the drive signal forming unit. The negative input terminal of the second operational amplifier U2 is connected to the first power supply +5V through a third resistor R8 and grounded through a fourth resistor R9. The output terminal of the second operational amplifier U2 forms an output of a second emission timing control sub-signal. Among them, the second operational amplifier U2 amplifies the second output terminal EPT50- of the drive signal forming unit to form a second emission timing control sub-signal.

[0054] In the above drive signal forming circuit, the first resistor R11 and the second resistor R12 are used to set the gain of the first operational amplifier U3. By adjusting the first resistor R11 and the second resistor R12, an output of a first emission timing control sub-signal that matches the subsequent circuit is formed. Similarly, the third resistor R8 and the fourth resistor R9 are used to set the gain of the second operational amplifier U2. By adjusting the third resistor R8 and the fourth resistor R9, an output of a second emission timing control sub-signal that matches the subsequent circuit is formed.

[0055] To further improve the stability of the drive signal forming circuit, on the basis of the above embodiment, it further includes:

[0056] The positive input terminal of the first operational amplifier U3 is connected to the first output terminal EPT50+ of the drive signal forming unit through a first capacitor C16. At the same time, the first output terminal EPT50+ of the drive signal forming unit is grounded through a fifth resistor R13. The first capacitor C16 and the fifth resistor R13 form a low-pass filter RC circuit. Through the first capacitor C16 and the fifth resistor R13, it is intended to remove high-frequency noise in the EPT50+ signal to form a stable first emission timing control sub-signal.

[0057] Similarly, the positive input terminal of the second operational amplifier U2 is connected to the second output terminal EPT50- of the drive signal forming unit through the second capacitor C11. At the same time, the second output terminal EPT50- of the drive signal forming unit is connected to the first power supply +5V through the sixth resistor R10. The second capacitor C11 and the sixth resistor R10 also form a low-pass filter RC circuit. Through the second capacitor C11 and the sixth resistor R10, it is intended to remove the high-frequency noise in the EPT50- signal to form a stable second emission timing control sub-signal.

[0058] To further improve the stability of the drive signal forming circuit, on the basis of the above embodiment, schematically, it further includes:

[0059] A first decoupling circuit is connected between the power supply terminal and the ground terminal of the first operational amplifier U3. The power supply terminal of the first operational amplifier U3 is connected to the first power supply +5V, and the ground terminal of the first operational amplifier U3 is connected to the common ground. The first decoupling circuit is formed by the parallel connection of the third capacitor C14 and the fourth capacitor C15. The first decoupling circuit is intended to absorb the ripple and high-frequency noise in the first power supply +5V, so that the first operational amplifier U3 obtains a stable power supply voltage and avoids abnormal operation of the first operational amplifier U3 due to voltage fluctuations.

[0060] A second decoupling circuit is connected between the power supply terminal and the ground terminal of the second operational amplifier U2. The power supply terminal of the second operational amplifier U2 is connected to the first power supply +5V, and the ground terminal of the second operational amplifier U2 is connected to the common ground. The second decoupling circuit is formed by the parallel connection of the fifth capacitor C12 and the sixth capacitor C13. The second decoupling circuit is intended to absorb the ripple and high-frequency noise in the first power supply +5V, so that the second operational amplifier U2 obtains a stable power supply voltage and avoids abnormal operation of the second operational amplifier U2 due to voltage fluctuations.

[0061] A high-voltage pulse forming circuit is used to receive the drive logic signal and form a high-voltage drive signal output according to the drive logic signal; the high-voltage drive signal includes a first high-voltage drive sub-signal and a second high-voltage drive sub-signal. Schematically, as Figure 2 shown, the high-voltage pulse forming circuit includes a third integrated circuit U4 and a fourth integrated circuit U5.

[0062] The input terminal IN pin of the third integrated circuit U4 receives the first emission timing control sub-signal, and is intended to convert the low-voltage first emission timing control sub-signal into a first high-voltage drive sub-signal output; the OE pin of the third integrated circuit U4 is connected to the second power supply 10V through the seventh resistor R14, and the VS of the third integrated circuit U4 +The pins are respectively connected to the second power supply of 10V and grounded through the fifth capacitor C17; the GND pins of the third integrated circuit U4 are respectively connected to the VS - pin of the third integrated circuit U4, the VL pin of the third integrated circuit U4 and grounded. The OUT pin of the third integrated circuit U4 forms the output end of the third integrated circuit U4 to output the first high-voltage drive sub-signal;

[0063] The input end of the fourth integrated circuit U5 receives the second emission timing control sub-signal, aiming to convert the low-voltage second emission timing control sub-signal into a second high-voltage drive sub-signal for output; the OE pin of the fourth integrated circuit U5 is connected to the second power supply of 10V through the eighth resistor R15, and the VS + pins of the fourth integrated circuit U5 are respectively connected to the second power supply of 10V and grounded through the sixth capacitor C19; the GND pins of the fourth integrated circuit U5 are respectively connected to the VS - pin of the fourth integrated circuit U5, the VL pin of the fourth integrated circuit U5 and grounded. The OUT pin of the fourth integrated circuit U5 forms the output end of the fourth integrated circuit U5 to output the second high-voltage drive sub-signal.

[0064] The seventh resistor R14 and the fifth capacitor C17, the eighth resistor R15 and the sixth capacitor C19 are both decoupling circuits, aiming to filter out the high-frequency noise in the second power supply of 10V, so that the third integrated circuit U4 and the fourth integrated circuit U5 obtain stable voltages and reduce the influence of the fluctuation of the second power supply of 10V on the third integrated circuit U4 and the fourth integrated circuit U5. It should be noted that the third integrated circuit and the fourth integrated circuit can both be operational amplifiers.

[0065] The high-voltage pulse forming circuit is formed by the third integrated circuit U4 and the fourth integrated circuit U5. The third integrated circuit U4 and the fourth integrated circuit U5 are relatively small in size and easy to be designed in a miniaturized manner.

[0066] The first energy conversion circuit is used to receive the high-voltage drive signal and form and output the ultrasonic signal matching the control information according to the high-voltage drive signal; specifically, it includes,

[0067] Such as Figure 3As shown, a first energy conversion sub-circuit, the first energy conversion sub-circuit includes a first PMOS transistor. The gate of the first PMOS transistor is connected to the OUT pin of the third integrated circuit U4 through the seventh capacitor C18, and the first current-limiting resistor R16 is connected to the source of the first PMOS transistor. The source of the first PMOS transistor is connected to the +10V pin through the tenth resistor R17, connected to the common ground through the first emission filtering circuit, and connected to the common ground through the first DC voltage regulation circuit. The drain of the first PMOS transistor is connected to the input end of the ultrasonic output device through the first diode D3. Among them, the first emission filtering circuit is formed by the parallel connection of the ninth capacitor C21 and the tenth capacitor TC2, and the first DC voltage regulation circuit is formed by three series-connected diodes. The first diode D3 is a protection diode, aiming to prevent the circuit from being damaged due to overvoltage or overcurrent. The seventh capacitor C18 aims to filter out the high-frequency noise in the first high-voltage drive sub-signal to ensure the stable operation of the circuit. The first current-limiting resistor R16 aims to achieve the functions of current limiting, voltage division, and biasing, prevent the first PMOS transistor from overcurrent, and at the same time combine with the tenth resistor R17 to achieve voltage division to provide a suitable bias voltage to drive the first PMOS transistor to conduct or cut off.

[0068] A second energy conversion sub-circuit, the second energy conversion sub-circuit includes a second NMOS transistor. The gate of the second NMOS transistor is connected to the OUT pin of the fourth integrated circuit U5 through the eighth capacitor C20, and the second current-limiting resistor R19 is connected to the source of the second NMOS transistor. The source of the second NMOS transistor is connected to the -10V pin through the eleventh resistor R18, connected to the common ground through the second emission filtering circuit, and connected to the common ground through the second DC voltage regulation circuit. The drain of the second NMOS transistor is connected to the input end of the ultrasonic output device through the second diode D4. Among them, the second emission filtering circuit is formed by the parallel connection of the eleventh capacitor C22 and the twelfth capacitor TC3, and the first DC voltage regulation circuit is formed by three series-connected diodes. The second diode D4 is a protection diode, aiming to prevent the circuit from being damaged due to overvoltage or overcurrent. The eighth capacitor C20 aims to filter out the high-frequency noise in the second high-voltage drive sub-signal to ensure the stable operation of the circuit. The second current-limiting resistor R19 aims to achieve the functions of current limiting, voltage division, and biasing, prevent the second NMOS transistor from overcurrent, and at the same time combine with the eleventh resistor R18 to achieve voltage division to provide a suitable bias voltage to drive the second NMOS transistor to conduct or cut off.

[0069] The first energy conversion circuit aims to achieve the function of transmitting ultrasonic signals, and forms a drive signal by controlling the conduction and cut-off of the first PMOS transistor and the second NMOS transistor to drive the ultrasonic output device to output ultrasonic signals.

[0070] A receiving unit, which collects a feedback signal formed based on the ultrasonic signal and outputs a display signal that matches the feedback signal according to the feedback signal.

[0071] The above-mentioned ultrasonic detection device, since it is built inside a neck card body, during the operation, the neck card body is fixed to the target area of the patient's neck, and the image of the subcutaneous detection area is obtained through the real-time detection of the ultrasonic detection device. Specifically, the drive signal forming unit is used to receive the externally input control information and form and output an ultrasonic signal matching the control information according to the control information. Specifically, it includes a control signal forming circuit, which is used to receive the control information and form and output a transmission timing control signal matching the control information according to the control information; a drive signal forming circuit, which is used to receive the transmission timing control signal and form the drive logic signal according to the transmission timing control signal. A high-voltage pulse forming circuit is used to receive the drive logic signal and form and output a high-voltage drive signal according to the drive logic signal; a first energy conversion circuit is used to receive the high-voltage drive signal and form and output the ultrasonic signal matching the control information according to the high-voltage drive signal; the ultrasonic signal acts on the patient's neck to form a feedback signal, and the receiving unit collects the feedback signal formed based on the ultrasonic signal and forms and outputs a display signal matching the feedback signal according to the feedback signal; the surgical operator performs surgical operations according to the display signal. This method greatly improves the safety and stability of the operation.

[0072] As a further preferred implementation, in the above-mentioned ultrasonic detection device, the drive signal forming unit further includes: a first suppression circuit, connected to the energy conversion unit, for suppressing the aftershock formed based on the ultrasonic signal after the ultrasonic signal is output. After the ultrasonic signal is output, aftershocks are likely to occur, and the aftershock signal is likely to interfere with the accuracy of the ultrasonic feedback signal acquisition. The first suppression circuit suppresses the aftershock signal to avoid the aftershock signal interfering with the subsequent echo signal. Specifically, as Figure 4 shown

[0073] A first inverter U6A, the input end of the first inverter U6A is connected to the 56th pin of the STM32F405RGT6 chip to output the RTZ signal, and the output end is connected to the input end of the fifth integrated circuit U7.

[0074] A second inverter U6B, the input end of the second inverter U6B is connected to the output end of the first inverter U6A, and the output end of the second inverter U6B is connected to the input end of the sixth integrated circuit U8.

[0075] The OE pin of the fifth integrated circuit U7 is connected to the second power supply 10V through the twelfth resistor R21. The VS+ pin of the fifth integrated circuit U7 is respectively connected to the VH pin of the fifth integrated circuit U7 and the second power supply 10V. The connection point formed by the VS+ pin and the VH pin of the fifth integrated circuit U7 is grounded through the filter capacitor C24. The filter capacitor C24 is designed to filter out the ripples in the second power supply 10V to improve the stability of the supply voltage. The VL pin, the VS- pin, and the GND pin of the fifth integrated circuit U7 are all grounded. The OE pin and the OUT pin of the fifth integrated circuit U7 are connected to the gate of the third MOS transistor Q3.

[0076] The OE pin of the sixth integrated circuit U8 is connected to the second power supply 10V through the thirteenth resistor R22. The VS+ pin of the sixth integrated circuit U8 is respectively connected to the VH pin of the sixth integrated circuit U8 and the second power supply 10V. The connection point formed by the VS+ pin and the VH pin of the sixth integrated circuit U8 is grounded through the filter capacitor C24. The filter capacitor C24 is designed to filter out the ripples in the second power supply 10V to improve the stability of the supply voltage. The VL pin, the VS- pin, and the GND pin of the sixth integrated circuit U8 are all grounded. The OE pin and the OUT pin of the sixth integrated circuit U8 are connected to the gate of the fourth MOS transistor Q4. The drain of the fourth MOS transistor Q4 is connected to the drain of the third MOS transistor Q3.

[0077] Since the input signals of the fifth integrated circuit U7 and the sixth integrated circuit U8 are opposite, and the drain of the fourth MOS transistor Q4 is connected to the drain of the third MOS transistor Q3, the fifth integrated circuit U7, the third MOS transistor Q3, the sixth integrated circuit U8, and the fourth MOS transistor Q4 are used to perform suppression processing on a pair of opposite signals to complete the suppression of aftershocks.

[0078] As a further preferred implementation, the receiving unit specifically includes:

[0079] As Figure 5 shown, a preamplifier, which includes three-stage amplification by the first triode Q5, the second triode Q6, and the third triode Q7, and is designed to amplify the weak feedback signal to form an amplified echo signal for output. Specifically, it includes:

[0080] The first triode Q5, the acquisition unit is connected to the base of the first triode. The collector of the first triode is respectively connected to the base of the second triode and connected to the third voltage 15V through the first echo resistor R28. The emitter of the first triode is connected to the fourth power supply -5V through the second echo resistor R25 and the third echo resistor R26.

[0081] The collector of the second triode Q6 is connected to the third voltage of 15V through the echo fourth resistor R29. The emitter of the second triode is grounded through the echo fifth resistor R30, and the emitter of the second triode is connected to the base of the third triode through the echo sixth resistor R31.

[0082] The collector of the third triode Q7 is connected to the third voltage of 15V. The emitter of the third triode Q7 is grounded through the echo sixth resistor R32 and is connected to the connection point of the echo second resistor R25 and the echo third resistor R26 through the echo seventh resistor R27. The echo seventh resistor R27 acts as a feedback resistor, and the emitter of the third triode Q7 forms the output terminal of the preamplifier.

[0083] A detection circuit, the input terminal of the detection circuit is connected to the output terminal of the preamplifier; specifically, as Figure 6 shown

[0084] A detection coupling capacitor C31, which should receive the amplified echo signal, filter out the high-frequency carrier signal in the amplified echo signal, and only allow the low-frequency carrier to pass through;

[0085] A detection filter circuit formed by a detection inductor L1 and a freewheeling diode D18, which is designed to filter out the low-frequency carrier signal in the amplified echo signal; at this time, both the high-frequency carrier signal and the low-frequency carrier signal in the amplified echo signal are filtered out;

[0086] A detection comparator U9, the reverse terminal of the detection comparator U9 is connected to the output terminal of the detection filter circuit through the fourteenth resistor R36. The positive terminal of the detection comparator U9 is connected to the output terminal of the detection filter circuit through the fifteenth resistor R38 and the sixteenth resistor R37. The output terminal of the detection comparator U9 is connected to the reverse terminal of the detection comparator U9 through a detection feedback circuit to form a negative feedback network. The detection feedback circuit is formed by the parallel connection of a detection feedback capacitor C35 and a detection feedback resistor R29.

[0087] As a further preferred implementation, on the basis of the above embodiment, a second suppression circuit is provided between the second conversion circuit and the detection circuit, which is designed to suppress the aftershock signal during the received echo stage. The working principle of the second suppression circuit is the same as that of the first suppression circuit, and will not be elaborated here.

[0088] A second conversion circuit, the second conversion circuit includes:

[0089] As Figure 7As shown, a second conversion comparator, the inverting terminal of the second conversion comparator U10 is connected to the output terminal of the detection comparator U9, the non-inverting terminal of the second conversion comparator U10 is connected to the REFL pin of the seventh integrated circuit U11 through a first conversion resistor R42, and the output terminal of the second conversion comparator is connected to the input pin of the seventh integrated circuit U11. The acquisition unit acquires a sound signal, that is, the sound signal feedback after the ultrasonic signal contacts the target area.

[0090] The REFM pin of the seventh integrated circuit U11 is connected to the second power supply of 10V, and the CK pin of the seventh integrated circuit U11 is connected to a clock signal. The D0 pin, D1 pin, D2 pin, and D3 pin of the seventh integrated circuit U11 convert the input analog signal into a digital signal for output. The digital signal is transmitted to the display unit for display.

[0091] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An ultrasonic detection device, characterized in that: Built into a set of neck card body, including, A driving signal forming unit, used for receiving control information input from the outside, and forming an ultrasonic signal output matching the control information according to the control information; Specifically include: A control signal forming circuit, used for receiving the control information and forming a transmission timing control signal output matching the control information according to the control information; A drive signal forming circuit, used for receiving the transmission timing control signal and forming a drive logic signal according to the transmission timing control signal; A high-voltage pulse forming circuit is used to receive the driving logic signal and form a high-voltage driving signal output according to the driving logic signal; the high-voltage driving signal includes a first high-voltage driving sub-signal and a second high-voltage driving sub-signal, An energy conversion unit, comprising a first energy conversion circuit, configured to receive the high-voltage drive signal and generate the ultrasonic signal output matching the control information according to the high-voltage drive signal; A receiving unit, which collects a feedback signal formed based on the ultrasonic signal, and forms a display signal output matching the feedback signal according to the feedback signal; The driving signal forming circuit includes two operational amplifier circuits, the reverse input terminals of the two operational amplifier circuits are respectively connected to the ground through a resistor, and the other resistor is connected to the first power supply, the positive input terminals of the two operational amplifier circuits are connected to the output terminal of the driving signal forming unit through a capacitor, and the output terminal of the driving signal forming unit is grounded through a resistor; The other driving signal forming circuit also includes a decoupling circuit connected between the power supply terminal and the ground terminal of the operational amplifier, and a first suppression circuit connected to the energy conversion unit, wherein the first suppression circuit includes a first inverter and a second inverter, the input end of the first inverter U6A is connected to the 56-pin output RTZ signal of the STM32F405RGT6 chip, and the output end is connected to the input end of the fifth integrated circuit U7, The second inverter U6B, the input end of the second inverter U6B is connected to the output end of the first inverter U6A, and the output end of the second inverter U6B is connected to the input end of the sixth integrated circuit U8.

2. The ultrasonic detection device according to claim 1, characterized in that: The drive signal forming circuit comprises: a first operational amplifier U3, wherein the positive input terminal of the first operational amplifier U3 is connected to the first output terminal EPT50+ of the drive signal forming unit, and the reverse input terminal of the first operational amplifier U3 is connected to the ground through the first resistor R11 and the second resistor R12 is connected to the first power supply +5V; the output terminal of the first operational amplifier U3 forms a first emission timing control sub-signal output; wherein the first operational amplifier U3 amplifies the first output terminal EPT50+ of the drive signal forming unit to form a first emission timing control sub-signal; A second operational amplifier U2, wherein the positive input terminal of the second operational amplifier U2 is connected to the second output terminal EPT50- of the drive signal forming unit, and the reverse input terminal of the second operational amplifier U2 is connected to the first power supply +5V and the fourth resistor R9 through the third resistor R8 and the ground respectively; the output terminal of the second operational amplifier U2 forms a second emission timing control sub-signal output; wherein the second operational amplifier U2 amplifies the second output terminal EPT50- of the drive signal forming unit to form a second emission timing control sub-signal.

3. The ultrasonic detection device according to claim 2, characterized in that: The positive input terminal of the first operational amplifier U3 is connected to the first output terminal EPT50+ of the drive signal forming unit through the first capacitor C16, and the first output terminal EPT50+ of the drive signal forming unit is grounded through the fifth resistor R13; The positive input terminal of the second operational amplifier U2 is connected to the second output terminal EPT50- of the driving signal forming unit through the second capacitor C11. At the same time, the second output terminal EPT50- of the driving signal forming unit is connected to the first power supply +5V through the sixth resistor R10. The second capacitor C11 and the sixth resistor R10 also form a low-pass filter RC circuit.

4. The ultrasonic detection device according to claim 3, characterized in that: The first decoupling circuit is connected between the power supply terminal and the ground terminal of the first operational amplifier U3. The power supply terminal of the first operational amplifier U3 is connected to the first power supply +5V, and the ground terminal of the first operational amplifier U3 is connected to the common ground. The first decoupling circuit is formed by connecting the third capacitor C14 and the fourth capacitor C15 in parallel. The second decoupling circuit is connected between the power supply terminal and the ground terminal of the second operational amplifier U2. The power supply terminal of the second operational amplifier U2 is connected to the first power supply +5V, and the ground terminal of the second operational amplifier U2 is connected to the common ground. The second decoupling circuit is formed by the fifth capacitor C12 and the sixth capacitor C13 in parallel.

5. The ultrasonic detection device according to claim 3, characterized in that: The high voltage pulse forming circuit includes a third integrated circuit U4 and a fourth integrated circuit U5. The input terminal IN pin of the third integrated circuit U4 receives the first transmission timing control sub-signal, the OE pin of the third integrated circuit U4 is connected to the second power supply 10V through the seventh resistor R14, and the VS of the third integrated circuit U4 + The GND pins of the third integrated circuit U4 are connected to the VS pins of the third integrated circuit U4. - pin, the VL pin of the third integrated circuit U4 and grounded; the OUT pin of the third integrated circuit U4 forms the output end of the third integrated circuit U4 to output the first high-voltage driving sub-signal; The input end of the fourth integrated circuit U5 receives the second transmission timing control sub-signal, the OE pin of the fourth integrated circuit U5 is connected to the second power supply 10V through the eighth resistor R15, and the VS of the fourth integrated circuit U5 is connected to the second power supply 10V through the eighth resistor R15. + The pins are connected to the second power supply 10V and the VH pin respectively, and are grounded through the sixth capacitor C19; the GND pins of the fourth integrated circuit U5 are connected to the VS pins of the fourth integrated circuit U5 respectively. - The pin is connected to the VL pin of the fourth integrated circuit U5 and is grounded; the OUT pin of the fourth integrated circuit U5 forms the output end of the fourth integrated circuit U5 to output the second high-voltage driving sub-signal.

6. The ultrasonic detection device according to claim 5, characterized in that: The first energy conversion circuit comprises: The first energy conversion sub-circuit includes a first PMOS tube, the gate of the first PMOS tube is connected to the OUT pin of the third integrated circuit U4 through the seventh capacitor C18, the first current limiting resistor R16 is connected to the source of the first PMOS tube, the source of the first PMOS tube is connected to the +10V pin through the tenth resistor R17, connected to the common ground through the first transmit filter circuit, and connected to the common ground through the first DC voltage stabilizing circuit, and the drain of the first PMOS tube is connected to the input end of the ultrasonic output device through the first diode D3; wherein the first transmit filter circuit is formed by the ninth capacitor C21 and the tenth capacitor TC2 connected in parallel, The second energy conversion sub-circuit, the second energy conversion sub-circuit includes a second NMOS tube, the gate of the second NMOS tube is connected to the OUT pin of the fourth integrated circuit U5 through the eighth capacitor C20, the second current limiting resistor R19 is connected to the source of the second NMOS tube, the source of the second NMOS tube is connected to the -10V pin through the eleventh resistor R18, connected to the common ground through the second transmit filter circuit, and connected to the common ground through the second DC voltage stabilizing circuit, and the drain of the second NMOS tube is connected to the input end of the ultrasonic output device through the second diode D4; wherein the second transmit filter circuit is formed by the eleventh capacitor C22 and the twelfth capacitor TC3 connected in parallel.

7. The ultrasonic detection device according to claim 3, characterized in that: The driving signal forming unit further includes: a first suppression circuit connected to the energy conversion unit, specifically including: A first inverter U6A, wherein the input end of the first inverter U6A is connected to the 56th pin of the STM32F405RGT6 chip to output the RTZ signal, and the output end is connected to the input end of the fifth integrated circuit U7, a second inverter U6B, wherein the input end of the second inverter U6B is connected to the output end of the first inverter U6A, and the output end of the second inverter U6B is connected to the input end of the sixth integrated circuit U8, The OE pin of the fifth integrated circuit U7 is connected to the second power supply 10V through the twelfth resistor R21, the VS+ pin of the fifth integrated circuit U7 is connected to the VH pin of the fifth integrated circuit U7 and the second power supply 10V respectively, and the connection point formed by the VS+ pin of the fifth integrated circuit U7 and the VH pin of the fifth integrated circuit U7 is grounded through the filter capacitor C24; the VL pin of the fifth integrated circuit U7, the VS- pin of the fifth integrated circuit U7 and the GND pin of the fifth integrated circuit U7 are all grounded, and the OE pin OUT pin of the fifth integrated circuit U7 is connected to the gate of the third MOS tube Q3, The OE pin of the sixth integrated circuit U8 is connected to the second power supply 10V through the thirteenth resistor R22, the VS+ pin of the sixth integrated circuit U8 is respectively connected to the VH pin of the sixth integrated circuit U8 and the second power supply 10V, and the connection point formed by the VS+ pin of the sixth integrated circuit U8 and the VH pin of the sixth integrated circuit U8 is grounded through the filter capacitor C24; the VL pin of the sixth integrated circuit U8, the VS- pin of the sixth integrated circuit U8 and the GND pin of the sixth integrated circuit U8 are all grounded, the OE pin OUT pin of the sixth integrated circuit U8 is connected to the gate of the fourth MOS tube Q4, and the drain of the fourth MOS tube Q4 is connected to the drain of the third MOS tube Q3.

8. The ultrasonic detection device according to claim 1, characterized in that: The receiving unit specifically includes: The preamplifier includes a first transistor Q5, a second transistor Q6, and a third transistor Q7 for three-stage amplification, and is used to amplify the weak feedback signal to form an amplified echo signal output, specifically including: The first transistor Q5, the acquisition unit is connected to the base of the first transistor, the collector of the first transistor is respectively connected to the base of the second transistor, connected to the third voltage 15V through the echo first resistor R28, and the emitter of the first transistor is connected to the fourth power supply -5V through the echo second resistor R25 and the echo third resistor R26; The collector of the second triode Q6 is connected to the third voltage 15V through the echo fourth resistor R29, the emitter of the second triode is grounded through the echo fifth resistor R30, and the emitter of the second triode is connected to the base of the third triode through the echo sixth resistor R31; The collector of the third transistor Q7 is connected to the third voltage 15V, the emitter of the third transistor Q7 is grounded through the echo sixth resistor R32, and is connected to the connection point of the echo second resistor R25 and the echo third resistor R26 through the echo seventh resistor R27, and the echo seventh resistor R27 is equivalent to a feedback resistor, wherein the emitter of the third transistor Q7 forms the output end of the preamplifier.

9. The ultrasonic detection device according to claim 8, characterized in that: Also includes: The detection circuit includes a detection coupling capacitor C31, which is used to receive the amplified echo signal. The detection filter circuit is formed by the detection inductor L1 and the freewheeling diode D18. The detection comparator U9, the reverse end of the detection comparator U9 is connected to the output end of the detection filter circuit through the fourteenth resistor R36, the forward end of the detection comparator U9 is connected to the output end of the detection filter circuit through the fifteenth resistor R38 and the sixteenth resistor R37, and the output end of the detection comparator U9 is connected to the reverse end of the detection comparator U9 through a detection feedback circuit to form a negative feedback network.

10. The ultrasonic detection device according to claim 9, characterized in that: It also includes a second conversion circuit, which includes a second conversion comparator U10, the inverting end of the second conversion comparator U10 is connected to the output end of the detection comparator U9, the non-phase end of the second conversion comparator U10 is connected to the REFL pin of the seventh integrated circuit U11 through the first conversion resistor R42, and the output end of the second conversion comparator is connected to the input pin of the seventh integrated circuit U11.

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