Manufacturing method of sleeve-cut mother board and sleeve-cut mother board

Abstract

The invention belongs to the technical field of microfluidics, and particularly relates to a manufacturing method of a nested cutting mother board and the nested cutting mother board. Forming a first transistor, a first metal block, a second metal block and a second transistor on the substrate; a first passivation layer is formed, and a first via hole and a second via hole are formed in the first passivation layer; forming a protective layer, and patterning the protective layer to obtain a first connecting block and a second connecting block; forming a semiconductor layer which is arranged on the first connecting block; a first pixel electrode is formed, the first pixel electrode in the display pixel area is connected with the first source electrode through a first connecting block, the first pixel electrode in the driving area is connected with the second source electrode through a second connecting block, and the first pixel electrode in the detection area corresponds to the second metal block; forming a second passivation layer, wherein the second passivation layer exposes the first pixel electrode in the driving region; and forming a second pixel electrode, wherein the second pixel electrode is connected with the first pixel electrode in the driving area. The manufacturing cost is reduced, and the utilization rate of the mother board is improved.

Description

Technical Field

[0001] The present application belongs to the field of microfluidic technology, and specifically relates to a method for manufacturing a sleeve-cut mother board and a sleeve-cut mother board. Background Art

[0002] Microfluidic technology is a technology that is mainly characterized by the manipulation of fluids in micrometer-scale space. It can concentrate multiple steps in biological, chemical, and medical analysis processes on a micrometer-level chip and automatically complete the entire analysis process. Due to the strong integration of microfluidic chips, the advantages of fast analysis speed, low loss, low material consumption, and low pollution when processing samples, it has shown great prospects in many fields such as biomedical research, drug synthesis screening, environmental monitoring and protection, health quarantine, forensic identification, and detection of biological reagents.

[0003] Microfluidic chips can automatically prepare and manipulate samples in the form of droplets, and they mainly use the dielectric wetting effect to drive the movement of droplets. However, microfluidic chips are currently still made of a single substrate, which has low preparation efficiency and cannot be prepared together with the main product, resulting in an increase in the cost of microfluidic chips. Summary of the invention

[0004] The purpose of the present application is to solve the technical problems in the prior art that the microfluidic chip is still made of a single substrate, has low preparation efficiency, cannot be prepared together with the main product, and causes an increase in the cost of the microfluidic chip.

[0005] The first aspect of the present application provides a method for manufacturing a sleeve-cut motherboard, comprising: providing a substrate, the substrate having at least a display area and a microfluidic area, the display area including a display pixel area, the microfluidic area including a detection area and a driving area connected to each other; forming a first transistor in the display pixel area, forming a first metal block and a second metal block in sequence in the detection area, and forming a second transistor in the driving area, the first metal block being arranged on a side of the second metal block close to the substrate; forming a first passivation layer on the substrate for covering the first transistor, the second metal block and the second transistor, and providing a first via hole and a second via hole on the first passivation layer, the first via hole being used to expose a portion of a first source electrode in the first transistor, and the second via hole being used to expose a portion of a second source electrode in the second transistor; forming a protective layer on the first passivation layer, and patterning the protective layer to form a first connection block in the display pixel area and a second connection block in the driving area, the first connection block being connected to the first source electrode through the first via hole, and the second connection block being connected to the first source electrode through the first via hole. The second source electrode is connected to the second source electrode through the second via hole; a semiconductor layer is formed on the display pixel area, and the semiconductor layer is connected to the first connection block in the display pixel area; a first pixel electrode is formed on the display pixel area, the detection area and the driving area, the first pixel electrode in the display pixel area is arranged on the side of the semiconductor layer away from the substrate and connected to the semiconductor layer, the first pixel electrode in the detection area is electrically connected to the first pixel electrode in the driving area, and the first pixel electrode in the detection area is arranged on the side of the first passivation layer away from the substrate, and the first pixel electrode in the driving area is connected to the first connection block in the driving area; a second passivation layer is formed on the first passivation layer, and in the display pixel area, the second passivation layer covers the first pixel electrode and the semiconductor layer; in the detection area, the second passivation layer covers the first pixel electrode; in the driving area, the second passivation layer exposes the first pixel electrode; a second pixel electrode is formed in the detection area and the driving area, and the second pixel electrode is connected to the first pixel electrode located in the driving area.

[0006] In an exemplary embodiment of the present application, the second transistor includes a second gate, a second active layer, and a second source and a second drain respectively overlapped at both ends of the second active layer, the second gate is arranged on a side of the second active layer close to the substrate, and a gate insulation layer is arranged between the second gate and the second active layer; when a protective layer is formed on the first passivation layer and the protective layer is patterned, the manufacturing method further includes: forming a protection block in the driving area, the protection block is arranged on a side of the first passivation layer away from the substrate, and the orthographic projection of the protection block on the substrate has an overlapping area with the orthographic projections of the second source and the second drain on the substrate.

[0007] In an exemplary embodiment of the present application, the material of the protective layer includes one or more of metal and metal oxide.

[0008] In an exemplary embodiment of the present application, before forming the second pixel electrode, the manufacturing method also includes: forming a flat layer on the second passivation layer, the flat layer covering the second passivation layer, and opening a third via hole on the flat layer to expose the first pixel electrode located in the driving area, the second pixel electrode being electrically connected to the first pixel electrode through the third via hole.

[0009] In an exemplary embodiment of the present application, a plurality of display areas and a plurality of microfluidic areas are provided on the substrate; after forming a flat layer on the second passivation layer, the manufacturing method further includes: in the display pixel area, a fourth via hole and a fifth via hole are respectively opened on the second passivation layer and the flat layer, the fourth via hole corresponds to and is connected to the fifth via hole, and the fourth via hole and the fifth via hole are used to expose a portion of the first pixel electrode; a third metal layer is formed on the flat layer, and the third metal layer is patterned to form a third metal block in the display pixel area of ​​at least part of the display area, the third metal block is connected to the first pixel electrode located in the display pixel area through the fourth via hole and the fifth via hole, and a fourth metal block is formed in the detection area of ​​at least part of the microfluidic area, and the second pixel electrode covers the fourth metal block.

[0010] In an exemplary embodiment of the present application, the first transistor includes a first gate, a first active layer, and a first source and a first drain respectively overlapped at two ends of the first active layer, the first gate is arranged on a side of the first active layer close to the substrate, and a gate insulating layer is provided between the first gate and the first active layer; when a third metal layer is formed on the flat layer and the third metal layer is patterned, the manufacturing method further includes: forming a fifth metal block in the display pixel area where the third metal block is formed, the fifth metal block is arranged at an interval with the third metal block, and the orthographic projection of the fifth metal block on the substrate has an overlapping area with the orthographic projection of the first source and the first drain on the substrate.

[0011] In an exemplary embodiment of the present application, in the detection area, the orthographic projection of the second pixel electrode on the substrate and the orthographic projection of the second metal block on the substrate have an overlapping area.

[0012] In an exemplary embodiment of the present application, in the detection area, the orthographic projection of the first pixel electrode on the substrate and the orthographic projection of the second metal block on the substrate have an overlapping area, and the voltages of the first pixel electrode and the second pixel electrode are the same.

[0013] In an exemplary embodiment of the present application, the manufacturing method further includes: forming a third passivation layer and a hydrophobic layer on the planar layer, the third passivation layer being disposed on a side of the hydrophobic layer close to the substrate, and the third passivation layer covering the second pixel electrode.

[0014] A second aspect of the present application provides a sleeve-cut motherboard, including a sleeve-cut display substrate and a sleeve-cut microfluidic substrate manufactured by any of the manufacturing methods described above.

[0015] The method for manufacturing the sleeved motherboard and the sleeved motherboard of the present application have the following beneficial effects:

[0016] The sleeve-cut microfluidic substrate in the present application scheme is compatible with the number of film layers and mask process of the sleeve-cut display substrate, so that the sleeve-cut display substrate and the sleeve-cut microfluidic substrate can be prepared on the same substrate, so that sleeve-cutting can be achieved between the microfluidic chip and the display substrate (main product), while reducing the manufacturing cost of the sleeve-cut display substrate and the sleeve-cut microfluidic substrate, it can also improve the utilization rate of the motherboard.

[0017] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A schematic flow chart of a method for making a sleeve-cut motherboard is shown.

[0021] Figure 2 A schematic diagram of the process of preparing a first transistor, a first metal block, a second metal block and a second transistor is shown.

[0022] Figure 3 A schematic structural diagram is shown in which a plurality of overcut display substrates and a plurality of overcut microfluidic substrates are arranged on a substrate.

[0023] Figure 4 A schematic diagram of the cross-sectional structure of the display area and the microfluidic area is shown.

[0024] Figure 5 A schematic diagram of the cross-sectional structure of a sleeve-cut microfluidic substrate is shown.

[0025] Figure 6 A schematic cross-sectional structure diagram of a sleeve-cut display substrate is shown.

[0026] Figure 7 A schematic cross-sectional structure diagram of forming a first gate, a first metal block and a first binding metal layer on a substrate is shown.

[0027] Figure 8 A schematic cross-sectional structure diagram of forming a gate insulating layer on a substrate is shown.

[0028] Fig. 9 A schematic cross-sectional structure diagram of forming a first active layer and a second active layer on a gate insulating layer is shown.

[0029] Fig.10 A schematic cross-sectional structure diagram of a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode formed on a gate insulating layer is shown.

[0030] Fig.11 A schematic cross-sectional structure diagram of a first passivation layer disposed on a gate insulating layer is shown.

[0031] Fig.12 A schematic cross-sectional structure diagram of a first connection block, a second connection block and a protection block formed on a substrate is shown.

[0032] Fig.13A schematic cross-sectional structure diagram of a semiconductor layer formed on a substrate is shown.

[0033] Fig.14 A schematic cross-sectional structure diagram of a first pixel electrode formed on a substrate is shown.

[0034] Fig.15 A schematic cross-sectional structure diagram of a second passivation layer formed on a substrate is shown.

[0035] Fig.16 A schematic cross-sectional structure diagram of a flat layer formed on a substrate is shown.

[0036] Fig.17 A schematic cross-sectional structure diagram of a third metal block, a fourth metal block and a fifth metal block formed on a substrate is shown.

[0037] Fig.18 A schematic cross-sectional structure diagram of a second pixel electrode formed on a substrate is shown.

[0038] Description of reference numerals:

[0039] 100, sleeve cutting mother board; 100a, sleeve cutting display substrate; 100b, sleeve cutting microfluidic substrate;

[0040] 110, substrate; 120, display area; 120a, display pixel area; 120b, first binding area; 130, microfluidic area; 130a, detection area; 130b, driving area; 130c, second binding area;

[0041] 140, a first transistor; 141, a first gate; 142, a first active layer; 143, a first source; 144, a first drain; 150, a first metal block; 160, a second metal block; 170, a second transistor; 171, a second gate; 172, a second active layer; 173, a second source; 174, a second drain; 180, a first binding metal layer; 190, a gate insulating layer; 191, a first through hole;

[0042] 1100, second binding metal layer; 1200, first passivation layer; 1210, first via hole; 1220, second via hole; 1230, second through hole; 1310, first connection block; 1320, second connection block; 1330, protection block; 1400, third binding metal layer; 1500, semiconductor layer; 1600, first pixel electrode; 1700, first binding pixel electrode; 1800, second passivation layer; 1810, fourth via hole; 1900, planar layer; 1910, fifth via hole;

[0043] 11110, a third metal block; 11120, a fourth metal block; 11130, a fifth metal block; 11200, a fourth binding metal layer; 11300, a second pixel electrode; 11400, a second binding pixel electrode; 11500, a third passivation layer; 11600, a hydrophobic layer. DETAILED DESCRIPTION

[0044] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0045] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0048] Embodiment 1

[0049] Figure 1 A schematic flow chart of a method for manufacturing a sleeve-cut motherboard provided in an embodiment of the present application is shown. Figure 2 A schematic diagram of a process for preparing a first transistor, a first metal block, a second metal block, and a second transistor provided in an embodiment of the present application is shown.

[0050] See also Figure 1 and Figure 2 As shown, the first embodiment of the present application provides a method for manufacturing a sleeve-cut motherboard 100, and the manufacturing method includes the following steps:

[0051] S100 , providing a substrate 110 .

[0052] The substrate 110 may be a rigid substrate made of glass, but is not limited thereto, and may also be a flexible substrate made of materials such as polyimide (abbreviated as polyimide). In other words, the sleeve-cut display panel of the present application is not limited to a rigid, non-bendable panel, but may also be a flexible, bendable panel.

[0053] It should be noted that the substrate 110 may include at least a display area 120 and a microfluidic area 130. The display area 120 is used to prepare a display substrate of a display device, and the microfluidic area 130 is used to prepare a microfluidic substrate of a microfluidic chip.

[0054] Figure 3 A schematic structural diagram is shown in which a plurality of overcut display substrates and a plurality of overcut microfluidic substrates are arranged on a substrate. Figure 4 A schematic diagram of the cross-sectional structure of the display area and the microfluidic area is shown. Figure 5 A schematic diagram of the cross-sectional structure of a sleeve-cut microfluidic substrate is shown. Figure 6 A schematic cross-sectional structure diagram of a sleeve-cut display substrate is shown.

[0055] In addition, see Figure 2 , Figure 5 and Figure 6 As shown, the substrate 110 may include a plurality of display regions 120 and a plurality of microfluidic regions 130, so that a plurality of overlay-cut display substrates 100a and a plurality of overlay-cut microfluidic substrates 100b can be produced simultaneously, so as to increase production quantity and reduce production cost.

[0056] In some embodiments of the present application, the substrate 110 also includes a cutting alignment line (not shown in the figure) located between the display area 120 and the microfluidic area 130, and a cutting tool is used to cut at the cutting alignment line to achieve sleeve cutting, so as to form a sleeve-cut display substrate 100a and a sleeve-cut microfluidic substrate 100b respectively.

[0057] It should be noted that see Figure 4 As shown, the display area 120 may include a display pixel area 120a and a first binding area 120b, wherein the first binding area 120b is disposed on one side of the display pixel area 120a and connected to the display pixel area 120a. It is understood that the first binding area 120b may be used to connect to a flexible circuit board for signal transmission.

[0058] In addition, the microfluidic area 130 may include a detection area 130a for detecting droplets, a driving area 130b for driving the movement of droplets, and a second binding area 130c for electrically connecting to the flexible circuit board. The detection area 130a is connected to the second binding area 130c through the driving area 130b, the driving area 130b can drive the droplets to move on the moving path, the detection area 130a can observe the position of the droplets, and the second binding area 130c is electrically connected to the flexible circuit board to transmit electrical signals to the driving area 130b and the detection area 130a to achieve the driving and observation of the droplets.

[0059] S200 , forming a first transistor 140 in the display pixel area 120 a , sequentially forming a first metal block 150 and a second metal block 160 in the detection area 130 a , and forming a second transistor 170 in the driving area 130 b .

[0060] It should be noted that, while forming the first transistor 140 in the display pixel area 120a, the first metal block 150 and the second metal block 160 in the detection area 130a and the second transistor 170 in the driving area 130b are formed together, so that the first transistor 140, the first metal block 150, the second metal block 160 and the second transistor 170 can be prepared simultaneously under the same process technology, thereby reducing production costs.

[0061] Among them, see Figure 2 As shown, the first transistor 140 includes a first gate 141 , a first active layer 142 , a first source 143 and a first drain 144 ; the second transistor 170 includes a second gate 171 , a second active layer 172 , a second source 173 and a second drain 174 .

[0062] Figure 7 A schematic cross-sectional structure diagram of forming a first gate, a first metal block and a first binding metal layer on a substrate is shown. Figure 8 A schematic cross-sectional structure diagram of forming a gate insulating layer on a substrate is shown.

[0063] Fig. 9 A schematic cross-sectional structure diagram of forming a first active layer and a second active layer on a gate insulating layer is shown.

[0064] Fig.10 A schematic cross-sectional structure diagram of a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode formed on a gate insulating layer is shown.

[0065] See also Figures 7 to 10 As shown, the manufacturing method of forming the first transistor 140 in the display pixel area 120a, sequentially forming the first metal block 150 and the second metal block 160 in the detection area 130a, and forming the second transistor 170 in the driving area 130b includes at least the following steps:

[0066] S210, forming a first metal layer on the substrate 110, and patterning the first metal layer to form a first gate 141 in the display pixel area 120a, a first metal block 150 in the detection area 130a, and a second gate 171 in the driving area 130b.

[0067] That is to say, Figure 7 As shown, the first metal block 150 , the first gate 141 and the second gate 171 are arranged in the same layer and spaced apart.

[0068] It should be noted that the first metal layer can be made of metal materials, such as molybdenum, aluminum and titanium, to ensure its good electrical conductivity, but is not limited thereto, and can also be made of other materials with good electrical conductivity.

[0069] It is worth mentioning that see Figure 7 As shown, after the first metal layer is patterned, a first binding metal layer 180 is formed in both the first binding region 120 b and the second binding region 130 c , and the first binding metal layer 180 and the first gate 141 and the second gate 171 are spaced apart from each other.

[0070] S220, forming a gate insulating layer 190 on the substrate 110, the gate insulating layer 190 covers the first gate 141, the first metal block 150 and the second gate 171. Figure 8 shown.

[0071] The material of the gate insulating layer 190 includes one or more of silicon oxide (SiOx) and silicon nitride (SiNx).

[0072] It should be noted that see Fig. 9 As shown, in the second binding area 130c: the above-mentioned gate insulation layer 190 is formed in the second binding area 130c, and after the gate insulation layer 190 is formed, a first through hole 191 is opened above the gate insulation layer 190, and the first through hole 191 exposes a portion of the first binding metal layer 180 to facilitate the subsequent filling of metal material in the second metal layer into the first through hole 191 to connect it to the first binding metal layer 180.

[0073] S230, forming a first inorganic silicon layer on the gate insulating layer 190, and patterning the first inorganic silicon layer to form a first active layer 142 in the display pixel area 120a and a second active layer 172 in the driving area 130b, as shown in FIG. Fig. 9 shown.

[0074] The orthographic projection of the first active layer 142 on the substrate 110 covers the orthographic projection of the first gate 141 on the substrate 110 . The orthographic projection of the second active layer 172 on the substrate 110 covers the orthographic projection of the second gate 171 on the substrate 110 .

[0075] It can be understood that the material of the first inorganic silicon layer may include one or more of amorphous silicon and polycrystalline silicon.

[0076] S240, forming a second metal layer on the gate insulating layer 190, and patterning the second metal layer to form a first source 143 and a first drain 144 in the display pixel area 120a, forming a second metal block 160 in the detection area 130a, and forming a second source 173 and a second drain 174 in the driving area 130b, as shown in FIG. Fig.10 shown.

[0077] That is, the first source electrode 143 , the first drain electrode 144 , the second metal block 160 , the second source electrode 173 , and the second drain electrode 174 are arranged in the same layer and spaced apart from each other.

[0078] The first source electrode 143 and the first drain electrode 144 are respectively disposed at opposite ends of the first active layer 142 and are spaced apart from each other. The second source electrode 173 and the second drain electrode 174 are respectively disposed at opposite ends of the second active layer 172 and are spaced apart from each other. The second metal block 160 is disposed on a side of the gate insulating layer 190 away from the substrate 110, and the orthographic projection of the second metal block 160 on the substrate 110 has an overlapping area with the orthographic projection of the first metal block 150 on the substrate 110.

[0079] In addition, if Fig.10 As shown, when the second metal layer is formed on the gate insulating layer 190, a second binding metal layer 1100 is formed at the second binding area 130c and is spaced apart from the second source 173 or the second drain 174. The metal material in the second binding metal layer 1100 is filled into the first through hole 191, so that the second binding metal layer 1100 is connected to the first binding metal layer 180.

[0080] That is, through the above steps, a first transistor 140 is formed in the display pixel area 120a on the substrate 110, a first metal block 150 and a second metal block 160 are formed in the detection area 130a, and a second transistor 170 is formed in the driving area 130b.

[0081] Fig.11 A schematic cross-sectional structure diagram of a first passivation layer disposed on a gate insulating layer is shown.

[0082] S300, forming a first passivation layer 1200 on the substrate 110, and providing a first via hole 1210 and a second via hole 1220 on the first passivation layer 1200, such as Fig.11 shown.

[0083] It should be noted that the first passivation layer 1200 can cover the first transistor 140 , the second metal block 160 and the second transistor 170 .

[0084] In addition, the first via hole 1210 is used to expose a portion of the first source electrode 143 in the first transistor 140 , and the second via hole 1220 is used to expose a portion of the second source electrode 173 in the second transistor 170 .

[0085] The first passivation layer 1200 is formed on a side of the gate insulating layer 190 away from the substrate 110 , and covers the first source 143 , the first drain 144 , the first active layer 142 , the second active layer 172 , the second source 173 , the second drain 174 and the second metal block 160 .

[0086] In some embodiments of the present application, see Fig.11 As shown, a first passivation layer 1200 may also be formed in the second binding region 130c. After the first passivation layer 1200 is formed, a second through hole 1230 is opened on the first passivation layer 1200 to expose a portion of the second binding metal layer 1100 for connection with the third binding metal layer 1400 described later.

[0087] Fig.12 A schematic cross-sectional structure diagram of the first connecting block, the second connecting block and the protection block is shown.

[0088] S400, forming a protective layer on the first passivation layer 1200, and patterning the protective layer to form a first connection block 1310 in the display pixel area 120a and a second connection block 1320 in the driving area 130b, as shown in FIG. Fig.12 shown.

[0089] The first connection block 1310 is connected to the first source 143 through the first via hole 1210 , and the second connection block 1320 is connected to the second source 173 through the second via hole 1220 .

[0090] In some embodiments of the present application, the material of the protective layer is filled into the first via 1210 and the second via 1220 so that a portion of the first connecting block 1310 overlaps with the first source 143 exposed at the first via 1210, and the second connecting block 1320 is connected to the second source 173 for signal transmission.

[0091] It should be noted that, in the driving area 130 b , the second connecting block 1320 is completely filled into the second via hole 1220 .

[0092] The material of the protective layer includes one or more of metals and metal oxides, such as molybdenum, aluminum, titanium, indium tin oxide, etc.

[0093] For example, the material of the protection layer is metal, and the protection layer is in a floating state, and does not receive any signal, but can transmit electrical signals.

[0094] It is worth mentioning that when the protective layer is patterned, the manufacturing method further includes forming a protective block 1330 in the driving area 130b, such as Fig.12 The protection block 1330 is disposed on a side of the first passivation layer 1200 away from the substrate 110 , and the orthographic projection of the protection block 1330 on the substrate 110 has an overlapping area with the orthographic projections of the second source 173 and the second drain 174 on the substrate 110 .

[0095] That is, the protection block 1330 can shield the channel region of the second transistor 170 so that the channel region of the second transistor 170 will not be affected by plasma shock waves of subsequent deposition, dry etching and other processes, thereby improving the stability of the second transistor 170.

[0096] In addition, if Fig.12 As shown, when the protective layer is patterned, a third binding metal layer 1400 is formed in the second binding area 130c and is spaced apart from the second connecting block 1320. The material of the third binding metal layer 1400 is filled into the second through hole 1230 to connect the third binding metal layer 1400 to the second binding metal layer 1100.

[0097] Fig.13 A schematic diagram of the cross-sectional structure of forming a semiconductor layer is shown.

[0098] S500, forming a semiconductor layer 1500 in the display pixel region 120a, the semiconductor layer 1500 is electrically connected to the first connection block 1310 in the display pixel region 120a, such as Fig.13 shown.

[0099] The material of the semiconductor layer 1500 includes one or more of silicon oxide (SiOx) and silicon nitride (SiNx).

[0100] The semiconductor layer 1500 can convert the received optical signal into an electrical signal to realize display.

[0101] That is to say, the display area 120 can be used as a substrate for an X-ray sensing screen or an X-ray detector, and can also be used as a substrate for other photoelectric sensing display devices.

[0102] Fig.14 A schematic cross-sectional structure diagram of forming a first pixel electrode is shown.

[0103] S600, forming a first pixel electrode 1600 on the display pixel area 120a, the detection area 130a and the driving area 130b, as shown in FIG. Fig.14 shown.

[0104] Among them, the first pixel electrode 1600 in the display pixel area 120a is arranged on a side of the semiconductor layer 1500 away from the substrate 110 and is electrically connected to the semiconductor layer 1500 so that the data signal on the first source 143 can be transmitted to the first pixel electrode 1600 through the first connecting block 1310 and the semiconductor layer 1500.

[0105] The first pixel electrode 1600 in the detection area 130a is arranged on a side of the first passivation layer 1200 away from the substrate 110, and the first pixel electrode 1600 in the detection area 130a is connected to the first pixel electrode 1600 in the driving area 130b to transmit the same electrical signal, and the orthographic projection of the first pixel electrode 1600 in the detection area 130a on the substrate 110 has an overlapping area with the orthographic projection of the second metal block 160 on the substrate 110 to form a storage capacitor between the second metal block 160 and the second metal block 160.

[0106] The first pixel electrode 1600 in the driving area 130 b is connected to the second connection block 1320 in the driving area 130 b , so that the electrical signal on the second source electrode 173 is transmitted to the first pixel electrode 1600 through the second connection block 1320 .

[0107] The first pixel electrode 1600 and the first binding pixel electrode 1700 described below may be made of a transparent conductive material, such as ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0108] In some embodiments of the present application, a first binding pixel electrode 1700 which is in the same layer as the first pixel electrode 1600 and is spaced apart from the first pixel electrode 1600 is further disposed in the second binding region 130 c , and the first binding pixel electrode 1700 is connected to the third binding metal layer 1400 .

[0109] Fig.15 A schematic cross-sectional structure diagram of forming a second passivation layer is shown.

[0110] S700, forming a second passivation layer 1800 on the first passivation layer 1200, such as Fig.15 shown.

[0111] In the display pixel area 120a, the second passivation layer 1800 covers the first pixel electrode 1600 and the semiconductor layer 1500. In the detection area 130a, the second passivation layer 1800 covers the first pixel electrode 1600. In the driving area 130b, the first pixel electrode 1600 is exposed on the second passivation layer 1800, that is, in the driving area 130b, the film thickness of the second passivation layer 1800 corresponding to the first pixel electrode 1600 is zero.

[0112] It should be noted that the second passivation layer 1800 can be made of the same material as the first passivation layer 1200 , such as silicon oxide or silicon nitride.

[0113] In addition, a second passivation layer 1800 is also disposed in the second binding region 130c, and in the second binding region 130c, the second passivation layer 1800 exposes the first binding pixel electrode 1700, that is, the film thickness of the second passivation layer 1800 corresponding to the first binding pixel electrode 1700 is zero.

[0114] Fig.16 A schematic cross-sectional structure diagram of forming a planar layer is shown.

[0115] S800, forming a planarization layer 1900 on the second passivation layer 1800, such as Fig.16 shown.

[0116] The flat layer 1900 in the display pixel area 120a and the detection area 130a covers the second passivation layer 1800. When the flat layer 1900 is formed on the second passivation layer 1800, a third via hole for exposing the first pixel electrode 1600 in the driving area 130b is opened on the flat layer 1900 in the driving area 130b.

[0117] It is worth mentioning that the flat layer 1900 can be made of soluble polytetrafluoroethylene material.

[0118] In some embodiments of the present application, a plurality of display regions 120 and a plurality of microfluidic regions 130 are provided on the substrate 110, and a material with an opaque background color may be added to at least a portion of the microfluidic region 130, so that the droplets can be observed more intuitively. In addition, an opaque background color material may be added to a portion of the display region 120 to cover the channel region of the first transistor 140 to prevent light from damaging the first transistor 140.

[0119] Fig.17 A schematic cross-sectional structure diagram of forming a third metal block, a fourth metal block and a fifth metal block is shown.

[0120] After forming the planar layer 1900, the manufacturing method may further include:

[0121] S900, preparing a third metal layer on the flat layer 1900, and patterning the third metal layer to form a third metal block 11110 in the display pixel area 120a of at least a portion of the display area 120, and forming a fourth metal block 11120 in the detection area 130a of at least a portion of the microfluidic area 130, such as Fig.17 shown.

[0122] It is understandable that the formation of an opaque fourth metal block 11120 in the detection area 130a of at least part of the microfluidic area 130 can provide an opaque background color to more intuitively observe the moving position of the droplet. In addition, the transparent state is still maintained at the position where the fourth metal block 11120 is not added. By setting the fourth metal block 11120 in different microfluidic areas 130 or not setting the fourth metal block 11120, it can be used for different observation needs, thereby improving the adaptability of the sleeve-cut microfluidic substrate 100b.

[0123] It is worth mentioning that in the display pixel area 120a where the third metal block 11110 is provided, it is necessary to open a fourth via hole 1810 on the second passivation layer 1800 and a fifth via hole 1910 on the flat layer 1900 to expose a portion of the first pixel electrode 1600 in the display pixel area 120a, so that the material in the third metal layer overlaps with the portion of the first pixel electrode 1600 located in the display pixel area 120a, so that the third metal block 11110 is electrically connected to the first pixel electrode 1600 for signal transmission.

[0124] It should be understood that the fourth via hole 1810 can be formed while preparing the second passivation layer 1800, and the fifth via hole 1910 can be formed while preparing the planar layer 1900. The fourth via hole 1810 and the fifth via hole 1910 can also be formed after preparing the second passivation layer 1800 and the planar layer 1900, which can be designed according to different embodiments.

[0125] In some embodiments of the present application, when preparing the third metal layer on the flat layer 1900 and performing patterning on the third metal layer, the manufacturing method further includes:

[0126] like Fig.17 As shown, a fifth metal block 11130 is formed in the display pixel region 120a where the third metal block 11110 is formed.

[0127] The fifth metal block 11130 and the third metal block 11110 are arranged at intervals with each other, and the orthographic projection of the fifth metal block 11130 on the substrate 110 has an overlapping area with the orthographic projections of the first source 143 and the first drain 144 on the substrate 110, so that the fifth metal block 11130 can shield the channel area of ​​the first transistor 140 to prevent damage to the first transistor 140 due to light exposure.

[0128] And when the third metal layer is prepared, a fourth binding metal layer 11200 is formed on the first binding metal layer 180 in the first binding region 120 b.

[0129] Fig.18 A schematic cross-sectional structure diagram of forming a second pixel electrode is shown.

[0130] S1000, forming a second pixel electrode 11300 in the detection area 130a and the driving area 130b, the second pixel electrode 11300 is electrically connected to the first pixel electrode 1600 in the driving area 130b, as shown in FIG. Fig.18 shown.

[0131] Among them, the second pixel electrode 11300 is arranged on the side of the flat layer 1900 away from the substrate 110, and the orthographic projection of the second pixel electrode 11300 in the detection area 130a on the substrate 110 has an overlapping area with the orthographic projection of the second metal block 160 on the substrate 110 to ensure that a storage capacitor is formed between the second pixel electrode 11300 and the second metal block 160.

[0132] It should be noted that a connection hole (not shown in the figure) is provided on the flat layer 1900, and the material of the second pixel electrode 11300 is filled in the connection hole so that the second pixel electrode 11300 is connected to the first pixel electrode 1600. The second pixel electrode 11300 in the driving area 130b is connected to the second source electrode 173 through the first pixel electrode 1600 and the second connection block 1320, so that the first pixel electrode 1600 and the second pixel electrode 11300 in the driving area 130b can pass the same electrical signal. And because the first pixel electrode 1600 in the detection area 130a is connected to the first pixel electrode 1600 in the driving area 130b, and the second pixel electrode 11300 in the detection area 130a is connected to the second pixel electrode 11300 in the driving area 130b, the electrical signals of the first pixel electrode 1600 and the second pixel electrode 11300 in the detection area 130a are the same, that is, the first pixel electrode 1600 and the second pixel electrode 11300 do not generate capacitance.

[0133] That is to say, by adding the first pixel electrode 1600 , the storage capacitance of the entire microfluidic substrate can be increased.

[0134] In addition, by supplying an electrical signal to the second pixel electrode 11300, the movement of the droplet can be controlled.

[0135] It is worth mentioning that due to the addition of a flat layer 1900 between the second pixel electrode 11300 and the second source 173 and the second drain 174, the distance between the second pixel electrode 11300 and the second source 173 / the second drain 174 in the driving area 130b is increased, so that the parasitic capacitance between the second pixel electrode 11300 and the second source 173 / the second drain 174 in the driving area 130b is reduced, thereby improving the stability of the output voltage of the second pixel electrode 11300.

[0136] In some embodiments of the present application, Fig.18 As shown, when the second pixel electrode 11300 is formed, a second binding pixel electrode 11400 can also be formed in both the first binding area 120b and the second binding area 130c. The second binding pixel electrode 11400 in the first binding area 120b is connected to the fourth binding metal layer 11200, and the second binding pixel electrode 11400 in the second binding area 130c is connected to the first binding pixel electrode 1700, and is spaced apart from the second pixel electrode 11300 in the driving area 130b.

[0137] The second pixel electrode 11300 and the second binding pixel electrode 11400 may be made of a transparent conductive material, such as ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0138] S1100, forming a third passivation layer 11500 and a hydrophobic layer 11600 on the flat layer 1900, as shown in FIG. Figure 4 shown.

[0139] The third passivation layer 11500 is disposed on a side of the hydrophobic layer 11600 close to the substrate 110. The third passivation layer 11500 covers the second pixel electrode 11300, the fifth metal block 11130 and the third metal block 11110. The third passivation layer 11500 can be made of the same material as the first passivation layer 1200 and the second passivation layer 1800, such as silicon oxide or silicon nitride.

[0140] The hydrophobic layer 11600 may be made of polytetrafluoroethylene, silane modified materials, etc.

[0141] It is understandable that the hydrophobic layer 11600 in the detection area 130a and the hydrophobic layer 11600 in the driving area 130b can be located at the same height to ensure that the droplets can slide smoothly in the driving area 130b and the detection area 130a without loss.

[0142] Through the above method for manufacturing the sleeve-cut motherboard 100, it can be seen that by changing the process film layer and mask sequence of the sleeve-cut microfluidic substrate 100b, the sleeve-cut microfluidic substrate 100b can be adapted to the sleeve-cut display substrate, so that the film layer and mask process used in the display area 120 and the microfluidic area 130 are similar. The sleeve-cut microfluidic substrate 100b can be compatible with the number of film layers and mask process of the sleeve-cut display substrate 100a, so that the sleeve-cut display substrate 100a and the sleeve-cut microfluidic substrate 100b can be prepared on the same substrate 110, so that sleeve-cutting can be achieved between the microfluidic chip and the display substrate (main product), which can reduce the manufacturing cost of the sleeve-cut display substrate 100a and the sleeve-cut microfluidic substrate 100b while improving the utilization rate of the motherboard.

[0143] Embodiment 2

[0144] The second embodiment of the present application provides a sleeve-cut motherboard 100, which includes a sleeve-cut display substrate 100a and a sleeve-cut microfluidic substrate 100b prepared by the manufacturing method in the first embodiment. The sleeve-cut display substrate 100a can be applied to the substrate of the photoelectric sensing display device, and the sleeve-cut microfluidic substrate 100b can be applied to the microfluidic chip.

[0145] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0146] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A method for manufacturing a sleeve-cut motherboard, characterized in that: include: Providing a substrate, the substrate having at least a display area and a microfluidic area, the display area including a display pixel area, the microfluidic area including a detection area and a driving area connected to each other; forming a first transistor in the display pixel area, forming a first metal block and a second metal block in the detection area in sequence, and forming a second transistor in the driving area, wherein the first metal block is disposed on a side of the second metal block close to the substrate; forming a first passivation layer on the substrate for covering the first transistor, the second metal block and the second transistor, and providing a first via hole and a second via hole on the first passivation layer, wherein the first via hole is used to expose a portion of a first source electrode in the first transistor, and the second via hole is used to expose a portion of a second source electrode in the second transistor; forming a protective layer on the first passivation layer, and patterning the protective layer to form a first connection block in the display pixel area and a second connection block in the driving area, wherein the first connection block is connected to the first source electrode through the first via hole, and the second connection block is connected to the second source electrode through the second via hole; forming a semiconductor layer on the display pixel area, wherein the semiconductor layer is connected to a first connection block in the display pixel area; A first pixel electrode is formed on the display pixel area, the detection area and the drive area, the first pixel electrode in the display pixel area is arranged on a side of the semiconductor layer away from the substrate and connected to the semiconductor layer, the first pixel electrode in the detection area is electrically connected to the first pixel electrode in the drive area, and the first pixel electrode in the detection area is arranged on a side of the first passivation layer away from the substrate, and the first pixel electrode in the drive area is connected to the first connection block in the drive area; forming a second passivation layer on the first passivation layer, wherein the second passivation layer covers the first pixel electrode and the semiconductor layer in the display pixel area; In the detection area, the second passivation layer covers the first pixel electrode; In the driving area, the second passivation layer exposes the first pixel electrode; A second pixel electrode is formed in the detection area and the driving area, and the second pixel electrode is connected to the first pixel electrode in the driving area.

2. The method according to claim 1, characterized in that: The second transistor includes a second gate, a second active layer, and a second source and a second drain respectively connected to two ends of the second active layer, the second gate is arranged on a side of the second active layer close to the substrate, and a gate insulating layer is arranged between the second gate and the second active layer; When a protective layer is formed on the first passivation layer and the protective layer is patterned, the manufacturing method further includes: A protection block is formed in the driving area. The protection block is arranged on a side of the first passivation layer away from the substrate, and an orthographic projection of the protection block on the substrate has an overlapping area with an orthographic projection of the second source and the second drain on the substrate.

3. The method according to claim 2, characterized in that: The material of the protective layer includes one or more of metal and metal oxide.

4. The method according to claim 1, characterized in that: Before forming the second pixel electrode, the manufacturing method further includes: A planar layer is formed on the second passivation layer, the planar layer covers the second passivation layer, and a third via hole is opened on the planar layer to expose the first pixel electrode in the driving area, and the second pixel electrode is electrically connected to the first pixel electrode through the third via hole.

5. The method according to claim 4, characterized in that: The substrate is provided with a plurality of display areas and a plurality of microfluidic areas; After forming a planar layer on the second passivation layer, the manufacturing method further includes: In the display pixel area, a fourth via hole and a fifth via hole are respectively formed on the second passivation layer and the planar layer, the fourth via hole corresponds to and is connected with the fifth via hole, and the fourth via hole and the fifth via hole are used to expose a portion of the first pixel electrode; A third metal layer is formed on the flat layer and patterned to form a third metal block in the display pixel region of at least part of the display region, the third metal block is connected to the first pixel electrode in the display pixel region through the fourth via hole and the fifth via hole, a fourth metal block is formed in the detection region of at least part of the microfluidic region, and the second pixel electrode covers the fourth metal block.

6. The method according to claim 5, characterized in that: The first transistor includes a first gate, a first active layer, and a first source and a first drain respectively connected to two ends of the first active layer, the first gate is arranged on a side of the first active layer close to the substrate, and a gate insulating layer is arranged between the first gate and the first active layer; When a third metal layer is formed on the planar layer and the third metal layer is patterned, the manufacturing method further includes: A fifth metal block is formed in the display pixel area where the third metal block is formed. The fifth metal block is spaced apart from the third metal block, and an orthographic projection of the fifth metal block on the substrate has an overlapping area with an orthographic projection of the first source and the first drain on the substrate.

7. The manufacturing method according to claim 1, characterized in that: In the detection area, an orthographic projection of the second pixel electrode on the substrate and an orthographic projection of the second metal block on the substrate have an overlapping area.

8. The method according to claim 7, characterized in that: In the detection area, an orthographic projection of the first pixel electrode on the substrate and an orthographic projection of the second metal block on the substrate have an overlapping area, and the voltages of the first pixel electrode and the second pixel electrode are the same.

9. The manufacturing method according to claim 4, characterized in that: The production method further comprises: A third passivation layer and a hydrophobic layer are formed on the planar layer, wherein the third passivation layer is disposed on a side of the hydrophobic layer close to the substrate, and the third passivation layer covers the second pixel electrode.

10. A sleeve-cut motherboard, characterized in that: It comprises a sleeve-cut display substrate and a sleeve-cut microfluidic substrate manufactured by the manufacturing method according to any one of claims 1 to 9.

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