A dual-pulse test protection device and method for SiC MOSFETs

Abstract

The application relates to a double-pulse test protection device and method for a SiC MOSFET, wherein the device is connected with an upper tube device and a lower tube device respectively; the upper tube device and the lower tube device are detected through the introduction of a turn-on detector and a turn-off detector; specifically, the turn-on detector is arranged at the source of the upper tube device, and the turn-off detector is arranged at the source of the lower tube device; dynamic parameters generated by the two devices are obtained under different test working conditions, and it is judged whether the dynamic parameters are within a safe threshold range, and then different processing measures are automatically executed according to different judgment results. The device has the advantages of high intelligence, high identification accuracy and high working reliability.

Description

Technical Field

[0001] This invention belongs to the field of automated testing technology, specifically relating to a dual-pulse test protection device and method for SiC MOSFETs. Background Technology

[0002] SiC MOSFETs have a faster switching speed than conventional Si-based devices. The switching transients can generate a large current change rate, which can easily cause severe high-frequency oscillations in the circuit. Under high-frequency switching, due to the rapid changes in parameters such as voltage and current, the high current change rate will generate an induced voltage through the parasitic inductance of the main circuit and produce a voltage spike on the drain-source voltage, which may damage the circuit and the device.

[0003] To fully leverage the advantages of SiC MOSFETs, characterizing their dynamic performance is crucial. Dual-pulse testing (DPT) is a commonly used method; by measuring voltage and current waveforms, information including losses, time, overshoot, and switching speed can be extracted and analyzed. The rate of change of current is a key parameter for evaluating and optimizing SiC device performance, and it also significantly impacts device reliability, directly affecting switching losses, dynamic response, and durability. Precise control and measurement of the rate of change of current can improve the performance and lifespan of SiC devices.

[0004] Existing dual-pulse testing schemes typically require experienced testers to monitor real-time test data to prevent damage to the power device under test during testing, such as when the device's operating conditions exceed safe limits. However, this reliance on manual monitoring severely restricts the possibility of conducting extensive testing of power devices under various operating conditions and is prone to introducing subjective errors. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a dual-pulse test protection device and method for SiC MOSFETs. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a dual-pulse test protection device for SiC MOSFETs, the device being connected to an upper-side MOSFET and a lower-side MOSFET respectively; the device includes: a power supply module, a pulse generator, a resistor regulator, a turn-off detector, a turn-on detector, and a data analyzer; the power supply module is connected to the pulse generator, the pulse generator is connected to the resistor regulator, the resistor regulator is connected to both the upper-side MOSFET and the lower-side MOSFET respectively, the pulse generator is used to provide a first pulse test signal and a second pulse test signal to the upper-side MOSFET and the lower-side MOSFET respectively; the turn-on detector is connected to both the lower-side MOSFET and the data analyzer, and is used to acquire a first detection parameter generated by the upper-side MOSFET under the first pulse test signal and a second detection parameter generated by the upper-side MOSFET under the second pulse test signal respectively, and send the first detection parameter or the second detection parameter to the data analyzer; The shutdown detector is connected to the upper transistor, the lower transistor, and the data analyzer, respectively. It is used to acquire the third detection parameter generated by the lower transistor under the first pulse test signal and the fourth detection parameter generated by the lower transistor under the second pulse test signal, and to send the third or fourth detection parameter to the data analyzer. The data analyzer is used to determine whether the first and third detection parameters are within their respective safety threshold ranges. If not, it generates a first adjustment signal to cause the resistor regulator to respond to the first adjustment signal and perform a first protection process. If yes, it determines whether the second and fourth detection parameters are within their respective safety threshold ranges. If not, it generates a second adjustment signal to cause the resistor regulator to respond to the second adjustment signal and perform a second protection process. If yes, the test ends.

[0007] In some embodiments, the pulse generator includes a pulse generator Vgs1; the resistor regulator includes a first resistor regulator, a second resistor regulator, a resistor R1, an inverter D1, and a capacitor C1; wherein, the negative terminal of the pulse generator Vgs1 is connected to a first terminal of the power module, and the positive terminal is connected to a first input terminal of the first resistor regulator; the output terminal of the first resistor regulator is connected to a first input terminal of the second resistor regulator and a first terminal of the resistor R1; the second terminal of the resistor R1 is connected to an input terminal of the inverter D1; the output terminal of the second resistor regulator is connected to a first terminal of the capacitor C1, the gate of the lower transistor device, and the output terminal of the inverter D1; the second terminal of the capacitor C1 is connected to the negative terminal of the pulse generator Vgs1 and grounded; the second input terminals of both the first and second resistor regulators are connected to the input terminal of the data analyzer.

[0008] In some embodiments, the pulse generator includes a pulse generator Vgs1; the resistor regulator includes a first resistor regulator, a second resistor regulator, an inverter D2, an inverter D3, and a capacitor C1; wherein, the negative terminal of the pulse generator Vgs1 is connected to a first terminal of the power module, and the positive terminal is connected to the first input terminal of the first resistor regulator and the first input terminal of the second resistor regulator, respectively; the output terminal of the first resistor regulator is connected to the input terminal of the inverter D2, the output terminal of the second resistor regulator is connected to the input terminal of the inverter D3, the output terminals of the inverter D2 and the inverter D3 are both connected to the first terminal of the capacitor C1 and the gate of the lower transistor device, and the second terminal of the capacitor C1 is connected to the negative terminal of the pulse generator Vgs1 and grounded; the second input terminals of the first resistor regulator and the second resistor regulator are both connected to the input terminal of the data analyzer.

[0009] In some embodiments, the pulse generator includes a pulse generator Vgs2; the turn-off detector includes a first detection module, an inductor L1, an inductor L2, and an inductor L3; wherein the positive terminal of the pulse generator Vgs2 is connected to the gate of the upper transistor device, and the negative terminal is connected to the first terminal of the inductor L3, the first terminal of the first detection module, and the first terminal of the inductor L1, respectively; the second terminal of the first detection module is connected to the source of the upper transistor device, the drain of the upper transistor device, the second terminal of the inductor L1, and the first terminal of the inductor L2 are connected, and the second terminal of the inductor L2 is connected to the second terminal of the power supply module; the third terminal of the first detection module is connected to the input terminal of the data analyzer.

[0010] In some embodiments, the continuity detector includes a second detection module and an inductor L4 connected in sequence; wherein, a first end of the second detection module is connected to the source of the lower transistor device, a third end of the second detection module is connected to the input of the data analyzer, and a second end of the inductor L4 is connected to the negative terminal of the pulse generator Vgs1 and grounded.

[0011] In some embodiments, the power module includes: a constant voltage source Vds and a capacitor C2 connected in parallel; the first end of the constant voltage source Vds and the first end of the capacitor C2 serve as the first end of the power module, and the second end of the constant voltage source Vds and the second end of the capacitor C2 serve as the second end of the power module.

[0012] In some embodiments, the first adjustment signal includes: a first signal and / or a second signal; the first signal is obtained by converting a first deviation value, the first deviation value including the value by which the first detection parameter deviates from the safety threshold range corresponding to the first detection parameter; the second signal is obtained by converting a second deviation value, the second deviation value including the value by which the third detection parameter deviates from the safety threshold range corresponding to the third detection parameter; the second adjustment signal includes: a third signal and / or a fourth signal; the third signal is obtained by converting a third deviation value, the third deviation value including the value by which the second detection parameter deviates from the safety threshold range corresponding to the second detection parameter; the fourth signal is obtained by converting a fourth deviation value, the fourth deviation value including the value by which the fourth detection parameter deviates from the safety threshold range corresponding to the fourth detection parameter.

[0013] In some embodiments, the resistor adjuster includes: a first resistor adjuster and a second resistor adjuster; the first protection process or the second protection process includes: in response to the first adjustment signal or the second adjustment signal, the first resistor adjuster adjusts the overall resistance of the device, and the second resistor adjuster adjusts the difference between the gate on-resistance and the gate off-resistance of the lower transistor device, so that the values ​​of the first detection parameter and the third detection parameter both fall within the corresponding safety threshold range.

[0014] In some embodiments, the first detection parameter, the second detection parameter, the third detection parameter, and the fourth detection parameter have the same parameter type, and each is at least one of current change rate, peak current, and peak voltage.

[0015] Secondly, the present invention provides a dual-pulse test protection method for SiC MOSFETs, the method being applied to the dual-pulse test protection device for SiC MOSFETs described in the first aspect above, the device being connected to an upper-side MOSFET and a lower-side MOSFET respectively; the method includes: acquiring a first detection parameter and a third detection parameter under a first pulse test signal, wherein the first detection parameter refers to the detection parameter generated by the lower-side MOSFET under the first pulse test signal, and the third detection parameter refers to the detection parameter generated by the upper-side MOSFET under the first pulse test signal; determining whether the first detection parameter and the third detection parameter are respectively within their corresponding safety threshold ranges, and if not, performing a first protection process; if yes, acquiring a second detection parameter and a fourth detection parameter under a second pulse test signal, wherein the third detection parameter refers to the detection parameter generated by the lower-side MOSFET under the second pulse test signal, and the fourth detection parameter refers to the detection parameter generated by the upper-side MOSFET under the second pulse test signal; determining whether the second detection parameter and the fourth detection parameter are respectively within their corresponding safety threshold ranges, and if not, performing a second protection process, and if yes, ending the test.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0017] To address the issue of low intelligence in existing dual-pulse testing schemes, this invention provides a dual-pulse testing protection device and method for SiCMOSFETs. This device introduces a conduction detector and a turn-off detector to detect the upper and lower transistors. Specifically, a conduction detector is set at the upper transistor, and a turn-off detector is set at the lower transistor. By acquiring the dynamic parameters generated by the two devices under different test conditions and determining whether these dynamic parameters are within a safe threshold range, different processing measures are automatically executed based on different judgment results. Compared to relying on technicians' experience-based judgments, which are inefficient and prone to human error, the technical solution proposed in this invention has the advantages of high intelligence, simple operation, and high reliability, effectively reducing the operational threshold for test personnel. Attached Figure Description

[0018] Figure 1 This is a structural block diagram of a dual-pulse test protection device for SiC MOSFET proposed in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the structural connection of a dual-pulse test protection device for SiC MOSFET proposed in an embodiment of the present invention;

[0020] Figure 3 This is another structural connection diagram of a dual-pulse test protection device for SiC MOSFET proposed in an embodiment of the present invention;

[0021] Figure 4 This is a schematic flowchart of a dual-pulse test protection method for SiC MOSFETs provided in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0023] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0025] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0026] The present invention will now be described in detail with reference to the accompanying drawings, providing a dual-pulse test protection device and method for SiC MOSFETs.

[0027] Figure 1 This is a structural block diagram of a dual-pulse test protection device for SiC MOSFETs proposed in an embodiment of the present invention. Figure 1As shown, the device is connected to the upper and lower transistors respectively; the device includes: a power module, a pulse generator, a resistor regulator, a turn-off detector, a turn-on detector, and a data analyzer; the power module is connected to the pulse generator, the pulse generator is connected to the resistor regulator, and the resistor regulator is connected to both the upper and lower transistors respectively; the pulse generator is used to provide a first pulse test signal and a second pulse test signal to the upper and lower transistors respectively; the turn-on detector is connected to the lower transistor and the data analyzer respectively, and is used to acquire the first detection parameter generated by the upper transistor under the first pulse test signal and the second detection parameter generated by the upper transistor under the second pulse test signal, and send the first detection parameter or the second detection parameter to the data analyzer; the turn-off detector is connected to the upper transistor and the lower transistor respectively; the pulse generator ... Connected to the upper transistor, lower transistor, and data analyzer, it is used to acquire the third detection parameter generated by the lower transistor under the first pulse test signal and the fourth detection parameter generated by the lower transistor under the second pulse test signal, and send the third or fourth detection parameter to the data analyzer. The data analyzer is used to determine whether the first and third detection parameters are within their respective safety threshold ranges. If not, it generates a first adjustment signal to make the resistor adjuster respond to the first adjustment signal and perform a first protection process. If yes, it determines whether the second and fourth detection parameters are within their respective safety threshold ranges. If not, it generates a second adjustment signal to make the resistor adjuster respond to the second adjustment signal and perform a second protection process. If yes, the test ends.

[0028] Here, the resistor regulator includes two types of connection relationships. The connection relationships of the device will now be described.

[0029] In one possible implementation, such as Figure 2 As shown, the pulse generator includes: a pulse generator Vgs1; the resistor regulator includes: a first resistor regulator, a second resistor regulator, a resistor R1, an inverter D1, and a capacitor C1; wherein, the negative terminal of the pulse generator Vgs1 is connected to the first terminal of the power supply module, and the positive terminal is connected to the first input terminal of the first resistor regulator; the output terminal of the first resistor regulator is connected to the first input terminal of the second resistor regulator and the first terminal of the resistor R1, respectively; the second terminal of the resistor R1 is connected to the input terminal of the inverter D1; the output terminal of the second resistor regulator is connected to the first terminal of the capacitor C1, the gate of the lower transistor device, and the output terminal of the inverter D1, respectively; the second terminal of the capacitor C1 is connected to the negative terminal of the pulse generator Vgs1 and grounded; the second input terminals of both the first and second resistor regulators are connected to the input terminals of the data analyzer.

[0030] In another possible implementation, such as Figure 3As shown, the pulse generator includes: a pulse generator Vgs1; the resistor regulator includes: a first resistor regulator, a second resistor regulator, an inverter D2, an inverter D3, and a capacitor C1; wherein, the negative terminal of the pulse generator Vgs1 is connected to the first terminal of the power supply module, and the positive terminal is connected to the first input terminal of the first resistor regulator and the first input terminal of the second resistor regulator respectively; the output terminal of the first resistor regulator is connected to the input terminal of the inverter D2, and the output terminal of the second resistor regulator is connected to the input terminal of the inverter D3; the output terminals of the inverters D2 and D3 are both connected to the first terminal of the capacitor C1 and the gate of the lower transistor device; the second terminal of the capacitor C1 is connected to the negative terminal of the pulse generator Vgs1 and grounded; the second input terminals of the first resistor regulator and the second resistor regulator are both connected to the input terminal of the data analyzer.

[0031] It should be noted that, Figure 2 and Figure 3 Except for the structure of the resistor regulator, all other structural components are the same.

[0032] Here, the conduction detector includes a second detection module and an inductor L4 connected in sequence; wherein, the first terminal of the second detection module is connected to the source of the lower transistor, the third terminal of the second detection module is connected to the input terminal of the data analyzer, and the second terminal of the inductor L4 is connected to the negative terminal of the pulse generator Vgs1 and grounded. Furthermore, the pulse generator includes a pulse generator Vgs2; the turn-off detector includes a first detection module, inductors L1, L2, and L3; wherein, the positive terminal of the pulse generator Vgs2 is connected to the gate of the upper transistor, and the negative terminal is connected to the first terminal of inductor L3, the first terminal of the first detection module, and the first terminal of inductor L1, respectively; the second terminal of the first detection module is connected to the source of the upper transistor, the drain of the upper transistor, the second terminal of inductor L1, and the first terminal of inductor L2 are connected, the second terminal of inductor L2 is connected to the second terminal of the power supply module; and the third terminal of the first detection module is connected to the input terminal of the data analyzer.

[0033] Here, the power supply module includes: a constant voltage source Vds and a capacitor C2 connected in parallel; the first end of the constant voltage source Vds and the first end of the capacitor C2 serve as the first end of the power supply module, and the second end of the constant voltage source Vds and the second end of the capacitor C2 serve as the second end of the power supply module.

[0034] The working principle of the dual-pulse test protection device for SiC MOSFET proposed in the embodiments of the present invention will now be described.

[0035] Here, during the test, the power supply Vds provides a constant voltage, and the pulse generator provides a positive voltage (typically 15V to 22V) to turn on the device and a negative voltage (typically -5V) to turn it off. The upper transistor, acting as a reverse recovery transistor, is always in the off state. The lower transistor, acting as the main test transistor, undergoes two pulse test signals (or two test conditions). The first pulse test signal turns the device on, transitioning it from the off state to the on state, and the second pulse test signal turns the device off, transitioning it from the on state to the off state. There is a time interval between these two pulse test signals, allowing the device to remain in a stable state between the two pulses. Correspondingly, the first test condition refers to the lower transistor transitioning from the off state to the on state in response to the first pulse signal; the second test condition refers to the lower transistor transitioning from the on state to the off state in response to the second pulse signal. It should be noted that both the upper and lower transistors are NMOS transistors.

[0036] Furthermore, dynamic parameters were acquired using a turn-off detector and a turn-on detector under both test conditions. Since SiCMOSFETs are prone to overstress conditions such as current peaks and voltage peaks during switching, which can damage the device, it is necessary to detect the switching current and peak switching voltage. Specifically, the first, second, third, and fourth detection parameters are of the same type and are all at least one of the following: current change rate, peak current, and peak voltage.

[0037] Here, the conduction detector and the turn-off detector can be a current sensing sensor, a voltage sensing sensor, and a multimeter. Since the upper transistor is susceptible to stress damage when the lower transistor is on and when it is off, a conduction detector is used to detect the current stress value at the upper transistor when the lower transistor is on (under the first test condition); and a turn-off detector is used to detect the current stress value at the lower transistor when the lower transistor is off (under the second test condition). The detected dynamic parameters are then sent to a data analyzer. The data analyzer determines whether the dynamic parameters at the corresponding upper or lower transistor are within the safety threshold range under the first or second test condition. If, under the first test condition, the first detected parameter is not within the corresponding safety threshold range and / or the third detected parameter is not within the corresponding safety threshold range, a first adjustment signal is generated. Similarly, under the second test condition, if the second detected parameter is not within the corresponding safety threshold range and / or the fourth detected parameter is not within the corresponding safety threshold range, a second adjustment signal is generated. Specifically, the first adjustment signal includes: a first signal and / or a second signal; the first signal is obtained by converting a first deviation value, the first deviation value including the value by which the first detection parameter deviates from the safety threshold range corresponding to the first detection parameter; the second signal is obtained by converting a second deviation value, the second deviation value including the value by which the third detection parameter deviates from the safety threshold range corresponding to the third detection parameter; and the second adjustment signal includes: a third signal and / or a fourth signal; the third signal is obtained by converting a third deviation value, the third deviation value including the value by which the second detection parameter deviates from the safety threshold range corresponding to the second detection parameter; the fourth signal is obtained by converting a fourth deviation value, the fourth deviation value including the value by which the fourth detection parameter deviates from the safety threshold range corresponding to the fourth detection parameter.

[0038] Here, the first protection process or the second protection process includes: in response to the first adjustment signal or the second adjustment signal, the first resistor adjuster adjusts the overall resistance value of the device, and the second resistor adjuster adjusts the difference between the gate on-resistance and the gate off-resistance of the lower transistor device, so that the values ​​of the first detection parameter and the third detection parameter both fall within the corresponding safety threshold range.

[0039] In one possible implementation, both the first and second resistor regulators are variable resistors, which may include: digital potentiometers, sliding rheostats, rotary variable resistors, linear variable resistors, and nonlinear rheostats.

[0040] It should be noted that, firstly, the resistance value of the overall test circuit is adjusted multiple times using the first resistor adjuster, with an adjustment range of 0 to 50Ω, to determine the approximate resistance variation range. Subsequently, the difference between the gate on-resistance and turn-off resistance of the lower transistor is adjusted multiple times using the second resistor adjuster, so that the dynamic parameters detected by the turn-off detector and the turn-on detector are within their respective safe threshold ranges. By using the first and second resistor adjusters together, the differences in the turn-on and turn-off performance of different devices can be adapted, which is beneficial to improving the dynamic detection performance of the dual-pulse test circuit and enhancing test safety.

[0041] Corresponding to the dual-pulse test protection device for SiC MOSFETs proposed in the embodiments of the present invention, the embodiments of the present invention also provide a dual-pulse test protection method for SiC MOSFETs. The method is applied to the aforementioned dual-pulse test protection device for SiC MOSFETs, and the device is connected to both the upper and lower MOSFET devices respectively. Figure 4 This is a schematic flowchart of a dual-pulse test protection method for SiC MOSFETs provided in an embodiment of the present invention. Figure 4 As shown, the method includes:

[0042] Step 110: Obtain the first detection parameter and the third detection parameter under the first pulse test signal. The first detection parameter refers to the detection parameter generated by the lower transistor device under the first pulse test signal, and the third detection parameter refers to the detection parameter generated by the upper transistor device under the first pulse test signal.

[0043] Here, the lower transistor device responds to the first pulse signal to switch from the off state to the on state, the on detector acquires the first detection parameter, and the off detector acquires the third detection parameter, wherein the first detection parameter or the third detection parameter includes at least one of the current change rate, peak current, and peak voltage.

[0044] Step 120: Determine whether the first detection parameter and the third detection parameter are within their respective safety threshold ranges. If not, execute the first protection process.

[0045] Here, after receiving the first and third detection parameters, the data analyzer judges them respectively and performs corresponding processing based on different results. For the sake of brevity, this will not be elaborated here.

[0046] Step 130: If yes, obtain the second detection parameter and the fourth detection parameter under the second pulse test signal. The third detection parameter refers to the detection parameter generated by the lower transistor device under the second pulse test signal, and the fourth detection parameter refers to the detection parameter generated by the upper transistor device under the second pulse test signal.

[0047] Here, the lower transistor device responds to the second pulse signal to switch from the on state to the off state. The on detector acquires the second detection parameter, and the off detector acquires the fourth detection parameter. The second or fourth detection parameter includes at least one of the current change rate, peak current, and peak voltage.

[0048] Step 140: Determine whether the second detection parameter and the fourth detection parameter are within their respective safety threshold ranges. If not, execute the second protection process; if yes, end the test.

[0049] To address the issue of low intelligence in existing dual-pulse testing schemes, this invention provides a dual-pulse testing protection device and method for SiCMOSFETs. This device introduces a conduction detector and a turn-off detector to detect the upper and lower transistors. Specifically, a conduction detector is set at the upper transistor, and a turn-off detector is set at the lower transistor. By acquiring the dynamic parameters generated by the two devices under different testing conditions and determining whether these dynamic parameters are within a safe threshold range, different processing measures are automatically executed based on different judgment results. Compared to relying on technicians' experience values ​​for judgment, which is inefficient and prone to human error, the technical solution proposed in this invention has the advantages of high intelligence, high recognition accuracy, and high operational reliability.

[0050] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A dual-pulse test protection device for SiC MOSFETs, wherein the device is connected to both the upper and lower MOSFET devices respectively; characterized in that, The device includes: a power module, a pulse generator, a resistor regulator, a shutdown detector, a conduction detector, and a data analyzer; the power module is connected to the pulse generator, the pulse generator is connected to the resistor regulator, the resistor regulator is connected to the upper transistor and the lower transistor respectively, and the pulse generator is used to provide a first pulse test signal and a second pulse test signal to the upper transistor and the lower transistor respectively; The conduction detector is connected to the lower transistor device and the data analyzer respectively, and is used to acquire the first detection parameter generated by the lower transistor device under the first pulse test signal and the second detection parameter generated by the lower transistor device under the second pulse test signal, and send the first detection parameter or the second detection parameter to the data analyzer. The shutdown detector is connected to the upper transistor, the lower transistor, and the data analyzer, respectively, and is used to acquire the third detection parameter generated by the upper transistor under the first pulse test signal and the fourth detection parameter generated by the upper transistor under the second pulse test signal, and send the third detection parameter or the fourth detection parameter to the data analyzer. The data analyzer is used to determine whether the first detection parameter and the third detection parameter are respectively within the corresponding safety threshold range. If not, it generates a first adjustment signal so that the resistor adjuster responds to the first adjustment signal and performs a first protection process. If yes, it determines whether the second detection parameter and the fourth detection parameter are respectively within the corresponding safety threshold range. If not, it generates a second adjustment signal so that the resistor adjuster responds to the second adjustment signal and performs a second protection process. If yes, it ends the test. The resistor adjuster includes: a first resistor adjuster and a second resistor adjuster; the first protection process or the second protection process includes: In response to the first adjustment signal or the second adjustment signal, the first resistor adjuster adjusts the overall resistance of the device, and the second resistor adjuster adjusts the difference between the gate on-resistance and the gate off-resistance of the lower transistor device, so that the values ​​of the first detection parameter and the third detection parameter both fall within the corresponding safety threshold range. The first detection parameter, the second detection parameter, the third detection parameter, and the fourth detection parameter have the same parameter type, and each of them is at least one of current change rate, peak current, and peak voltage.

2. The dual-pulse test protection device for SiC MOSFET according to claim 1, characterized in that, The pulse generator includes: a pulse generator Vgs1; the resistor adjuster includes: a first resistor adjuster, a second resistor adjuster, a resistor R1, an inverter D1, and a capacitor C1; Wherein, the negative terminal of the pulse generator Vgs1 is connected to the first terminal of the power module, and the positive terminal is connected to the first input terminal of the first resistor regulator. The output terminal of the first resistor regulator is connected to the first input terminal of the second resistor regulator and the first terminal of the resistor R1. The second terminal of the resistor R1 is connected to the input terminal of the inverter D1. The output terminal of the second resistor regulator is connected to the first terminal of the capacitor C1, the gate of the lower transistor device, and the output terminal of the inverter D1. The second terminal of the capacitor C1 is connected to the negative terminal of the pulse generator Vgs1 and grounded. The second input terminal of the first resistor regulator and the second input terminal of the second resistor regulator are both connected to the input terminal of the data analyzer.

3. The dual-pulse test protection device for SiC MOSFET according to claim 1, characterized in that, The pulse generator includes: a pulse generator Vgs1; the resistor adjuster includes: a first resistor adjuster, a second resistor adjuster, an inverter D2, an inverter D3, and a capacitor C1; In this configuration, the negative terminal of the pulse generator Vgs1 is connected to the first terminal of the power module, and the positive terminal is connected to the first input terminal of the first resistor regulator and the first input terminal of the second resistor regulator. The output terminal of the first resistor regulator is connected to the input terminal of the inverter D2, and the output terminal of the second resistor regulator is connected to the input terminal of the inverter D3. The output terminals of the inverter D2 and the inverter D3 are both connected to the first terminal of the capacitor C1 and the gate of the lower transistor. The second terminal of the capacitor C1 is connected to the negative terminal of the pulse generator Vgs1 and grounded. The second input terminal of the first resistor regulator and the second input terminal of the second resistor regulator are both connected to the input terminal of the data analyzer.

4. The dual-pulse test protection device for SiC MOSFET according to claim 1, characterized in that, The pulse generator includes: pulse generator Vgs2; the shutdown detector includes: a first detection module, inductor L1, inductor L2 and inductor L3; The positive terminal of the pulse generator Vgs2 is connected to the gate of the upper transistor device, and the negative terminal is connected to the first terminal of the inductor L3, the first terminal of the first detection module, and the first terminal of the inductor L1, respectively. The second terminal of the first detection module is connected to the source of the upper transistor device, the drain of the upper transistor device, the second terminal of the inductor L1 and the first terminal of the inductor L2 are connected, and the second terminal of the inductor L2 is connected to the second terminal of the power supply module. The third end of the first detection module is connected to the input end of the data analyzer.

5. The dual-pulse test protection device for SiC MOSFET according to claim 2 or 3, characterized in that, The continuity detector includes: a second detection module and an inductor L4 connected in sequence; The first end of the second detection module is connected to the source of the lower transistor device, the third end of the second detection module is connected to the input of the data analyzer, and the second end of the inductor L4 is connected to the negative terminal of the pulse generator Vgs1 and grounded.

6. The dual-pulse test protection device for SiC MOSFET according to claim 1, characterized in that, The power module includes a constant voltage source Vds and a capacitor C2 connected in parallel. The first end of the constant voltage source Vds and the first end of the capacitor C2 serve as the first end of the power supply module, and the second end of the constant voltage source Vds and the second end of the capacitor C2 serve as the second end of the power supply module.

7. The dual-pulse test protection device for SiC MOSFET according to claim 1, characterized in that, The first adjustment signal includes: a first signal and / or a second signal; the first signal is obtained by converting a first deviation value, the first deviation value including the value by which the first detection parameter deviates from the safety threshold range corresponding to the first detection parameter; the second signal is obtained by converting a second deviation value, the second deviation value including the value by which the third detection parameter deviates from the safety threshold range corresponding to the third detection parameter; The second adjustment signal includes: a third signal and / or a fourth signal; the third signal is obtained by converting a third deviation value, the third deviation value including the value by which the second detection parameter deviates from the safety threshold range corresponding to the second detection parameter; the fourth signal is obtained by converting a fourth deviation value, the fourth deviation value including the value by which the fourth detection parameter deviates from the safety threshold range corresponding to the fourth detection parameter.

8. A dual-pulse test protection method for SiC MOSFETs, characterized in that, The method is applied to the dual-pulse test protection device for SiC MOSFETs according to any one of claims 1 to 7, wherein the device is connected to the upper MOSFET and the lower MOSFET respectively; the method includes: Acquire a first detection parameter and a third detection parameter under the first pulse test signal. The first detection parameter refers to the detection parameter generated by the lower transistor device under the first pulse test signal, and the third detection parameter refers to the detection parameter generated by the upper transistor device under the first pulse test signal. Determine whether the first detection parameter and the third detection parameter are within their respective safety threshold ranges. If not, execute the first protection process. If so, obtain the second detection parameter and the fourth detection parameter under the second pulse test signal, wherein the third detection parameter refers to the detection parameter generated by the lower transistor device under the second pulse test signal, and the fourth detection parameter refers to the detection parameter generated by the upper transistor device under the second pulse test signal; Determine whether the second detection parameter and the fourth detection parameter are within their respective safety threshold ranges. If not, perform the second protection process; if yes, end the test.

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