RTL parallel test method and system of RISC-V DSP chip and medium

Abstract

The embodiment of the invention provides an RTL parallel test method and system for an RISC-V DSP chip and a medium, and the method comprises the steps: obtaining a plurality of test items, classifying the plurality of test items based on a classification rule, and obtaining different types of test items; constructing a plurality of test channels based on an RTL test framework, and obtaining test parameter information of each test channel; matching different types of test items with the test parameters of each test channel to obtain a matching degree, and judging whether the matching degree is greater than or equal to a set matching degree threshold; if yes, the corresponding test channel is matched, and if not, unmatched test items are shielded through the test channel; testing the plurality of test items in parallel according to the matched test channels; the test items are classified by analyzing the categories of the test items, and different test items select different test channels, so that parallel testing of different categories of test items is realized, and the test efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to an RTL parallel testing method, system and medium for a RISC-V DSP chip. Background Art

[0002] The RTL batch automatic testing framework is used to perform batch automatic testing in the scenario of multiple projects / multiple test case sets at the RTL (Register-Transfer Level) level during VERILOG design.

[0003] The RTL batch automatic testing framework includes general configuration and independent configuration information for each project, a set of input stimuli (test cases) for each project, and RTL design code for each project. It conforms to the test stimulus-test environment-test output architecture design and can be used to test the RTL code of each project itself, as well as the key data used by the RTL code. It can also test various input stimuli, which may have specific functions in subsequent applications. Existing chip testing methods cannot perform multi-test channel parallel testing according to different test items, making it difficult to test the chip efficiently and accurately, affecting the test effect. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide an RTL parallel testing method, system and medium for a RISC-V DSP chip, which classifies the test items by analyzing the categories of the test items, selects different test channels for different test items, implements parallel testing of test items of different categories, and improves test efficiency.

[0005] The embodiment of the present application also provides an RTL parallel testing method for a RISC-V DSP chip, including:

[0006] Acquire multiple test items, and classify the multiple test items based on classification rules to obtain test items of different categories;

[0007] Build multiple test channels based on the RTL test framework and obtain the test parameter information of each test channel;

[0008] Matching different categories of test items with the test parameters of each test channel to obtain a matching degree, and determining whether the matching degree is greater than or equal to a set matching degree threshold;

[0009] If it is greater than or equal to the set matching threshold, the test item is matched with the corresponding test channel. If it is less than, the unmatched test items are blocked through the test channel.

[0010] Multiple test items are tested in parallel according to matching test channels to obtain parallel test data.

[0011] Optionally, in the RTL parallel testing method of the RISC-V DSP chip described in the embodiment of the present application, multiple test items are obtained, and the multiple test items are classified based on the classification rules to obtain test items of different categories, specifically including:

[0012] Obtain the test requirement information and test target information for each test item;

[0013] Establish multiple test requirement intervals and multiple test target intervals based on classification rules;

[0014] Analyze the test requirement interval and test target interval to which the test project belongs, and obtain the analysis results;

[0015] Based on the analysis results, multiple test items are classified to obtain test items of different categories.

[0016] Optionally, in the RTL parallel testing method of the RISC-V DSP chip described in the embodiment of the present application, multiple test channels are constructed based on the RTL test framework, and test parameter information of each test channel is obtained, specifically including:

[0017] Based on the RTL test framework, general configuration information and independent configuration information are obtained. The general configuration information includes interaction logic, test process control logic, data processing logic, and result summary logic; the independent configuration information includes the project's dependency path, required special variables, data processing / transfer detail configuration, and post-compilation processing logic;

[0018] Matching the common configuration information with the independent configuration information to obtain multiple matching categories;

[0019] Establish multiple test channels based on multiple matching categories, and obtain common configuration information and independent configuration information for each test channel;

[0020] Based on the common configuration information and independent configuration information of each test channel, the test parameter information of the corresponding test channel is obtained.

[0021] Optionally, in the RTL parallel testing method of the RISC-V DSP chip described in the embodiment of the present application, different categories of test items are matched with the test parameters of each test channel to obtain a matching degree, specifically including:

[0022] Get the category of the test item;

[0023] Analyze the requirements and objectives of the test items based on their categories;

[0024] Get the general configuration information and independent configuration information of the test channel;

[0025] The requirement information and target information of the test project are matched with the general configuration information and independent configuration information of the test channel to obtain the matching degree.

[0026] Optionally, in the RTL parallel testing method of the RISC-V DSP chip described in the embodiment of the present application, matching the test items to corresponding test channels specifically includes:

[0027] Get the matching degree between the test items and the test channels;

[0028] Comparing the matching degree with a set matching degree threshold, wherein the set matching degree threshold includes a first matching degree threshold and a second matching degree threshold, and the first matching degree threshold is less than the second matching degree threshold;

[0029] If the matching degree is greater than the first matching degree threshold and less than the second matching degree threshold, the test items are allocated to at least two test channels, and the test channels are adjusted according to the running queue time of the test channels;

[0030] If the matching degree is greater than the second matching degree threshold, the test item is analyzed into the current test channel.

[0031] Optionally, in the RTL parallel testing method of the RISC-V DSP chip described in the embodiment of the present application, multiple test items are tested in parallel according to matching test channels to obtain parallel test data, specifically including:

[0032] Obtain the test items and the test channels that match the test items, queue the test items under each test channel, and obtain the queue information;

[0033] Get the running time and remaining test time of the current test item of each test channel, and analyze the running queue time of the test item based on the remaining test time;

[0034] Test the test items in different test channels in parallel and analyze the test status information synchronously;

[0035] Dynamically adjust the test channel matching the test items based on the test status information and the running queue time.

[0036] In a second aspect, an embodiment of the present application provides an RTL parallel testing system for a RISC-V DSP chip, the system comprising: a memory and a processor, the memory comprising a program of an RTL parallel testing method for a RISC-V DSP chip, and the program of the RTL parallel testing method for a RISC-V DSP chip is executed by the processor to implement the following steps:

[0037] Acquire multiple test items, and classify the multiple test items based on classification rules to obtain test items of different categories;

[0038] Build multiple test channels based on the RTL test framework and obtain the test parameter information of each test channel;

[0039] Matching different categories of test items with the test parameters of each test channel to obtain a matching degree, and determining whether the matching degree is greater than or equal to a set matching degree threshold;

[0040] If it is greater than or equal to the set matching threshold, the test item is matched with the corresponding test channel. If it is less than, the unmatched test items are blocked through the test channel.

[0041] Multiple test items are tested in parallel according to matching test channels to obtain parallel test data.

[0042] Optionally, in the RTL parallel test system of the RISC-V DSP chip described in the embodiment of the present application, multiple test items are obtained, and the multiple test items are classified based on the classification rules to obtain test items of different categories, specifically including:

[0043] Obtain the test requirement information and test target information for each test item;

[0044] Establish multiple test requirement intervals and multiple test target intervals based on classification rules;

[0045] Analyze the test requirement interval and test target interval to which the test project belongs, and obtain the analysis results;

[0046] Based on the analysis results, multiple test items are classified to obtain test items of different categories.

[0047] Optionally, in the RTL parallel test system of the RISC-V DSP chip described in the embodiment of the present application, multiple test channels are constructed based on the RTL test framework, and test parameter information of each test channel is obtained, specifically including:

[0048] Based on the RTL test framework, general configuration information and independent configuration information are obtained. The general configuration information includes interaction logic, test process control logic, data processing logic, and result summary logic; the independent configuration information includes the project's dependency path, required special variables, data processing / transfer detail configuration, and post-compilation processing logic;

[0049] Matching the common configuration information with the independent configuration information to obtain multiple matching categories;

[0050] Establish multiple test channels based on multiple matching categories, and obtain common configuration information and independent configuration information for each test channel;

[0051] Based on the common configuration information and independent configuration information of each test channel, the test parameter information of the corresponding test channel is obtained.

[0052] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium includes an RTL parallel testing method program for a RISC-V DSP chip. When the RTL parallel testing method program for a RISC-V DSP chip is executed by a processor, the steps of the RTL parallel testing method for a RISC-V DSP chip as described in any one of the above items are implemented.

[0053] As can be seen from the above, an RTL parallel testing method, system and medium for a RISC-V DSP chip provided in an embodiment of the present application obtains multiple test items, classifies the multiple test items based on classification rules, and obtains test items of different categories; constructs multiple test channels based on an RTL test framework, and obtains test parameter information of each test channel; matches test items of different categories with test parameters of each test channel to obtain a matching degree, and determines whether the matching degree is greater than or equal to a set matching degree threshold; if greater than or equal to, matches the test item to the corresponding test channel, and if less than, shields the unmatched test item through the test channel; tests multiple test items in parallel according to matching test channels to obtain parallel test data; classifies the test items by analyzing their categories, selects different test channels for different test items, and implements parallel testing of test items of different categories, thereby improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 A flowchart of the RTL parallel testing method for a RISC-V DSP chip provided in an embodiment of the present application;

[0056] Figure 2 A flow chart of category analysis of test items of the RTL parallel testing method for a RISC-V DSP chip provided in an embodiment of the present application;

[0057] Figure 3 A flow chart of a method for analyzing test parameter information of a test channel of an RTL parallel test method for a RISC-V DSP chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0059] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0060] Please refer to Figure 1 , Figure 1 The flowchart of the RTL parallel testing method of a RISC-V DSP chip in some embodiments of the present application. The RTL parallel testing method of the RISC-V DSP chip is used in a terminal device, and the RTL parallel testing method of the RISC-V DSP chip includes the following steps:

[0061] S101, obtaining a plurality of test items, and classifying the plurality of test items based on a classification rule to obtain test items of different categories;

[0062] S102, building multiple test channels based on the RTL test framework, and obtaining test parameter information of each test channel;

[0063] S103, matching different types of test items with the test parameters of each test channel to obtain a matching degree, and determining whether the matching degree is greater than or equal to a set matching degree threshold;

[0064] S104, if it is greater than or equal to the set matching degree threshold, the test item is matched with the corresponding test channel; if it is less than, the unmatched test items are shielded through the test channel;

[0065] S105, testing multiple test items in parallel according to matching test channels to obtain parallel test data.

[0066] It should be noted that by analyzing the categories of the test items and selecting different test channels, it is ensured that test items of different categories can be tested in parallel in multiple test channels, thereby improving the test efficiency.

[0067] Please refer to Figure 2 , Figure 2 This is a flow chart of category analysis of test items of a RTL parallel test method for a RISC-V DSP chip in some embodiments of the present application. According to an embodiment of the present invention, multiple test items are obtained, and the multiple test items are classified based on classification rules to obtain test items of different categories, specifically including:

[0068] S201, obtaining test requirement information and test target information of each test item;

[0069] S202, establishing multiple test requirement intervals and multiple test target intervals based on the classification rules;

[0070] S203, analyzing the test requirement interval and the test target interval to which the test item belongs, and obtaining an analysis result;

[0071] S204: Classify the multiple test items based on the analysis result to obtain test items of different categories.

[0072] It should be noted that by analyzing the test requirements and test objectives of the test items, the test items can be accurately analyzed to improve the classification accuracy.

[0073] Please refer to Figure 3 , Figure 3 The present invention is a flow chart of a test parameter information analysis method of a test channel of an RTL parallel test method for a RISC-V DSP chip in some embodiments of the present invention. According to an embodiment of the present invention, multiple test channels are constructed based on an RTL test framework, and test parameter information of each test channel is obtained, specifically including:

[0074] S301, obtaining general configuration information and independent configuration information based on the RTL test framework, wherein the general configuration information includes interaction logic, test process control logic, data processing logic, and result aggregation logic; the independent configuration information includes the project's dependency path, required special variables, data processing / transfer detail configuration, and post-compilation processing logic;

[0075] S302, matching the general configuration information with the independent configuration information to obtain a plurality of matching categories;

[0076] S303, establishing multiple test channels based on multiple matching categories, and obtaining common configuration information and independent configuration information of each test channel;

[0077] S304: Acquire test parameter information of the corresponding test channel based on the common configuration information and independent configuration information of each test channel.

[0078] It should be noted that by analyzing the general configuration and independent configuration of the test framework, matching category analysis is performed, and then multiple test channels are established to ensure that different test channels correspond to different test parameters, thereby preventing repeated settings of test channels.

[0079] According to an embodiment of the present invention, different types of test items are matched with the test parameters of each test channel to obtain a matching degree, which specifically includes:

[0080] Get the category of the test item;

[0081] Analyze the requirements and objectives of the test items based on their categories;

[0082] Get the general configuration information and independent configuration information of the test channel;

[0083] The requirement information and target information of the test project are matched with the general configuration information and independent configuration information of the test channel to obtain the matching degree.

[0084] It should be noted that by analyzing the categories to which the test items belong, it is possible to determine whether the general configuration and independent configuration of the test channel meet the requirements, and to analyze the matching degree between the test channel and the test items to improve the analysis accuracy.

[0085] According to an embodiment of the present invention, matching a test item to a corresponding test channel specifically includes:

[0086] Get the matching degree between the test items and the test channels;

[0087] Comparing the matching degree with a set matching degree threshold, where the set matching degree threshold includes a first matching degree threshold and a second matching degree threshold, and the first matching degree threshold is less than the second matching degree threshold;

[0088] If the matching degree is greater than the first matching degree threshold and less than the second matching degree threshold, the test items are allocated to at least two test channels, and the test channels are adjusted according to the running queue time of the test channels;

[0089] If the matching degree is greater than the second matching degree threshold, the test item is analyzed into the current test channel.

[0090] It should be noted that by analyzing the matching degree between the test item and the test channel and comparing the matching degree with different matching degree thresholds, different matching degrees correspond to different test channels, thereby ensuring that the test item can be efficiently tested in the matching test channel, thereby improving test efficiency.

[0091] According to an embodiment of the present invention, multiple test items are tested in parallel according to matching test channels to obtain parallel test data, which specifically includes:

[0092] Obtain the test items and the test channels that match the test items, queue the test items under each test channel, and obtain the queue information;

[0093] Get the running time and remaining test time of the current test item of each test channel, and analyze the running queue time of the test item based on the remaining test time;

[0094] Test the test items in different test channels in parallel and analyze the test status information synchronously;

[0095] Dynamically adjust the test channel matching the test items based on the test status information and the running queue time.

[0096] It should be noted that by analyzing the queuing information of the test items, the running queuing time of the test items is analyzed, and the test channels are dynamically adjusted according to the running queuing time to ensure that the test items can be tested quickly and improve the test efficiency.

[0097] According to an embodiment of the present invention, the method further includes: obtaining the number of queued test items under each test channel, analyzing the required test time of each test item, and obtaining the queue time of the test item;

[0098] Analyze the total queue time of each test channel based on the queue time of the test items;

[0099] Analyze the test time based on the sum of the queue time for each test channel;

[0100] Dynamically adjust the test items to other matching test channels based on the test time to obtain adjustment results;

[0101] Dynamically adjust the test channels of the test items based on the adjustment results.

[0102] It should be noted that by analyzing the queuing time of the test items and dynamically testing the channels, it is ensured that the queuing time of the test items in each test channel is basically the same, and that all test items are completed in the same time period, thereby improving the test efficiency of the test items.

[0103] In a second aspect, an embodiment of the present application provides an RTL parallel testing system for a RISC-V DSP chip, the system comprising: a memory and a processor, the memory comprising a program of an RTL parallel testing method for a RISC-V DSP chip, and when the program of the RTL parallel testing method for a RISC-V DSP chip is executed by the processor, the following steps are implemented:

[0104] Acquire multiple test items, and classify the multiple test items based on classification rules to obtain test items of different categories;

[0105] Build multiple test channels based on the RTL test framework and obtain the test parameter information of each test channel;

[0106] Match different categories of test items with the test parameters of each test channel to obtain a matching degree, and determine whether the matching degree is greater than or equal to a set matching degree threshold;

[0107] If it is greater than or equal to the set matching threshold, the test item is matched with the corresponding test channel. If it is less than, the unmatched test items are blocked through the test channel.

[0108] Multiple test items are tested in parallel according to matching test channels to obtain parallel test data.

[0109] It should be noted that by analyzing the categories of the test items and selecting different test channels, it is ensured that test items of different categories can be tested in parallel in multiple test channels, thereby improving the test efficiency.

[0110] According to an embodiment of the present invention, a plurality of test items are obtained, and the plurality of test items are classified based on a classification rule to obtain test items of different categories, specifically including:

[0111] Obtain the test requirement information and test target information for each test item;

[0112] Establish multiple test requirement intervals and multiple test target intervals based on classification rules;

[0113] Analyze the test requirement interval and test target interval to which the test project belongs, and obtain the analysis results;

[0114] Based on the analysis results, multiple test items are classified to obtain test items of different categories.

[0115] It should be noted that by analyzing the test requirements and test objectives of the test items, the test items can be accurately analyzed to improve the classification accuracy.

[0116] According to an embodiment of the present invention, multiple test channels are constructed based on the RTL test framework, and test parameter information of each test channel is obtained, which specifically includes:

[0117] Based on the RTL test framework, general configuration information and independent configuration information are obtained. General configuration information includes interaction logic, test process control logic, data processing logic, and result summary logic; independent configuration information includes the project's dependency path, required special variables, data processing / transfer details configuration, and post-compilation processing logic;

[0118] Matching the common configuration information with the independent configuration information to obtain multiple matching categories;

[0119] Establish multiple test channels based on multiple matching categories, and obtain common configuration information and independent configuration information for each test channel;

[0120] Based on the common configuration information and independent configuration information of each test channel, the test parameter information of the corresponding test channel is obtained.

[0121] It should be noted that by analyzing the general configuration and independent configuration of the test framework, matching category analysis is performed, and then multiple test channels are established to ensure that different test channels correspond to different test parameters, thereby preventing repeated settings of test channels.

[0122] According to an embodiment of the present invention, different types of test items are matched with the test parameters of each test channel to obtain a matching degree, which specifically includes:

[0123] Get the category of the test item;

[0124] Analyze the requirements and objectives of the test items based on their categories;

[0125] Get the general configuration information and independent configuration information of the test channel;

[0126] The requirement information and target information of the test project are matched with the general configuration information and independent configuration information of the test channel to obtain the matching degree.

[0127] It should be noted that by analyzing the categories to which the test items belong, it is possible to determine whether the general configuration and independent configuration of the test channel meet the requirements, and to analyze the matching degree between the test channel and the test items to improve the analysis accuracy.

[0128] According to an embodiment of the present invention, matching a test item to a corresponding test channel specifically includes:

[0129] Get the matching degree between the test items and the test channels;

[0130] Comparing the matching degree with a set matching degree threshold, where the set matching degree threshold includes a first matching degree threshold and a second matching degree threshold, and the first matching degree threshold is less than the second matching degree threshold;

[0131] If the matching degree is greater than the first matching degree threshold and less than the second matching degree threshold, the test items are allocated to at least two test channels, and the test channels are adjusted according to the running queue time of the test channels;

[0132] If the matching degree is greater than the second matching degree threshold, the test item is analyzed into the current test channel.

[0133] It should be noted that by analyzing the matching degree between the test item and the test channel and comparing the matching degree with different matching degree thresholds, different matching degrees correspond to different test channels, thereby ensuring that the test item can be efficiently tested in the matching test channel, thereby improving test efficiency.

[0134] According to an embodiment of the present invention, multiple test items are tested in parallel according to matching test channels to obtain parallel test data, which specifically includes:

[0135] Obtain the test items and the test channels that match the test items, queue the test items under each test channel, and obtain the queue information;

[0136] Get the running time and remaining test time of the current test item of each test channel, and analyze the running queue time of the test item based on the remaining test time;

[0137] Test the test items in different test channels in parallel and analyze the test status information synchronously;

[0138] Dynamically adjust the test channel matching the test items based on the test status information and the running queue time.

[0139] It should be noted that by analyzing the queuing information of the test items, the running queuing time of the test items is analyzed, and the test channels are dynamically adjusted according to the running queuing time to ensure that the test items can be tested quickly and improve the test efficiency.

[0140] According to an embodiment of the present invention, the method further includes: obtaining the number of queued test items under each test channel, analyzing the required test time of each test item, and obtaining the queue time of the test item;

[0141] Analyze the total queue time of each test channel based on the queue time of the test items;

[0142] Analyze the test time based on the sum of the queue time for each test channel;

[0143] Dynamically adjust the test items to other matching test channels based on the test time to obtain adjustment results;

[0144] Dynamically adjust the test channels of the test items based on the adjustment results.

[0145] It should be noted that by analyzing the queuing time of the test items and dynamically testing the channels, it is ensured that the queuing time of the test items in each test channel is basically the same, and that all test items are completed in the same time period, thereby improving the test efficiency of the test items.

[0146] A third aspect of the present invention provides a computer-readable storage medium, which includes an RTL parallel testing method program for a RISC-V DSP chip. When the RTL parallel testing method program for a RISC-V DSP chip is executed by a processor, the steps of the RTL parallel testing method for a RISC-V DSP chip as described in any of the above items are implemented.

[0147] The present invention discloses an RTL parallel testing method, system and medium for a RISC-V DSP chip. The method comprises the following steps: obtaining a plurality of test items, classifying the plurality of test items based on a classification rule, and obtaining test items of different categories; constructing a plurality of test channels based on an RTL test framework, and obtaining test parameter information of each test channel; matching the test items of different categories with the test parameters of each test channel to obtain a matching degree, and judging whether the matching degree is greater than or equal to a set matching degree threshold; if the matching degree is greater than or equal to the matching degree, matching the test items with the corresponding test channels, and if the matching degree is less than the matching degree, shielding the unmatched test items through the test channels; testing the plurality of test items in parallel according to the matched test channels to obtain parallel test data; classifying the test items by analyzing the categories of the test items, selecting different test channels for different test items, and implementing parallel testing of test items of different categories, thereby improving test efficiency.

[0148] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0149] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0150] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0151] Those skilled in the art can understand that: all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions, the aforementioned program can be stored in a readable storage medium, and when the program is executed, it executes the steps of the above method embodiments; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), disks or optical disks, and other media that can store program codes.

[0152] Or, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

Claims

1. A RTL parallel testing method for a RISC-V DSP chip, characterized in that: include: Acquire multiple test items, and classify the multiple test items based on classification rules to obtain test items of different categories; Build multiple test channels based on the RTL test framework and obtain the test parameter information of each test channel; Matching different categories of test items with the test parameters of each test channel to obtain a matching degree, and determining whether the matching degree is greater than or equal to a set matching degree threshold; If it is greater than or equal to the set matching threshold, the test item is matched with the corresponding test channel. If it is less than, the unmatched test items are blocked through the test channel. Multiple test items are tested in parallel according to matching test channels to obtain parallel test data.

2. The RTL parallel testing method of the RISC-V DSP chip according to claim 1, characterized in that: Obtain multiple test items, classify the multiple test items based on classification rules, and obtain test items of different categories, including: Obtain the test requirement information and test target information for each test item; Establish multiple test requirement intervals and multiple test target intervals based on classification rules; Analyze the test requirement interval and test target interval to which the test project belongs, and obtain the analysis results; Based on the analysis results, multiple test items are classified to obtain test items of different categories.

3. The RTL parallel testing method of the RISC-V DSP chip according to claim 2, characterized in that: Build multiple test channels based on the RTL test framework and obtain the test parameter information of each test channel, including: Based on the RTL test framework, general configuration information and independent configuration information are obtained. The general configuration information includes interaction logic, test process control logic, data processing logic, and result summary logic; the independent configuration information includes the project's dependency path, required special variables, data processing / transfer detail configuration, and post-compilation processing logic; Matching the common configuration information with the independent configuration information to obtain multiple matching categories; Establish multiple test channels based on multiple matching categories, and obtain common configuration information and independent configuration information for each test channel; Based on the common configuration information and independent configuration information of each test channel, the test parameter information of the corresponding test channel is obtained.

4. The RTL parallel testing method of the RISC-V DSP chip according to claim 3, characterized in that: Match different categories of test items with the test parameters of each test channel to obtain the matching degree, including: Get the category of the test item; Analyze the requirements and objectives of the test items based on their categories; Get the general configuration information and independent configuration information of the test channel; The requirement information and target information of the test project are matched with the general configuration information and independent configuration information of the test channel to obtain the matching degree.

5. The RTL parallel testing method of the RISC-V DSP chip according to claim 1, characterized in that: Match the test items to the corresponding test channels, including: Get the matching degree between the test items and the test channels; Comparing the matching degree with a set matching degree threshold, wherein the set matching degree threshold includes a first matching degree threshold and a second matching degree threshold, and the first matching degree threshold is less than the second matching degree threshold; If the matching degree is greater than the first matching degree threshold and less than the second matching degree threshold, the test items are allocated to at least two test channels, and the test channels are adjusted according to the running queue time of the test channels; If the matching degree is greater than the second matching degree threshold, the test item is analyzed into the current test channel.

6. The RTL parallel testing method of the RISC-V DSP chip according to claim 5, characterized in that: Test multiple test items in parallel according to the matching test channels to obtain parallel test data, including: Obtain the test items and the test channels that match the test items, queue the test items under each test channel, and obtain the queue information; Get the running time and remaining test time of the current test item of each test channel, and analyze the running queue time of the test item based on the remaining test time; Test the test items in different test channels in parallel and analyze the test status information synchronously; Dynamically adjust the test channel matching the test items based on the test status information and the running queue time.

7. An RTL parallel test system for a RISC-V DSP chip, characterized in that: The system includes: a memory and a processor, wherein the memory includes a program of an RTL parallel testing method for a RISC-V DSP chip, and when the program of the RTL parallel testing method for a RISC-V DSP chip is executed by the processor, the following steps are implemented: Acquire multiple test items, and classify the multiple test items based on classification rules to obtain test items of different categories; Build multiple test channels based on the RTL test framework and obtain the test parameter information of each test channel; Matching different categories of test items with the test parameters of each test channel to obtain a matching degree, and determining whether the matching degree is greater than or equal to a set matching degree threshold; If it is greater than or equal to the set matching threshold, the test item is matched with the corresponding test channel. If it is less than, the unmatched test items are blocked through the test channel. Multiple test items are tested in parallel according to matching test channels to obtain parallel test data.

8. The RTL parallel test system of the RISC-V DSP chip according to claim 7, characterized in that: Obtain multiple test items, classify the multiple test items based on classification rules, and obtain test items of different categories, including: Obtain the test requirement information and test target information for each test item; Establish multiple test requirement intervals and multiple test target intervals based on classification rules; Analyze the test requirement interval and test target interval to which the test project belongs, and obtain the analysis results; Based on the analysis results, multiple test items are classified to obtain test items of different categories.

9. The RTL parallel test system of the RISC-V DSP chip according to claim 8, characterized in that: Build multiple test channels based on the RTL test framework and obtain the test parameter information of each test channel, including: Based on the RTL test framework, general configuration information and independent configuration information are obtained. The general configuration information includes interaction logic, test process control logic, data processing logic, and result summary logic; the independent configuration information includes the project's dependency path, required special variables, data processing / transfer detail configuration, and post-compilation processing logic; Matching the common configuration information with the independent configuration information to obtain multiple matching categories; Establish multiple test channels based on multiple matching categories, and obtain common configuration information and independent configuration information for each test channel; Based on the common configuration information and independent configuration information of each test channel, the test parameter information of the corresponding test channel is obtained.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes an RTL parallel testing method program for a RISC-V DSP chip. When the RTL parallel testing method program for a RISC-V DSP chip is executed by a processor, the steps of the RTL parallel testing method for a RISC-V DSP chip as described in any one of claims 1 to 6 are implemented.

Images