Electrical testing method and circuit for low-temperature polycrystalline silicon liquid crystal display panel

Abstract

The invention discloses an electrical testing method and circuit for a low-temperature polycrystalline silicon liquid crystal display panel. The method comprises the following steps: providing an electrical testing circuit; driving the odd-numbered rows of gate lines at a prescribed driving timing, driving the first R signal control line or the first G signal control line or the first B signal control line at a prescribed driving timing, and driving a first portion of the plurality of R pixel data lines or the plurality of G pixel data lines or the plurality of B pixel data lines at a prescribed driving timing; driving the odd-numbered rows of gate lines at a prescribed driving timing, driving the second R signal control line or the second G signal control line or the second B signal control line at a prescribed driving timing, and driving a second portion of the plurality of R pixel data lines or the plurality of G pixel data lines or the plurality of B pixel data lines at a prescribed driving timing; according to the invention, the pure-color picture display test of the low-temperature polycrystalline silicon liquid crystal display panel in the RGBG pixel mode adopting zigzag wiring is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical measurement of low-temperature polysilicon liquid crystal display panels, and in particular to an electrical measurement method and circuit for low-temperature polysilicon liquid crystal display panels. Background Art

[0002] Display devices have developed rapidly. Low-temperature polysilicon is usually used in higher-end products due to its advantages such as high mobility. RGBG pixel arrangement is widely used in LTPS LCD and AMOLED display devices. RGBG pixels, that is, every two pixels share a green sub-pixel, make the panel have a higher aperture ratio, and at the same time, a higher dot matrix can be achieved with fewer dot matrices.

[0003] Existing low-temperature polysilicon liquid crystal display panels generally use zigzag wiring, which can increase the wiring length, thereby reducing the resistance and capacitance of the wiring to a certain extent, which helps to reduce delays and distortions in the signal transmission process. When the display panel is affected by external forces or temperature changes, the bending shape of the zigzag wiring can effectively disperse the stress and avoid stress concentration at one point or a certain area.

[0004] However, when using RGBG pixel zigzag wiring, it is impossible to electrically measure a pure color image, that is, it is impossible to electrically measure red, green, and blue, so that some defective products enter the post-process, resulting in some material waste in the post-process. Summary of the invention

[0005] The existing low-temperature polysilicon liquid crystal display panels cannot be tested for pure color images due to the use of zigzag wiring, resulting in defective products being sent to the subsequent processes.

[0006] In view of the above problems, an electrical testing method and circuit for a low-temperature polysilicon liquid crystal display panel are proposed. By setting an electrical testing circuit in the low-temperature polysilicon liquid crystal display panel, the odd-numbered rows are first turned on to display a part of the pure color picture, and then the even-numbered rows are turned on to display another part of the pure color picture. The pure color picture display test of the low-temperature polysilicon liquid crystal display panel using the RGBG pixel mode with zigzag wiring is realized, which solves the problem that the existing low-temperature polysilicon liquid crystal display panel cannot be tested for pure color pictures due to the use of zigzag wiring, resulting in defective products being used for subsequent processes.

[0007] In a first aspect, a method for electrical testing of a low temperature polysilicon liquid crystal display panel comprises: Step 100, providing an electrical testing circuit, including a driving module, a plurality of first R transistors, a plurality of second R transistors, a first R signal control line, a second R signal control line, a plurality of R pixel data lines, a plurality of first G transistors, a plurality of second G transistors, a first G signal control line, a second G signal control line, a plurality of G pixel data lines, a plurality of first B transistors, a plurality of second B transistors, a first B signal control line, a second B signal control line, and a plurality of B pixel data lines, wherein the driving module is electrically connected to the first R signal control line, the second R signal control line, the first G signal control line, the second G signal control line, the first B signal control line, the second B signal control line, the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines; Step 200, using the driving module to drive the odd-numbered gate lines at a specified driving timing, drive the first R signal control line, the first G signal control line, or the first B signal control line at a specified driving timing, and drive a first part of a plurality of R pixel data lines, a plurality of G pixel data lines, or a plurality of B pixel data lines at a specified driving timing, so that the odd-numbered rows display an R color picture, a G color picture, or a B color picture; Step 300, using the driving module to drive the odd-numbered gate lines at a specified driving timing, drive the second R signal control line or the second G signal control line or the second B signal control line at a specified driving timing, and drive the second part of the plurality of R pixel data lines or the plurality of G pixel data lines or the plurality of B pixel data lines at a specified driving timing, so that the even-numbered rows display an R color picture or a G color picture or a B color picture; The first part of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines and the second part of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines constitute the total number of R pixel data lines or G pixel data lines or multiple B pixel data lines.

[0008] In combination with the electrical measurement method of the low-temperature polysilicon liquid crystal display panel described in the first aspect of the present invention, in a first possible implementation manner, the sources and drains of the plurality of first R transistors, the plurality of first G transistors, and the plurality of first B transistors are respectively electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, and the sources and drains of the plurality of second R transistors, the plurality of second G transistors, and the plurality of second B transistors are respectively electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, and the first R signal The first R signal control line, the second G signal control line, and the first B signal control line are electrically connected to the gates of the multiple first R transistors, the multiple first G transistors, and the multiple first B transistors, respectively; the second R signal control line, the second G signal control line, and the second B signal control line are electrically connected to the gates of the multiple second R transistors, the multiple second G transistors, and the multiple second B transistors, respectively; and the driving module is electrically connected to the first R signal control line, the second R signal control line, the first G signal control line, the second G signal control line, the first B signal control line, the second B signal control line, the multiple R pixel data lines, the multiple G pixel data lines, and the multiple B pixel data lines, respectively.

[0009] In combination with the first possible implementation of the first aspect of the present invention, in a second possible implementation, step 200 includes: Step 210, turning on the odd-numbered gate lines in sequence according to a first driving timing; Step 220: During the opening process of the odd-numbered row gate lines, the first R signal control line, the first G signal control line, or the first B signal control line is driven with a second driving timing sequence to input a high level to the plurality of first R transistors, the plurality of first G transistors, or the plurality of first B transistors; Step 230 , input a high level to the input ends of the multiple R pixel data lines, the multiple G pixel data lines, or the multiple B pixel data lines corresponding to the multiple first R transistors, the multiple first G transistors, or the multiple first B transistors at a third driving timing.

[0010] In combination with the first possible implementation of the first aspect of the present invention, in a third possible implementation, step 300 includes: Step 310, turning on the even-numbered gate lines in sequence according to a first driving timing; Step 320: During the opening process of the even-numbered row gate lines, the second R signal control line, the second G signal control line, or the second B signal control line is driven with a second driving timing sequence to input a high level to the plurality of second R transistors, the plurality of second G transistors, or the plurality of second B transistors; Step 330 , input a high level to the input ends of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines corresponding to the multiple second R transistors or the multiple second G transistors or the multiple second B transistors at a third driving timing.

[0011] In combination with the electrical testing method of the low-temperature poly-silicon liquid crystal display panel described in the first aspect of the present invention, in a fourth possible implementation manner, the pixel arrangement of the low-temperature poly-silicon liquid crystal display panel adopts an RGBG mode.

[0012] In a second aspect, an electrical measurement circuit adopts the electrical measurement method described in the first aspect, including a driving module, a plurality of first R transistors, a plurality of second R transistors, a first R signal control line, a second R signal control line, a plurality of R pixel data lines, a plurality of first G transistors, a plurality of second G transistors, a first G signal control line, a second G signal control line, a plurality of G pixel data lines, a plurality of first B transistors, a plurality of second B transistors, a first B signal control line, a second B signal control line, and a plurality of B pixel data lines; The sources and drains of the plurality of first R transistors, the plurality of first G transistors, and the plurality of first B transistors are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The sources and drains of the plurality of second R transistors, the plurality of second G transistors, and the plurality of second B transistors are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The first R signal control line, the first G signal control line, and the first B signal control line are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The control lines are electrically connected to the gates of multiple first R transistors, multiple first G transistors, and multiple first B transistors, respectively; the second R signal control line, the second G signal control line, and the second B signal control line are electrically connected to the gates of multiple second R transistors, multiple second G transistors, and multiple second B transistors, respectively; the driving module is electrically connected to the first R signal control line, the second R signal control line, the first G signal control line, the second G signal control line, the first B signal control line, the second B signal control line, multiple R pixel data lines, multiple G pixel data lines, and multiple B pixel data lines, respectively.

[0013] In conjunction with the electric measuring circuit described in the second aspect of the present invention, in a first possible implementation manner, the driving module is used to: driving the odd-numbered gate lines at a prescribed driving sequence, driving the first R signal control line, the first G signal control line, or the first B signal control line at a prescribed driving sequence, and driving a first part of a plurality of R pixel data lines, a plurality of G pixel data lines, or a plurality of B pixel data lines at a prescribed driving sequence, so that the odd-numbered lines display an R color picture, a G color picture, or a B color picture; driving the odd-numbered gate lines at a prescribed driving sequence, driving the second R signal control line, the second G signal control line, or the second B signal control line at a prescribed driving sequence, and driving the second part of the plurality of R pixel data lines, the plurality of G pixel data lines, or the plurality of B pixel data lines at a prescribed driving sequence, so that the even-numbered lines display an R color picture, a G color picture, or a B color picture; The first part of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines and the second part of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines constitute the total number of R pixel data lines or G pixel data lines or multiple B pixel data lines.

[0014] In combination with the first possible implementation manner of the second aspect of the present invention, in a second possible implementation manner, the driving module is further used for: Turning on the odd-numbered gate lines in sequence according to a first driving timing sequence; During the turning on of the odd-numbered row gate lines, driving the first R signal control line, the first G signal control line, or the first B signal control line with a second driving timing sequence, and inputting a high level to the plurality of first R transistors, the plurality of first G transistors, or the plurality of first B transistors; A high level is input to the input ends of the multiple R pixel data lines, the multiple G pixel data lines, or the multiple B pixel data lines corresponding to the multiple first R transistors, the multiple first G transistors, or the multiple first B transistors at a third driving timing.

[0015] In combination with the second possible implementation manner of the second aspect of the present invention, in a third possible implementation manner, the driving module is further used for: Turning on the even-numbered gate lines in sequence according to a first driving timing sequence; During the even-numbered row gate line opening process, driving the second R signal control line or the second G signal control line or the second B signal control line with a second driving timing sequence, inputting a high level to the plurality of second R transistors or the plurality of second G transistors or the plurality of second B transistors; A high level is input to the input ends of the multiple R pixel data lines, the multiple G pixel data lines, or the multiple B pixel data lines corresponding to the multiple second R transistors, the multiple second G transistors, or the multiple second B transistors at a third driving timing.

[0016] In combination with the electrical measuring circuit of the low-temperature poly-silicon liquid crystal display panel described in the second aspect of the present invention, in a fourth possible implementation manner, the pixel arrangement of the low-temperature poly-silicon liquid crystal display panel adopts an RGBG mode.

[0017] The electrical testing method and circuit of the low-temperature polysilicon liquid crystal display panel in the present invention are implemented by setting an electrical testing circuit in the low-temperature polysilicon liquid crystal display panel, first turning on the odd-numbered rows to display a part of the pure color picture, and then turning on the even-numbered rows to display another part of the pure color picture, thereby realizing a pure color picture display test of the low-temperature polysilicon liquid crystal display panel using an RGBG pixel mode with zigzag wiring, thereby solving the problem that the existing low-temperature polysilicon liquid crystal display panel cannot be tested for pure color pictures due to the use of zigzag wiring, resulting in defective products being used in subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the scheme in the present application, a brief introduction is given below to the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 It is a schematic diagram of pixel arrangement of a low-temperature polysilicon liquid crystal display panel in this application; Figure 2 It is a schematic diagram of the principle of the electrical test circuit of the low-temperature polysilicon liquid crystal display panel in this application; Figure 3 It is a driving timing diagram for displaying a red pure color electrical measurement screen in this application; Figure 4 It is a driving timing diagram for displaying a red pure color electrical measurement screen in this application; Figure 5 It is a driving timing diagram for displaying a red pure color electrical measurement screen in this application; Figure 6 It is a flow chart of an embodiment of an electrical testing method of a low-temperature polysilicon liquid crystal display panel of the present application; Figure 7 yes Figure 6 A flowchart of a specific implementation of S200; Figure 8 yes Figure 6 A flowchart of a specific implementation of S300. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the invention to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0021] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0023] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0024] The existing low-temperature polysilicon liquid crystal display panels cannot be tested for pure color images due to the use of zigzag wiring, resulting in defective products being sent to the subsequent processes.

[0025] In view of the above problems, an electrical testing method and circuit for a low-temperature polysilicon liquid crystal display panel are proposed.

[0026] In a first aspect, a method for electrical testing of a low temperature polysilicon liquid crystal display panel is provided. Figure 6 , Figure 6 This is a flow chart of an embodiment of an electrical testing method for a low-temperature polysilicon liquid crystal display panel of the present application; it includes: S100, providing an electrical measurement circuit, including a driving module, a plurality of first R transistors, a plurality of second R transistors, a first R signal control line (R_ODD), a second R signal control line (R_EVEN), a plurality of R pixel data lines (R1, R2, ..., RN), a plurality of first G transistors, a plurality of second G transistors, a first G signal control line (G_ODD), a second G signal control line (G_EVEN), a plurality of G pixel data lines (G1, G2, ..., GN), a plurality of first B transistors, a plurality of second B transistors, a first B signal control line (B_ODD), a second B signal control line (B_EVEN), A driving module is electrically connected to a first R signal control line (R_ODD), a second R signal control line (R_EVEN), a first G signal control line (G_ODD), a second G signal control line (G_EVEN), a first B signal control line (B_ODD), a second B signal control line (B_EVEN), a plurality of R pixel data lines (R1, R2, ..., RN), a plurality of G pixel data lines (G1, G2, ..., GN), and a plurality of B pixel data lines (B1, B2, ..., BN).

[0027] In the embodiments of the present application, Figure 1 , Figure 1 : is a schematic diagram of the pixel arrangement of the low-temperature polysilicon liquid crystal display panel in this application, which adopts the RGBG pixel arrangement mode. In the embodiment of this application, regarding the specific connection method of the electrical measurement circuit, such as Figure 2 , Figure 2 This is a schematic diagram of the principle of the electrical measurement circuit of the low-temperature polysilicon liquid crystal display panel in this application; Figure 2In the embodiment of the present application, the specific connection mode of the electric measuring circuit is as follows: the sources and drains of the plurality of first R transistors, the plurality of first G transistors, and the plurality of first B transistors are respectively electrically connected to the plurality of R pixel data lines (R1, R2, ..., RN), the plurality of G pixel data lines (G1, G2, ..., GN), and the plurality of B pixel data lines (B1, B2, ..., BN) corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, the sources and drains of the plurality of second R transistors, the plurality of second G transistors, and the plurality of second B transistors are respectively electrically connected to the plurality of R pixel data lines (R1, R2, ..., RN), the plurality of G pixel data lines (G1, G2, ..., GN), and the plurality of B pixel data lines (B1, B2, ..., BN) corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, the first R signal control line (R_ODD), the first G signal control line (G_ODD), the first B signal The control line (B_ODD) is electrically connected to the gates of the plurality of first R transistors, the plurality of first G transistors, and the plurality of first B transistors, respectively; the second R signal control line (R_EVEN), the second G signal control line (G_EVEN), and the second B signal control line (B_EVEN) are electrically connected to the gates of the plurality of second R transistors, the plurality of second G transistors, and the plurality of second B transistors, respectively; and the driving module is electrically connected to the first R signal control line (R_ODD), the second R signal control line (R_EVEN), the first G signal control line (G_ODD), the second G signal control line (G_EVEN), the first B signal control line (B_ODD), the second B signal control line (B_EVEN), the plurality of R pixel data lines (R1, R2, ..., RN), the plurality of G pixel data lines (G1, G2, ..., GN), and the plurality of B pixel data lines (B1, B2, ..., BN), respectively.

[0028] S200, using a driving module to drive odd-numbered row gate lines at a specified driving timing, drive a first R signal control line (R_ODD) or a first G signal control line (G_ODD) or a first B signal control line (B_ODD) at a specified driving timing, and drive a first part of a plurality of R pixel data lines (R1, R2, ..., RN) or a plurality of G pixel data lines (G1, G2, ..., GN) or a plurality of B pixel data lines (B1, B2, ..., BN) at a specified driving timing, so that the odd-numbered rows display an R color picture or a G color picture or a B color picture. Preferably, as Figure 7 , Figure 7 yes Figure 6A flowchart of a specific implementation of S200 in the embodiment; S200 includes: S210, turning on the odd-numbered row gate lines in sequence with a first driving timing; S220, in the process of turning on the odd-numbered row gate lines, driving the first R signal control line (R_ODD) or the first G signal control line (G_ODD) or the first B signal control line (B_ODD) with a second driving timing, and inputting a high level to a plurality of first R transistors or a plurality of first G transistors or a plurality of first B transistors; S230, inputting a high level to the input ends of a plurality of R pixel data lines (R1, R2, ..., RN) or a plurality of G pixel data lines (G1, G2, ..., GN) or a plurality of B pixel data lines (B1, B2, ..., BN) corresponding to the plurality of first R transistors or the plurality of first G transistors or the plurality of first B transistors with a third driving timing.

[0029] S300, using a driving module to drive odd-numbered row gate lines at a prescribed driving timing, drive a second R signal control line (R_EVEN) or a second G signal control line (G_EVEN) or a second B signal control line (B_EVEN) at a prescribed driving timing, and drive a second part of a plurality of R pixel data lines (R1, R2, ..., RN) or a plurality of G pixel data lines (G1, G2, ..., GN) or a plurality of B pixel data lines (B1, B2, ..., BN) at a prescribed driving timing, so that even-numbered rows display an R color picture, a G color picture, or a B color picture; A first part of the multiple R pixel data lines (R1, R2, ..., RN) or the multiple G pixel data lines (G1, G2, ..., GN) or the multiple B pixel data lines (B1, B2, ..., BN) and a second part of the multiple R pixel data lines (R1, R2, ..., RN) or the multiple G pixel data lines (G1, G2, ..., GN) or the multiple B pixel data lines (B1, B2, ..., BN) constitute the total number of R pixel data lines (R1, R2, ..., RN) or G pixel data lines (G1, G2, ..., GN) or the multiple B pixel data lines (B1, B2, ..., BN).

[0030] Preferably, if Figure 8 , Figure 8 yes Figure 6A flowchart of a specific implementation of S300 in the embodiment. S300 includes: S310, turning on the even-numbered row gate lines in sequence with a first driving timing; S320, in the process of turning on the even-numbered row gate lines, driving the second R signal control line (R_EVEN) or the second G signal control line (G_EVEN) or the second B signal control line (B_EVEN) with a second driving timing, and inputting a high level to a plurality of second R transistors or a plurality of second G transistors or a plurality of second B transistors; S330, inputting a high level to the input end of a plurality of R pixel data lines (R1, R2, ..., RN) or a plurality of G pixel data lines (G1, G2, ..., GN) or a plurality of B pixel data lines (B1, B2, ..., BN) corresponding to the plurality of second R transistors or a plurality of second G transistors or a plurality of second B transistors with a third driving timing.

[0031] Regarding the driving timing in the embodiment of the present application, Figure 3 , Figure 4 and Figure 5 , Figure 3 This is a driving timing diagram for displaying a pure red electrical measurement screen in this application. Figure 4 This is a driving timing diagram for displaying a pure red electrical measurement screen in this application. Figure 5 This is a driving timing diagram for displaying a pure red electric measurement screen in this application; taking the display of a red electric measurement screen as an example, you can refer to Figure 3 In one frame time, the odd-numbered gate lines are driven to open one by one with the first driving timing, and the first R signal control line (R_ODD) and the R1 pixel data line are high with the second driving timing. Similarly, in one frame time, the even-numbered gate lines are driven to open one by one with the first driving timing, and the second R signal control line (R_EVEN) and the R2 pixel data line are high with the second driving timing, so as to realize the display of the red pure color electrical picture. Similarly, the display of the green pure color electrical picture and the blue pure color electrical picture are realized by this principle. The pixel arrangement of the low-temperature polysilicon liquid crystal display panel adopts the RGBG mode. By setting an electrical testing circuit in the low-temperature polysilicon liquid crystal display panel, the odd-numbered rows are turned on first to display a part of the pure color picture, and then the even-numbered rows are turned on to display another part of the pure color picture, thereby realizing a pure color picture display test of the low-temperature polysilicon liquid crystal display panel using an RGBG pixel mode with zigzag wiring, thereby solving the problem that the existing low-temperature polysilicon liquid crystal display panel cannot be tested for pure color pictures due to the use of zigzag wiring, resulting in defective products being used for subsequent processes.

[0032] In a second aspect, an electrical measurement circuit adopts the electrical measurement method of the first aspect, including a driving module, a plurality of first R transistors, a plurality of second R transistors, a first R signal control line (R_ODD), a second R signal control line (R_EVEN), a plurality of R pixel data lines (R1, R2, ..., RN), a plurality of first G transistors, a plurality of second G transistors, a first G signal control line (G_ODD), a second G signal control line (G_EVEN), a plurality of G pixel data lines (G1, G2, ..., GN), a plurality of first B transistors, a plurality of second B transistors, a first B signal control line (B_ODD), a second B signal control line (B_EVEN), and a plurality of B pixel data lines (B1, B2, ..., BN); Sources and drains of the plurality of first R transistors, the plurality of first G transistors, and the plurality of first B transistors are electrically connected to the plurality of R pixel data lines (R1, R2, ..., RN), the plurality of G pixel data lines (G1, G2, ..., GN), and the plurality of B pixel data lines (B1, B2, ..., BN) corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively; sources and drains of the plurality of second R transistors, the plurality of second G transistors, and the plurality of second B transistors are electrically connected to the plurality of R pixel data lines (R1, R2, ..., RN), the plurality of G pixel data lines (G1, G2, ..., GN), and the plurality of B pixel data lines (B1, B2, ..., BN) corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively; a first R signal control line (R_ODD), a first G signal control line (G_ODD), and a first B signal control line (B_ODD) are electrically connected to the plurality of R pixel data lines (R1, R2, ..., RN), the plurality of G pixel data lines (G1, G2, ..., GN), and the plurality of B pixel data lines (B1, B2, ..., BN) corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively; The first R signal control line (R_EVEN), the second G signal control line (G_EVEN), and the second B signal control line (B_EVEN) are electrically connected to the gates of the plurality of first R transistors, the plurality of first G transistors, and the plurality of first B transistors, respectively. The second R signal control line (R_EVEN), the second G signal control line (G_EVEN), and the second B signal control line (B_EVEN) are electrically connected to the gates of the plurality of second R transistors, the plurality of second G transistors, and the plurality of second B transistors, respectively. The driving module is electrically connected to the first R signal control line (R_ODD), the second R signal control line (R_EVEN), the first G signal control line (G_ODD), the second G signal control line (G_EVEN), the first B signal control line (B_ODD), the second B signal control line (B_EVEN), the plurality of R pixel data lines (R1, R2, ..., RN), the plurality of G pixel data lines (G1, G2, ..., GN), and the plurality of B pixel data lines (B1, B2, ..., BN), respectively.

[0033] Furthermore, the driver module is used to: The odd-numbered rows of gate lines are driven at a prescribed driving timing, the first R signal control line (R_ODD) or the first G signal control line (G_ODD) or the first B signal control line (B_ODD) is driven at a prescribed driving timing, and the first part of the plurality of R pixel data lines (R1, R2, ..., RN) or the plurality of G pixel data lines (G1, G2, ..., GN) or the plurality of B pixel data lines (B1, B2, ..., BN) is driven at a prescribed driving timing, so that the odd-numbered rows display an R color picture, a G color picture or a B color picture; The odd-numbered rows of gate lines are driven at a prescribed driving timing, the second R signal control line (R_EVEN) or the second G signal control line (G_EVEN) or the second B signal control line (B_EVEN) is driven at a prescribed driving timing, and the second part of the plurality of R pixel data lines (R1, R2, ..., RN) or the plurality of G pixel data lines (G1, G2, ..., GN) or the plurality of B pixel data lines (B1, B2, ..., BN) is driven at a prescribed driving timing, so that the even-numbered rows display an R color picture, a G color picture or a B color picture; A first part of the multiple R pixel data lines (R1, R2, ..., RN) or the multiple G pixel data lines (G1, G2, ..., GN) or the multiple B pixel data lines (B1, B2, ..., BN) and a second part of the multiple R pixel data lines (R1, R2, ..., RN) or the multiple G pixel data lines (G1, G2, ..., GN) or the multiple B pixel data lines (B1, B2, ..., BN) constitute the total number of R pixel data lines (R1, R2, ..., RN) or G pixel data lines (G1, G2, ..., GN) or the multiple B pixel data lines (B1, B2, ..., BN).

[0034] Furthermore, the driver module is further used to: Turning on the odd-numbered gate lines in sequence according to a first driving timing sequence; During the opening process of the odd-numbered row gate lines, the first R signal control line (R_ODD) or the first G signal control line (G_ODD) or the first B signal control line (B_ODD) is driven with the second driving timing sequence to input a high level to the plurality of first R transistors or the plurality of first G transistors or the plurality of first B transistors; A high level is input to the input ends of multiple R pixel data lines (R1, R2, ..., RN) or multiple G pixel data lines (G1, G2, ..., GN) or multiple B pixel data lines (B1, B2, ..., BN) corresponding to multiple first R transistors or multiple first G transistors or multiple first B transistors at a third driving timing.

[0035] Furthermore, the driver module is further used to: Turning on the even-numbered gate lines in sequence according to a first driving timing sequence; During the opening process of the even-numbered row gate lines, the second R signal control line (R_EVEN) or the second G signal control line (G_EVEN) or the second B signal control line (B_EVEN) is driven with a second driving timing sequence to input a high level to the plurality of second R transistors or the plurality of second G transistors or the plurality of second B transistors; A high level is input to the input ends of multiple R pixel data lines (R1, R2, ..., RN) or multiple G pixel data lines (G1, G2, ..., GN) or multiple B pixel data lines (B1, B2, ..., BN) corresponding to multiple second R transistors or multiple second G transistors or multiple second B transistors at a third driving timing.

[0036] The electrical testing method and circuit of the low-temperature polysilicon liquid crystal display panel in the present invention are implemented by setting an electrical testing circuit in the low-temperature polysilicon liquid crystal display panel, first turning on the odd-numbered rows to display a part of the pure color picture, and then turning on the even-numbered rows to display another part of the pure color picture, thereby realizing a pure color picture display test of the low-temperature polysilicon liquid crystal display panel using an RGBG pixel mode with zigzag wiring, thereby solving the problem that the existing low-temperature polysilicon liquid crystal display panel cannot be tested for pure color pictures due to the use of zigzag wiring, resulting in defective products being used in subsequent processes.

[0037] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for electrical testing of a low-temperature polysilicon liquid crystal display panel, comprising: Step 100, providing an electrical testing circuit, including a driving module, a plurality of first R transistors, a plurality of second R transistors, a first R signal control line, a second R signal control line, a plurality of R pixel data lines, a plurality of first G transistors, a plurality of second G transistors, a first G signal control line, a second G signal control line, a plurality of G pixel data lines, a plurality of first B transistors, a plurality of second B transistors, a first B signal control line, a second B signal control line, and a plurality of B pixel data lines, wherein the driving module is electrically connected to the first R signal control line, the second R signal control line, the first G signal control line, the second G signal control line, the first B signal control line, the second B signal control line, the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines; Step 200, using the driving module to drive the odd-numbered gate lines at a specified driving timing, drive the first R signal control line, the first G signal control line, or the first B signal control line at a specified driving timing, and drive a first part of a plurality of R pixel data lines, a plurality of G pixel data lines, or a plurality of B pixel data lines at a specified driving timing, so that the odd-numbered rows display an R color picture, a G color picture, or a B color picture; Step 300, using the driving module to drive the odd-numbered gate lines at a specified driving timing, drive the second R signal control line or the second G signal control line or the second B signal control line at a specified driving timing, and drive the second part of the plurality of R pixel data lines or the plurality of G pixel data lines or the plurality of B pixel data lines at a specified driving timing, so that the even-numbered rows display an R color picture or a G color picture or a B color picture; The first part of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines and the second part of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines constitute the total number of R pixel data lines or G pixel data lines or multiple B pixel data lines.

2. The electrical testing method of a low-temperature polysilicon liquid crystal display panel according to claim 1, characterized in that: The sources and drains of the plurality of first R transistors, the plurality of first G transistors, and the plurality of first B transistors are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The sources and drains of the plurality of second R transistors, the plurality of second G transistors, and the plurality of second B transistors are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The first R signal control line, the first G signal control line, and the first B signal control line are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The control lines are electrically connected to the gates of multiple first R transistors, multiple first G transistors, and multiple first B transistors, respectively; the second R signal control line, the second G signal control line, and the second B signal control line are electrically connected to the gates of multiple second R transistors, multiple second G transistors, and multiple second B transistors, respectively; the driving module is electrically connected to the first R signal control line, the second R signal control line, the first G signal control line, the second G signal control line, the first B signal control line, the second B signal control line, multiple R pixel data lines, multiple G pixel data lines, and multiple B pixel data lines, respectively.

3. The electrical testing method of a low-temperature polysilicon liquid crystal display panel according to claim 2, characterized in that: The step 200 comprises: Step 210, turning on the odd-numbered gate lines in sequence according to a first driving timing; Step 220: During the turning-on process of the odd-numbered row gate lines, the first R signal control line, the first G signal control line, or the first B signal control line is driven with a second driving timing sequence to input a high level to the plurality of first R transistors, the plurality of first G transistors, or the plurality of first B transistors; Step 230 , input a high level to the input ends of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines corresponding to the multiple first R transistors or the multiple first G transistors or the multiple first B transistors at a third driving timing.

4. The electrical testing method of a low-temperature polysilicon liquid crystal display panel according to claim 3, characterized in that: The step 300 includes: Step 310, turning on the even-numbered gate lines in sequence according to a first driving timing; Step 320: During the opening process of the even-numbered row gate lines, the second R signal control line, the second G signal control line, or the second B signal control line is driven with a second driving timing sequence to input a high level to the plurality of second R transistors, the plurality of second G transistors, or the plurality of second B transistors; Step 330 , input a high level to the input ends of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines corresponding to the multiple second R transistors or the multiple second G transistors or the multiple second B transistors at a third driving timing.

5. The electrical testing method of a low-temperature polysilicon liquid crystal display panel according to any one of claims 1 to 4, characterized in that: The pixel arrangement of the low-temperature polysilicon liquid crystal display panel adopts an RGBG mode.

6. An electrical testing circuit for a low-temperature polysilicon liquid crystal display panel, using the electrical testing method according to claim 5, characterized in that: It includes a driving module, a plurality of first R transistors, a plurality of second R transistors, a first R signal control line, a second R signal control line, a plurality of R pixel data lines, a plurality of first G transistors, a plurality of second G transistors, a first G signal control line, a second G signal control line, a plurality of G pixel data lines, a plurality of first B transistors, a plurality of second B transistors, a first B signal control line, a second B signal control line, and a plurality of B pixel data lines; The sources and drains of the plurality of first R transistors, the plurality of first G transistors, and the plurality of first B transistors are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The sources and drains of the plurality of second R transistors, the plurality of second G transistors, and the plurality of second B transistors are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The first R signal control line, the first G signal control line, and the first B signal control line are electrically connected to the plurality of R pixel data lines, the plurality of G pixel data lines, and the plurality of B pixel data lines corresponding to the odd-numbered rows of R pixels, G pixels, and B pixels, respectively. The control lines are electrically connected to the gates of multiple first R transistors, multiple first G transistors, and multiple first B transistors, respectively; the second R signal control line, the second G signal control line, and the second B signal control line are electrically connected to the gates of multiple second R transistors, multiple second G transistors, and multiple second B transistors, respectively; the driving module is electrically connected to the first R signal control line, the second R signal control line, the first G signal control line, the second G signal control line, the first B signal control line, the second B signal control line, multiple R pixel data lines, multiple G pixel data lines, and multiple B pixel data lines, respectively.

7. The electrical testing circuit of the low-temperature polysilicon liquid crystal display panel according to claim 6, characterized in that: The driver module is used for: driving the odd-numbered gate lines at a prescribed driving sequence, driving the first R signal control line, the first G signal control line, or the first B signal control line at a prescribed driving sequence, and driving a first part of a plurality of R pixel data lines, a plurality of G pixel data lines, or a plurality of B pixel data lines at a prescribed driving sequence, so that the odd-numbered lines display an R color picture, a G color picture, or a B color picture; driving the odd-numbered gate lines at a prescribed driving sequence, driving the second R signal control line, the second G signal control line, or the second B signal control line at a prescribed driving sequence, and driving the second part of the plurality of R pixel data lines, the plurality of G pixel data lines, or the plurality of B pixel data lines at a prescribed driving sequence, so that the even-numbered lines display an R color picture, a G color picture, or a B color picture; The first part of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines and the second part of the multiple R pixel data lines or the multiple G pixel data lines or the multiple B pixel data lines constitute the total number of R pixel data lines or G pixel data lines or multiple B pixel data lines.

8. The electrical testing circuit of the low-temperature polysilicon liquid crystal display panel according to claim 7, characterized in that: The driving module is further used for: Turning on the odd-numbered gate lines in sequence according to a first driving timing sequence; During the turning on of the odd-numbered row gate lines, driving the first R signal control line, the first G signal control line, or the first B signal control line with a second driving timing sequence, and inputting a high level to the plurality of first R transistors, the plurality of first G transistors, or the plurality of first B transistors; A high level is input to the input ends of the multiple R pixel data lines, the multiple G pixel data lines, or the multiple B pixel data lines corresponding to the multiple first R transistors, the multiple first G transistors, or the multiple first B transistors at a third driving timing.

9. The electrical testing circuit of the low-temperature polysilicon liquid crystal display panel according to claim 8, characterized in that: The driving module is further used for: Turning on the even-numbered gate lines in sequence according to a first driving timing sequence; During the even-numbered row gate line opening process, driving the second R signal control line or the second G signal control line or the second B signal control line with a second driving timing sequence, inputting a high level to the plurality of second R transistors or the plurality of second G transistors or the plurality of second B transistors; A high level is input to the input ends of the multiple R pixel data lines, the multiple G pixel data lines, or the multiple B pixel data lines corresponding to the multiple second R transistors, the multiple second G transistors, or the multiple second B transistors at a third driving timing.

10. The electrical measuring circuit of the low temperature polysilicon liquid crystal display panel according to any one of claims 6 to 10, characterized in that: The pixel arrangement of the low-temperature polysilicon liquid crystal display panel adopts an RGBG mode.

Images