Defect detection method and system for integrated circuit manufacturing

Abstract

The invention provides a defect detection method and system for integrated circuit manufacturing. Wherein in the integrated circuit packaging stage, packaged chips are divided into a first type of chips meeting a preset physical characteristic threshold value and a second type of chips exceeding the physical characteristic threshold value through a pneumatic sorting device; performing scanning electron microscope imaging on the surface of the second type of chip, generating a three-dimensional topological structure by using an image reconstruction technology, and positioning a micron-sized particle defect area by comparing reference type differences; synchronously applying high-frequency electric signal excitation in the sorting process, detecting impedance response of the second type of chips, and recording an abnormal signal sequence exceeding a preset frequency domain range; performing space-time correlation matching on the micron-sized particle defect area and the abnormal signal sequence, and judging that the defect is a multi-layer composite defect when a preset coupling condition is met; and dynamically adjusting the mesh diameter and vibration frequency parameters of the pneumatic sorting device. According to the technical scheme provided by the invention, accurate identification of the multi-layer composite defect of the chip is realized, and the defect interception efficiency is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of defect detection technology, and in particular to a defect detection method and system for integrated circuit manufacturing. Background Art

[0002] In the integrated circuit packaging stage, as the chip integration increases and the packaging process develops towards high-density, multi-layer stacking, high-density packaging structures (such as 2.5D / 3D packaging) require detection methods to simultaneously capture the geometric features of the surface morphology (such as particle attachment, depression) and internal electrical response characteristics (such as microcracks, short circuits) to ensure packaging reliability and yield. In addition, the post-packaging sorting link needs to achieve real-time linkage between detection and sorting to avoid the problem of misscreening of good products or secondary damage caused by the disconnection between sorting parameters and defect characteristics.

[0003] The current mainstream solution adopts a phased independent detection mode: first, the chip surface is reconstructed with high resolution three-dimensional morphology through the automatic optical inspection (AOI) system to screen out abnormal surface areas; then the screened chips are subjected to X-ray layered imaging, and local defect detection is performed on the corresponding layers of the abnormal areas. This solution realizes the step-by-step determination of surface and internal defects through the combination of optical and radiographic technologies, and relies on the secondary positioning and clamping of the sorted chips to complete internal detection.

[0004] The existing solutions have the following defects: X-ray layered imaging requires multiple rotations and scanning of the chip to obtain tomographic images. The detection time of a single chip exceeds 30 seconds, which cannot meet the real-time sorting requirements of the production line; surface and internal detection belong to independent workstations, and the chip needs to be repositioned and clamped after sorting, resulting in mechanical vibration and contact errors, affecting the stability of high-frequency electrical signal detection; there is a lack of spatiotemporal correlation rules between the surface defect coordinates and the internal electrical signal characteristics, and cross-layer composite defects cannot be determined (such as the propagation path of surface particles causing metal layer fractures), resulting in an increase in the missed detection rate of small surface defects and low defect interception efficiency. Summary of the invention

[0005] The present application provides a defect detection method and system for integrated circuit manufacturing, which are used to solve the problem of low defect interception efficiency in the prior art.

[0006] In a first aspect, the present application provides a defect detection method for integrated circuit manufacturing, comprising: In the integrated circuit packaging stage, the packaged chips are classified into a first type of chips that meet a preset physical property threshold and a second type of chips that exceed the physical property threshold by a pneumatic sorting device based on the size deviation or surface roughness data of the packaged chips; Performing scanning electron microscopy imaging on the surface of the second type of chip, generating a three-dimensional topological structure using machine learning-driven image reconstruction technology, and locating micron-scale particle defect areas by comparing the three-dimensional topological structure with a reference type of a standard packaged chip; During the sorting process, high-frequency electrical signal excitation is synchronously applied, and an abnormal signal sequence in which the current fluctuation exceeds a preset frequency domain range is recorded by detecting the impedance response of the internal metal layer of the second type chip to the high-frequency electrical signal excitation; Performing temporal and spatial correlation matching between the micron-sized particle defect region and the abnormal signal sequence, and determining that the defect is a multi-layer composite defect that penetrates the chip surface and the interior when the coordinates of the micron-sized particle defect region and the phase offset of the abnormal signal sequence meet a preset coupling condition; The mesh size and vibration frequency parameters of the pneumatic sorting device are dynamically adjusted according to the multi-layer composite defects.

[0007] Optionally, when the coordinates of the micron-scale particle defect area and the phase offset of the abnormal signal sequence meet a preset coupling condition, it is determined to be a multi-layer composite defect that penetrates the surface and interior of the chip, including: Based on the surface physical coordinate system of the micron-sized particle defect region and the phase offset of the abnormal signal sequence, a three-dimensional spatial mapping relationship with the center of the package chip solder ball array as the origin is established; According to the three-dimensional spatial mapping relationship, the boundary coordinates of the micron-scale particle defect area are extended in three-dimensional space along the stacking direction of the package substrate to generate a metal interconnect layer defect diffusion path corresponding to the phase offset; When the continuous extension distance of the metal interconnect layer defect diffusion path and the cumulative change amount of the phase offset amount meet a preset cross-layer correlation threshold, determining that the micron-scale particle defect area forms a penetrating correlation with the internal metal layer defect; A correlation analysis is performed on the extension direction of the metal interconnect layer defect diffusion path and the frequency distribution of the phase offset. If the extension direction is consistent with the delay gradient direction of the energy concentration frequency band in the frequency distribution, environmental noise interference is eliminated and it is determined to be a multi-layer composite defect.

[0008] Optionally, the step of performing a three-dimensional spatial extension simulation on the boundary coordinates of the micron-scale particle defect region along the stacking direction of the package substrate according to the three-dimensional spatial mapping relationship to generate a metal interconnect layer defect diffusion path corresponding to the phase offset includes: According to the three-dimensional spatial mapping relationship, extracting the projection starting point of the boundary coordinates of the micron-scale particle defect area in the packaging substrate stacking direction; Based on the propagation attenuation characteristics of the phase offset in the metal interconnect layer, calculating the curvature radius of the projection path of the boundary coordinate along the stacking direction; Extending the boundary coordinates layer by layer along the projection path to generate an initial defect diffusion path corresponding to the phase offset; A spatial superposition analysis is performed on the initial defect diffusion path and the distribution of through holes between layers of the packaging substrate, and a metal interconnect layer defect diffusion path corresponding to the phase offset is generated through a distance distribution feature between the initial defect diffusion path and the through hole edge.

[0009] Optionally, the three-dimensional topological structure is generated by using a machine learning driven image reconstruction technology, and the micron-scale particle defect area is located by comparing the three-dimensional topological structure with a reference type difference of a standard packaged chip, including: Based on the surface scanning electron microscope image data of the second type of chip, an initial three-dimensional surface model is constructed by multi-scale feature fusion, and the image reconstruction technology driven by machine learning is used to iteratively optimize the spatial continuity of the initial three-dimensional surface model to generate a three-dimensional topological structure consistent with the microscopic morphology of the packaged chip surface; The three-dimensional topological structure is divided into a continuous slice sequence perpendicular to the surface direction according to a preset layer thickness, and the continuous slice sequence is overlapped and compared layer by layer with the corresponding layer slices of a reference type of a standard packaged chip; Based on the layer-by-layer overlapping comparison results, extract the difference area with local curvature mutation in the three-dimensional topological structure, and map the geometric center coordinates of the difference area to the physical space coordinate system of the microscopic morphology of the packaged chip surface; According to the curvature mutation direction of the difference area and the topological connection relationship between the adjacent areas, the target area that meets the isolated distribution and the curvature gradient direction deviates from the surface normal direction by more than a preset angle is screened out and marked as a micron-scale particle defect area.

[0010] Optionally, according to the curvature mutation direction of the difference area and the topological connection relationship between the adjacent areas, the target area that satisfies the isolated distribution and the curvature gradient direction deviates from the surface normal direction by more than a preset angle is screened out and marked as a micron-level particle defect area, including: Extracting the curvature mutation direction of the difference area in the microscopic morphology of the packaged chip surface based on the geometric center coordinates of the difference area; According to the topological connection relationship between the difference region and the adjacent regions, the isolation distribution characteristics of the difference region are quantitatively calculated by the number of interruptions in the continuity of the curvature gradient between the difference region and the adjacent regions; Comparing the angle of the sudden change of curvature with the direction of the surface normal, and screening out candidate areas where the curvature gradient direction deviates from the surface normal direction by more than a preset angle; In combination with the isolation distribution characteristics and the angle comparison result, a set of regions satisfying the isolation distribution in the candidate regions is marked as a micron-scale particle defect region.

[0011] Optionally, the step of synchronously applying high-frequency electrical signal excitation during the sorting process, detecting the impedance response of the internal metal layer of the second type chip to the high-frequency electrical signal excitation, and recording an abnormal signal sequence in which the current fluctuation exceeds a preset frequency domain range comprises: Establishing a contact connection between the conductive probe of the pneumatic sorting device and the pin of the second type chip, and applying a high-frequency sinusoidal wave excitation signal to the pin; During the loading process of the high-frequency sinusoidal wave excitation signal, synchronously collecting the transient voltage signal and the loop current signal between the pin and the ground terminal, and converting the phase difference between the transient voltage signal and the loop current signal into a frequency domain impedance response spectrum; Performing bandpass filtering on the frequency domain impedance response spectrum, extracting abnormal frequency bands within the frequency range where the impedance amplitude fluctuation exceeds a preset stability threshold, and recording the starting frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band as an abnormal signal sequence; According to the starting frequency distribution density of the abnormal signal sequence, the frequency scanning step length and the voltage amplitude gain coefficient of the high-frequency sinusoidal wave excitation signal in the subsequent sorting batches are dynamically adjusted.

[0012] Optionally, the frequency domain impedance response spectrum is subjected to bandpass filtering to extract abnormal frequency bands in which impedance amplitude fluctuations exceed a preset stability threshold within a frequency range, and the start frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band are recorded as an abnormal signal sequence, including: Based on the frequency distribution characteristics of the frequency domain impedance response spectrum, a typical response frequency band covering defects in the metal interconnect layer of the packaged chip is determined by a bandpass filter to generate a bandpass range; Performing filtering processing on the frequency domain impedance response spectrum within the bandpass range to extract frequency bands where impedance amplitude fluctuations exceed a preset stability threshold; Dividing the frequency band exceeding a preset stability threshold into a plurality of continuous sub-frequency bands, and recording frequency distribution characteristics of the sub-frequency bands; According to the frequency distribution characteristics, adjacent sub-frequency bands with a frequency interval less than a preset minimum interval are merged into abnormal frequency bands, and the starting frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band are recorded as an abnormal signal sequence.

[0013] Optionally, the step of establishing a contact connection between the conductive probe of the pneumatic sorting device and the pin of the second type chip and applying a high-frequency sinusoidal wave excitation signal to the pin includes: A retractable conductive probe array is arranged below the vibrating screen of the pneumatic sorting device, and the probe spacing is matched with the standard pitch of the package chip pins; When the second type of chip moves to a preset sorting station along with the vibration screen, the retractable conductive probe array is controlled to be pressed down in a vertical direction to form a contact connection with the pin surface of the second type of chip; According to the contact connection, a high-frequency sinusoidal wave excitation signal is applied to the retractable conductive probe array by a high-frequency signal generator; According to the distribution density of the second type of chips on the vibration screen, the probe spacing and the loading timing of the high-frequency sinusoidal wave excitation signal are dynamically adjusted.

[0014] Optionally, dynamically adjusting the mesh size and vibration frequency parameters of the pneumatic sorting device according to the multi-layer composite defect includes: Calculating the mesh diameter of the pneumatic sorting device according to the geometric features and spatial distribution characteristics of the multi-layer composite defects; Determining a vibration frequency parameter of the pneumatic sorting device based on a depth position of the multi-layer composite defect in the packaging substrate; Inputting the mesh diameter and the vibration frequency parameters into the control unit of the pneumatic sorting device to adjust the physical parameters of the vibration screen and the vibration motor driving signal in real time; When performing the sorting operation, by monitoring the consistency between the change trend of the detection results of the multi-layer composite defects and the preset defect distribution optimization target, the current values ​​of the mesh diameter and the vibration frequency parameters are locked to complete the closed-loop control process of the sorting and detection linkage.

[0015] In a second aspect, the present application provides a defect detection system for integrated circuit manufacturing, comprising: A sorting module is used to classify the packaged chips into first-category chips that meet a preset physical property threshold and second-category chips that exceed the physical property threshold through a pneumatic sorting device during the integrated circuit packaging stage based on the size deviation or surface roughness data of the packaged chips; A positioning module is used to perform scanning electron microscope imaging on the surface of the second type of chip, generate a three-dimensional topological structure using machine learning driven image reconstruction technology, and locate the micron-scale particle defect area by comparing the three-dimensional topological structure with the reference type of the standard packaged chip; A detection module, used for synchronously applying high-frequency electrical signal excitation during the sorting process, detecting the impedance response of the internal metal layer of the second type of chip to the high-frequency electrical signal excitation, and recording an abnormal signal sequence in which the current fluctuation exceeds a preset frequency domain range; A determination module, used for performing temporal and spatial correlation matching between the micron-sized particle defect region and the abnormal signal sequence, and determining that the defect is a multi-layer composite defect that penetrates the chip surface and the interior when the coordinates of the micron-sized particle defect region and the phase offset of the abnormal signal sequence meet a preset coupling condition; The adjustment module is used to dynamically adjust the mesh diameter and vibration frequency parameters of the pneumatic sorting device according to the multi-layer composite defects.

[0016] In an embodiment of the present application, during the integrated circuit packaging stage, a pneumatic sorting device is used to divide the packaged chips into a first type of chips that meet a preset physical property threshold and a second type of chips that exceed the physical property threshold based on the size deviation or surface roughness data of the packaged chips; a scanning electron microscope is used to image the surface of the second type of chips, and a three-dimensional topological structure is generated using a machine learning-driven image reconstruction technology. The micron-level particle defect area is located by comparing the three-dimensional topological structure with a reference type difference of a standard packaged chip; a high-frequency electric signal excitation is synchronously applied during the sorting process, and an abnormal signal sequence whose current fluctuation exceeds a preset frequency domain range is recorded by detecting the impedance response of the internal metal layer of the second type of chip to the high-frequency electric signal excitation; the micron-level particle defect area is temporally and spatially correlated with the abnormal signal sequence, and when the coordinates of the micron-level particle defect area and the phase offset of the abnormal signal sequence meet the preset coupling condition, it is determined to be a multi-layer composite defect that penetrates the surface and interior of the chip; and the mesh diameter and vibration frequency parameters of the pneumatic sorting device are dynamically adjusted according to the multi-layer composite defect.

[0017] The technical solution of this application has the following beneficial effects: Through the physical property threshold, qualified and out-of-standard chips are quickly separated to reduce the redundant load of subsequent detection and improve the overall sorting efficiency; combining scanning electron microscope imaging and machine learning reconstruction technology, surface micron-level defects are accurately identified to enhance the accuracy and automation level of defect detection; internal metal layer defects are captured through impedance response anomalies, and potential hidden dangers inside the chip are simultaneously exposed to avoid the limitations of relying solely on surface detection; the surface defect position and the electrical signal phase shift characteristics are dynamically correlated to realize the determination of cross-layer composite defects and reduce the misjudgment or missed detection of single-dimensional detection; the parameters of the sorting device are optimized in real time based on the composite defect characteristics to improve the targeted defect interception and the adaptability of the sorting process.

[0018] Furthermore, based on the mapping relationship between the surface defect coordinates and the phase offset of the electrical signal, a three-dimensional space model centered on the solder ball array is constructed to simulate the diffusion path of the defect along the stacking direction of the package substrate; the penetration of the surface and internal defects is verified through the cross-layer correlation threshold, and the delay gradient consistency of the defect path extension direction and the signal frequency band energy distribution is combined to eliminate noise interference and finally confirm the multi-layer composite defects. Through three-dimensional space modeling and cross-layer path simulation, the correlation verification capability of surface defects and internal electrical performance anomalies is significantly improved. At the same time, the consistency analysis based on time-frequency domain characteristics effectively reduces the risk of misjudgment of environmental noise, and strengthens the accurate judgment and classification reliability of penetrating multi-layer composite defects.

[0019] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A flow chart of a defect detection method for integrated circuit manufacturing provided by the present application is shown; Figure 2 A schematic structural diagram of a defect detection system for integrated circuit manufacturing provided by the present application is shown. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0023] In some of the processes described in the specification and claims of this application and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0024] This application uses a pneumatic sorting device to perform initial screening of chips (based on size / surface roughness) during the packaging stage, and the second type of chips screened out enter the surface and internal collaborative detection process: using scanning electron microscope imaging combined with machine learning-driven three-dimensional topological reconstruction technology to accurately locate surface micron-level particle defects; at the same time, high-frequency electrical signal excitation is synchronously loaded during the sorting process, and potential internal defects are captured by analyzing the frequency domain abnormal characteristics of the internal metal layer impedance response spectrum; the surface defect coordinates and the abnormal signal phase offset are further modeled for time-space correlation, and the penetration correlation between surface and internal defects is determined by preset coupling conditions; finally, the sorting parameters are dynamically adjusted based on the distribution characteristics of multi-layer composite defects, forming a closed-loop control system in which the detection results are fed back to the sorting process in real time, thereby achieving technical synergy between sorting accuracy and deep linkage of defect detection.

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0026] Figure 1 A flowchart of a defect detection method for integrated circuit manufacturing is provided for an embodiment of the present application, such as Figure 1 As shown, the method includes: 101. In the integrated circuit packaging stage, the packaged chips are classified into a first type of chips that meet a preset physical property threshold and a second type of chips that exceed the physical property threshold by a pneumatic sorting device based on the size deviation or surface roughness data of the packaged chips; In this step, the physical property threshold refers to the pre-set allowable deviation range of chip size after packaging and the critical value of surface roughness, which is used to divide the boundary standard between qualified chips and chips to be re-inspected. The second type of chips refers to a collection of chips whose size deviation or surface roughness data exceeds the physical property threshold and needs to enter the deep inspection process.

[0027] In the embodiment of the present application, a vibrating screen of a pneumatic sorting device is used to separate chips in a high-speed vibration mode, and a multi-spectral confocal sensor is used to capture the three-dimensional morphology data of the chip surface in real time, and a laser interferometer is used to measure the chip edge size fluctuation. Based on the Gaussian mixture model (GMM), the size and roughness data are clustered and analyzed, and the expectation maximization algorithm (EM) is used to iteratively optimize the cluster centers and dynamically divide the chip categories. The physical property threshold is generated by reversely deducing the thermal map distribution of historical good product data and the thermal expansion coefficient of the packaging material. Finally, the aperture opening and closing parameters of the vibrating screen are adaptively controlled by a random forest classifier to achieve physical separation of the first and second types of chips.

[0028] Assume that a high-end packaging production line uses a pneumatic sorting device, and sets the dimension deviation threshold to ±3.5μm (X / Y / Z three axes) and the surface roughness Ra threshold to 0.15μm. In a batch of chips, the chip numbered E-509 has a Y-axis dimension deviation of +4.2μm (standard value ±3.5μm) and a surface roughness Ra value of 0.18μm (0.22μm in the local area), which triggers the infrared sensor alarm of the sorting device. Based on the real-time classification results, the pneumatic screen pushes the E-509 chip to the second-category chip buffer area, while the first-category chips are directly sent to the packaging section through the conveyor belt, with a sorting speed of 1,500 chips per hour.

[0029] 102. Perform scanning electron microscopy imaging on the surface of the second type of chip, generate a three-dimensional topological structure using machine learning driven image reconstruction technology, and locate micron-scale particle defect areas by comparing the three-dimensional topological structure with a reference type of a standard packaged chip; In this step, the reference type difference refers to the difference between the three-dimensional topological structure and the geometric model of the standard packaged chip in terms of curvature gradient, height field distribution and other dimensions, which is used to quantify the degree of geometric distortion of surface defects. Micron-scale particle defect area refers to an isolated defect area with a diameter of 1-10μm attached to the surface and a curvature gradient direction that deviates from the surface normal by more than 15°.

[0030] In the embodiment of the present application, multi-angle scanning electron microscope imaging (inclination range 15°-65°, step length 5°) is performed on the second type of chip, and image super-resolution reconstruction (4K resolution enhanced to 8K) is performed by an improved generative adversarial network (GAN). Using the three-dimensional reconstruction model of the Transformer architecture, the multi-view image sequence is mapped into a voxelized three-dimensional point cloud, and aligned with the standard reference type through a non-rigid ICP algorithm. The difference area detection uses a graph convolutional network (GCN) based on curvature sensitivity to extract local curvature mutation points (curvature change rate ≥ 0.05 / μm) and calculate its Hausdorff distance with the reference model (the threshold is set to 2μm). The geometric center coordinates of the micron-scale particle defect area are determined by Delaunay triangulation and centroid iteration algorithm, and finally mapped to the UV coordinate system of the chip surface.

[0031] For example, continuing the above example, the E-509 chip enters the surface inspection station and uses a field emission scanning electron microscope (FESEM) for multi-angle imaging (inclination angle 20°, 45°, 60°) with a resolution of 5nm. The three-dimensional topological structure is reconstructed through multi-view image fusion technology, and micron-level particle defect areas are detected. The main defect area is a spherical particle located at the coordinates (X=7.8mm, Y=10.3mm), with a diameter of 9.5μm, a curvature gradient direction that deviates from the normal by 28°, and a height field difference of 1.2μm; the linear scratch in the secondary defect area is 15μm long, 0.8μm deep, and the number of curvature continuity interruptions is 4 times / μm; the edge warping is a local warping height of the edge of the packaging material of 0.5μm, covering an area of ​​2.3mm²; the main defect area is automatically marked as a key detection target, and the remaining areas are stored in the secondary log.

[0032] 103. During the sorting process, a high-frequency electric signal excitation is synchronously applied, and an abnormal signal sequence in which the current fluctuation exceeds a preset frequency domain range is recorded by detecting the impedance response of the internal metal layer of the second type chip to the high-frequency electric signal excitation; In this step, the frequency domain abnormal characteristics refer to the abnormal frequency bands in which the impedance amplitude fluctuation in the impedance response spectrum of the metal layer exceeds the stability threshold (such as ±5%) and the phase mutation point density is higher than 10 / MHz under the excitation of high-frequency electrical signals. The abnormal signal sequence is a time series data set consisting of the start frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band, which is used to characterize the electrical response characteristics of internal defects.

[0033] In the embodiment of the present application, a sweep frequency signal (500MHz-3GHz, step size 10MHz) is loaded to the chip pin by a vector network analyzer (VNA), and the reflection and transmission characteristics of the metal layer are analyzed by the S parameter matrix. After the impedance response spectrum is denoised by wavelet packet transform, the frequency domain characteristic mode is extracted by variational mode decomposition (VMD). An adaptive threshold segmentation algorithm is used for abnormal frequency band detection, in which the stability threshold is dynamically calculated by the impedance standard deviation within a sliding window (window width 50MHz), the instantaneous phase is extracted by Hilbert transform, and the abnormal signal sequence whose current fluctuation exceeds the preset stability threshold range is recorded.

[0034] For example, continuing the above example, a 2.8GHz high-frequency excitation signal is loaded on the E-509 chip, and the S11 reflection coefficient is measured by the RF probe station. The detection found that the abnormal frequency band is 2.6-2.75GHz, the impedance amplitude fluctuation peak value reaches 12.5dB, and the phase nonlinear distortion angle is 45°; the abnormal frequency band 2 is 3.1-3.3GHz, and the second harmonic resonance occurs, and the harmonic energy accounts for 18%; delay characteristics: the signal propagation delay corresponding to the main defect area is 32ps, which is 28% offset from the standard value (25ps); finally, the abnormal signal sequence Cluster_12 is generated, which contains the frequency band boundary, harmonic characteristics and delay labels, and is bound to the surface defect coordinates.

[0035] 104. Performing temporal and spatial correlation matching on the micron-sized particle defect region and the abnormal signal sequence, and when the coordinates of the micron-sized particle defect region and the phase offset of the abnormal signal sequence meet a preset coupling condition, determining it as a multi-layer composite defect that penetrates the surface and the interior of the chip; In this step, spatiotemporal correlation modeling refers to the joint analysis of the physical coordinates of the surface defect and the time domain characteristics of the abnormal signal phase offset to construct the association rules of the defect propagation in space and time evolution. The preset coupling condition means that the projection path of the surface defect coordinate along the stacking direction of the package substrate and the time delay gradient direction of the phase offset must meet the angle ≤30° and the path length correlation coefficient ≥0.7.

[0036] In the embodiment of the present application, the surface defect coordinates (XYZ) of the micron-scale particle defect area are mapped to the time-frequency domain feature space through a spatiotemporal encoder, and the connection weights between the defect area and the abnormal signal node are established using a graph attention network (GAT). The time delay gradient of the phase offset is calculated by the Wigner and Viril distribution (WVD) to calculate the instantaneous frequency slope, and the propagation path of the surface defect is simulated by the finite element method (FEM) to simulate the stress distribution of the metal layer. The coupling condition is determined based on the improved dynamic time warping (DTW) algorithm, and the Pearson correlation coefficient of the path length and the phase delay is calculated, and the random forest classifier is combined to evaluate the probability of cross-layer defects. When the phase offset meets the preset coupling condition, it is determined to be a multi-layer composite defect that runs through the surface and interior of the chip.

[0037] For example, continuing with the above example, the spatiotemporal correlation engine maps the coordinates of the main defect area of ​​the E-509 chip (7.8mm, 10.3mm) to the L2 metal layer of the packaging substrate. First, the stress propagation path is displayed through finite element simulation. The defect extends to the L3 layer along the stacking direction. The path length is 1.2mm, and the Pearson correlation coefficient with the phase delay is 0.81; secondly, the electric field distortion is displayed, and the local electric field strength abnormality appears in the L2-L3 interlayer medium (the peak value reaches 5.6kV / m, the standard value ≤3.8kV / m); finally, the coupling judgment is performed, the path angle is 19° (threshold ≤30°), and the energy attenuation gradient matching degree is 92%, which is determined to be a multi-layer composite defect that penetrates the surface and interior of the chip, triggering a multi-layer composite defect alarm.

[0038] 105. Dynamically adjust the mesh size and vibration frequency parameters of the pneumatic sorting device according to the multi-layer composite defects.

[0039] In this step, multi-layer composite defects refer to a set of defects that exist simultaneously on the chip surface and in more than two metal interconnection layers inside the chip and have spatial propagation correlation. Their depth distribution and geometric dimensions constitute the decision-making basis for adjusting the sorting parameters.

[0040] In the embodiment of the present application, based on the three-dimensional coordinate data set of multi-layer composite defects, a mixed integer programming (MIP) is used to construct a collaborative optimization model of mesh aperture and vibration frequency, in which the decision variables are the mesh aperture adjustment amount (discrete variable, step size 5μm) and the vibration frequency increment (continuous variable, resolution 0.1Hz). The defect depth feature is converted into a vibration energy attenuation factor through the acoustic impedance coefficient of the interlayer dielectric material, and the drive frequency adjustment amount is calculated; the defect size feature is extracted by the morphological corrosion algorithm to extract the maximum inscribed circle diameter and mapped to the safety margin threshold of the mesh aperture; the digital twin technology is used to construct a multi-body dynamics simulation model of the sorting process, and the Lissajous graphics analysis predicts the chip motion trajectory after parameter adjustment, and the model reference adaptive system (MRAS) in the adaptive control theory is combined to correct the parameter deviation online. The final generated sorting parameter combination is synchronized to the pneumatic actuator through the industrial bus to achieve sub-millisecond response.

[0041] For example, in the above example, dynamic adjustment is performed for the composite defect of the L2-L3 layer of the E-509 chip (depth 1.2mm, defect cluster area 92μm²). First, the mesh aperture is adjusted. According to the maximum inscribed circle diameter of the defect 8.7μm and the safety factor 1.5, the mesh aperture is reduced from 125μm to 112μm to prevent similar size defects from being missed. Secondly, the vibration frequency is optimized. Based on the acoustic impedance of the L2 layer medium (4.6×10 6 Rayl) and defect depth, the frequency was increased from 85Hz to 93.5Hz to enhance the separation efficiency of deep defect chips; finally, airflow compensation, according to the adhesion model of epoxy resin particles, the airflow pressure was increased from 0.2MPa to 0.28MPa to prevent microparticles from being retained on the screen. After the adjustment, the sorting misjudgment rate of this batch of chips decreased by 37%, and no new surface mechanical damage was caused.

[0042] Steps 101-105 build a closed-loop control system for the entire process of packaged chip defects by integrating precision mechanical sorting, multi-physics field detection, and intelligent decision-making algorithms. Surface morphology reconstruction technology breaks through the accuracy limitations of traditional optical detection, high-frequency electrical signal analysis enables non-destructive detection of metal layer defects, and the spatiotemporal correlation model effectively identifies the propagation mechanism of cross-layer composite defects. The dynamic sorting strategy driven by reinforcement learning significantly improves the yield and efficiency of the production line, providing a reliable defect control solution for high-density packaging processes.

[0043] In order to solve the problem of missed detection of cross-layer correlation between surface defects of packaged chips and internal metal layer defects, and further improve the accuracy of determining the defect propagation path, accurate identification of multi-layer composite defects is achieved through spatiotemporal data fusion and physical field coupling modeling. In some embodiments, when the coordinates of the micron-scale particle defect area and the phase offset of the abnormal signal sequence meet the preset coupling conditions, it is determined to be a multi-layer composite defect that runs through the surface and interior of the chip, including: 201. Establishing a three-dimensional spatial mapping relationship with the center of the solder ball array of the packaged chip as the origin based on the surface physical coordinate system of the micron-scale particle defect area and the phase offset of the abnormal signal sequence; In step 201, the surface physical coordinate system refers to the XYZ three-dimensional coordinate system established with the center of the package chip solder ball array as the origin, which is used to calibrate the geometric position of the surface defect. The phase offset refers to the time delay phase difference caused by the defect during the propagation of the high-frequency electrical signal in the metal interconnect layer, reflecting the degree of influence of the defect on the signal propagation path.

[0044] In the embodiment of the present application, the center coordinates of the solder ball array are calibrated by a laser tracker (accuracy ±0.1μm), and the UVW local coordinate system of the surface defect (based on scanning electron microscope imaging) is converted into a global surface physical coordinate system. A spatial transformation algorithm (SE(3) group transformation) is used to align the time domain sequence of the phase offset with the surface coordinates, where the phase data is extracted through a phase-locked amplifier with an instantaneous phase angle (resolution 0.01°). When establishing the mapping relationship, the anisotropic thermal expansion coefficient of the package substrate is introduced to correct the coordinate offset error, and the spatial data distribution is optimized by kernel density estimation (KDE), and finally a three-dimensional spatial mapping relationship with the center of the package chip solder ball array as the origin is generated.

[0045] 202. According to the three-dimensional spatial mapping relationship, perform a three-dimensional spatial extension simulation on the boundary coordinates of the micron-scale particle defect region along the stacking direction of the package substrate to generate a metal interconnect layer defect diffusion path corresponding to the phase offset; In step 202, the three-dimensional space extension simulation refers to projecting and extending the surface defect coordinates along the stacking direction (Z axis) of the package substrate to simulate the potential propagation path of the defect to the internal metal layer. The defect diffusion path refers to the virtual trajectory of the surface defect extending along the grain boundary or dielectric crack in the metal interconnect layer, and its shape is determined by the cumulative effect of the phase offset.

[0046] In the embodiment of the present application, based on the three-dimensional spatial mapping relationship, the finite element method (FEM) is used to simulate the stress distribution of surface defects under the action of the thermal-mechanical coupling field, and the phase field model is combined to predict the crack extension direction. The radius of curvature of the defect diffusion path is dynamically adjusted by the gradient descent direction of the phase offset, where the gradient value is obtained by calculating the group delay (GroupDelay) of the signal propagation path. The path generation adopts an improved A* search algorithm, and the dielectric constant mutation interface (such as the interface between SiO2 and Cu) is preferentially selected as the extension node, and the path probability distribution is verified by the Monte Carlo method to generate the metal interconnect layer defect diffusion path corresponding to the phase offset.

[0047] 203. When the continuous extension distance of the metal interconnect layer defect diffusion path and the cumulative change amount of the phase offset amount meet a preset cross-layer correlation threshold, it is determined that the micron-scale particle defect area forms a penetrating correlation with the internal metal layer defect; In step 203, the cross-layer correlation threshold refers to a joint judgment criterion of the continuous extension distance (≥50 μm) of the metal interconnect layer defect diffusion path between adjacent metal layers and the cumulative change amount of the phase offset (≥120°).

[0048] In the embodiment of the present application, the diffusion path is subjected to a piecewise differential geometry analysis, and the arc length and curvature integral of each path segment are extracted. The cumulative change of the phase offset is extracted by the Hilbert-Huang transform (HHT) to extract the phase accumulation value of the intrinsic mode function. The dynamic time warping (DTW) algorithm is used to align the path extension distance and the phase change curve, and the Pearson correlation coefficient between the two is calculated. When the correlation coefficient exceeds the cross-layer correlation threshold of 0.75 and the path penetrates at least two layers of metal, the penetration correlation judgment is triggered, and the continuity of the defect propagation state is verified by the hidden Markov model (HMM).

[0049] 204. Perform correlation analysis on the extension direction of the metal interconnect layer defect diffusion path and the frequency distribution of the phase offset. If the extension direction is consistent with the delay gradient direction of the energy concentration frequency band in the frequency distribution, then eliminate environmental noise interference and determine it as a multi-layer composite defect.

[0050] In step 204, the time delay gradient direction refers to the direction of the phase delay change rate of the energy concentrated frequency band in the frequency distribution of the abnormal signal, reflecting the influence trend of the defect on the signal propagation speed.

[0051] In an embodiment of the present application, principal component analysis (PCA) is performed on the tangent direction vector of the defect diffusion path to extract the main direction component of the path extension. The frequency distribution of the phase offset is extracted by Welch power spectral density estimation (PSD) to extract the energy peak frequency band, and the delay gradient direction is calculated by the instantaneous frequency derivative of the complex wavelet transform. The correlation analysis uses canonical correlation analysis (CCA) to fuse the path direction and the frequency band delay gradient, and the KS test is used to eliminate random noise interference. The final basis for determining multi-layer composite defects is the cosine similarity of the direction angle (≥0.85) and the frequency band energy proportion (≥15%).

[0052] Here is a specific example: A surface particle defect was detected in a 3D packaged chip production line, and it was necessary to verify whether it caused the internal metal layer to break. Through step 201, the center coordinates of the solder ball array were calibrated to (X=50.0mm, Y=50.0mm), and the coordinates of the surface particle defect were detected (X=52.3mm, Y=48.7mm); a 3GHz high-frequency signal was loaded to measure the phase offset Δφ=135°, and a three-dimensional spatial mapping relationship was established. Through step 202, the simulation showed that the defect extended along the Z axis to the L2 metal layer, the path curvature radius R=12μm, passed through the Cu / SiO2 interface 3 times, and generated a metal interconnect layer defect diffusion path with a path length of 180μm, covering the L1-L3 metal layers. Through step 203, the path continuous extension distance was 200μm, the phase cumulative change Δφ=142°, the correlation coefficient was 0.81, and the HMM verified state transition probability was >90%, which was determined to be a penetration association. Through step 204, it is calculated that the angle between the path extension direction and the delay gradient direction of the 2.6-2.8 GHz frequency band is 8°, the cosine similarity is 0.92, and the frequency band energy accounts for 18%. After excluding environmental noise, it is confirmed to be a multi-layer composite defect.

[0053] Steps 201-204 achieve accurate correlation between surface defects and internal metal layer defects through spatial mapping, physical field coupling simulation and multimodal data analysis. Spatiotemporal data fusion technology breaks through the limitations of traditional step-by-step detection, the dynamic matching of phase offset and diffusion path improves the sensitivity of cross-layer defect recognition, and the frequency band energy correlation analysis effectively suppresses environmental noise interference, providing reliable full-process defect propagation mechanism analysis capabilities for high-density packaged chips.

[0054] In order to solve the problem of insufficient modeling accuracy of surface defects and internal metal layer defect diffusion paths in high-density packaged chips and further improve the physical consistency of defect propagation trajectory prediction, this solution integrates three-dimensional space projection, phase attenuation characteristic modeling and interlayer structure constraint analysis to achieve accurate generation and verification of metal interconnect layer defect diffusion paths. In some embodiments, according to the three-dimensional space mapping relationship, the boundary coordinates of the micron-scale particle defect area are extended in three dimensions along the stacking direction of the package substrate to generate the metal interconnect layer defect diffusion path corresponding to the phase offset, including: 301. Extracting a projection starting point of the boundary coordinates of the micron-scale particle defect region in a stacking direction of the packaging substrate according to the three-dimensional space mapping relationship; In step 301 , the projection starting point refers to the initial projection position of the boundary coordinates of the micron-scale particle defect region in the packaging substrate stacking direction (Z axis), which is used to define the starting point of the defect extending inward.

[0055] In the embodiment of the present application, based on the homogeneous coordinate matrix of the three-dimensional space mapping relationship, the inverse projection transformation algorithm is used to convert the UVW local coordinates of the surface defects into XYZ coordinates in the global coordinate system. The reference plane in the stacking direction is calibrated by laser interferometer, and the projection error caused by the warping of the packaging substrate is eliminated by combining Kalman filtering. The projection starting point is calculated by fitting the Z-axis distribution of the boundary coordinates using the weighted least squares method, and the curvature extreme point is preferentially selected as the starting position. The spatiotemporal labels of the phase offset are aligned through the Lie group SE (3) transformation, and finally the projection starting point of the boundary coordinates of the micron-scale particle defect area in the stacking direction of the packaging substrate is output.

[0056] 302. Calculate the curvature radius of the projection path of the boundary coordinate along the stacking direction based on the propagation attenuation characteristics of the phase offset in the metal interconnect layer; In step 302, the propagation attenuation characteristic refers to the quantitative relationship between the signal amplitude attenuation and the phase delay caused by dielectric loss, skin effect, etc. when the high-frequency electrical signal propagates in the metal interconnection layer.

[0057] In the embodiment of the present application, the finite difference time domain method (FDTD) is used to simulate the propagation process of high-frequency signals in a multi-layer metal structure, and the attenuation gradient of the phase offset with the propagation distance is extracted. The curvature radius calculation is based on the Frenet frame theory of differential geometry. The projection path of the defect boundary coordinates is decomposed into tangent vector, normal vector and binormal vector components, and the curvature radius is dynamically adjusted in combination with the logarithmic fitting curve of the signal attenuation coefficient. The path smoothness is optimized by Bezier curve fitting, and the gradient descent algorithm is introduced to iteratively correct the curvature mutation point (curvature change rate > 0.1 / μm), and finally the projection path curvature radius matching the phase attenuation characteristics is generated.

[0058] 303. Extend the boundary coordinates layer by layer along the projection path to generate an initial defect diffusion path corresponding to the phase offset; In step 303, layer-by-layer extension refers to gradually extending the defect path along the stacking direction according to the thickness of the metal layer and the interval between the dielectric layers of the packaging substrate to simulate the dynamic process of defect cross-layer propagation.

[0059] In the embodiment of the present application, the metal layer grid units are divided by adaptive mesh refinement (AMR) technology based on boundary coordinates, and the defect path extension direction is determined by the principal strain direction of the local stress tensor. The phase offset is mapped to the propagation weight of each layer of grid through wavelet packet decomposition, and is extended layer by layer along the stacking direction of each layer of grid, and the Hamiltonian Monte Carlo (HMC) sampling is combined to generate a probabilistic extension path. The path optimization adopts the rapidly expanding random tree (RRT*) algorithm to preferentially bypass the interlayer interface with a sudden change in dielectric constant (such as the interface between Low-K medium and copper interconnect), and finally generates an initial defect diffusion path set corresponding to the phase offset.

[0060] 304. Perform spatial superposition analysis on the initial defect diffusion path and the distribution of through holes between layers of the package substrate, and generate a metal interconnect layer defect diffusion path corresponding to the phase offset through a distance distribution feature between the initial defect diffusion path and the through hole edge.

[0061] In step 304, the distance distribution characteristics refer to spatial relationship parameters such as the minimum Euclidean distance and average proximity between the initial defect diffusion path and the edge of the interlayer through hole.

[0062] In the embodiment of the present application, point cloud registration is performed on the interlayer vias of the package substrate, and the iterative closest point (ICP) algorithm is used to align the distance distribution characteristics between the initial defect diffusion path and the edge of the via. Spatial superposition analysis is combined with morphological corrosion and expansion operations to extract the contact area between the path and the via, and a three-dimensional buffer zone of the via influence zone is generated by implicit surface reconstruction (IMR). The defect diffusion path correction adopts constrained Delaunay triangulation (CDT) to remove the path segments overlapping with the via buffer zone, and the credibility of the remaining path is weighted based on the frequency domain energy distribution of the phase offset, and finally the metal interconnect layer defect diffusion path corresponding to the phase offset is output.

[0063] Here is a specific example: A 2.5D packaged chip production line detected a surface particle defect (coordinates X=15.2mm, Y=8.7mm), and its internal diffusion path needed to be predicted. First, based on the three-dimensional spatial mapping relationship, the starting point of the projection of the defect boundary coordinates in the stacking direction of the package substrate was extracted, and the initial projection position was determined to be the upper surface of the L1 layer (Z=0.12mm), with an error controlled within ±0.03μm. Then, according to the propagation attenuation characteristics of the phase offset in the metal interconnect layer, the curvature radius of the projection path of the defect boundary coordinates along the stacking direction was calculated, and the projection path curvature radius was generated, L1-L2 layer R=9.8μm, L2-L3 layer R=14.2μm, and the path smoothness was optimized by the Bezier curve. Subsequently, the boundary coordinates were extended layer by layer along the projection path, and the metal layer grid units were divided by the adaptive grid refinement technology. Combined with Hamiltonian Monte Carlo sampling, three initial defect diffusion paths were generated, of which the longest path extended to the L4 layer (total length 320μm) and covered 8 metal grid units. Finally, a spatial superposition analysis is performed on the initial defect diffusion path and the distribution of through-holes between the packaging substrate layers. The path segments with a distance of less than 2μm from the TSV through-hole (diameter 10μm) are removed, and two metal interconnect layer defect diffusion paths that comply with physical design rules are retained. The path credibility is weighted by frequency domain energy distribution to ensure the reliability of path prediction.

[0064] Steps 301-304 significantly improve the prediction accuracy of the metal interconnect layer defect diffusion path through technologies such as 3D projection starting point calibration, phase attenuation driven curvature modeling, and interlayer constraint path optimization. Dynamic adjustment of the curvature radius avoids the physical distortion of the traditional fixed model, Monte Carlo sampling and RRT* algorithm enhance the robustness of path generation, and the through-hole buffer constraint ensures that the path complies with the actual process design rules, providing high-confidence defect propagation trajectory data for packaging reliability evaluation.

[0065] In order to solve the problem of insufficient accuracy of three-dimensional morphology reconstruction and high missed detection rate of local distortion features in the detection of micron-level particle defects on the surface of high-density packaged chips, and to further improve the accuracy and noise resistance of defect positioning, a high-fidelity three-dimensional model is constructed through multi-scale feature fusion and topological continuity optimization, and accurate screening of defects is achieved by combining inter-layer comparison and curvature gradient analysis. In some embodiments, the image reconstruction technology driven by machine learning generates a three-dimensional topological structure, and locates the micron-level particle defect area by comparing the three-dimensional topological structure with the reference type of the standard packaged chip, including: 401. Based on the surface scanning electron microscope image data of the second type of chip, construct an initial three-dimensional surface model by multi-scale feature fusion, and use the machine learning driven image reconstruction technology to iteratively optimize the spatial continuity of the initial three-dimensional surface model to generate a three-dimensional topological structure consistent with the microscopic morphology of the packaged chip surface; In step 401, multi-scale feature fusion refers to the process of extracting global contour features and local detail features of surface morphology from SEM images of different resolutions and fields of view, and performing cross-scale joint analysis. Spatial continuity iterative optimization refers to multiple corrections to geometric discontinuous areas (such as step edges and particle gaps) of the three-dimensional model through machine learning technology to ensure the physical continuity of the model surface curvature.

[0066] In the embodiment of the present application, a multi-resolution scanning electron microscope imaging system is used to collect surface image data of the second type of chip. The low-magnification image (100X) captures the global morphology, and the high-magnification image (10kX) focuses on local details. Multi-scale features are fused through a pyramid convolutional network (PCN) to generate point cloud data of the initial three-dimensional surface model. The discriminator branch of the generative adversarial network (GAN) is used to detect surface discontinuities, and the generator branch corrects the offset of the point cloud coordinates through residual connections. A curvature-driven loss function is introduced in the iterative optimization process to penalize the normal vector mutations of adjacent point clouds (angle difference > 5°), and finally output a three-dimensional topological structure consistent with the microscopic morphology of the packaged chip surface.

[0067] 402. Segment the three-dimensional topological structure into a continuous slice sequence perpendicular to the surface direction according to a preset layer thickness, and perform layer-by-layer overlap comparison between the continuous slice sequence and corresponding layer slices of a reference type of a standard packaged chip; In step 402, the continuous slice sequence refers to a set of two-dimensional cross-sectional images generated by cutting the three-dimensional topological structure along the direction perpendicular to the surface with a fixed layer thickness (such as 0.1 μm). Layer-by-layer overlap comparison refers to the process of performing pixel-level spatial alignment and difference detection on the slice sequence of the chip to be tested and the corresponding layer slice of the standard reference type.

[0068] In the embodiment of the present application, the three-dimensional topological structure is voxelized, and the marching cubes algorithm is used to generate equally spaced slices. The feature points of the slice to be tested and the reference slice (such as the edge of the solder ball and the corner of the metal wire) are aligned by the non-rigid ICP registration algorithm, and the registration error is nonlinearly corrected by thin plate spline interpolation (TPS). The difference detection uses a dual-channel convolutional network (DC-CNN) to extract the texture features of the slice to be tested and the reference slice for layer-by-layer overlapping comparison.

[0069] 403. Based on the layer-by-layer overlapping comparison result, extract the difference area with local curvature mutation in the three-dimensional topological structure, and map the geometric center coordinates of the difference area to the physical space coordinate system of the microscopic morphology of the packaged chip surface; In step 403, the local curvature mutation refers to an abnormal area where the difference between the Gaussian curvature of a point in the three-dimensional topological structure and the average curvature of the adjacent area exceeds a preset threshold (such as ±0.2 / μm). The physical space coordinate system refers to an XYZ coordinate system established with a specific structure (such as a reference mark point) on the surface of the packaged chip as the origin, which is used to calibrate the absolute position of the defect.

[0070] In the embodiment of the present application, based on the layer-by-layer overlapping comparison results, the difference area with local curvature mutation in the three-dimensional topological structure is extracted, the differential geometry analysis is performed on the difference area, the Gaussian curvature and the average curvature of each voxel point are calculated, and the curvature mutation points are aggregated through the regional growing algorithm to form a candidate defect cluster. The geometric center coordinates are determined by the weighted centroid method, and the weight is the curvature mutation amplitude of each point. The coordinate system mapping adopts the affine transformation matrix, combined with the reference point coordinates calibrated by the laser interferometer, to transform the defect cluster center to the physical space coordinate system of the microscopic morphology of the packaged chip surface, and the Kalman filter is used to eliminate the cumulative error in the coordinate system conversion.

[0071] 404. According to the curvature mutation direction of the difference area and the topological connection relationship between the adjacent areas, select the target area that meets the isolated distribution and the curvature gradient direction deviates from the surface normal direction by more than a preset angle, and mark it as a micron-level particle defect area.

[0072] In step 404, the topological connection relationship refers to the geometric continuity characteristics between the difference area and the adjacent area, such as the length of the shared boundary, the transition smoothness of the curvature gradient, etc. The curvature gradient direction deviation refers to the abnormal state that the angle between the curvature gradient direction of the defect area and the surface normal direction exceeds a preset angle (such as 15°).

[0073] In the embodiment of the present application, a graph convolutional network (GCN) is used to construct a surface topological connection diagram, where the nodes are the center points of the difference regions, and the edge weights are calculated by the covariance matrix of the curvature gradient between regions. The isolated distribution is determined based on the analysis of the node degree and the eigenvalue of the adjacency matrix, and isolated nodes with a number of connected edges ≤ 2 are screened out. The curvature gradient direction is extracted by principal component analysis (PCA) to extract the main curvature direction of the defective area, and the vector dot product is performed with the surface normal direction to calculate the angle. Finally, the target area is comprehensively determined by density clustering (DBSCAN) and random forest classifier, and marked as a micron-level particle defect area.

[0074] Here is a specific example: A high-end packaging production line detected abnormal protrusions on the surface of the second-class chip (number F-112) and executed the following process. Step 401 acquires surface data through multi-scale SEM imaging (100X global + 10kX local), generates an initial 3D model through PCN network fusion, obtains a 3D topological structure with continuous curvature after GAN iterative correction, and optimizes the surface roughness Ra from 0.25μm to 0.12μm; Step 402 slices the 3D model with a layer thickness of 0.1μm, compares it with the reference after non-rigid ICP registration, and finds that there is a difference area of ​​120μm² in the L3 layer slice; Step 403 extracts the curvature mutation point of the difference area (Gaussian curvature difference 0.35 / μm), calculates the geometric center coordinates as (X=7.2mm, Y=4.8mm, Z=0.32mm), and maps them to the physical space coordinate system; According to step 404, GCN analysis shows that the area is an isolated node (number of connected edges = 1), the curvature gradient direction deviates from the normal by 23°, and is marked as an epoxy resin micron-scale particle defect area with a diameter of 9.5μm.

[0075] Steps 401-404 construct a high-precision three-dimensional morphology model through multi-scale fusion and iterative optimization, and accurately locate micron-level particle defects through inter-layer comparison and curvature gradient analysis. Topological connection relationship modeling effectively distinguishes isolated defects from process textures, and curvature direction deviation judgment enhances noise resistance, providing multi-dimensional analysis capabilities from global to local, from geometry to topology for packaged chip surface defect detection, significantly reducing the false detection rate and improving defect classification reliability.

[0076] In order to solve the problems of high misjudgment rate of isolated micron-sized particles and inaccurate extraction of defect direction features in surface defect detection of high-density packaged chips, and to further improve the accuracy and anti-interference ability of defect screening, the precise positioning of particle defects is achieved through curvature mutation direction analysis, topological connection relationship modeling and gradient direction deviation determination. In some embodiments, according to the curvature mutation direction of the difference area and the topological connection relationship of the adjacent area, the target area that meets the isolated distribution and the curvature gradient direction deviates from the surface normal direction by more than a preset angle is screened out, and marked as a micron-sized particle defect area, including: 501. Extracting a curvature mutation direction of the difference region in the microscopic morphology of the packaged chip surface based on the geometric center coordinates of the difference region; In step 501, the curvature mutation direction refers to the main direction in which the surface curvature of the difference area undergoes a significant change in microscopic morphology (such as a curvature value jump exceeding a threshold), reflecting the trend of defect geometric distortion.

[0077] In the embodiment of the present application, based on the geometric center coordinates of the difference area, multi-angle scanning electron microscope imaging (inclination angles of 30°, 45°, and 60°) is used to obtain multi-view point cloud data of the surface micromorphology. The local curvature distribution map is reconstructed by phase shift interferometry (PSI), and the main direction component of the curvature change is extracted by principal component analysis (PCA). The calculation of the curvature mutation direction is combined with the Gaussian and Bonnet theorems in differential geometry, and the manifold is fitted to the regional boundary. The Laplace smoothing algorithm is used to eliminate noise interference, and finally the curvature mutation direction that characterizes the defect deformation trend is generated.

[0078] 502. According to the topological connection relationship between the difference region and the adjacent regions, quantitatively calculate the isolated distribution characteristics of the difference region by the number of interruptions of the continuity of the curvature gradient between the difference region and the adjacent regions; In step 502, the number of interruptions in curvature gradient continuity refers to the number of connecting edges where the curvature gradient direction between the difference region and the adjacent region changes suddenly, and is used to quantify the degree of isolation of the defect.

[0079] In the embodiment of the present application, a surface topological connection diagram is constructed, the nodes are the center points of the difference areas, and the edge weights are calculated by the covariance matrix of the curvature gradients of the adjacent areas. The node degree analysis in graph theory is used to count the number of connected edges in each difference area, and the number of continuity interruptions is determined by comparing the directional angles of the curvature gradients of adjacent nodes (the threshold is set to 20°). The calculation of the isolated distribution characteristics of the difference area adopts the information entropy model, and the isolation index (range 0-1) is calculated in combination with the area weight. An index of > 0.7 is determined as a highly isolated area.

[0080] 503. Compare the angle of the sudden change direction of curvature with the direction of the surface normal, and select candidate areas where the curvature gradient direction deviates from the surface normal direction by more than a preset angle; In step 503, the surface normal direction refers to the vertical direction of the packaged chip surface at the geometric center point of the defect area, which is obtained by calculating the three-dimensional curvature field of the microscopic morphology.

[0081] In the embodiment of the present application, local surface fitting is performed on the defective area, a smooth surface model is generated using non-uniform rational B-spline (NURBS), and the normal direction of the geometric center point is calculated. The curvature gradient direction is obtained by vector field integral path tracing. The angle comparison uses the vector space model (VSM) to calculate the cosine similarity of the direction angle, and the preset angle threshold (such as 15°) is determined by ROC curve analysis of historical defect data, and candidate areas with similarity <0.966 (corresponding angle >15°) are screened out.

[0082] 504. In combination with the isolation distribution feature and the angle comparison result, a set of regions satisfying the isolation distribution in the candidate regions is marked as a micron-scale particle defect region.

[0083] In step 504, the set of isolated distribution regions refers to a subset of defect regions that simultaneously meet the curvature gradient direction deviation threshold and the topological connection interruption number threshold.

[0084] In the embodiment of the present application, the isolation index and angle deviation value of the candidate area are input into the multi-objective optimization model, and the Pareto front analysis is used to screen the optimal solution set. The spatially adjacent candidate areas are merged by the density clustering (DBSCAN) algorithm to eliminate pseudo defects caused by process textures (such as metal wire edges). Finally, the set of areas in the candidate area that meet the isolation distribution is marked as micron-level particle defect areas, and the semantic segmentation network (U-Net++) is used to perform pixel-level refinement on the defective area to ensure that the boundary accuracy reaches the micron level.

[0085] Here is a specific example: Multiple abnormal areas were detected on the surface of a 3D packaged chip (No. G-205). Through step 501, the difference area (coordinate X=10.3mm, Y=6.8mm) was imaged from multiple angles. The curvature mutation direction analysis showed that the main direction had an angle of 58° with the X-axis, and the curvature jump value was 0.28 / μm. Based on step 502, the topological connection diagram showed that the area had only one connecting edge (threshold ≥3), 4 curvature gradient interruptions, and an isolation index of 0.83. Through step 503, the surface normal direction was calculated to be (0.12, -0.05, 0.99), the curvature gradient direction angle was 19°, and the cosine similarity was 0.945, and the candidate area whose curvature gradient direction deviated from the surface normal direction by more than a preset angle was screened out. Step 504 eliminated the interference of adjacent metal lines through DBSCAN clustering, marked the area as a solder ball splash micron-level particle defect area with a diameter of 7.2μm, and the boundary positioning error was less than 0.3μm.

[0086] Steps 501-504 significantly improve the recognition accuracy of micron-level particle defects through principal component analysis of curvature mutation direction, quantification of topological connection interruption and determination of gradient direction deviation. Manifold fitting and vector space modeling enhance the ability to extract directional features, and multi-objective optimization and density clustering effectively distinguish real defects from process noise, providing multi-dimensional defect screening capabilities from geometric features to topological associations for high-density packaged chips, greatly reducing the false detection rate and improving the reliability of defect classification.

[0087] In order to solve the problem that the traditional sorting device cannot synchronously detect the defects of the metal layer inside the chip during the sorting process, and the high-frequency signal loading and sorting action are not coordinated enough, the defect detection efficiency and the targeting of the signal excitation are further improved, and the integrated coordination of sorting and detection is realized through contact signal loading, impedance response spectrum analysis and dynamic frequency optimization. In some embodiments, the high-frequency electrical signal excitation is synchronously applied during the sorting process, and the impedance response of the internal metal layer of the second type of chip to the high-frequency electrical signal excitation is detected, and the abnormal signal sequence of the current fluctuation exceeding the preset frequency domain range is recorded, including: 601. Establish contact connection between the conductive probe of the pneumatic sorting device and the pin of the second type chip, and apply a high-frequency sinusoidal wave excitation signal to the pin; In step 601, contact connection refers to the physical contact between the conductive probe of the pneumatic sorting device and the chip pin to establish a stable electrical signal transmission channel. The high-frequency sinusoidal wave excitation signal refers to a radio frequency signal with a frequency range of 500MHz to 3GHz and a continuous sinusoidal wave waveform, which is used to excite the impedance response of the metal interconnect layer.

[0088] In the embodiment of the present application, a multi-degree-of-freedom robotic arm is used to control the conductive probe array, and the pin position of the second type chip is identified by the real-time visual positioning system (RVS) during the movement of the vibrating screen of the pneumatic sorting device. The probe contact pressure is fed back to the PID controller through a piezoelectric ceramic sensor, and the downward pressure is dynamically adjusted (range 0.1-0.5N) to ensure that the contact impedance is stable at 50Ω±5% and a contact connection is established. The high-frequency sinusoidal wave excitation signal is loaded with a direct digital frequency synthesizer (DDS), and the output signal voltage amplitude (1-5V) is adjusted according to the adaptive impedance matching algorithm of the pin material (such as Cu / Ni / Au) to avoid arc discharge at the contact point.

[0089] 602. During the loading process of the high-frequency sinusoidal wave excitation signal, synchronously collect a transient voltage signal and a loop current signal between the pin and the ground terminal, and convert a phase difference between the transient voltage signal and the loop current signal into a frequency domain impedance response spectrum; In step 602, the frequency domain impedance response spectrum refers to converting the time domain voltage / current signal into a spectrum of the relationship between the frequency domain impedance amplitude and phase through Fourier transformation.

[0090] In the embodiment of the present application, during the signal loading process, the transient voltage signal and loop current signal of the pin and the ground terminal are synchronously captured by a high-speed data acquisition card (sampling rate 10GS / s). Signal preprocessing uses adaptive noise cancellation (ANC) technology to eliminate the vibration noise of the sorting device, and extracts the instantaneous phase of the signal through Hilbert transform. The phase difference calculation is combined with the cross-correlation function and least squares fitting optimization, the frequency domain conversion uses a windowed fast Fourier transform (FFT), and the window function uses the Blackman-Harris window to suppress spectrum leakage, and finally generates a frequency domain impedance response spectrum with a resolution of 1MHz.

[0091] 603. Perform bandpass filtering on the frequency domain impedance response spectrum, extract abnormal frequency bands in which impedance amplitude fluctuations exceed a preset stability threshold within the frequency range, and record the start frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band as an abnormal signal sequence; In step 603, the abnormal frequency band refers to a continuous frequency interval in which the amplitude fluctuation in the impedance response spectrum exceeds a stability threshold (such as ±5%) and the phase is nonlinearly distorted.

[0092] In the embodiment of the present application, the impedance response spectrum is subjected to variational mode decomposition (VMD) to separate the intrinsic mode function (IMF) reflecting the defects of the metal layer. Bandpass filtering uses a zero-phase digital filter group, and the passband range is set according to the typical defect response frequency band of the packaging process (such as 2.4-2.6GHz). Abnormal frequency band detection is based on an improved spectral clustering algorithm, which jointly models the impedance amplitude fluctuation and phase jump of adjacent frequency points, divides the abnormal signal clusters by fuzzy C-means clustering (FCM), and records its starting frequency, cutoff frequency and fluctuation peak value (taking the maximum amplitude in the cluster) to form an abnormal signal sequence.

[0093] 604. Dynamically adjust the frequency scanning step and voltage amplitude gain coefficient of the high-frequency sinusoidal wave excitation signal in subsequent sorting batches according to the starting frequency distribution density of the abnormal signal sequence.

[0094] In step 604, the frequency scanning step refers to the interval value of adjacent frequency points of the high-frequency signal generator in the frequency sweep mode (such as 10 MHz). The voltage amplitude gain coefficient refers to the output signal voltage amplification factor (such as 1.2-2.0 times) dynamically adjusted according to the abnormal signal distribution density.

[0095] In the embodiment of the present application, based on the starting frequency distribution density of the abnormal signal sequence, the kernel density estimation (KDE) is used to generate the frequency heat map, and the focus frequency band (such as density peak ± 50MHz) of the next batch scan is determined by the gradient ascent algorithm. The frequency scanning step size is adaptively adjusted according to the full width at half maximum (FWHM) of the heat map (step size = FWHM / 10). The voltage gain coefficient is calculated by the defect response sensitivity model, and the sensitivity is derived from the regression relationship between the defect size and the signal amplitude in the historical data, and is dynamically adjusted after being written into the control register of the sorting device.

[0096] Here is a specific example: A packaging production line performs a coordinated process of sorting and testing on the second type of chips (number H-308): first, the pneumatic probe array precisely contacts the chip BGA pins (pressure 0.3N) and loads a 2.5GHz sinusoidal wave signal (voltage 3.2V); second, the transient voltage peak of 1.8V and the current phase lag of 42° are collected to generate a frequency domain impedance response spectrum and identify the 2.3-2.5GHz frequency band anomaly; third, VMD decomposition is used to extract three IMF components, and after clustering, the abnormal frequency band start = 2.32GHz, end = 2.48GHz, and fluctuation peak = 14dB are recorded as an abnormal signal sequence; finally, KDE analysis shows that the frequency hotspots are concentrated at 2.4GHz±30MHz, and the subsequent batch scanning step size is adjusted to 6MHz and the voltage gain to 1.8 times.

[0097] Steps 601-604 achieve efficient online detection of internal defects of packaged chips through hardware coordination of contact signal loading and sorting actions, time-frequency joint analysis of impedance response spectrum, and dynamic parameter optimization. Adaptive impedance matching and noise cancellation technology ensure signal stability, variational mode decomposition and fuzzy clustering enhance the accuracy of abnormal frequency band extraction, and the frequency focusing mechanism driven by kernel density significantly improves the targeting of defect detection, providing closed-loop quality control capabilities for integrated sorting and detection for high-density packaging production lines.

[0098] In order to solve the problems of inaccurate extraction of defect characteristic frequency bands and high redundancy of abnormal signal segmentation in traditional impedance response analysis, and to further improve the targeting of defect detection and signal analysis efficiency, accurate extraction of abnormal signal sequences is achieved through frequency band focusing, adaptive filtering and intelligent merging strategies. In some embodiments, the frequency domain impedance response spectrum is subjected to bandpass filtering to extract abnormal frequency bands in which the impedance amplitude fluctuation exceeds a preset stability threshold within the frequency range, and the starting frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band are recorded as abnormal signal sequences, including: 701. Based on the frequency distribution characteristics of the frequency domain impedance response spectrum, determine a typical response frequency band covering defects in the metal interconnect layer of the packaged chip through a bandpass filter to generate a bandpass range; In step 701, the frequency distribution characteristics refer to the statistical distribution of impedance amplitude, phase and harmonic components at different frequency points in the frequency domain impedance response spectrum. The passband range refers to the filter passband interval set according to the typical response frequency band of metal interconnect layer defects (such as 2.4-2.6GHz).

[0099] In the embodiment of the present application, a frequency domain feature template library of metal interconnect layer defects is constructed based on the historical defect database, and the frequency distribution characteristics of the impedance response spectrum are decomposed by wavelet packet transform (WPT), and candidate areas with frequency band energy entropy values ​​higher than the threshold are extracted; the typical response frequency band is determined by kernel density estimation (KDE), and the frequency band boundary is corrected in combination with packaging process parameters (such as metal layer thickness and dielectric constant) to generate a passband range. The center frequency of the passband range is determined by the energy peak point, and the bandwidth is adaptively adjusted according to the spectrum expansion characteristics of the defect type (such as cracks and voids).

[0100] 702. Filter the frequency domain impedance response spectrum within the bandpass range to extract frequency bands where impedance amplitude fluctuations exceed a preset stability threshold; In step 702, the impedance amplitude fluctuation refers to the amplitude change rate of adjacent frequency points in the frequency domain impedance response spectrum, reflecting the impedance instability caused by defects in the metal layer.

[0101] In the embodiment of the present application, a zero-phase digital filter group is applied within the bandpass range to filter the signal and eliminate out-of-band noise interference. The impedance amplitude fluctuation is calculated by the standard deviation within the sliding window (window width 50MHz), and the stability threshold is dynamically calibrated by the robust statistical method (Huber regression) combined with the process tolerance range (such as ±3σ). The abnormal frequency band detection adopts an improved morphological gradient algorithm, which enhances the boundary contrast of the amplitude mutation area through the expansion-erosion operation, and combines the regional growth algorithm to aggregate adjacent abnormal points, and extract the frequency band where the impedance amplitude fluctuation exceeds the preset stability threshold.

[0102] 703. Divide the frequency band exceeding the preset stability threshold into a plurality of continuous sub-frequency bands, and record frequency distribution characteristics of the sub-frequency bands; In step 703, the frequency distribution characteristics refer to a set of parameters such as the amplitude distribution pattern, harmonic component proportion, and phase continuity of the frequency points in the abnormal frequency band.

[0103] In the embodiment of the present application, multi-resolution analysis is performed on the frequency band that exceeds the stability threshold, and the empirical wavelet transform (EWT) is used to decompose it into several sub-bands. The sub-band division is based on local maximum detection and watershed algorithm to ensure that each sub-band contains only a single energy peak. The frequency distribution feature extraction of the sub-band includes: main frequency amplitude, -3dB bandwidth, phase linearity, and feature dimensionality reduction is performed through the autoencoder (AE) for subsequent merging decisions.

[0104] 704. According to the frequency distribution characteristics, merge adjacent sub-frequency bands whose frequency interval is less than a preset minimum interval into an abnormal frequency band, and record the start frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band as an abnormal signal sequence.

[0105] In step 704, the frequency interval refers to the frequency difference between the boundaries of adjacent sub-bands, which is used to determine the physical relevance of the frequency band merging.

[0106] In the embodiment of the present application, an adjacency graph model of the sub-band is constructed, the nodes are the sub-band feature vectors, and the edge weights are calculated jointly by the frequency interval and the phase similarity. The connected component analysis (CCA) in graph theory is used to merge the sub-bands whose intervals are less than the preset minimum interval (such as 20MHz), and the merged band boundaries are optimized by spectral clustering. The fluctuation peak of the abnormal frequency band takes the maximum amplitude in the merged sub-band, and the starting frequency and the cutoff frequency are determined by the convex hull algorithm, and finally a high-confidence abnormal signal sequence is generated.

[0107] Here is a specific example: A packaging production line performs internal defect detection on chip number J-410. Firstly, the frequency domain impedance response spectrum was analyzed and it was found that the energy entropy value of 2.3-2.7GHz was significantly higher. Combined with the process parameters, the generated bandpass range was 2.35-2.65GHz; secondly, after filtering, the impedance fluctuation in the 2.4-2.5GHz band was extracted to be 8.2% (threshold 5%), and the frequency band with impedance amplitude fluctuation exceeding the preset stability threshold was extracted after morphological gradient enhancement; thirdly, it was decomposed into three sub-bands (2.40-2.44GHz, 2.46-2.51GHz, 2.55-2.60GHz) through EWT, and the amplitudes of the main frequencies were extracted to be 12dB, 15dB, and 10dB respectively, and the frequency distribution characteristics were recorded; finally, the sub-bands with an interval of <20MHz were merged (2.40-2.44GHz and 2.46-2.51GHz were merged into 2.40-2.51GHz), and the abnormal signal sequence was recorded as start = 2.40GHz, end = 2.51GHz, and peak = 15dB.

[0108] Steps 701-704 significantly improve the extraction accuracy and physical interpretability of abnormal signal sequences through dynamic bandpass range focusing, morphological gradient enhancement, and frequency band merging driven by graph theory. Wavelet packet energy entropy analysis achieves accurate locking of defect frequency bands, robust statistical calibration enhances threshold adaptability, and connected component analysis ensures process consistency of frequency band merging, providing efficient and reliable full-band signal analysis capabilities for metal layer defect detection of packaged chips.

[0109] In order to solve the problem of poor coordination between high-frequency signal loading and chip sorting action and insufficient probe contact stability in traditional sorting devices, and to further improve defect detection efficiency and signal excitation reliability, the coordination of sorting and detection hardware is achieved through adaptive probe array design, dynamic control of contact pressure, and parameter optimization driven by sorting density. In some embodiments, the conductive probe of the pneumatic sorting device establishes a contact connection with the pin of the second type of chip, and loads a high-frequency sinusoidal wave excitation signal to the pin, including: 801. Arrange a retractable conductive probe array below the vibrating screen of the pneumatic sorting device, and match the probe spacing with the standard pitch of the packaged chip pins; In step 801, the retractable conductive probe array refers to a probe group whose retractable stroke is controlled by a piezoelectric ceramic driver, and its arrangement spacing can be dynamically adjusted to adapt to the pin layout of different packaged chips. The standard pitch refers to the designed spacing between the center points of the packaged chip pins (such as 0.5mm), which is used as the reference matching parameter of the probe array.

[0110] In the embodiment of the present application, based on the pin design drawings of the packaged chip (such as BGA packaging), a genetic algorithm is used to optimize the initial spacing layout of the retractable conductive probe array to minimize the probability of misalignment between the probe and the pin. The probe telescopic stroke is controlled by the inverse piezoelectric effect of the piezoelectric ceramic driver, and the stroke resolution reaches 0.1μm. The standard pitch matching adopts a template matching algorithm, and the pin position is identified in real time by the machine vision system, and the feedback is fed back to the micro-displacement platform of the retractable conductive probe array (accuracy ±2μm) to ensure that the probe spacing is aligned with the standard pitch.

[0111] 802. When the second type of chip moves to a preset sorting station along with the vibration screen, the retractable conductive probe array is controlled to be pressed down in a vertical direction to form a contact connection with the pin surface of the second type of chip; In step 802, the preset sorting station refers to a detection area on the vibrating screen that is specially designed for the second type of chips, and its spatial coordinates are pre-calibrated by the kinematic model of the sorting device.

[0112] In the embodiment of the present application, when the second type of chip enters the preset sorting station, the chip position is monitored in real time by a laser triangulation sensor, and the movement trajectory of the chip on the vibrating screen is predicted in combination with a particle filter algorithm. The retractable conductive probe array pressure control adopts an impedance control strategy. The initial pressure speed is calculated by the relative height difference between the probe and the pin. The contact is switched to force control mode at the moment of contact, and the contact pressure (target value 0.2-0.4N) is fed back in real time through a strain gauge sensor. Finally, a contact connection is formed, and the contact stability is monitored by the sliding mean filter of the contact resistance. If the fluctuation exceeds 5%, the probe position fine-tuning is triggered.

[0113] 803. According to the contact connection, a high-frequency sinusoidal wave excitation signal is applied to the retractable conductive probe array by a high-frequency signal generator; In step 803, the high-frequency sinusoidal wave excitation signal refers to a continuous sinusoidal signal with a frequency in the range of 1-5 GHz and a waveform distortion of less than 1%, which is used to excite the impedance response of the metal interconnection layer.

[0114] In the embodiment of the present application, a direct digital frequency synthesizer (DDS) is used to generate a reference high-frequency sinusoidal wave excitation signal, and the signal amplitude is increased to an adjustable 1-10V through a power amplifier (PA). Impedance matching calibration is performed before the reference high-frequency sinusoidal wave excitation signal is loaded: the S11 parameters of the probe-pin contact point are measured based on a vector network analyzer (VNA), and the capacitance / inductance value of the matching network (such as a π-type network) is iteratively adjusted using the conjugate gradient method to make the reflection coefficient <-20dB. During the loading process of the reference high-frequency sinusoidal wave excitation signal, the nonlinear distortion of the power amplifier is compensated by the digital pre-distortion (DPD) technology to ensure the purity of the signal waveform.

[0115] 804. Dynamically adjust the probe spacing and the loading timing of the high-frequency sinusoidal wave excitation signal according to the distribution density of the second-type chips on the vibration screen.

[0116] In step 804, the distribution density refers to the number of the second type of chips per unit area on the vibrating screen, which is used to quantify the spatiotemporal distribution characteristics of the sorting load.

[0117] In the embodiment of the present application, the real-time image of the vibrating screen is collected by an industrial camera, and the YOLOv5 target detection algorithm is used to count the chip distribution density. The probe spacing adjustment is based on the dynamic calculation of the density value: the probe spacing is reduced in the high-density area (to a minimum of 90% of the standard pitch) to improve the detection coverage, and the spacing is expanded in the low-density area (to a maximum of 110% of the standard pitch) to reduce the mechanical wear of the probe. The loading timing optimization adopts the time interleaved multiple access (TDMA) strategy to dynamically adjust the loading timing of the signal loading time slice according to the chip position sequence to avoid electromagnetic crosstalk caused by multiple probes working at the same time.

[0118] Here is a specific example: A high-end packaging production line performs a coordinated sorting and testing process for the second type of chips (number K-503). First, according to the BGA pin pitch of the K-503 chip (0.4mm), the probe array spacing is adjusted to 0.396mm for matching (matching error ±1%), and the piezoelectric ceramic driver is preloaded with a telescopic stroke of 0.15mm; secondly, after the chip enters the preset station, the laser sensor positioning accuracy reaches ±5μm, the probe array is pressed down at a speed of 0.1m / s, the contact pressure is stabilized at 0.32N (fluctuation <3%), and the contact resistance is maintained at 48Ω±2Ω, forming a contact connection; thirdly, a 3.2GHz high-frequency sine wave excitation signal (voltage 4.5V) is loaded, and the waveform distortion after DPD compensation is 0.8%, and S11=-23dB is measured; finally, the current distribution density is detected to be 12 pieces / cm², the probe spacing is reduced to 0.36mm, and the loading timing of the 0.5ms time slice is dynamically adjusted according to the TDMA strategy, and the signal loading efficiency is improved by 40%.

[0119] Steps 801-804 achieve efficient coordination of high-frequency signal loading and sorting action through adaptive matching of probe array, closed-loop control of contact impedance and dynamic parameter adjustment of sorting density. Piezoelectric drive and machine vision ensure probe positioning accuracy, impedance matching and digital pre-distortion improve signal quality, and time-space diversity strategy optimizes detection throughput, providing a stable and reliable integrated hardware solution for sorting and detection for packaging production lines.

[0120] In order to solve the problem of misscreening of good products or missed detection of defects caused by the disconnection between sorting parameters and defect characteristics, and to further improve sorting accuracy and process stability, the whole process of sorting and detection is coordinated and optimized through defect feature-driven sorting parameter modeling, multi-physics field coupling simulation and dynamic closed-loop control. In some embodiments, the mesh diameter and vibration frequency parameters of the pneumatic sorting device are dynamically adjusted according to the multi-layer composite defect, including: 901. Calculate the mesh diameter of the pneumatic sorting device according to the geometric features and spatial distribution characteristics of the multi-layer composite defects; In step 901, the geometric features refer to the spatial properties of the multi-layer composite defects, such as size (such as maximum diameter), shape (such as spherical, crack-shaped) and projected area. The spatial distribution characteristics refer to the density distribution of defects in the package substrate, the depth of interlayer penetration and the position relationship with the through hole / solder ball.

[0121] In the embodiment of the present application, based on the three-dimensional point cloud data of the defect detection results, the morphological skeleton extraction algorithm is used to remove redundant noise points, and the defect principal axis length and equivalent projected area are calculated by principal component analysis (PCA). The mesh aperture of the pneumatic sorting device is calculated using a safety margin model based on the maximum inscribed circle diameter of the defect, and the mesh aperture threshold is reversely derived in combination with the adhesion parameters of the substrate material (such as the van der Waals force coefficient). The defect distribution density is completed by kernel density estimation (KDE), and the high-density area corresponds to the aperture reduction ratio (such as a 2μm decrease in aperture for every 10% increase in density).

[0122] 902. Determine a vibration frequency parameter of the pneumatic sorting device based on a depth position of the multi-layer composite defect in the packaging substrate; In step 902 , the depth position refers to the penetration level (eg, L1-L3 layers) of the defect along the stacking direction (Z-axis) of the package substrate and its absolute distance from the surface.

[0123] In the embodiment of the present application, acoustic impedance modeling is performed on the defect depth position, the acoustic impedance difference of each layer of medium is extracted by ultrasonic pulse echo signal, and the vibration energy attenuation coefficient is calculated by combining the stress and strain finite element simulation results of the defect. The vibration frequency parameter is determined by the product of the defect depth and the elastic modulus of the medium between the substrate layers, and the gradient descent algorithm is used to optimize the frequency and depth response curve. For deep defects (such as below the L3 layer), a resonant frequency offset compensation mechanism is introduced to dynamically adjust the vibration frequency parameter according to the change of the group velocity of the sound wave in the multi-layer medium.

[0124] 903. Input the mesh diameter and the vibration frequency parameters into the control unit of the pneumatic sorting device to adjust the physical parameters of the vibration screen and the vibration motor driving signal in real time; In step 903, the physical parameters refer to mechanical properties of the vibration screen, such as aperture size, inclination angle, and surface roughness. The vibration motor drive signal refers to electrical parameters such as frequency, amplitude, and phase for controlling the operation of the vibration motor.

[0125] In the embodiment of the present application, the mesh aperture and vibration frequency parameters are input into the digital twin control unit, and the model predictive control (MPC) algorithm is used to generate parameter adjustment instructions. The mesh aperture is dynamically adjusted (resolution ±1μm) by a micro-hole array driven by a stepper motor, and the vibration frequency is controlled by a direct digital frequency synthesizer (DDS) outputting a PWM signal to control the motor speed. The real-time adjustment process introduces the Lyapunov stability criterion, and the phase lag of the drive signal is corrected by the accelerometer feedback signal to ensure a smooth transition of the sorting action.

[0126] 904. When performing the sorting operation, by monitoring the consistency between the change trend of the detection result of the multi-layer composite defect and the preset defect distribution optimization target, the current values ​​of the mesh diameter and the vibration frequency parameter are locked to complete the closed-loop control process of the sorting and detection linkage.

[0127] In step 904, the defect distribution optimization target refers to the preset multi-objective constraints such as defect missed detection rate, false screening rate and sorting efficiency.

[0128] In the embodiment of the present application, during the sorting process, the changing trend of the defect detection results is monitored through online statistical process control (SPC), and the dynamic time warping (DTW) algorithm is used to align the timing curve of the actual defect distribution and the optimization target. The consistency judgment is based on multi-objective Pareto front analysis, and the conditions for locking the current parameters are: the slope of the missed detection rate is greater than 5% / h, and the fluctuation range of the false screening rate is less than ±2%. The closed-loop control process updates the parameter optimization model through the federated learning framework to ensure that the sorting strategy is adaptively adjusted with process fluctuations.

[0129] Here is a specific example: A 3D packaging production line performs sorting optimization on a batch of M-606 chips. First, the L2 layer composite defect (diameter 25μm, density 8 / cm²) is detected, and the mesh diameter is calculated to be adjusted from 150μm to 138μm; secondly, based on the defect depth of 0.8mm (corresponding to the L3 layer), the vibration frequency parameter output by the acoustic impedance model is determined to be increased from 80Hz to 92Hz; thirdly, the control unit adjusts the screen inclination to 12° and adjusts the phase synchronization error of the vibration motor drive signal to <0.1ms; finally, the monitoring miss detection rate is reduced from 1.2% to 0.7%, and the false screening rate is stabilized at 0.5%. The current parameters are locked and the optimization model is updated to complete the closed-loop control process of sorting and detection linkage.

[0130] Steps 901-904 significantly improve the accuracy and stability of the sorting process through parameter modeling driven by defect geometry and deep features, digital twin control, and multi-objective closed-loop optimization. Morphological skeleton extraction and acoustic impedance modeling ensure the physical consistency of parameter calculation, and model predictive control and federated learning frameworks achieve dynamic adaptive adjustment, providing a full-link collaborative solution of defect features-sorting parameters-quality control for high-density packaging production lines.

[0131] Figure 2 A structural diagram of a defect detection system for integrated circuit manufacturing is provided for an embodiment of the present application, such as Figure 2 As shown, the system includes: A sorting module 21 is used to sort the packaged chips into first-category chips that meet a preset physical property threshold and second-category chips that exceed the physical property threshold by using a pneumatic sorting device during the integrated circuit packaging stage based on the size deviation or surface roughness data of the packaged chips; A positioning module 22 is used to perform scanning electron microscope imaging on the surface of the second type of chip, generate a three-dimensional topological structure using machine learning driven image reconstruction technology, and locate the micron-scale particle defect area by comparing the three-dimensional topological structure with the reference type of the standard packaged chip; A detection module 23 is used to synchronously apply high-frequency electrical signal excitation during the sorting process, detect the impedance response of the internal metal layer of the second type of chip to the high-frequency electrical signal excitation, and record the abnormal signal sequence of the current fluctuation exceeding the preset frequency domain range; A determination module 24 is used to perform spatiotemporal correlation matching between the micron-sized particle defect region and the abnormal signal sequence, and when the coordinates of the micron-sized particle defect region and the phase offset of the abnormal signal sequence meet a preset coupling condition, it is determined to be a multi-layer composite defect that penetrates the surface and the interior of the chip; The adjustment module 25 is used to dynamically adjust the mesh size and vibration frequency parameters of the pneumatic sorting device according to the multi-layer composite defects.

[0132] Figure 2 The XX system can perform Figure 1 The implementation principle and technical effect of the XX method described in the embodiment shown will not be repeated. The specific way in which each module and unit performs operations in the defect detection system for integrated circuit manufacturing in the above embodiment has been described in detail in the embodiment of the method, and will not be elaborated here.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A defect detection method for integrated circuit manufacturing, characterized in that: include: In the integrated circuit packaging stage, the packaged chips are classified into a first type of chips that meet a preset physical property threshold and a second type of chips that exceed the physical property threshold by a pneumatic sorting device based on the size deviation or surface roughness data of the packaged chips; Performing scanning electron microscopy imaging on the surface of the second type of chip, generating a three-dimensional topological structure using machine learning-driven image reconstruction technology, and locating micron-scale particle defect areas by comparing the three-dimensional topological structure with a reference type of a standard packaged chip; During the sorting process, high-frequency electrical signal excitation is synchronously applied, and an abnormal signal sequence in which the current fluctuation exceeds a preset frequency domain range is recorded by detecting the impedance response of the internal metal layer of the second type chip to the high-frequency electrical signal excitation; Performing temporal and spatial correlation matching between the micron-sized particle defect region and the abnormal signal sequence, and determining that the defect is a multi-layer composite defect that penetrates the chip surface and the interior when the coordinates of the micron-sized particle defect region and the phase offset of the abnormal signal sequence meet a preset coupling condition; The mesh size and vibration frequency parameters of the pneumatic sorting device are dynamically adjusted according to the multi-layer composite defects.

2. The method according to claim 1, characterized in that When the coordinates of the micron-scale particle defect area and the phase offset of the abnormal signal sequence meet the preset coupling condition, it is determined to be a multi-layer composite defect that penetrates the surface and the interior of the chip, including: Based on the surface physical coordinate system of the micron-sized particle defect region and the phase offset of the abnormal signal sequence, a three-dimensional spatial mapping relationship with the center of the package chip solder ball array as the origin is established; According to the three-dimensional spatial mapping relationship, the boundary coordinates of the micron-scale particle defect area are extended in three-dimensional space along the stacking direction of the package substrate to generate a metal interconnect layer defect diffusion path corresponding to the phase offset; When the continuous extension distance of the metal interconnect layer defect diffusion path and the cumulative change amount of the phase offset amount meet a preset cross-layer correlation threshold, determining that the micron-scale particle defect area forms a penetrating correlation with the internal metal layer defect; A correlation analysis is performed on the extension direction of the metal interconnect layer defect diffusion path and the frequency distribution of the phase offset. If the extension direction is consistent with the delay gradient direction of the energy concentration frequency band in the frequency distribution, environmental noise interference is eliminated and it is determined to be a multi-layer composite defect.

3. The method according to claim 2, characterized in that The step of performing a three-dimensional spatial extension simulation on the boundary coordinates of the micron-scale particle defect region along the stacking direction of the package substrate according to the three-dimensional spatial mapping relationship to generate a metal interconnect layer defect diffusion path corresponding to the phase offset includes: According to the three-dimensional spatial mapping relationship, extracting the projection starting point of the boundary coordinates of the micron-scale particle defect area in the packaging substrate stacking direction; Based on the propagation attenuation characteristics of the phase offset in the metal interconnect layer, calculating the curvature radius of the projection path of the boundary coordinate along the stacking direction; Extending the boundary coordinates layer by layer along the projection path to generate an initial defect diffusion path corresponding to the phase offset; A spatial superposition analysis is performed on the initial defect diffusion path and the distribution of through holes between layers of the packaging substrate, and a metal interconnect layer defect diffusion path corresponding to the phase offset is generated through a distance distribution feature between the initial defect diffusion path and the through hole edge.

4. The method according to claim 1, characterized in that: The method of using machine learning driven image reconstruction technology to generate a three-dimensional topological structure and locating a micron-scale particle defect area by comparing the three-dimensional topological structure with a reference type of a standard packaged chip includes: Based on the surface scanning electron microscope image data of the second type of chip, an initial three-dimensional surface model is constructed by multi-scale feature fusion, and the image reconstruction technology driven by machine learning is used to iteratively optimize the spatial continuity of the initial three-dimensional surface model to generate a three-dimensional topological structure consistent with the microscopic morphology of the packaged chip surface; The three-dimensional topological structure is divided into a continuous slice sequence perpendicular to the surface direction according to a preset layer thickness, and the continuous slice sequence is overlapped and compared layer by layer with the corresponding layer slices of a reference type of a standard packaged chip; Based on the layer-by-layer overlapping comparison results, extract the difference area with local curvature mutation in the three-dimensional topological structure, and map the geometric center coordinates of the difference area to the physical space coordinate system of the microscopic morphology of the packaged chip surface; According to the curvature mutation direction of the difference area and the topological connection relationship between the adjacent areas, the target area that meets the isolated distribution and the curvature gradient direction deviates from the surface normal direction by more than a preset angle is screened out and marked as a micron-scale particle defect area.

5. The method according to claim 4, characterized in that According to the curvature mutation direction of the difference area and the topological connection relationship between the adjacent areas, the target area that satisfies the isolated distribution and the curvature gradient direction deviates from the surface normal direction by more than a preset angle is screened out and marked as a micron-level particle defect area, including: Extracting the curvature mutation direction of the difference area in the microscopic morphology of the packaged chip surface based on the geometric center coordinates of the difference area; According to the topological connection relationship between the difference region and the adjacent regions, the isolation distribution characteristics of the difference region are quantitatively calculated by the number of interruptions in the continuity of the curvature gradient between the difference region and the adjacent regions; Comparing the angle of the sudden change of curvature with the direction of the surface normal, and screening out candidate areas where the curvature gradient direction deviates from the surface normal direction by more than a preset angle; In combination with the isolation distribution characteristics and the angle comparison result, a set of regions satisfying the isolation distribution in the candidate regions is marked as a micron-scale particle defect region.

6. The method according to claim 1, characterized in that The step of synchronously applying high-frequency electrical signal excitation during the sorting process, detecting the impedance response of the internal metal layer of the second type chip to the high-frequency electrical signal excitation, and recording an abnormal signal sequence in which the current fluctuation exceeds a preset frequency domain range comprises: Establishing a contact connection between the conductive probe of the pneumatic sorting device and the pin of the second type chip, and applying a high-frequency sinusoidal wave excitation signal to the pin; During the loading process of the high-frequency sinusoidal wave excitation signal, synchronously collecting the transient voltage signal and the loop current signal between the pin and the ground terminal, and converting the phase difference between the transient voltage signal and the loop current signal into a frequency domain impedance response spectrum; Performing bandpass filtering on the frequency domain impedance response spectrum, extracting abnormal frequency bands within the frequency range where the impedance amplitude fluctuation exceeds a preset stability threshold, and recording the starting frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band as an abnormal signal sequence; According to the starting frequency distribution density of the abnormal signal sequence, the frequency scanning step length and the voltage amplitude gain coefficient of the high-frequency sinusoidal wave excitation signal in the subsequent sorting batches are dynamically adjusted.

7. The method according to claim 6, characterized in that The bandpass filtering is performed on the frequency domain impedance response spectrum to extract the abnormal frequency band in which the impedance amplitude fluctuation exceeds the preset stability threshold within the frequency range, and the starting frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band are recorded as an abnormal signal sequence, including: Based on the frequency distribution characteristics of the frequency domain impedance response spectrum, a typical response frequency band covering defects in the metal interconnect layer of the packaged chip is determined by a bandpass filter to generate a bandpass range; Performing filtering processing on the frequency domain impedance response spectrum within the bandpass range to extract frequency bands where impedance amplitude fluctuations exceed a preset stability threshold; Dividing the frequency band exceeding a preset stability threshold into a plurality of continuous sub-frequency bands, and recording frequency distribution characteristics of the sub-frequency bands; According to the frequency distribution characteristics, adjacent sub-frequency bands with a frequency interval less than a preset minimum interval are merged into abnormal frequency bands, and the starting frequency, cutoff frequency and fluctuation peak value of the abnormal frequency band are recorded as an abnormal signal sequence.

8. The method according to claim 6, characterized in that The method of establishing a contact connection between the conductive probe of the pneumatic sorting device and the pin of the second type chip and applying a high-frequency sinusoidal wave excitation signal to the pin includes: A retractable conductive probe array is arranged below the vibrating screen of the pneumatic sorting device, and the probe spacing is matched with the standard pitch of the package chip pins; When the second type of chip moves to a preset sorting station along with the vibration screen, the retractable conductive probe array is controlled to be pressed down in a vertical direction to form a contact connection with the pin surface of the second type of chip; According to the contact connection, a high-frequency sinusoidal wave excitation signal is applied to the retractable conductive probe array by a high-frequency signal generator; According to the distribution density of the second type of chips on the vibration screen, the probe spacing and the loading timing of the high-frequency sinusoidal wave excitation signal are dynamically adjusted.

9. The method according to claim 1, characterized in that: The method of dynamically adjusting the mesh size and vibration frequency parameters of the pneumatic sorting device according to the multi-layer composite defect includes: Calculating the mesh diameter of the pneumatic sorting device according to the geometric features and spatial distribution characteristics of the multi-layer composite defects; Determining a vibration frequency parameter of the pneumatic sorting device based on a depth position of the multi-layer composite defect in the packaging substrate; Inputting the mesh diameter and the vibration frequency parameters into the control unit of the pneumatic sorting device to adjust the physical parameters of the vibration screen and the vibration motor driving signal in real time; When performing the sorting operation, by monitoring the consistency between the change trend of the detection results of the multi-layer composite defects and the preset defect distribution optimization target, the current values ​​of the mesh diameter and the vibration frequency parameters are locked to complete the closed-loop control process of the linkage between sorting and detection.

10. A defect detection system for integrated circuit manufacturing, characterized in that: include: A sorting module is used to classify the packaged chips into first-category chips that meet a preset physical property threshold and second-category chips that exceed the physical property threshold through a pneumatic sorting device during the integrated circuit packaging stage based on the size deviation or surface roughness data of the packaged chips; A positioning module is used to perform scanning electron microscope imaging on the surface of the second type of chip, generate a three-dimensional topological structure using machine learning driven image reconstruction technology, and locate the micron-scale particle defect area by comparing the three-dimensional topological structure with the reference type of the standard packaged chip; A detection module, used for synchronously applying high-frequency electrical signal excitation during the sorting process, detecting the impedance response of the internal metal layer of the second type of chip to the high-frequency electrical signal excitation, and recording an abnormal signal sequence in which the current fluctuation exceeds a preset frequency domain range; A determination module, used for performing temporal and spatial correlation matching between the micron-sized particle defect region and the abnormal signal sequence, and determining that the defect is a multi-layer composite defect that penetrates the chip surface and the interior when the coordinates of the micron-sized particle defect region and the phase offset of the abnormal signal sequence meet a preset coupling condition; The adjustment module is used to dynamically adjust the mesh diameter and vibration frequency parameters of the pneumatic sorting device according to the multi-layer composite defects.

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