Mask plate assembly and chip exposure method
By setting dense detection marks in the mask template component, the position parameters and heating conditions of the graphics area are obtained, and the problem of engraving errors during the exposure of multi-layer masks is solved, and more accurate chip exposure is achieved.
Patent Information
- Application Number
- CN202311513630.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-13
- Publication Date
- 2025-05-13
AI Technical Summary
During the exposure process of multi-layer masks, different areas of the mask assembly are deformed due to lens thermal effects, and it is impossible to accurately collect the heating conditions of a single graphics area, resulting in large incision errors on the chip.
A mask assembly is designed that includes multiple interval-set mask sets and detection marks. The detection mark is arranged on the non-graphic area, including a first detection mark and a second detection mark, through which the position parameters and heating conditions of the graphics area are obtained to adjust the parameters of the lithography machine to compensate for the engraving error.
By setting dense detection marks in the mask template assembly, the position data of each graphic area can be effectively obtained, the overturn error can be reduced, and the accuracy of chip exposure can be improved.
Smart Images
Figure CN119987123A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of photolithography, and in particular to a mask assembly and a chip exposure method. Background Art
[0002] Since lens heating or reticle heating (lens thermal effect or mask thermal effect) will occur when the mask is exposed, different areas of the mask component will be deformed. In the relevant technology of MLR (Multi-Layer Reticle), the PARIS mark (Parallel Inegrated lens interferometer at the scanner mask) is only distributed on the periphery of the entire mask. When exposing a single graphic area in the multi-layer mask, it is impossible to accurately collect the actual heating condition of a single graphic area. Therefore, the overlay error of MLR cannot be compensated or compensated inadequately, which will eventually lead to a large overlay error on the chip. Summary of the invention
[0003] The purpose of the present disclosure is to provide a mask assembly and a chip exposure method, which collects position parameters between graphic areas to obtain actual heating conditions to compensate for chip overlay errors.
[0004] In order to achieve the above object, the present disclosure provides a mask assembly, comprising:
[0005] a plurality of mask groups arranged at intervals, the mask groups comprising a graphic area and a non-graphic area surrounding the graphic area; and
[0006] A detection mark, wherein the detection mark is arranged on the non-graphic area, the detection mark includes a first detection mark and a second detection mark, a plurality of the first detection marks are arranged on both sides of the width direction of the graphic area and are spaced apart along the length direction of the graphic area, and the second detection mark is arranged on both sides of the length direction of the graphic area and are spaced apart along the width direction of the graphic area, wherein the interval between adjacent first detection marks is smaller than the interval between adjacent second detection marks.
[0007] Optionally, a plurality of the mask groups are spaced apart along the length direction of the mask template assembly, and the length direction of the graphic area is the same as the width direction of the mask template assembly, and the length direction of the mask template assembly is used to correspond to the moving direction of the lithography machine assembly.
[0008] Optionally, the first detection marks on both sides of the graphic area correspond one to one, and the second detection marks on both sides of the graphic area correspond one to one.
[0009] Optionally, the line between two corresponding first detection marks is parallel to the width direction of the mask assembly or the length direction of the mask assembly, and the line between two corresponding second detection marks is perpendicular to the line between two corresponding first detection marks.
[0010] Optionally, the distances between the plurality of first detection marks in the graphic area and the graphic area are the same, and the distances between the plurality of second detection marks in the graphic area and the graphic area are the same.
[0011] According to another aspect of the present disclosure, a method for exposing a chip is provided, wherein the method uses a photolithography machine and the above-mentioned mask assembly, and the method comprises:
[0012] Placing the mask assembly and the test piece in the photolithography machine, wherein the test piece corresponds to one of the mask sets;
[0013] Controlling the photolithography machine to expose the test piece through the mask assembly, and recording the pattern on the pattern area and the detection mark on the non-pattern area onto the test piece;
[0014] Acquiring information of a detection mark of the test piece;
[0015] Adjusting the parameters of the lithography machine by using the information of the acquired detection mark; and
[0016] The test piece is replaced with the chip, and the photolithography machine is controlled to expose the chip through the mask assembly.
[0017] Optionally, the lithography machine comprises an exposure assembly, a first workbench and a second workbench which are sequentially arranged from top to bottom. In the step of placing the mask assembly and the test piece in the lithography machine, and the test piece corresponds to one of the mask sets, the exposure method comprises:
[0018] placing the mask assembly on the first workbench;
[0019] placing the test piece in the second workbench and below one of the mask sets of the mask plate assembly; and
[0020] Cover the area where the remaining mask groups on the mask plate assembly are located.
[0021] Optionally, in the step of adjusting the parameters of the lithography machine by using the acquired detection mark information, the parameters are parameters of at least one of the first workbench, the second workbench and the exposure component.
[0022] Optionally, in the step of adjusting the parameters of the lithography machine by using the acquired detection mark information, the parameters are position parameters and / or angle parameters of at least one of the first workbench, the second workbench and the exposure assembly.
[0023] Optionally, in the step of acquiring information of the detection mark of the test piece, the acquired information includes coordinate information corresponding to the detection mark of the test piece.
[0024] Through the above technical solution, detection marks are placed around each graphic area in the mask template assembly, which can effectively detect the position data of each graphic area accordingly. Compared with the lack of marks between adjacent graphic areas, the overlay error can be reduced. Since the longer side of the graphic area is more likely to be deformed by heat, the detection marks are set more densely, which can make the compensation for the overlay error more accurate.
[0025] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0027] Figure 1 is a schematic diagram of a mask assembly according to an embodiment of the present disclosure.
[0028] Figure 2 is a schematic diagram of a single mask set in a mask plate assembly according to an embodiment of the present disclosure.
[0029] Figure 3 The figure is a flow chart of a chip exposure method according to an embodiment of the present disclosure.
[0030] Figure 4 is a flow chart of a chip exposure method according to another embodiment of the present disclosure.
[0031] Description of Reference Numerals
[0032] 1-graphic area; 2-non-graphic area; 3-first detection mark; 4-second detection mark. DETAILED DESCRIPTION
[0033] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0034] In the present disclosure, unless otherwise stated, directional words such as "upper" and "lower" are defined for the overall arrangement of the device, and "inner" and "outer" are defined for the outline of the corresponding components. The use of terms such as "first" and "second" is intended to distinguish different components and does not have order and importance. In addition, in the following description, when referring to the drawings, unless otherwise explained, the same reference numerals in different drawings represent the same or similar elements.
[0035] According to one embodiment of the present disclosure, Figure 1 and Figure 2 As shown, a mask assembly is provided, comprising a plurality of mask groups and detection marks arranged at intervals, wherein the mask group comprises a graphic area 1 and a non-graphic area 2 surrounding the graphic area 1. The detection mark can be arranged on the non-graphic area 2, and the detection mark comprises a first detection mark 3 and a second detection mark 4, wherein the plurality of first detection marks 3 are arranged on both sides of the width direction of the graphic area 1 and are arranged at intervals along the length direction of the graphic area, and the second detection mark 4 is arranged on both sides of the length direction of the graphic area 1 and is arranged at intervals along the width direction of the graphic area, wherein the interval between adjacent first detection marks 3 is smaller than the interval between adjacent second detection marks 4. It should be noted that the non-graphic area 2 can be made of chrome or chrome alloy, and the detection mark can be engraved on the non-graphic area 2. The detection mark can be any one of a PARIS mark (Parallel Inegrated lens interferometer at the scanner mask) and an RSC mark (Reticle sharp correction mark mask shape correction mark), or the two detection marks can be combined into one detection mark to reduce the occupied area of the non-graphic area 2, which is not limited in the present disclosure.
[0036] Through the above technical solution, detection marks are arranged around each graphic area 1 in the mask template assembly, so that the position data of each graphic area 1 can be effectively detected. Compared with the lack of marks between adjacent graphic areas 1, the overlay error can be reduced. Since the longer side of the graphic area 1 is more likely to be deformed by heat, the detection marks are set more densely, which can make the compensation for the overlay error more accurate.
[0037] Furthermore, if Figure 1 As shown, multiple mask groups are arranged at intervals along the length direction of the mask assembly to reduce the problem of thermal deformation of the mask assembly. The length direction of the graphic area 1 is the same as the width direction of the mask assembly, and the length direction of the mask assembly is used to correspond to the moving direction of the lithography machine assembly.
[0038] In addition, for the setting of detection mark, such as Figure 1 As shown, the first detection marks 3 on both sides of the graphic area 1 can correspond one to one, and the second detection marks 4 on both sides of the graphic area 1 can also correspond one to one. To enhance the detection effect. The connection line between the two corresponding first detection marks 3 can be parallel to the width direction of the mask template assembly or the length direction of the mask template assembly, and the connection line between the two corresponding second detection marks 4 is perpendicular to the connection line between the two corresponding first detection marks 3. That is, when the connection line between the two first detection marks 3 is parallel to the width direction of the mask template assembly, the connection line between the two corresponding second detection marks 4 can be parallel to the length direction of the mask template assembly. When the connection line between the two first detection marks 3 is parallel to the length direction of the mask template assembly, the connection line between the two corresponding second detection marks 4 can be parallel to the width direction of the mask template assembly.
[0039] According to one embodiment of the present disclosure, the distances between multiple first detection marks 3 in the graphic area 1 and the graphic area 1 can be the same, and the distances between multiple second detection marks 4 in the graphic area 1 and the graphic area 1 can also be the same, so as to reduce the error caused by unequal distances between the detection marks.
[0040] In the mask template assembly, the interval between the two graphic areas 1 must be no less than 1.5mm to prevent light leakage from the exposure machine in the subsequent photolithography process. One or a combination of the mask type and grade of the graphic area 1 can be the same, and the specific mask type and mask grade can include mask type (mask template type), pellicle type (mask protection film type), mask grade (mask template grade), scanner type (scanning device type) and mask tone (mask template data writing category), etc. The mask template type can be PSM (Phase shift mask phase shift mask) or Binary (bipolar mask). The mask protection film type can be one of ArF (193 wavelength deep ultraviolet light photoresist), KrF (248 wavelength deep ultraviolet light photoresist) and I-line (365 wavelength photoresist). If the graphic areas 1 with different mask template grades need to be merged into the same mask template assembly, the graphic area 1 with low mask template specifications needs to follow the graphic area 1 with high mask template specifications.
[0041] According to another aspect of the present disclosure, Figure 3As shown, a chip exposure method can also be provided. The exposure method can use a photolithography machine and the above-mentioned mask assembly. The exposure method can include step 301, placing the mask assembly and the test piece in the photolithography machine, and the test piece can correspond to one of the mask sets. After the test piece corresponds to the mask set, step 302 can be performed to control the photolithography machine to expose the test piece through the mask assembly, and burn the graphics on the graphic area and the detection mark on the non-graphic area onto the test piece. After the exposure of the test piece is completed, step 303 is performed to obtain the information of the detection mark of the test piece. Here, the acquired information may include at least one of the coordinate information, angle information and temperature information corresponding to the detection mark of the test piece, and the present disclosure does not limit this. The information exposed on the test piece can be collected, and the heat deformation of the corresponding mask set during the exposure process can be obtained. According to the acquired information, step 304 can be performed to adjust the parameters of the photolithography machine through the acquired detection mark information to compensate for the overlay error caused by the heat deformation of the corresponding mask set. After the parameters of the lithography machine are adjusted, step 305 is executed to replace the test piece with a chip, and the lithography machine is controlled to expose the chip through the mask assembly. In this way, after adjusting the parameters of the lithography machine according to the detection mark on the exposed test piece, the formal chip is exposed, which can compensate for the overlay error caused by the thermal deformation of the mask assembly and improve the exposure accuracy of the chip.
[0042] Furthermore, the lithography machine may include an exposure assembly, a first workbench and a second workbench arranged in sequence from top to bottom, such as Figure 4 As shown, in the step of placing the mask assembly and the test piece in the lithography machine, and the test piece corresponds to one of the mask groups, the exposure method further includes 401, placing the mask assembly in the first workbench, and then performing step 402, placing the test piece in the second workbench, the second workbench is located below the first workbench, so that the test piece is located below one of the mask groups of the mask assembly. After the mask assembly and the test piece are installed, step 403 is performed to block the area where the remaining mask groups are located on the mask assembly to prevent light leakage in the remaining areas and affect the exposure.
[0043] Furthermore, in the step of adjusting the parameters of the lithography machine by obtaining the detection mark information, the parameters may be parameters of at least one of the first workbench, the second workbench and the exposure assembly. That is, the information of the detection mark on the test piece may be obtained to correct at least one of the first workbench, the second workbench and the exposure assembly, wherein the parameter may be at least one of the position parameter and the angle parameter, that is, when the information of the detection mark on the test piece is obtained, the position and angle of the first workbench, the position and angle of the second workbench and the position and angle of the exposure assembly may be compared with the target parameters to adjust any one or more of them, thereby compensating for the overlay error caused by the thermal deformation of the mask assembly during the exposure process, and improving the accuracy of the chip.
[0044] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0045] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.
[0046] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. A mask assembly, characterized in that: include: A plurality of mask groups arranged at intervals, wherein the mask groups include a graphic area and a non-graphic area surrounding the graphic area; and A detection mark, wherein the detection mark is arranged on the non-graphic area, the detection mark includes a first detection mark and a second detection mark, a plurality of the first detection marks are arranged on both sides of the width direction of the graphic area and are spaced apart along the length direction of the graphic area, and the second detection mark is arranged on both sides of the length direction of the graphic area and are spaced apart along the width direction of the graphic area, wherein the interval between adjacent first detection marks is smaller than the interval between adjacent second detection marks.
2. The mask assembly according to claim 1, characterized in that: The plurality of mask groups are spaced apart along the length direction of the mask assembly, and the length direction of the graphic area is the same as the width direction of the mask assembly. The length direction of the mask assembly is used to correspond to the moving direction of the lithography machine assembly.
3. The mask assembly according to claim 1, characterized in that: The first detection marks on both sides of the graphic area correspond one to one, and the second detection marks on both sides of the graphic area correspond one to one.
4. The mask assembly according to claim 3, characterized in that: The connection line between two corresponding first detection marks is parallel to the width direction of the mask assembly or the length direction of the mask assembly, and the connection line between two corresponding second detection marks is perpendicular to the connection line between two corresponding first detection marks.
5. The mask assembly according to claim 1, characterized in that: The distances between the plurality of first detection marks in the graphic area and the graphic area are the same, and the distances between the plurality of second detection marks in the graphic area and the graphic area are the same.
6. A chip exposure method, characterized in that: The exposure method uses a photolithography machine and a mask assembly according to any one of claims 1 to 5, and the exposure method comprises: Placing the mask assembly and the test piece in the photolithography machine, wherein the test piece corresponds to one of the mask sets; Controlling the photolithography machine to expose the test piece through the mask assembly, and recording the pattern on the pattern area and the detection mark on the non-pattern area onto the test piece; Acquiring information of a detection mark of the test piece; Adjusting the parameters of the lithography machine by using the information of the acquired detection mark; and The test piece is replaced with the chip, and the photolithography machine is controlled to expose the chip through the mask assembly.
7. The chip exposure method according to claim 6, characterized in that: The photolithography machine comprises an exposure assembly, a first workbench and a second workbench which are sequentially arranged from top to bottom. In the step of placing the mask assembly and the test piece in the photolithography machine and the test piece corresponding to one of the mask sets, the exposure method comprises: placing the mask assembly on the first workbench; placing the test piece in the second workbench and below one of the mask sets of the mask plate assembly; and Cover the area where the remaining mask groups on the mask plate assembly are located.
8. The chip exposure method according to claim 7, characterized in that: In the step of adjusting the parameters of the lithography machine by using the acquired detection mark information, the parameters are parameters of at least one of the first workbench, the second workbench and the exposure component.
9. The chip exposure method according to claim 8, characterized in that: In the step of adjusting the parameters of the lithography machine by using the acquired detection mark information, the parameters are position parameters and / or angle parameters of at least one of the first workbench, the second workbench and the exposure assembly.
10. The chip exposure method according to claim 6, characterized in that: In the step of acquiring information of the detection mark of the test piece, the acquired information includes coordinate information corresponding to the detection mark of the test piece.