Cold reset method and system, electronic equipment and storage medium

Abstract

The invention provides a cold reset method and system, electronic equipment and a storage medium, and relates to the technical field of computers. The cold reset method comprises the steps that any processor on a first control panel triggers cold reset, and a target processor on the first control panel obtains reset information of the cold reset; the first control panel is a board card for controlling all tasks of the system, and the target processor is the same as or different from the processor triggering cold reset; the target processor sends the reset information to a reset processor on the second control panel; the second control board is a board card for executing an image processing task; the reset processor resets a retimer on the second control panel based on the reset information, and the retimer is connected with a graphics processor on the second control panel. Therefore, it can be guaranteed that the retimer is reset in time when the system carries out cold reset, and therefore it is guaranteed that the retimer reloads the graphics processor connected with the retimer, the graphics processor is prevented from being lost, and normal use of other devices is not affected.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a cold reset method, system, electronic device and storage medium. Background Art

[0002] The speed supported by the high-speed Peripheral Component Interconnect Express (PCIe) standard is getting higher and higher. For the sake of signal quality, the length limit of PCIe signals is also getting higher and higher. In order to extend the length of PCIe signal routing and ensure signal quality, a retimer chip is added to the PCIe link. The retimer chip is a graphics processor extender or retimer, which can enhance the transmission quality of PCIe signals in the PCIe link.

[0003] When a server that uses PCIe for communication between internal components performs a cold reset, the main power on the system will not be cut off, but the PCIe reference clock signal (PCIe RECLK) issued by the corresponding processing unit will be interrupted for a certain period of time, causing the back-end connected HGX platform with a retimer to lose the graphics processing unit (GPU). The HGX platform is a GPU accelerated computing framework.

[0004] Therefore, a solution to the problem of GPU loss caused by retimer exception during cold reset is crucial. Summary of the invention

[0005] The present disclosure provides a cold reset method, system, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0006] According to a first aspect of the present disclosure, a cold reset method is provided, including: any processor on a first control board triggers a cold reset, and a target processor on the first control board obtains reset information of the cold reset; the first control board is a board for controlling all tasks of the system, and the target processor is the same as or different from the processor that triggers the cold reset; the target processor sends the reset information to a reset processor on a second control board; the second control board is a board for performing image processing tasks; the reset processor resets a retimer on the second control board based on the reset information, and the retimer is connected to a graphics processor on the second control board.

[0007] In one possible implementation manner, any processor on the first control board triggers a cold reset, comprising: any processor on the first control board triggers a cold reset, and sends the reset information of the cold reset to a first signal controller on the first control board; the first signal controller stores the reset information in a register in the first signal controller, generates a prompt signal, and sends the prompt signal to the target processor.

[0008] In one possible implementation manner, the target processor on the first control board obtains the reset information of the cold reset, including: the target processor reads the reset information in the register through an internal integrated circuit bus in response to the prompt signal.

[0009] In one possible implementation, a cold reset method further includes: in response to the target processor having read the reset information, the first signal controller clears the reset information from the register.

[0010] In one possible implementation, the processor that triggers the cold reset is a first processor, which is different from the target processor, and sending the reset information of the cold reset to the first signal controller on the first control board includes: the first processor sending the reset information of the cold reset to the first signal controller through a general input and output interface.

[0011] In one possible implementation, the processor that triggers the cold reset is a second processor, the second processor is the same as the target processor, and the sending of the reset information of the cold reset to the first signal controller on the first control board includes: the second processor sending the reset information of the cold reset to the first signal controller via a hardware reset signal.

[0012] In one possible implementation manner, the target processor sends the reset information to the reset processor on the second control board, including: the target processor sends the reset information to the reset processor on the second control board via a universal serial bus.

[0013] In one possible implementation manner, the reset processor resets the retimer on the second control board based on the reset information, including: the reset processor pulls down the enable signal of the retimer to a first level in response to the reset information, and pulls up the enable signal to a second level after a first target time to complete the resetting of the retimer; the first level is less than the second level.

[0014] In one possible implementation, after the target processor responds to the prompt signal and reads the reset information in the register through the internal integrated circuit bus, the method further includes: in response to the target processor being unable to read the reset information in the register, the first signal controller sends the reset information to a second signal controller on a third control board; the third control board is a board for signal exchange; and the second signal controller resets the second control board based on the reset information.

[0015] In one possible implementation manner, the second signal controller resets the second control board based on the reset information, including: the second signal controller pulls down the power enable signal of the second control board to a third level in response to the reset information, and pulls up the power enable signal to a fourth level after a second target time to complete the resetting of the second control board; the third level is less than the fourth level.

[0016] In one possible implementation, after any processor on the first control board triggers a cold reset, the method further includes: in response to the target processor being unable to obtain reset information for the cold reset, the target processor generating a warning message and displaying the warning message; the warning message is used to indicate that the cold reset is incomplete.

[0017] According to a second aspect of the present disclosure, a cold reset system is provided, comprising: a first control board, the first control board is a board for controlling all tasks of the system, and comprises at least two processors; any one of the at least two processors is used to trigger a cold reset, a target processor of the at least two processors is used to obtain reset information of the cold reset, and send the reset information to a reset processor on a second control board, the target processor is the same as or different from the processor that triggers the cold reset; a second control board, the second control board is a board for performing image processing tasks, and comprises a reset processor, a retimer and a graphics processor, the retimer is connected to the graphics processor on the second control board; the reset processor is used to reset the retimer on the second control board based on the reset information.

[0018] In one embodiment, the first control board also includes a first signal controller; any one of the at least two processors is used to trigger a cold reset, and send the reset information of the cold reset to the first signal controller on the first control board; the first signal controller is used to store the reset information in a register in the first signal controller, and generate a prompt signal, and send the prompt signal to the target processor.

[0019] In one possible implementation manner, the target processor is further configured to: in response to the prompt signal, read the reset information from the register via an internal integrated circuit bus.

[0020] In one possible implementation manner, the first signal controller is further configured to: in response to the target processor having read the reset information, clear the reset information from the register.

[0021] In one possible implementation manner, the at least two processors include a first processor, and the first processor is used to send the reset information of the cold reset to the first signal controller through a general purpose input and output interface.

[0022] In one possible implementation manner, the at least two processors include a second processor, and the second processor is used to send the reset information of the cold reset to the first signal controller through a hardware reset signal.

[0023] In one possible implementation manner, the target processor is further configured to: send the reset information to a reset processor on the second control board via a universal serial bus.

[0024] According to a third aspect of the present disclosure, an electronic device is provided, comprising the cold reset system described in the present disclosure, wherein the cold reset system can execute the cold reset method described in the present disclosure.

[0025] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, where the computer instructions are used to cause a computer to execute the method of the present disclosure.

[0026] The present invention discloses a cold reset method, system, electronic device and storage medium. If any processor on the first control board triggers a cold reset, the target processor on the first control board obtains the reset information of the cold reset, and the target processor is the same as or different from the processor that triggers the cold reset. Then the target processor sends the reset information to the reset processor on the second control board. The reset processor resets the retimer on the second control board based on the reset information. The retimer is connected to the graphics processor on the second control board. Thus, after the cold reset occurs on the first control board, the target processor on the first control board obtains the reset information of the cold reset, and directly sends the reset information to the reset processor on the second control board. The reset processor resets the retimer on the second control board alone, thereby ensuring that the retimer reloads the graphics processor connected to it, avoiding the loss of the graphics processor, and does not affect the normal use of other devices.

[0027] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0029] Figure 1 A schematic diagram showing a cold reset method according to an embodiment of the present disclosure Figure 1 ; Figure 2 A schematic diagram showing a cold reset method according to an embodiment of the present disclosure Figure 2 ; Figure 3 A schematic diagram showing a cold reset method according to an embodiment of the present disclosure Figure 3 ; Figure 4 A schematic diagram of the structure of a cold reset system in the prior art is shown; Figure 5 The structure of a cold reset system according to an embodiment of the present disclosure is shown. Figure 1 ; Figure 6 The structure of a cold reset system according to an embodiment of the present disclosure is shown. Figure 2 ; Figure 7 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0030] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0031] The speed supported by PCIe is getting higher and higher. For the sake of signal quality, the length limit of PCIe signals is also getting higher and higher. In order to extend the length of PCIe signal routing and ensure signal quality, a retimer chip will be added to the PCIe link. In practical applications, the retimer chip is used to balance and enhance the transmitted signal. For example, the transmission distance of PCIe5.0 signal is relatively long. The use of retimer chips can make the transmission distance of PCIe5.0 signal longer to ensure the quality of PCIe5.0 signal. When the length of the PCIe link exceeds the length required by the PCIe specification, the role of the retimer is indispensable.

[0032] All manufacturers' retimer chip designs follow the retimer-supplemental-features specification, which defines the signals that must be used by the retimer chip, and a small number of additional signals can be designed by the manufacturer. In the actual design of the retimer chip, it is possible to design compatibility between chips from different manufacturers.

[0033] For some retimer chips, during various verification or testing processes, if a clock interruption (CLK interruption) occurs, the reset signal of the retimer chip needs to be reset once to make the retimer work normally, otherwise, the retimer chip cannot link the PCIe signal. Specifically, when a server that uses PCIe as a communication between internal components performs a cold reset, the main power on the system will not be cut off, but the PCIe RECLK signal sent by the corresponding processing unit will be interrupted for a certain period of time, causing the HGX platform with the retimer chip connected to the back end to lose the GPU, where the corresponding processing unit can be a central processing unit (CPU, Central Processing Unit), and the HGX platform is a GPU accelerated computing framework.

[0034] When a clock interrupt occurs on the retimer chip, the chip must be reset before normal operation can resume. However, since the delta-next of the HGX architecture is often a finished system of a GPU manufacturer, no external signal is reserved. Therefore, the chip reset signal of the retimer cannot be controlled. Among them, delta-next is a high-performance computing platform that provides users with excellent computing performance and flexible deployment options through powerful GPU configuration and optimized interconnection technology.

[0035] The following methods are generally used to solve the problem of GPU loss caused by retimer exception during cold reset: Figure 4 The schematic diagram of the structure of the cold reset system in the prior art is shown as follows: Figure 4 As shown in the figure, the cold reset system includes a motherboard (MB), a switch board and an HGX platform. The motherboard includes a CPU, a baseboard management controller (BMC) and a complex programmable logic device (CPLD), namely, MB CPLD; the switch board also includes a CPLD. To distinguish it from the CPLD on the motherboard, the CPLD on the switch board can be called a SW CPLD; the HGX platform includes a field programmable gate array (FPGA), a retimer and a GPU.

[0036] When a cold reset occurs on the motherboard, the SW CPLD on the Switch board can be informed through the General Purpose Input / Output (GPIO) interface. After receiving the reset signal, the SW CPLD pulls the HGX base power enable signal (BASE_PWR_EN signal) low and then high, so that the HGX can be powered off and then powered on as a whole. At the same time, the retimer is also powered off and then powered on, so that the retimer reloads the firmware.

[0037] like Figure 4 As shown, the process of resetting HGX is as follows: 1. There are two situations in which the system cold reset occurs. One is triggered by the Basic Input / Output System (BIOS), and the other is triggered by the BMC. When the BIOS is triggered, the CPU will execute the BIOS trigger instruction, and the CPU will inform the MB CPLD that the cold reset is triggered through the GPIO1 signal between the CPU and the MB CPLD; when the BMC is triggered, the BMC will inform the MB CPLD through the hardware reset signal (such as the SYS_RESET_N signal).

[0038] 2. When MB CPLD obtains the cold reset signal triggered by BIOS or BMC, it informs SW CPLD of the cold reset signal through the GPIO2 signal between MB CPLD and SW CPLD.

[0039] 3. After receiving the notification signal, SW CPLD will pull down the BASE_PWR_EN signal of HGX to enable HGX to perform power-off timing, and release it after pulling it down for 2s, so that the power-off time of HGX can meet the specification requirements and power on again.

[0040] 4. The Retimer will also power on and reload the firmware during the HGX power-on and power-off process, and reload the PCIe link to avoid GPU loss.

[0041] However, this method requires that the CPU can notify the MB CPLD, and the MB CPLD can notify the SW CPLD, that is, there must be reserved signals between the CPU and MB CPLD, and between the MB CPLD and SW CPLD. Otherwise, the HGX cannot be powered on again, and the main board or switch board needs to be redesigned, which wastes time and cost.

[0042] Based on the above shortcomings of the existing cold reset method, the present disclosure proposes a cold reset method, system, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0043] Figure 5 The structure of a cold reset system according to an embodiment of the present disclosure is shown. Figure 1 ,like Figure 5 As shown, a cold reset system comprises: A first control board 10, which is a board for controlling all tasks of the system, and includes at least two processors; any one of the at least two processors is used to trigger a cold reset, and a target processor of the at least two processors is used to obtain reset information of the cold reset and send the reset information to a reset processor 31 on a second control board 30, and the target processor is the same as or different from the processor that triggers the cold reset; The second control board 30 is a board for performing image processing tasks, including a reset processor 31, a retimer 32 and a graphics processor 33. The retimer 32 is connected to the graphics processor 33 on the second control board 30; the reset processor 31 is used to reset the retimer 32 on the second control board 30 based on reset information.

[0044] In this embodiment, the first control board is a board that controls all tasks of the system, and the first control board can be a main board; the second control board is a board that performs image processing tasks, and the second control board can be an HGX. At least two processors in the first control board 10 can be a first processor 11 and a second processor 12, and the target processor can be the second processor 12. After any of the at least two processors triggers a cold reset, the reset information generated may include the source of the reset event, the type of the reset event, a timestamp or a serial number, the reset trigger reason, and system status information, etc., wherein the source of the reset event may include a BIOS trigger or a BMC trigger; the timestamp or the serial number can be used to distinguish different reset events; the reset trigger reason may include a BIOS setting change, a system abnormality, a user operation through the BMC web interface, etc.; the system status information includes the power status, the device status, etc., for subsequent analysis or processing.

[0045] In this embodiment, if the target processor is the second processor 12, the second processor 12 can obtain the reset information of the cold reset and send the reset information to the reset processor 31 on the second control board 30. The reset processor 31 can reset the retimer 32 (i.e., Retimer) on the second control board 30 based on the reset information. After the retimer 32 is reset, the firmware will be reloaded and the PCIe link will be reloaded at the same time, thereby avoiding the loss of the GPU. It should be emphasized that the target processor will send the reset information to the reset processor 31 only when the system triggers a cold reset. If the system triggers a warm reset, the reset information will not be obtained, that is, the process of resetting the retimer 32 will not be started.

[0046] In the present disclosure, the target processor (such as the second processor 12) on the first control board 10 will obtain the reset information of the cold reset after the cold reset occurs on the first control board 10, and directly send the reset information to the reset processor 31 on the second control board 30, and the reset processor 31 will reset the retimer 32 on the second control board 30 alone, thereby ensuring that the retimer 32 reloads the graphics processor 33 connected to it, avoiding the loss of the graphics processor and not affecting the normal use of other devices; in addition, there is no need for reserved signals between the CPU and MB CPLD, and between the MB CPLD and SW CPLD, and the retimer 32 can be reset directly, avoiding wasting time and cost.

[0047] In one embodiment, the first control board 10 also includes a first signal controller 13; any one of the at least two processors is used to trigger a cold reset, and send the reset information of the cold reset to the first signal controller 13 on the first control board 10; the first signal controller 13 is used to store the reset information in a register 14 in the first signal controller 13, and generate a prompt signal, and send the prompt signal to the target processor.

[0048] In this embodiment, a register 14 is provided in the first signal controller 13. After any one of at least two processors triggers a cold reset, the reset information will be sent to the first signal controller 13. The first signal controller 13 will store the reset information in the register 14, generate a prompt signal, and send the prompt signal to the target processor. The prompt signal indicates that the reset information has been stored in the register 14, and is used to prompt the target processor to read the reset information in the register 14.

[0049] In one embodiment, the target processor is further configured to: in response to the prompt signal, read the reset information from the register 14 through the internal integrated circuit bus. That is, the target processor can read the reset information from the register 14 through the internal integrated circuit bus (I2C, Inter-Integrated Circuit), which is a serial communication protocol used in electronic devices, mainly used in short-distance, low-speed communication scenarios.

[0050] In one embodiment, the first signal controller 13 is further configured to: clear the reset information from the register 14 in response to the target processor having read the reset information.

[0051] In this possible implementation mode, a flag is set in the first signal controller 13, and the flag is used to indicate whether the target processor has read the reset information in the register 14. The first signal controller 13 stores the reset information in the register 14 and sets the flag to "not read". After the target processor reads the reset information from the register 14, the flag is cleared or set to "read". In response to the flag being cleared or set to "read", the first signal controller 13 clears the reset information from the register 14.

[0052] In one possible implementation, the at least two processors include a first processor 11, and the first processor 11 is used to send the reset information of the cold reset to the first signal controller 13 through a general purpose input and output interface. That is, the first processor 11 can send the reset information of the cold reset to the first signal controller 13 through a general purpose input and output interface GPIO. GPIO is a common hardware interface, which is widely used in devices such as embedded systems, microcontrollers, and computer motherboards. The GPIO interface allows hardware devices to communicate with external circuits through simple digital signals to achieve input and output functions.

[0053] In one embodiment, at least two processors include a second processor 12, and the second processor 12 is used to send the reset information of the cold reset to the first signal controller 13 through a hardware reset signal. That is, the second processor 12 can send the reset information of the cold reset to the first signal controller 13 through hardware reset signals such as SYS_RESET_N and RST_N, wherein "N" in the hardware reset signals such as SYS_RESET_N and RST_N indicates that this is a low-level valid signal, that is, when the signal is at a low level, the system will trigger a reset operation, and the SYS_RESET_N signal is a common hardware signal, which is usually used for system reset operations, while RST_N is usually used for resetting specific devices or modules.

[0054] In one embodiment, the target processor is further configured to send the reset information to the reset processor 31 on the second control board 30 via a universal serial bus. That is, the target processor can send the reset information to the reset processor 31 on the second control board 30 via a universal serial bus (USB).

[0055] In one embodiment, the reset processor 31 is further used to: in response to the reset information, pull down the enable signal of the retimer 32 to a first level, and pull up the enable signal to a second level after a first target time length to enable the retimer 32 to complete the reset; the first level is less than the second level.

[0056] In this embodiment, after the reset processor 31 responds to the received reset information, it will parse the reset information and determine the operation to be performed indicated by the reset information. For example, if the reset processor 31 parses the reset information to indicate that the retimer 32 needs to be reset, it will pull down the enable signal of the retimer 32 to a first level, that is, a low level, usually 0V or ground, so that the retimer 32 enters a reset state and maintains this state for a first target duration, such as 1 second, to ensure that the retimer 32 is completely reset, and then pull up the enable signal of the retimer 32 to a second level, that is, a high level, usually 3.3V or 5V, so that the retimer 32 is powered on again, thereby completing the reset. Among them, whether the first target duration is reached can be determined by a timer or counter inside the FPGA.

[0057] After the enable signal of the retimer 32 is pulled high to the second level, the retimer 32 will be powered on again. At this time, the internal circuit of the retimer 32 will be reinitialized, all registers and status information will be cleared, and the retimer 32 will reload the firmware. The firmware usually contains the device driver and configuration parameters, and also checks the hardware status to ensure that the device is working properly.

[0058] After reloading the firmware, the retimer 32 will try to reestablish the PCIe link. This process includes: detecting the integrity of the PCIe signal; reestablishing the connection with other devices on the PCIe bus (such as the CPU, GPU, etc.); setting the relevant parameters of the PCIe link, including the rate, width, etc., according to the configuration parameters in the firmware; verifying whether the link is working properly to ensure the reliability of data transmission. In this way, the loss of the GPU can be avoided.

[0059] In one embodiment, a cold reset system also includes a third control board 20, and the first signal controller 13 is also used to: send reset information to the second signal controller 21 on the third control board 20, the third control board 20 is a board for signal exchange; the second signal controller 21 is used to reset the second control board 30 based on the reset information.

[0060] In this embodiment, the third control board 20 is arranged between the first control board 10 and the second control board 30, and is used for signal exchange between the first control board 10 and the second control board 30, so as to realize efficient transmission of data between the first control board 10 and the second control board 30. The third control board 20 includes a second signal controller 21. If the target processor cannot read the reset information in the register, for example, the I2C bus between the target processor and the register 14 is poorly connected, short-circuited or open-circuited, and the BMC is damaged or misconfigured, etc., the first signal controller 13 will send the reset information to the second signal controller 21 on the third control board 20. The second signal controller 21 can reset the second control board 30 as a whole based on the reset information. During this process, the retimer 32 in the second control board 30 will also be powered on again to complete the reset, and the firmware will be reloaded, and the PCIe link will be reloaded at the same time, so as to avoid GPU loss.

[0061] In one embodiment, the second signal controller 21 is also used to: in response to reset information, pull down the power enable signal of the second control board 30 to a third level, and pull up the power enable signal to a fourth level after a second target time to complete the reset of the second control board 30; the third level is less than the fourth level.

[0062] In this embodiment, after the second signal controller 21 responds to the received reset information, it will parse the reset information and determine the operation to be performed indicated by the reset information. For example, if the second signal controller 21 parses the reset information to indicate that the second control board 30 needs to be reset, it will pull down the power enable signal of the second control board 30 to the third level, that is, the low level, usually 0V or ground, so that the second control board 30 enters the reset state and maintains this state for a second target duration, such as 2 seconds, to ensure that the second control board 30 is completely reset, and then pull up the power enable signal of the second control board 30 to the fourth level, that is, the high level, usually 3.3V or 5V, so that the second control board 30 is powered on again, thereby completing the reset. Among them, whether the first target duration is reached can be determined by a timer or counter inside the second signal controller 21.

[0063] During the resetting process of the second control board 30, the retimer 32 in the second control board 30 will also be powered on again. At this time, the internal circuit of the retimer 32 will be reinitialized, all registers and status information will be cleared, and the retimer 32 will reload the firmware. The firmware usually contains the device driver and configuration parameters, and also checks the hardware status to ensure that the device is working properly.

[0064] After reloading the firmware, the retimer 32 will try to reestablish the PCIe link. This process includes: detecting the integrity of the PCIe signal; reestablishing the connection with other devices on the PCIe bus (such as the CPU, GPU, etc.); setting the relevant parameters of the PCIe link, including the rate, width, etc., according to the configuration parameters in the firmware; verifying whether the link is working properly to ensure the reliability of data transmission. In this way, the loss of the GPU can be avoided.

[0065] In one possible implementation manner, the target processor is further used to: generate warning information and display the warning information; the warning information is used to indicate that the cold reset is not completed.

[0066] In this possible implementation mode, if the target processor cannot obtain the reset information of the cold reset, such as the target processor is in a restart state, and the BMC configuration is wrong, a warning message can be generated on the BMC web interface and the warning message can be displayed; the warning message is used to indicate that the cold reset is not completed, and the user can shut down and restart the device based on the warning message to ensure that the user takes corresponding measures in time for the situation where the cold reset is not completed.

[0067] Figure 6 The structure of a cold reset system according to an embodiment of the present disclosure is shown. Figure 2 ,like Figure 6 As shown, Figure 5 The first control board 10 may be a mainboard, the first processor 11 may be a CPU, the second processor 12 may be a BMC, the target processor may be a BMC, and the first signal controller 13 may be an MB CPLD; the second control board 30 may be an HGX, the reset processor 31 may be an FPGA, the retimer 32 may be a retimer chip, and the graphics processor 33 may be a GPU; the second control board 20 may be a Switch board, and the second signal controller 21 may be a SW CPLD.

[0068] When a cold reset occurs on the motherboard, the MB CPLD on the motherboard is notified through GPIO1. The MB CPLD stores the reset information in the register and sends an ALERT signal to the BMC. The BMC reads the register of the MB CPLD to obtain the reset information. After that, the BMC notifies the FPGA on the HGX through the USB link that the FPGA needs to reset the retimer chip. The above process specifically includes: 1. When the server is running, a cold reset occurs in the following situations: a. When modifying some configuration options in BIOS configuration, a cold reset is required to make the modified options effective. Or when the system is running, some abnormalities in the operating system require a cold reset. The operating system will inform the BIOS, and the BIOS triggers a cold reset. At the same time, the CPU executes the trigger instruction of the BIOS. The CPU will inform the MB CPLD that the cold reset is triggered through the GPIO1 signal between the CPU and the MB CPLD. b. The server user forces a system restart on the server (i.e., cold resets the system) in the BMC web interface. The BMC triggers the SYS_RESET_N signal and informs the MB CPLD of the reset information. 2. When the CPU or BMC triggers a cold reset, the MB CPLD stores the reset information in the register inside the MB CPLD and sends an ALERT signal to inform the BMC that it needs to read the reset information in the register. After the BMC reads the reset information in the register, the MB CPLD clears the data in the register. 3. After receiving the prompt signal ALERT, BMC reads the register in MB CPLD. When it determines that the system triggers coldreset, it directly transmits the read reset information to FPGA on HGX through USB link; 4. After receiving the information, FPGA will pull down the EN signal of the retimer chip for 1s and then release it. After the retimer chip is powered on, it will reload the firmware and relink the PCIe signal to avoid GPU loss. 5. If the BMC cannot read the reset information in the register, the MB CPLD informs the SW CPLD of the reset information through the GPIO signal between it and the SW CPLD; 6. After obtaining the reset information, the SW CPLD will pull down the BASE_PWR_EN signal of the HGX, so that the HGX can perform the power-off timing, and release it after pulling it down for 2 seconds, so that the power-off time of the HGX can meet the specification requirements, and then power on again; 7. The retimer chip will also power on and reload the firmware during the HGX power-on and power-off process, and reload the PCIe link to avoid GPU loss; 8. If the BMC cannot obtain the reset information of the cold reset, a warning message will be generated and displayed in the BMC web. The warning message is used to indicate that the system cold reset is not completed. The user can shut down and restart the device based on the warning message to ensure that the user takes corresponding measures in time if the cold reset is not completed.

[0069] Therefore, when a cold reset occurs on the BIOS or BMC side, the BMC notifies the FPGA on the HGX through the USB link to power on and off the retimer chip separately without affecting the normal use of other devices. After a cold reset occurs, the retimer can be guaranteed to reload the firmware and relink the PCIe signal.

[0070] Figure 1 A schematic diagram showing a cold reset method according to an embodiment of the present disclosure Figure 1 ,like Figure 1 As shown, a cold reset method is applied to a cold reset system, comprising: Step S101: any processor on the first control board triggers a cold reset, and a target processor on the first control board obtains reset information of the cold reset.

[0071] In this embodiment, the first control board is a board that controls all tasks of the system. The first control board can be a main board. The first control board 10 includes at least two processors. The at least two processors can be a first processor 11 and a second processor 12. The target processor is the same as or different from the processor that triggers the cold reset. The target processor can be the second processor 12. After any of the at least two processors triggers the cold reset, the reset information generated may include the source of the reset event, the type of the reset event, a timestamp or a serial number, a reset triggering reason, and system status information, etc., wherein the source of the reset event may include a BIOS trigger or a BMC trigger; the timestamp or the serial number can be used to distinguish different reset events; the reset triggering reason may include a BIOS setting change, a system abnormality, a user operation through the BMC web interface, etc.; the system status information includes a power status, a device status, etc., which is used for subsequent analysis or processing.

[0072] Step S102: The target processor sends reset information to the reset processor on the second control board.

[0073] In this embodiment, the second control board is a board that performs image processing tasks. The second control board can be HGX. If the target processor is the second processor 12, the second processor 12 can obtain the reset information of the cold reset and send the reset information to the reset processor 31 on the second control board 30.

[0074] Step S103: the reset processor resets the retimer on the second control board based on the reset information.

[0075] In this embodiment, the retimer 32 is connected to the graphics processor on the second control board, and the reset processor 31 can reset the retimer 32 (i.e., Retimer) on the second control board 30 based on the received reset information. After the retimer 32 is reset, the firmware will be reloaded, and the PCIe link will be reloaded at the same time, thereby avoiding GPU loss. It should be emphasized that the target processor will send the reset information to the reset processor 31 only when the system triggers a cold reset. If the system triggers a warm reset, the reset information will not be obtained, that is, the process of resetting the retimer 32 will not be started.

[0076] In the present disclosure, the target processor (such as the second processor 12) on the first control board 10 will obtain the reset information of the cold reset after the cold reset occurs on the first control board 10, and directly send the reset information to the reset processor 31 on the second control board 30, and the reset processor 31 will reset the retimer 32 on the second control board 30 alone, thereby ensuring that the retimer 32 reloads the graphics processor 33 connected to it, avoiding the loss of the graphics processor and not affecting the normal use of other devices; in addition, there is no need for reserved signals between the CPU and MB CPLD, and between the MB CPLD and SW CPLD, and the retimer 32 can be reset directly, avoiding wasting time and cost.

[0077] Figure 2 A schematic diagram showing a cold reset method according to an embodiment of the present disclosure Figure 2 ,like Figure 2 As shown, a cold reset method includes: Step S201: any processor on the first control board triggers a cold reset, and sends reset information of the cold reset to a first signal controller on the first control board.

[0078] In this embodiment, the first control board 10 further includes a first signal controller 13 . After any processor on the first control board triggers a cold reset, the reset information of the cold reset is sent to the first signal controller 13 on the first control board 10 .

[0079] Step S202: The first signal controller stores the reset information in a register in the first signal controller, generates a prompt signal, and sends the prompt signal to the target processor.

[0080] In this embodiment, a register 14 is provided in the first signal controller 13. After receiving the reset information, the first signal controller 13 stores the reset information in the register 14, generates a prompt signal, and sends the prompt signal to the target processor. The prompt signal indicates that the reset information has been stored in the register 14, and is used to prompt the target processor to read the reset information in the register 14.

[0081] Step S203: the target processor reads reset information from a register via the internal integrated circuit bus in response to the prompt signal.

[0082] In this embodiment, after receiving the prompt signal, the target processor will respond to the prompt signal and read the reset information from register 14 through I2C. I2C is a serial communication protocol used in electronic devices, mainly used in short-distance, low-speed communication scenarios.

[0083] Step S204: the target processor sends the reset information to the reset processor on the second control board.

[0084] Step S205: the reset processor resets the retimer on the second control board based on the reset information.

[0085] The specific implementation details of step S204-step S205 are similar to those of step S102-step S103 and will not be repeated here.

[0086] In another embodiment, a cold reset method further includes: in response to the target processor having read the reset information, the first signal controller clears the reset information from the register.

[0087] In this embodiment, a flag is set in the first signal controller 13, and the flag is used to indicate whether the target processor has read the reset information in the register 14. The first signal controller 13 stores the reset information in the register 14 and sets the flag to "not read". After the target processor reads the reset information from the register 14, the flag is cleared or set to "read". In response to the flag being cleared or set to "read", the first signal controller 13 clears the reset information from the register 14.

[0088] In another embodiment, the processor that triggers the cold reset is the first processor, which is different from the target processor, and sends the reset information of the cold reset to the first signal controller on the first control board, including: the first processor sends the reset information of the cold reset to the first signal controller through the general input and output interface. That is, the first processor 11 can send the reset information of the cold reset to the first signal controller 13 through the general input and output interface GPIO. GPIO is a common hardware interface, which is widely used in embedded systems, microcontrollers, computer motherboards and other devices. The GPIO interface allows hardware devices to communicate with external circuits through simple digital signals to achieve input and output functions.

[0089] In another embodiment, the processor that triggers the cold reset is a second processor, which is the same as the target processor, and sends the reset information of the cold reset to the first signal controller on the first control board, including: the second processor sends the reset information of the cold reset to the first signal controller through a hardware reset signal. That is, the second processor 12 can send the reset information of the cold reset to the first signal controller 13 through hardware reset signals such as SYS_RESET_N and RST_N, wherein the "N" in the hardware reset signals such as SYS_RESET_N and RST_N indicates that this is a low-level valid signal, that is, when the signal is low, the system will trigger a reset operation, and the SYS_RESET_N signal is a common hardware signal, which is usually used for system reset operations, while RST_N is usually used for resetting specific devices or modules.

[0090] In another embodiment, step S102 "the target processor sends the reset information to the reset processor on the second control board" includes: the target processor sends the reset information to the reset processor on the second control board via a universal serial bus. That is, the target processor can send the reset information to the reset processor 31 on the second control board 30 via a USB.

[0091] In another embodiment, step S103 "the reset processor resets the retimer on the second control board based on the reset information" includes: the reset processor responds to the reset information, pulls down the enable signal of the retimer to a first level, and pulls up the enable signal to a second level after a first target time to complete the reset of the retimer; the first level is less than the second level.

[0092] In this embodiment, after the reset processor 31 responds to the received reset information, it will parse the reset information and determine the operation to be performed indicated by the reset information. For example, if the reset processor 31 parses the reset information to indicate that the retimer 32 needs to be reset, it will pull down the enable signal of the retimer 32 to a first level, that is, a low level, usually 0V or ground, so that the retimer 32 enters a reset state and maintains this state for a first target duration, such as 1 second, to ensure that the retimer 32 is completely reset, and then pull up the enable signal of the retimer 32 to a second level, that is, a high level, usually 3.3V or 5V, so that the retimer 32 is powered on again, thereby completing the reset. Among them, whether the first target duration is reached can be determined by a timer or counter inside the FPGA.

[0093] After the enable signal of the retimer 32 is pulled high to the second level, the retimer 32 will be powered on again. At this time, the internal circuit of the retimer 32 will be reinitialized, all registers and status information will be cleared, and the retimer 32 will reload the firmware. The firmware usually contains the device driver and configuration parameters, and also checks the hardware status to ensure that the device is working properly.

[0094] After reloading the firmware, the retimer 32 will try to reestablish the PCIe link. This process includes: detecting the integrity of the PCIe signal; reestablishing the connection with other devices on the PCIe bus (such as the CPU, GPU, etc.); setting the relevant parameters of the PCIe link, including the rate, width, etc., according to the configuration parameters in the firmware; verifying whether the link is working properly to ensure the reliability of data transmission. In this way, the loss of the GPU can be avoided.

[0095] Figure 3 A schematic diagram showing a cold reset method according to an embodiment of the present disclosure Figure 3 ,like Figure 3 As shown, a cold reset method includes: Step S301: any processor on the first control board triggers a cold reset, and sends reset information of the cold reset to a first signal controller on the first control board.

[0096] Step S302: The first signal controller stores the reset information in a register in the first signal controller, generates a prompt signal, and sends the prompt signal to the target processor.

[0097] The specific implementation details of step S301-step S302 are similar to those of step S201-step S202 and will not be repeated here.

[0098] If the target processor can read the reset information in the register, then execute step S303-step S304: Step S303: the target processor sends the reset information to the reset processor on the second control board.

[0099] Step S304: the reset processor resets the retimer on the second control board based on the reset information.

[0100] The specific implementation details of step S303-step S304 are similar to those of step S204-step S205 and will not be repeated here.

[0101] If the target processor cannot read the reset information in the register, then execute steps S305-S306: Step S305: The first signal controller sends reset information to the second signal controller on the third control board.

[0102] In this embodiment, the cold reset system also includes a third control board 20, which is a board for signal exchange. The third control board 20 is arranged between the first control board 10 and the second control board 30, and is used for signal exchange between the first control board 10 and the second control board 30, thereby realizing efficient transmission of data between the first control board 10 and the second control board 30. The third control board 20 includes a second signal controller 21. If the target processor cannot read the reset information in the register, for example, the I2C bus between the target processor and the register 14 is poorly connected, short-circuited or open-circuited, and the BMC is damaged or configured incorrectly, the first signal controller 13 will send the reset information to the second signal controller 21 on the third control board 20.

[0103] Step S306: The second signal controller resets the second control board based on the reset information.

[0104] In this embodiment, the second signal controller 21 can reset the entire second control board 30 based on the reset information. During this process, the retimer 32 in the second control board 30 will also be powered on again to complete the reset, and the firmware will be reloaded, and the PCIe link will be reloaded at the same time, thereby avoiding GPU loss.

[0105] In another embodiment, step S306 "the second signal controller resets the second control board based on the reset information" includes: the second signal controller pulls down the power enable signal of the second control board to a third level in response to the reset information, and pulls up the power enable signal to a fourth level after the second target time to complete the resetting of the second control board; the third level is less than the fourth level.

[0106] In this embodiment, after the second signal controller 21 responds to the received reset information, it will parse the reset information and determine the operation to be performed indicated by the reset information. For example, if the second signal controller 21 parses the reset information to indicate that the second control board 30 needs to be reset, it will pull down the power enable signal of the second control board 30 to the third level, that is, the low level, usually 0V or ground, so that the second control board 30 enters the reset state and maintains this state for a second target duration, such as 2 seconds, to ensure that the second control board 30 is completely reset, and then pull up the power enable signal of the second control board 30 to the fourth level, that is, the high level, usually 3.3V or 5V, so that the second control board 30 is powered on again, thereby completing the reset. Among them, whether the first target duration is reached can be determined by a timer or counter inside the second signal controller 21.

[0107] During the resetting process of the second control board 30, the retimer 32 in the second control board 30 will also be powered on again. At this time, the internal circuit of the retimer 32 will be reinitialized, all registers and status information will be cleared, and the retimer 32 will reload the firmware. The firmware usually contains the device driver and configuration parameters, and also checks the hardware status to ensure that the device is working properly.

[0108] After reloading the firmware, the retimer 32 will try to reestablish the PCIe link. This process includes: detecting the integrity of the PCIe signal; reestablishing the connection with other devices on the PCIe bus (such as the CPU, GPU, etc.); setting the relevant parameters of the PCIe link, including the rate, width, etc., according to the configuration parameters in the firmware; verifying whether the link is working properly to ensure the reliability of data transmission. In this way, the loss of the GPU can be avoided.

[0109] In another embodiment, after "any processor on the first control board triggers a cold reset" in step S101, the method further includes: in response to the target processor being unable to obtain reset information for the cold reset, the target processor generates a warning message and displays the warning message; the warning message is used to indicate that the cold reset is not completed.

[0110] In this embodiment, if the target processor cannot obtain the reset information of the cold reset, such as the target processor is in a restart state, and the BMC configuration is wrong, a warning message can be generated on the BMC web interface and displayed; the warning message is used to indicate that the cold reset is not completed, and the user can shut down and restart the device based on the warning information to ensure that the user takes corresponding measures in time for the situation where the cold reset is not completed.

[0111] According to an embodiment of the present disclosure, the present disclosure further provides an electronic device and a readable storage medium, wherein the electronic device includes the cold reset system described in the present disclosure, and the cold reset system can execute the cold reset method described in the present disclosure.

[0112] Figure 7 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0113] like Figure 7 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory ROM 802 or a computer program loaded from a storage unit 808 to a random access memory RAM 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0114] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0115] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as a cold reset method. For example, in some embodiments, a cold reset method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of a cold reset method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform a cold reset method in any other appropriate manner (e.g., by means of firmware).

[0116] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0117] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0118] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0119] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0120] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0121] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0122] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0123] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0124] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A cold reset method, characterized in that: The method comprises: Any processor on the first control board triggers a cold reset, and a target processor on the first control board obtains reset information of the cold reset; the first control board is a board card controlling all tasks of the system, and the target processor is the same as or different from the processor that triggers the cold reset; The target processor sends the reset information to a reset processor on a second control board; the second control board is a board for performing image processing tasks; The reset processor resets a retimer on the second control board based on the reset information, and the retimer is connected to the graphics processor on the second control board.

2. The method according to claim 1, characterized in that: Any processor on the first control board triggers a cold reset, including: Any processor on the first control board triggers a cold reset, and sends reset information of the cold reset to a first signal controller on the first control board; The first signal controller stores the reset information in a register in the first signal controller, generates a prompt signal, and sends the prompt signal to the target processor.

3. The method according to claim 2, characterized in that The target processor on the first control board obtains the reset information of the cold reset, including: The target processor reads the reset information from the register via an inter-integrated circuit bus in response to the prompt signal.

4. The method according to claim 3, characterized in that The method further comprises: The first signal controller clears the reset information from the register in response to the target processor having read the reset information.

5. The method according to claim 2, characterized in that: The processor that triggers the cold reset is a first processor, the first processor is different from the target processor, and the sending of the reset information of the cold reset to the first signal controller on the first control board includes: The first processor sends the reset information of the cold reset to the first signal controller through a general input and output interface.

6. The method according to claim 2, characterized in that The processor that triggers the cold reset is a second processor, the second processor is the same as the target processor, and the reset information of the cold reset is sent to the first signal controller on the first control board, including: The second processor sends the reset information of the cold reset to the first signal controller through a hardware reset signal.

7. The method according to claim 1, characterized in that The target processor sends the reset information to the reset processor on the second control board, including: The target processor sends the reset information to the reset processor on the second control board through a universal serial bus.

8. The method according to claim 1, characterized in that The reset processor resets the retimer on the second control board based on the reset information, including: In response to the reset information, the reset processor pulls down the enable signal of the retimer to a first level, and pulls up the enable signal to a second level after a first target time period, so that the retimer completes the reset; the first level is less than the second level.

9. The method according to claim 3, characterized in that: After the target processor reads the reset information from the register via an internal integrated circuit bus in response to the prompt signal, the method further includes: In response to the target processor being unable to read the reset information in the register, the first signal controller sending the reset information to a second signal controller on a third control board; the third control board is a board card for signal exchange; The second signal controller resets the second control board based on the reset information.

10. The method according to claim 9, characterized in that The second signal controller resets the second control board based on the reset information, including: In response to the reset information, the second signal controller pulls down the power enable signal of the second control board to a third level, and pulls up the power enable signal to a fourth level after a second target time to complete the reset of the second control board; the third level is less than the fourth level.

11. The method according to claim 1, characterized in that: After any processor on the first control board triggers a cold reset, the method further includes: In response to the target processor being unable to obtain the reset information of the cold reset, the target processor generates warning information and displays the warning information; the warning information is used to indicate that the cold reset is not completed.

12. A cold reset system, characterized in that: The system comprises: A first control board, which is a board for controlling all tasks of the system, and includes at least two processors; any one of the at least two processors is used to trigger a cold reset, and a target processor of the at least two processors is used to obtain reset information of the cold reset and send the reset information to a reset processor on a second control board, and the target processor is the same as or different from the processor that triggers the cold reset; The second control board is a board for performing image processing tasks, including a reset processor, a retimer and a graphics processor, wherein the retimer is connected to the graphics processor on the second control board; the reset processor is used to reset the retimer on the second control board based on the reset information.

13. The system according to claim 12, characterized in that The first control board further includes a first signal controller; any one of the at least two processors is used to trigger a cold reset and send reset information of the cold reset to the first signal controller on the first control board; The first signal controller is used to store the reset information in a register in the first signal controller, generate a prompt signal, and send the prompt signal to the target processor.

14. The system according to claim 13, characterized in that The target processor is further configured to: In response to the prompt signal, the reset information is read in the register through an inter-integrated circuit bus.

15. The system according to claim 14, characterized in that The first signal controller is also used for: In response to the target processor having read the reset information, clearing the reset information from the register.

16. The system according to claim 13, characterized in that The at least two processors include a first processor, and the first processor is used to send the reset information of the cold reset to the first signal controller through a general input and output interface.

17. The system according to claim 13, characterized in that The at least two processors include a second processor, and the second processor is used to send the reset information of the cold reset to the first signal controller through a hardware reset signal.

18. The system according to claim 12, characterized in that The target processor is further configured to: The reset information is sent to a reset processor on the second control board via a universal serial bus.

19. An electronic device, characterized in that: The cold reset system comprises any one of claims 12-18, wherein the cold reset system can execute any one of claims 1-11 cold reset method.

20. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1-11.

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