Chip power consumption control method and device, equipment and medium

Abstract

The invention discloses a chip power consumption control method, device and equipment and a medium, relates to the technical field of chips, is applied to a clock controller, and comprises the following steps: monitoring whether the state of any peripheral of a chip is changed or not; if it is monitored that the state of any peripheral is changed, updating a peripheral working list of the chip to obtain an updated working list; wherein the peripheral work list is used for recording the state of each peripheral of the chip; determining a bus clock frequency of the chip and a target frequency division coefficient corresponding to the target peripheral according to the updated work list; the target peripheral is a peripheral, which is in a working state currently, of the chip; and correspondingly adjusting a bus clock of the chip based on the bus clock frequency, and configuring a clock of the target peripheral based on the target frequency division coefficient to complete power consumption control of the chip. Therefore, on the premise of ensuring the performance of the chip, the bus working frequency is reduced, and the power consumption of the chip is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip power consumption control method, device, equipment and medium. Background Art

[0002] The power consumption of a chip mainly includes static power consumption and dynamic power consumption. Static power consumption is stable relative to the chip, while dynamic power consumption is mainly composed of flip power consumption and short-circuit power consumption. Flip power consumption is the most critical power consumption in the chip execution function, also known as effective power consumption. Flip power consumption is an important source of chip power consumption and is directly related to the clock frequency. The APB (Advanced Peripheral Bus) bus clock is generally a fixed-frequency clock. The system connects multiple peripherals through the APB bus and distributes the APB clock to multiple peripherals through the APB bus clock tree. Generally, multiple peripherals will use the APB bus clock to interact with the APB bus for data and external functions. If there is a clock requirement, the APB bus clock will be divided based on the APB bus clock to achieve the clock required by the peripheral. If the chip has a low power consumption requirement, the general practice is to turn off the power supply of the corresponding peripheral or stop the clock interface clock corresponding to the peripheral. This practice only stops the clock of the corresponding peripheral, but the bus still maintains the original rate. Unless all peripherals stop working, the bus clock can be turned off. The above method can only shut down the bus and enter low power mode after all peripherals are turned off. Even if one peripheral is still working, the bus still needs to maintain the original frequency and will not be reduced. In the actual application of many chips, not all peripherals of the chip are actually used. There are always some peripherals that do not need to work, and some peripherals need to keep in touch with the outside world. The bus cannot be shut down and the original working frequency is always maintained, which will generate relatively high power consumption.

[0003] It can be seen that how to reduce the clock frequency while ensuring chip performance is a problem that technical personnel in this field need to solve. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a chip power consumption control method, device, equipment and medium, which can dynamically adjust the bus clock and control the bus operating frequency while ensuring the basic performance of the chip, thereby effectively controlling the chip power consumption.

[0005] In a first aspect, the present invention provides a chip power consumption control method, which is applied to a clock controller, comprising:

[0006] Monitor whether the status of any peripheral of the chip has changed;

[0007] If the state of any peripheral is detected to be changed, the peripheral work list of the chip is updated to obtain an updated work list; wherein the peripheral work list is used to record the state of each peripheral of the chip;

[0008] Determine the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral according to the updated work list; the target peripheral is the peripheral of the chip that is currently in working state;

[0009] The bus clock of the chip is adjusted accordingly based on the bus clock frequency, and the clock of the target peripheral is configured based on the target frequency division coefficient to complete the power consumption control of the chip.

[0010] Optionally, monitor whether the status of any peripheral of the chip has changed, including:

[0011] Determine the source clock corresponding to the bus clock;

[0012] Perform periodic monitoring on the peripheral online indication signal line corresponding to any peripheral of the chip according to the source clock; wherein any peripheral of the chip sends a signal to the clock controller through the peripheral online indication signal line;

[0013] According to the signal sent by any peripheral of the chip to the clock controller through the peripheral online indication signal line monitored by the peripheral status monitor within a preset period, it is judged whether the state of any peripheral of the chip has changed; the state includes working state and offline state; the peripheral status monitor is located inside the clock controller;

[0014] Among them, if the peripheral status monitor detects the offline signal sent by the peripheral to the clock controller through the peripheral online indication signal line within the preset period, it is determined that the state of any peripheral of the chip has changed; if the peripheral status monitor does not detect the offline signal sent by the peripheral to the clock controller through the peripheral online indication signal line within the preset period, it is determined that the state of any peripheral of the chip has not changed.

[0015] Optionally, determining the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral according to the updated work list includes:

[0016] The updated work list is synchronized to the preset clock configurator and the preset adjustable clock, so as to determine the bus clock frequency based on the updated work list using the preset adjustable clock, and determine the target frequency division coefficient corresponding to the target peripheral based on the updated work list using the preset clock configurator.

[0017] Optionally, determining a bus clock frequency based on the updated work list using a preset adjustable clock includes:

[0018] Determine the minimum working clock of each target peripheral in the updated working list by presetting the adjustable clock;

[0019] The bus clock frequency is determined based on the least common multiple of the minimum operating clocks of each target peripheral.

[0020] Optionally, determining a target frequency division coefficient corresponding to a target peripheral device based on the updated work list using a preset clock configurator includes:

[0021] The target frequency division coefficient corresponding to each target peripheral is determined by presetting the clock configurator and according to the minimum working clock of each target peripheral and the bus clock frequency in the updated working list.

[0022] Optionally, before adjusting the bus clock of the chip accordingly based on the bus clock frequency, the method further includes:

[0023] The bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral are stored in the target storage area;

[0024] determining the state of the peripheral device through a peripheral device state monitor based on a signal sent by a peripheral device online indication signal line corresponding to the peripheral device;

[0025] An idle time of the peripheral device is determined according to a state of the peripheral device, and an update signal is generated based on the idle time.

[0026] Optionally, the bus clock of the chip is adjusted accordingly based on the bus clock frequency, and the clock of the target peripheral is configured based on the target frequency division factor, including:

[0027] Obtaining the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral from the target storage area according to the update signal;

[0028] The bus clock of the chip is adjusted accordingly based on the bus clock frequency, and the clock of the target peripheral is configured based on the target frequency division factor.

[0029] In a second aspect, the present invention provides a chip power consumption control device, which is applied to a clock controller, comprising:

[0030] The status monitoring module is used to monitor whether the status of any peripheral of the chip has changed;

[0031] A work list update module is used to update the peripheral work list of the chip if it detects that the state of any peripheral has changed, so as to obtain an updated work list; wherein the peripheral work list is used to record the state of each peripheral of the chip;

[0032] The frequency and coefficient acquisition module is used to determine the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral according to the updated working list; the target peripheral is the peripheral of the chip that is currently in working state;

[0033] The adjustment and configuration module is used to adjust the bus clock of the chip accordingly based on the bus clock frequency, and configure the clock of the target peripheral based on the target frequency division coefficient to complete the power consumption control of the chip.

[0034] In a third aspect, the present invention provides an electronic device, comprising:

[0035] Memory for storing computer programs;

[0036] The processor is used to execute a computer program to implement the aforementioned chip power consumption control method.

[0037] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the aforementioned chip power consumption control method when executed by a processor.

[0038] In the present invention, a clock controller monitors whether the state of any peripheral of a chip changes; if it is detected that the state of any peripheral changes, the peripheral work list of the chip is updated to obtain an updated work list; wherein the peripheral work list is used to record the state of each peripheral of the chip; the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral are determined according to the updated work list; the target peripheral is the peripheral of the chip that is currently in working state; the bus clock of the chip is adjusted accordingly based on the bus clock frequency, and the clock of the target peripheral is configured based on the target frequency division coefficient to complete the power consumption control of the chip.

[0039] Beneficial effects: The present invention monitors whether the state of any peripheral of the chip changes through the clock controller, calculates the frequency required by the bus and the target frequency division coefficient corresponding to the target peripheral in real time according to whether the chip peripheral is used or not, dynamically adjusts the bus clock, and configures the clock of the target peripheral. Then, under the premise of ensuring the basic performance of the chip and without changing the performance of the application peripherals, the bus operating frequency is adjusted to further achieve the purpose of controlling the power consumption of the chip. At the same time, the chip does not need to design the power consumption of the peripherals in advance according to the usage scenario, and the bus clock can be dynamically adjusted at any time based on whether the chip peripherals are used or not, which increases the flexibility of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1A flow chart of a chip power consumption control method provided by an embodiment of the present invention;

[0042] Figure 2 A schematic diagram of a chip power consumption control system provided by an embodiment of the present invention;

[0043] Figure 3 A schematic diagram of the structure of a clock controller provided by an embodiment of the present invention;

[0044] Figure 4 A flow chart of a bus clock adjustment method provided by an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of the structure of a chip power consumption control device provided by an embodiment of the present invention;

[0046] Figure 6 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0049] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0050] In some technologies, the bus can only be shut down and enter low-power mode after all peripherals are turned off. Even if there is a peripheral still working, the bus still needs to maintain the original frequency and will not be reduced. In the actual application of many chips, not all peripherals of the chip are actually applied. There will always be some peripherals that do not need to work, and some peripherals need to keep in touch with the outside world. The bus cannot be shut down and the original operating frequency is always maintained, which will result in relatively high power consumption. In order to solve the above technical problems, the present invention discloses a chip power consumption control method, device, equipment and medium, which can dynamically adjust the bus clock and adjust the bus operating frequency while ensuring the basic performance of the chip, thereby effectively controlling the chip power consumption.

[0051] See also Figure 1 As shown, an embodiment of the present invention provides a chip power consumption control method, which is applied to a clock controller, including:

[0052] Step S11, monitoring whether the status of any peripheral device of the chip changes.

[0053] The present invention includes but is not limited to being applied to chips that require low power consumption control peripherals, such as Figure 2 As shown, the present invention is constructed by adding a configurable clock module to the peripheral and configuring a clock controller module on the bus clock source. The two are associated through a configuration line, and the peripheral provides an online indication line for the clock controller to ensure that the clock power consumption controller can monitor the working status of the peripheral. First, monitor whether the state of any peripheral of the chip has changed. In this process, first determine the source clock corresponding to the bus clock; then, according to the source clock, periodically monitor the peripheral online indication signal line corresponding to any peripheral of the chip; wherein, any peripheral of the chip sends a signal to the clock controller through the peripheral online indication signal line; finally, according to the signal sent by any peripheral of the chip to the clock controller through the peripheral online indication signal line monitored by the peripheral status monitor within a preset period, determine whether the state of any peripheral of the chip has changed; the state includes working state and offline state; the peripheral status monitor is located inside the clock controller; wherein, if the offline signal sent by the peripheral to the clock controller through the peripheral online indication signal line is detected by the peripheral status monitor within the preset period, then it is determined that the state of any peripheral of the chip has changed; if the offline signal sent by the peripheral to the clock controller through the peripheral online indication signal line is not detected by the peripheral status monitor within the preset period, then it is determined that the state of any peripheral of the chip has not changed.

[0054] It is important to know that the bus base clock is input to the clock configurator to provide the base source clock for the bus clock; at the same time, the peripherals provide online indication lines for the clock controller to ensure that the clock controller can monitor the working status of the peripherals. Figure 3 As shown, the peripheral status monitor in the clock controller periodically monitors the peripheral online indication signal line based on the bus basic clock, and any peripheral of the chip sends a signal to the clock controller through the peripheral online indication signal line. Therefore, it is possible to determine whether the state of any peripheral of the chip has changed based on the signal sent to the clock controller through the peripheral online indication signal line by any peripheral of the chip monitored by the peripheral status monitor within a preset period. If the peripheral goes offline for N consecutive idle cycles of normal operation (N can be set as needed), the peripheral is offline instead of idle, and then the peripheral online indication signal line will send an offline signal to the clock controller, which can determine that the state of any peripheral of the chip has changed.

[0055] Step S12: if it is detected that the state of any peripheral device has changed, the peripheral device work list of the chip is updated to obtain an updated work list; wherein the peripheral device work list is used to record the state of each peripheral device of the chip.

[0056] In an embodiment of the present invention, if it is monitored that the state of any peripheral changes, that is, the number of peripherals currently in working state changes, and a peripheral changes from working state to offline, then the peripheral work list of the chip is updated, and the peripheral work list here is used to record the state of each peripheral of the chip. The state of the peripheral recorded in the peripheral work list is updated to obtain the updated work list. The state of the peripheral recorded in the updated work list strictly corresponds to the real peripheral. In this way, the number of peripherals in operation and the number of peripherals offline can be known according to the peripheral work list.

[0057] Step S13, determining the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral according to the updated working list; the target peripheral is the peripheral of the chip that is currently in working state.

[0058] In an embodiment of the present invention, after obtaining the updated work list, the updated work list is synchronized to the preset clock configurator and the preset adjustable clock inside the clock controller, so as to determine the bus clock frequency based on the updated work list using the preset adjustable clock, and determine the target division coefficient corresponding to the target peripheral based on the updated work list using the preset clock configurator. It can be known that the division coefficient (N) refers to reducing the frequency of the input signal to 1 / N of the original frequency. For example, if the frequency of a signal is 33MHz and its frequency is reduced to 11MHz by a divider, then the division coefficient is 3. The division coefficient is usually used for clock division in digital circuits to obtain lower clock signals, selection signals or interrupt signals, etc.

[0059] When the bus clock frequency is determined based on the updated work list using a preset adjustable clock, the present invention determines the minimum working clock of each target peripheral in the updated work list by using a preset adjustable clock; the bus clock frequency is determined according to the lowest common multiple of the minimum working clocks of each target peripheral. Specifically, the minimum working clock of all peripherals to ensure performance has been stored in the clock controller as basic information. Therefore, the peripheral currently in the working state is determined according to the updated work list, and then the minimum working clock of the peripheral previously in the working state is obtained, and then the bus clock frequency is determined using these minimum working clocks. In a specific embodiment, assuming that the minimum working clock required by the peripheral is f1, f2, ..., fn, the bus clock is a natural number multiple of the lowest common multiple of the set. Generally, in order to reduce power consumption, the bus clock is selected as the lowest common multiple of the working clock set: bus clock f=[f1, f2, ..., fn].

[0060] It should be pointed out that the bus clock frequency is calculated by the least common multiple of the minimum clock of the peripherals in the present invention. It is also possible to configure the table lookup mode, that is, to configure the bus clock frequency table in advance, and record the number of various peripherals and the corresponding bus clock frequency under the condition of the minimum working clock of the peripherals in the bus clock frequency table. After obtaining the updated work list, according to the number of peripherals in the working state in the updated work list and the minimum working clock of each peripheral in the working state, the corresponding bus clock frequency is then searched in the bus clock frequency table according to these two numbers. Of course, the content that can be recorded in the bus clock frequency table includes not only the number of various peripherals and the corresponding bus clock frequency under the condition of the minimum working clock of the peripherals, but also other parameters. Then, by means of table lookup, the calculation process is omitted, the occupation of computing resources is reduced, and the final bus clock frequency is quickly selected by simpler comparison and search. At the same time, it can also be further applied to chips with the same scenario.

[0061] In addition, when the target frequency division coefficient corresponding to the target peripheral is determined based on the updated work list using the preset clock configurator, the present invention determines the target frequency division coefficient corresponding to each target peripheral by using the preset clock configurator and according to the minimum working clock and bus clock frequency of each target peripheral in the updated work list. Since the calculation of the frequency division coefficient is usually based on the required output frequency and input frequency, the frequency division coefficient = external clock frequency (equivalent to the minimum working clock) / output clock frequency (equivalent to the bus clock frequency). The clock configuration configures the frequency division coefficient of the peripheral according to the peripheral situation and the bus clock frequency. For example, the minimum working clock of peripheral 1 is f1=2MHz, and the minimum working clock of peripheral 2 is f2=3MHz. The adjustable clock recalculates the bus clock as f=[2M, 3M]=6MHz based on the minimum working clocks of peripheral 1 and peripheral 2. The clock configuration configures the frequency division coefficient of peripheral 1 to 3 and the frequency division coefficient of peripheral 2 to 2 according to the peripheral situation.

[0062] Step S14: adjusting the bus clock of the chip accordingly based on the bus clock frequency, and configuring the clock of the target peripheral device based on the target frequency division coefficient, so as to complete the power consumption control of the chip.

[0063] In the embodiment of the present invention, the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral are determined, and the bus clock is not adjusted immediately. Instead, the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral are first stored in the target storage area before the bus clock of the chip is adjusted accordingly based on the bus clock frequency; the state of the peripheral is determined by the peripheral state monitor based on the signal sent by the peripheral online indication signal line corresponding to the peripheral; the idle time of the peripheral is determined according to the state of the peripheral, and an update signal is generated based on the idle time. In other words, the adjustment of the bus clock and the configuration of the peripheral clock can only be performed after receiving the update signal. The peripheral state monitor inside the clock controller determines whether the current peripheral is in normal operation or in an idle period of normal operation based on the online indication state of the peripheral, and sends an update indication when the peripheral is idle.

[0064] After receiving the update signal, the present invention obtains the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral from the target storage area according to the update signal; the bus clock of the chip is adjusted accordingly based on the bus clock frequency, and the clock of the target peripheral is configured based on the target frequency division coefficient. Then the bus clock switching is completed. At the same time, it is ensured that the work of the peripheral is not affected. It should be pointed out that although the present invention is applied on the peripheral bus, it can be extended to the application of other buses to match the different performance and power consumption requirements of the chip.

[0065] Beneficial effects: The present invention monitors whether the state of any peripheral of the chip changes through the clock controller, calculates the frequency required by the bus and the target frequency division coefficient corresponding to the target peripheral in real time according to whether the chip peripheral is used or not, dynamically adjusts the bus clock, and configures the clock of the target peripheral. Then, under the premise of ensuring the basic performance of the chip and without changing the performance of the application peripherals, the bus operating frequency is adjusted to further achieve the purpose of controlling the power consumption of the chip. At the same time, the chip does not need to design the power consumption of the peripherals in advance according to the usage scenario, and the bus clock can be dynamically adjusted at any time based on whether the chip peripherals are used or not, which increases the flexibility of the chip.

[0066] See also Figure 2 As shown, the method of the present invention adds a configurable clock to the peripheral and configures a clock controller on the bus clock source. Next, the specific chip power consumption control method will be described in detail in combination with the configurable clock module and the clock controller module.

[0067] In the present invention, the configurable clock module and the clock controller module are associated through configuration lines, and the peripherals provide online indication lines for the clock power controller to ensure that the clock power controller can monitor the working status of the peripherals. The bus base clock is input to the clock power configurator to provide a basic source clock for the bus clock; when the peripheral does not need to work for various reasons, the peripheral sends an offline signal to the clock power controller through the peripheral online indication signal line. The clock power controller sends updated clock parameters to the adjustable clock based on the list of peripherals, updates the bus clock in the intervals when the peripherals stop, and provides new configuration parameters to the configurable clock unit of the peripheral to ensure that the peripheral completes the clock update before the next work. The clock power controller module structure is as follows: Figure 3 As shown. The calculation logic of the internal adjustable clock bus clock of the clock power controller is as follows: Assuming that the minimum working clock required by the peripheral is f1, f2, ..., fn, the bus clock is a natural number multiple of the least common multiple of the set. Generally, in order to reduce power consumption, the bus clock is selected as the least common multiple of the working clock set: bus clock f = [f1, f2, ..., fn].

[0068] Afterwards, the clock power controller adjusts the clock division factor through the configurable clock module, configures the division factor of each module to the corresponding parameter, and restarts the clock bus at the appropriate time. In this way, the module can reach the minimum working clock of the module and ensure the normal operation of each peripheral. At the same time, the bus clock is effectively reduced, and the chip power consumption is reduced.

[0069] The peripheral status monitor performs periodic monitoring of the peripheral online indicator line based on the bus basic clock. If it detects that the status of any peripheral has changed, that is, a peripheral has gone offline and is no longer working, it enters the peripheral update state, updates the peripheral work list, and sends the peripheral update list to the clock configurator and adjustable clock.

[0070] Specifically, through Figure 4 Combined with Figure 2The process of dynamically adjusting the bus clock through the clock controller is described in detail. In a specific embodiment, the minimum working clock of peripheral 1 is f1=2MHz, the minimum working clock of peripheral 2 is f2=3MHz, the minimum working clock of peripheral 3 is f3=5MHz, and the original clock configuration is 30MHz. The peripheral status is monitored by the peripheral status monitor. After peripheral 3 stops working, the peripheral online indication is pulled down. The clock power consumption controller detects the peripheral online indication 3 online. It is low for multiple consecutive cycles, which exceeds the idle cycle of normal operation. At this time, the peripheral status change is detected, and the clock power consumption controller updates the peripheral list and synchronizes the list to the internal module. The adjustable clock recalculates the bus clock to f=[2M, 3M]=6MHz according to the minimum working clock of peripheral 1 and peripheral 2. The clock configuration configures the frequency division coefficient of peripheral 1 to 3 and the frequency division coefficient of peripheral 2 to 2 according to the peripheral situation, and waits for the update signal. That is to say, after the calculation is completed, the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral are first stored in the target storage area; the peripheral status monitor determines the status of the peripheral based on the signal sent by the peripheral online indication signal line corresponding to the peripheral; the idle time of the peripheral is determined according to the status of the peripheral, and an update signal is generated based on the idle time. In other words, the peripheral status monitor inside the clock power controller sends an update indication based on the online indication status of the peripheral when the peripheral is idle. After receiving the update indication, the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral are obtained from the target storage area; the bus clock of the chip is adjusted accordingly based on the bus clock frequency, and the clock of the target peripheral is configured based on the target frequency division coefficient. That is, the bus clock and the peripheral configurable clock parameters are updated synchronously, and the bus clock switching is completed, which ensures that the bus clock is reduced from 30MHz to 6MHz without interfering with the operation of the peripheral. Finally, the chip enters low power mode.

[0071] Beneficial effect: The present invention establishes a dynamically adjustable bus clock mechanism by designing a configurable clock and clock power consumption controller. It can flexibly adjust the bus clock according to the usage of the peripherals without relying on the main control, thereby achieving the purpose of reducing chip power consumption without reducing the basic performance of the peripherals.

[0072] See also Figure 5 As shown, an embodiment of the present invention provides a chip power consumption control device, which is applied to a clock controller, including:

[0073] The status monitoring module 11 is used to monitor whether the status of any peripheral of the chip has changed;

[0074] The work list update module 12 is used to update the peripheral work list of the chip if the state of any peripheral is detected to be changed, so as to obtain an updated work list; wherein the peripheral work list is used to record the state of each peripheral of the chip;

[0075] The frequency and coefficient acquisition module 13 is used to determine the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral according to the updated working list; the target peripheral is the peripheral of the chip that is currently in working state;

[0076] The adjustment and configuration module 14 is used to adjust the bus clock of the chip accordingly based on the bus clock frequency, and configure the clock of the target peripheral device based on the target frequency division coefficient to complete the power consumption control of the chip.

[0077] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0078] Beneficial effects: The present invention monitors whether the state of any peripheral of the chip changes through the clock controller, calculates the frequency required by the bus and the target frequency division coefficient corresponding to the target peripheral in real time according to whether the chip peripheral is used or not, dynamically adjusts the bus clock, and configures the clock of the target peripheral. Then, under the premise of ensuring the basic performance of the chip and without changing the performance of the application peripherals, the bus operating frequency is adjusted to further achieve the purpose of controlling the power consumption of the chip. At the same time, the chip does not need to design the power consumption of the peripherals in advance according to the usage scenario, and the bus clock can be dynamically adjusted at any time based on whether the chip peripherals are used or not, which increases the flexibility of the chip.

[0079] Furthermore, an embodiment of the present invention also discloses an electronic device, Figure 6 It is a structural diagram of an electronic device according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of the present invention. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the chip power consumption control method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0080] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present invention, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0081] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0082] The operating system 221 is used to manage and control various hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the chip power consumption control method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0083] Furthermore, the present invention also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed chip power consumption control method. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0084] Furthermore, the present invention also discloses a computer program product, including a computer program / instruction; wherein, when the computer program / instruction is executed by a processor, the chip power consumption control method disclosed above is implemented. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the above embodiments, and no further description will be given here.

[0085] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0086] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0087] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0088] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0089] The technical solution provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A chip power consumption control method, characterized in that: Applicable to clock controllers, including: Monitor whether the status of any peripheral of the chip has changed; If it is detected that the state of any peripheral device has changed, the peripheral device work list of the chip is updated to obtain an updated work list; wherein the peripheral device work list is used to record the state of each peripheral device of the chip; Determine the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral according to the updated work list; the target peripheral is a peripheral of the chip that is currently in working state; The bus clock of the chip is adjusted accordingly based on the bus clock frequency, and the clock of the target peripheral is configured based on the target frequency division coefficient to complete the power consumption control of the chip.

2. The chip power consumption control method according to claim 1, characterized in that: Whether the state of any peripheral of the monitoring chip has changed includes: Determine the source clock corresponding to the bus clock; Performing periodic monitoring on a peripheral online indication signal line corresponding to any peripheral of the chip according to the source clock; wherein any peripheral of the chip sends a signal to a clock controller through the peripheral online indication signal line; According to the signal sent by any peripheral of the chip through the peripheral online indication signal line to the clock controller monitored by the peripheral status monitor within a preset period, it is judged whether the state of any peripheral of the chip changes; the state includes working state and offline state; the peripheral status monitor is located inside the clock controller; Among them, if the peripheral status monitor detects the offline signal sent by the peripheral to the clock controller through the peripheral online indication signal line within a preset period, it is determined that the state of any peripheral of the chip has changed; if the peripheral status monitor does not detect the offline signal sent by the peripheral to the clock controller through the peripheral online indication signal line within the preset period, it is determined that the state of any peripheral of the chip has not changed.

3. The chip power consumption control method according to claim 1, characterized in that: The step of determining the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral according to the updated work list includes: The updated work list is synchronized to a preset clock configurator and a preset adjustable clock so as to determine the bus clock frequency based on the updated work list using the preset adjustable clock, and to determine the target frequency division coefficient corresponding to the target peripheral device based on the updated work list using the preset clock configurator.

4. The chip power consumption control method according to claim 3, characterized in that: The method of determining the bus clock frequency based on the updated work list using the preset adjustable clock includes: Determine the minimum working clock of each of the target peripherals in the updated working list by using the preset adjustable clock; The bus clock frequency is determined according to the least common multiple of the minimum operating clocks of each of the target peripherals.

5. The chip power consumption control method according to claim 3, characterized in that: The using the preset clock configurator to determine the target frequency division coefficient corresponding to the target peripheral based on the updated work list includes: The target frequency division coefficient corresponding to each of the target peripherals is determined by the preset clock configurator according to the minimum working clock of each of the target peripherals in the updated working list and the bus clock frequency.

6. The chip power consumption control method according to any one of claims 1 to 5, characterized in that: Before the bus clock of the chip is adjusted accordingly based on the bus clock frequency, the method further includes: Storing the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral device in a target storage area; Determining the state of the peripheral device by a peripheral device state monitor based on a signal sent by a peripheral device online indication signal line corresponding to the peripheral device; An idle time of the peripheral device is determined according to a state of the peripheral device, and an update signal is generated based on the idle time.

7. The chip power consumption control method according to claim 6, characterized in that: The step of adjusting the bus clock of the chip accordingly based on the bus clock frequency, and configuring the clock of the target peripheral device based on the target frequency division coefficient, includes: Acquire the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral from the target storage area according to the update signal; The bus clock of the chip is adjusted accordingly based on the bus clock frequency, and the clock of the target peripheral is configured based on the target frequency division coefficient.

8. A chip power consumption control device, characterized in that: Applicable to clock controllers, including: The status monitoring module is used to monitor whether the status of any peripheral of the chip has changed; A work list update module, used for updating the peripheral work list of the chip if it is detected that the state of any peripheral device has changed, so as to obtain an updated work list; wherein the peripheral work list is used to record the state of each peripheral device of the chip; A frequency and coefficient acquisition module, used to determine the bus clock frequency of the chip and the target frequency division coefficient corresponding to the target peripheral according to the updated working list; the target peripheral is a peripheral currently in working state of the chip; The adjustment and configuration module is used to adjust the bus clock of the chip accordingly based on the bus clock frequency, and configure the clock of the target peripheral device based on the target frequency division coefficient to complete the power consumption control of the chip.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the chip power consumption control method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip power consumption control method according to any one of claims 1 to 7 are implemented.

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