Memory and memory system

Abstract

The embodiment of the invention provides a memory and a memory system. The memory is configured to receive a first command, wherein information of the first command comprises a first target address and a first address offset; outputting first target data corresponding to the first target address; pre-reading second target data corresponding to the second target address; the second target address is determined based on the first target address and the first address offset, and is different from the first target address.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory and a memory system. Background Art

[0002] In the memory system, the memory and the controller are connected through the command address bus (CA) and the data bus (DQ). The controller sends different operation commands and the target address to be accessed through the command address bus, and writes the target data into the memory or reads the target data from the memory through the data bus.

[0003] The Joint Electron Device Engineering Council (JEDEC) is a standards organization for the microelectronics industry. It publishes a series of protocols that specify the specifications of the command address bus and the data bus for memory manufacturers and controller manufacturers to follow together to integrate and interconnect more efficiently and conveniently. In the storage protocol, read latency (RL) is defined. Read latency refers to the time from when the controller sends a read command to when the memory returns the target data, that is, the time from when the memory receives the read command to when the memory outputs the target data. The smaller the read latency, the faster the controller can get the target data, which can improve the operating efficiency of the entire memory system. The smaller the read latency of the memory, the more applications the memory can have, and it can be used in memory systems with higher performance requirements.

[0004] Currently, there is a great need for memory improvements to reduce read latency. Summary of the invention

[0005] In view of this, embodiments of the present disclosure provide a memory and a memory system.

[0006] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0007] In a first aspect, an embodiment of the present disclosure provides a memory, which is configured to: receive a first command, wherein information of the first command includes a first target address and a first address offset; output first target data corresponding to the first target address; and pre-read second target data corresponding to a second target address; the second target address is determined based on the first target address and the first address offset, and is different from the first target address.

[0008] In some embodiments, the memory includes: a storage cell array and a first data buffer coupled to the storage cell array; outputting the first target data corresponding to the first target address includes: reading the first target data corresponding to the first target address in the storage cell array into the first data buffer; and outputting the first target data in the first data buffer.

[0009] In some embodiments, the memory includes: a storage cell array and a second data buffer coupled to the storage cell array; outputting the first target data corresponding to the first target address includes: outputting the first target data corresponding to the first target address pre-stored in the second data buffer.

[0010] In some embodiments, the memory includes: a storage cell array and a second data buffer coupled to the storage cell array; the pre-reading of the second target data corresponding to the second target address includes: pre-reading the second target data corresponding to the second target address in the storage cell array into the second data buffer.

[0011] In some embodiments, the memory is further configured to: receive a second command, information of the second command including a second target address and a second address offset; output second target data corresponding to the second target address pre-stored in the second data buffer; and pre-read third target data corresponding to the third target address in the storage cell array into the second data buffer; the third target address is determined based on the second target address and the second address offset, and is different from the second target address.

[0012] In some embodiments, pre-reading the second target data corresponding to the second target address is performed simultaneously with outputting the first target data corresponding to the first target address; or, pre-reading the second target data corresponding to the second target address is performed after outputting the first target data corresponding to the first target address.

[0013] In some embodiments, the first command includes a first read command and a first pre-read command, and the memory is configured to: output first target data corresponding to the first target address according to the first read command; and pre-read second target data corresponding to the second target address according to the first pre-read command.

[0014] In a second aspect, an embodiment of the present disclosure provides a memory system, comprising: the memory in the above technical solution and a controller coupled to the memory; the controller is configured to: send a first command, wherein information of the first command comprises a first target address and a first address offset; the memory is configured to: receive the first command; output first target data corresponding to the first target address; and pre-read second target data corresponding to a second target address; the second target address is determined based on the first target address and the first address offset, and is different from the first target address; the controller is further configured to: receive the first target data.

[0015] In some embodiments, the first command includes a first read command and a first pre-read command, and the memory is configured to: output first target data corresponding to the first target address according to the first read command; and pre-read second target data corresponding to the second target address according to the first pre-read command.

[0016] In some embodiments, the memory includes: a memory cell array and a first data buffer and a second data buffer coupled to the memory cell array; the memory is configured to: read the first target data corresponding to the first target address in the memory cell array into the first data buffer; and output the first target data in the first data buffer; and pre-read the second target data corresponding to the second target address in the memory cell array into the second data buffer.

[0017] The disclosed embodiment provides a memory and a memory system. In the disclosed embodiment, after receiving a first command, the memory can output first target data corresponding to a first target address, and pre-read second target data corresponding to a second target address; thus, after receiving the first command, the memory can read and output the first target data, and pre-read the second target data, so as to shorten the read delay of the subsequent reading of the second target data. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagrams of memory systems are provided for some examples;

[0019] Figure 2 Schematic diagram of memory read latency for some examples;

[0020] Figure 3 Timing diagrams for read commands provided for some examples;

[0021] Figure 4 A schematic diagram of a memory system provided by an embodiment of the present disclosure;

[0022] Figure 5 A schematic diagram of a method for operating a memory provided by an embodiment of the present disclosure;

[0023] Figure 6 A read latency diagram of a first command of a memory provided by an embodiment of the present disclosure;

[0024] Figure 7 A read latency diagram of a second command of a memory provided by an embodiment of the present disclosure;

[0025] Figure 8 A timing diagram of a first command and a second command provided for an embodiment of the present disclosure;

[0026] Fig. 9 A schematic diagram of a flow chart of a method for operating a memory provided by an embodiment of the present disclosure;

[0027] Fig.10 A schematic diagram of a computer-readable storage medium provided for an embodiment of the present disclosure.

[0028] The figure includes: 100, memory system; 110, memory; 120, controller; 111, storage cell array; 112, data buffer; 200, memory system; 210, memory; 220, controller; 211, storage cell array; 212, first data buffer; 213, second data buffer; 400, computer readable storage medium; 410, computer program. DETAILED DESCRIPTION

[0029] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0031] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0033] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0036] refer to Figure 1 , Figure 1 Schematic diagrams of memory systems are provided for some examples. Figure 1 As shown, the memory system 100 includes: a memory 110 and a controller 120 coupled to the memory 110, the memory 110 includes a storage cell array 111 and a data buffer 112 (Data Buffer) coupled to the storage cell array 111; wherein the memory 110 and the controller 120 are connected via a command address bus and a data bus, the controller 120 sends a read command to the memory 110 via the command address bus, and the memory 110 returns the target data to the controller 120 via the data bus.

[0037] refer to Figure 2 , Figure 2 A schematic diagram of memory read latency for some examples. Figure 2 As shown, the memory receives a read command through a command address bus, and the information of the read command includes a target address; the memory generally includes two processes in response to the read command, the first process is: based on the target address, read the target data from the storage cell array into the data buffer (i.e., array read), that is, based on the target address, read the target data corresponding to the target address in the storage cell array into the data buffer; the second process is: read the target data from the data buffer and output (i.e., databuffer read), that is, output the target data corresponding to the target address in the data buffer through the data bus. A complete read command operation includes the above two processes, that is, the read delay includes: the sum of the first duration of receiving the read command, reading the target data corresponding to the target address from the storage cell array into the data buffer, and the second duration of reading the target data corresponding to the target address from the data buffer and outputting it.

[0038] refer to Figure 3 , Figure 3 Timing diagrams for read commands are provided for some examples. Figure 3As shown in Figure (a), for the first read command, the read delay (i.e., RL) includes: a first time duration (i.e., array RL) for reading the target data (i.e., addr0 data) corresponding to the target address (i.e., addr0) from the storage cell array to the data buffer, and a second time duration (i.e., DBRL) for reading the target data (i.e., addr0 data) corresponding to the target address (i.e., addr0) from the data buffer and outputting it, that is, the read delay includes the sum of the first time duration and the second time duration (i.e., RL=array RL+DB RL).

[0039] like Figure 3 As shown in Figure (b), for the second read command, the read delay (i.e., RL) includes: a first duration (i.e., array RL) of reading the target data (i.e., addr1 data) corresponding to the target address (i.e., addr1) from the storage cell array to the data buffer, and a second duration (i.e., DB RL) of reading the target data (i.e., addr1 data) corresponding to the target address (i.e., addr1) from the data buffer and outputting it, that is, the read delay includes the sum of the first duration and the second duration (i.e., RL = array RL + DB RL). In this way, the read delay for each read command is substantially the same.

[0040] At present, the read latency of dynamic random access memory (DRAM) is usually in the order of a few nanoseconds to tens of nanoseconds, the read latency of phase change memory (PCM) is usually in the order of hundreds of nanoseconds, and the read latency of NOT AND (NAND) memory is usually in the order of milliseconds. The industry has been working to shorten the read latency of memory, for example, by improving the electrical properties of memory materials to improve the read performance of memory.

[0041] In view of this, embodiments of the present disclosure provide a memory and a memory system.

[0042] refer to Figure 4 , Figure 4 Schematic diagram of a memory system provided by an embodiment of the present disclosure. Figure 4As shown, an embodiment of the present disclosure provides a memory, which includes: a memory cell array 211, a first data buffer 212 coupled to the memory cell array 211, and a second data buffer 213 coupled to the memory cell array 211; the above-mentioned memory 210 is configured to: receive a first command, the information of the first command includes a first target address and a first address offset; output first target data corresponding to the first target address, and pre-read second target data corresponding to the second target address; the second target address is determined based on the first target address and the first address offset, and is different from the first target address.

[0043] Here, the storage cell array 211 may include a plurality of storage cells arranged in an array, and each storage cell may be used to store data. Exemplarily, the plurality of storage cells may be arranged in an array along the X direction, the Y direction, and the Z direction, and the row address, column address, and vertical address of each storage cell may be determined according to the coordinate position of each storage cell in the X direction, the Y direction, and the Z direction. According to the row address, the column address, and the vertical address, a specific storage cell may be determined, and data may be written into or read from the storage cell.

[0044] Here, the first data buffer 212 may include one or more data buffers, that is, the first data buffer 212 may include a group of data buffers for temporarily storing the target data corresponding to the target address read from the storage cell array, and outputting the target data corresponding to the target address read from the first data buffer. The first data buffer 212 is used to temporarily store the target data that needs to be output by the current command.

[0045] Here, the second data buffer 213 may include one or more data buffers, that is, the second data buffer 213 may include a group of data buffers for temporarily storing the target data corresponding to the target address read from the storage cell array, and subsequently the target data corresponding to the target address read from the second data buffer will be output. The second data buffer 213 is used to temporarily store the target data that needs to be pre-read for the current command, and a subsequent command can output the target data pre-stored in the second data buffer 213.

[0046] In some embodiments, the first command includes a first read command and a first pre-read command, and the memory 210 is configured to: output first target data corresponding to the first target address according to the first read command; and pre-read second target data corresponding to the second target address according to the first pre-read command.

[0047] Here, the information of the first command includes the first target address and the first address offset. The information of the first command received by the memory includes the first target address and the first address offset, that is, the first command carries N information bits as the first address offset.

[0048] Here, the first target address refers to a specific address in the storage cell array, and the first target storage cell can be located according to the first target address in the storage cell array, thereby obtaining the first target data stored in the first target storage cell. The memory can receive the first command, and output the first target data corresponding to the first target address according to the first read command in the first command.

[0049] In the present disclosure, according to the first read command, outputting the first target data corresponding to the first target address may include different implementations. In some embodiments, the first target data corresponding to the first target address in the storage cell array may be read into the first data buffer, and the first target data in the first data buffer may be output. In other embodiments, the first target data corresponding to the first target address pre-stored in the second data buffer may also be output. Figure 5 This is a schematic diagram of the operating method of the memory provided by the embodiment of the present disclosure. Figure 4 and Figure 5 Provide explanation.

[0050] like Figure 4 and Figure 5 As shown, in some embodiments, the memory 210 is configured to: receive a first command, information of the first command including a first target address and a first address offset; read first target data corresponding to the first target address in the storage cell array 211 into the first data buffer 212 according to a first read command in the first command; and output the first target data in the first data buffer 212.

[0051] At this time, receiving the first command from the memory 210 to outputting the first target data from the memory 210 can include two processes. The first process is: reading the first target data from the storage cell array 211 to the first data buffer 212; the second process is: reading the first target data from the first data buffer 212 and outputting it.

[0052] like Figure 4 and Figure 5 As shown, in some other embodiments, the memory 210 is configured to: receive a first command, information of the first command including a first target address and a first address offset; and output the first target data corresponding to the first target address pre-stored in the second data buffer 213 according to a first read command in the first command.

[0053] At this time, the process from receiving the first command from the memory 210 to outputting the first target data from the memory 210 may include a process of reading and outputting the first target data pre-stored in the second data buffer 213 .

[0054] Here, the second target address can be determined according to the first target address and the first address offset (i.e., the second target address = the first target address + the first address offset), the second target address refers to a specific address in the storage cell array, and the second target storage cell can be located according to the second target address in the storage cell array, thereby obtaining the second target data stored in the second target storage cell. The memory can receive the first command, and pre-read the second target data corresponding to the second target address according to the first pre-read command in the first command.

[0055] like Figure 4 and Figure 5 As shown, in some embodiments, the memory 210 is further configured to: pre-read the second target data corresponding to the second target address in the storage cell array 211 into the second data buffer 213 .

[0056] At this time, after receiving the first command, the memory 210 outputs the first target data and does not output the second target data, and pre-reads the second target data from the storage cell array 211 to the second data buffer 213, so that after the subsequent memory 210 receives a certain command (for example, the second command), the second target data pre-stored in the second data buffer 213 can be output.

[0057] It should be noted that, in the above technical solution, the first target address and the second target address are different, indicating that the first address offset is not 0. The following is a brief description of the case where the first address offset is 0. If the first address offset is 0, then the first command includes a first read command, and the memory is configured to: output the first target data corresponding to the first target address according to the first read command in the first command. At this time, the first command does not include a first pre-read command, and there is no need to pre-read the second target data corresponding to the second target address in the storage cell array into the second data buffer.

[0058] like Figure 4 and Figure 5As shown, in some embodiments, the memory 210 is further configured to: receive a second command, the information of the second command including a second target address and a second address offset; the second command includes a second read command and a second pre-read command, and according to the second read command in the second command, output the second target data corresponding to the second target address pre-stored in the second data buffer 213; according to the second pre-read command in the second command, pre-read the third target data corresponding to the third target address in the storage cell array 211 into the second data buffer 213; the third target address is determined based on the second target address and the second address offset, and is different from the second target address.

[0059] Here, the third target address can be determined according to the second target address and the second address offset (i.e., the third target address = the second target address + the second address offset), and the third target address refers to a specific address in the storage cell array. The third target storage cell can be located according to the third target address in the storage cell array, thereby obtaining the third target data stored in the third target storage cell. The memory can receive the second command, read the pre-stored second target data according to the second read command in the second command, and can also pre-read the third target data corresponding to the third target address according to the second pre-read command in the second command.

[0060] At this time, receiving the second command from the memory 210 to outputting the second target data from the memory 210 may include a process of reading and outputting the second target data pre-stored in the second data buffer 213 .

[0061] At this time, after receiving the second command, the memory 210 outputs the second target data and does not output the third target data, and pre-reads the third target data from the storage cell array 211 to the second data buffer 213, so that after the subsequent memory 210 receives a certain command (for example, the third command), the third target data pre-stored in the second data buffer 213 can be output.

[0062] It should be noted that, in the above technical solution, the second target address and the third target address are different, indicating that the second address offset is not 0. The following is a brief description of the case where the second address offset is 0. If the second address offset is 0, the second command includes a second read command, and the memory is configured to: output the second target data corresponding to the second target address according to the second read command in the second command. At this time, the second command does not include a second pre-read command, and there is no need to pre-read the third target data corresponding to the third target address in the storage cell array into the second data buffer.

[0063] refer to Figure 6 , Figure 6 The read delay diagram of the first command of the memory provided by the embodiment of the present disclosure is shown in FIG. Figure 6 As shown in Figure (a), if the first address offset is 0, the first command only includes the first read command and does not include the first pre-read command. The read delay of the first command includes: the sum of the first duration of reading the first target data corresponding to the first target address from the memory cell array to the first data buffer (i.e., array read) and the second duration of reading the first target data from the first data buffer and outputting it (i.e., data buffer 1read), that is, the read delay of the first command refers to the total duration from the memory receiving the first command until the memory outputs the first target data.

[0064] refer to Figure 6 As shown in Figure (b), if the first address offset is not 0, the first command includes a first read command and a first pre-read command. The read delay of the first command includes: the sum of a first duration of reading the first target data from the memory cell array to the first data buffer (i.e., array read) and a second duration of reading the first target data from the first data buffer and outputting it (i.e., data buffer 1read), that is, the read delay of the first command refers to the total duration from when the memory receives the first command until the memory outputs the first target data.

[0065] At this time, since the second target data is not the first target data that needs to be output by the current first command, based on the second target address, the duration of pre-reading the second target data corresponding to the second target address in the storage cell array into the second data buffer (i.e., array read (addr+addr_offset)) will not be included in the read delay of the first command.

[0066] In the embodiment of the present disclosure, after receiving the first command, the memory can output the first target data corresponding to the first target address, and pre-read the second target data corresponding to the second target address; in this way, the memory can read and output the first target data, and pre-read the second target data, after receiving the first command, so as to shorten the subsequent reading delay of the second target data.

[0067] In some embodiments, pre-reading the second target data corresponding to the second target address is performed simultaneously with outputting the first target data corresponding to the first target address; or, pre-reading the second target data corresponding to the second target address is performed after outputting the first target data corresponding to the first target address.

[0068] like Figure 6As shown in Figure (b), pre-reading the second target data corresponding to the second target address and outputting the first target data corresponding to the first target address are performed simultaneously. In the process of pre-reading the second target data corresponding to the second target address, the second target data corresponding to the second target address in the storage cell array needs to be pre-read into the second data buffer; and in the process of outputting the first target data corresponding to the first target address, the first target data corresponding to the first target address in the storage cell array needs to be read into the first data buffer, and the first target data in the first data buffer needs to be output. Therefore, the memory includes at least a first data buffer and a second data buffer, and the first data buffer is different from the second data buffer. In this way, pre-reading the second target data corresponding to the second target address and outputting the first target data corresponding to the first target address can be performed simultaneously.

[0069] In some embodiments, pre-reading the second target data corresponding to the second target address is performed after outputting the first target data corresponding to the first target address. The memory may include only a first data buffer, first using the first data buffer to output the first target data corresponding to the first target address, and then using the first data buffer to pre-read the second target data corresponding to the second target address, and the above two processes may use the same data buffer in turn. Since the duration of pre-reading the second target data corresponding to the second target address will not be included in the read delay of the current command, this can not only simplify the internal structure of the memory, but also will not affect the effect of shortening the read delay in this solution.

[0070] refer to Figure 7 , Figure 7 The read delay diagram of the second command of the memory provided by the embodiment of the present disclosure. Figure 7 As shown in Figure (a), if the second address offset is 0, the second command only includes the second read command and does not include the second pre-read command. The read delay of the second command includes: a third duration of reading the second target data corresponding to the second target address from the second data buffer and outputting (i.e., data buffer 2read), that is, the read delay of the second command refers to the total duration from the memory receiving the second command until the memory outputs the second target data.

[0071] refer to Figure 7 As shown in Figure (b), if the second address offset is not 0, the second command includes a second read command and a second pre-read command. The read delay of the second command includes: a third duration of reading the second target data corresponding to the second target address from the second data buffer and outputting (i.e., data buffer 2read), that is, the read delay of the second read command refers to the total duration from when the memory receives the second command until the memory outputs the second target data.

[0072] At this time, since the third target data is not the second target data that needs to be output by the current second command, based on the third target address, the time required to read the third target data corresponding to the third target address in the storage cell array into the second data buffer (i.e., array read (addr+addr_offset)) will not be included in the read delay of the second command.

[0073] refer to Figure 8 As shown, Figure 8 The timing diagram of the first read command and the second command provided in the embodiment of the present disclosure. Figure 8 As shown in Figure (a), for the first command, the read delay (i.e., RL) includes: a first time duration (i.e., array RL) for reading the first target data (i.e., addr0data) corresponding to the first target address (i.e., addr0) from the storage cell array to the first data buffer, and a second time duration (i.e., DB RL) for reading the first target data (i.e., addr0 data) corresponding to the first target address (i.e., addr0) from the first data buffer and outputting it, that is, the read delay of the first command includes the sum of the first time duration and the second time duration (i.e., RL=array RL+DB RL).

[0074] like Figure 8 As shown in Figure (b), for the second command, the read delay (i.e., RL) includes: reading the second target data (i.e., addr1 data) corresponding to the second target address (i.e., addr1) pre-stored in the second data buffer and outputting it for a third time duration (i.e., DB RL), that is, the read delay of the second read command includes the third time duration (i.e., RL=DB RL); wherein, the second target address=the first target address+the first address offset (i.e., addr1=addr0+addr_offset).

[0075] In the present disclosure, after receiving the first command, the memory outputs the first target data and pre-stores the second target data in the second data buffer. In this way, after receiving the second command, the memory can directly read the second target data pre-stored in the second data buffer without reading the second target data from the storage cell array, thereby shortening the read delay. The memory can also continue to receive the third command and directly read the third target data pre-stored in the second data buffer without reading the third target data from the storage cell array. In this way, the target data pre-stored in the second data buffer last time can be read each time, which can shorten the read delay of each command execution, and is particularly suitable for accessing large-scale continuous addresses.

[0076] The present disclosure has no special limitation on the type of memory, and the read delay can be shortened by setting a second data buffer in the memory to temporarily store target data required for subsequent commands.

[0077] In some embodiments, the memory 210 may include a phase change memory.

[0078] The basic principle of phase change memory is: an electric pulse with a large signal value and a short duration (i.e., high and narrow) is applied to the phase change memory unit. Under the action of Joule heat, a part of the initial crystalline phase change memory layer melts because the temperature is higher than the melting temperature. After the electric pulse is interrupted, the melted part cools rapidly and stays in the amorphous state with low atomic order, thus completing the conversion from low resistance to high resistance. This is the erase (Reset) process. The melted part in this process is called the programming volume. If an electric pulse with a small signal value and a long duration (i.e., low and wide) is applied, so that the temperature in the programming volume reaches above the crystallization temperature and below the melting temperature, and lasts for a sufficient time to crystallize the amorphous structure in the programming volume, a low resistance state is obtained, which is the write (Set) process. The reading process of phase change memory is to apply a low and narrow electric pulse to the phase change memory unit, so that the phase change memory layer is below the crystallization temperature, and the resistance value of the phase change memory unit is measured.

[0079] Phase change memory materials are used as storage media for phase change memory, and their performance directly affects the quality of device characteristics. Usually, the characteristics of phase change memory are mainly measured by indicators such as write operation speed, data retention and switching ratio. Therefore, the performance research of phase change memory materials includes the research of parameters such as crystallization rate, crystallization temperature, amorphous structure stability, thermal stability and resistance window (i.e., the ratio of resistivity of amorphous state to that of crystalline state).

[0080] For phase change memory, among the write operation, erase operation and read operation, the write operation time is generally longer, which becomes the key factor restricting the high-speed operation of phase change memory. The write operation time is related to the crystallization rate of the phase change memory material. The faster the crystallization rate, the shorter the write operation time, and the faster the operation speed of the phase change memory.

[0081] The data retention of phase change memory is determined by the amorphous structure stability and thermal stability of the phase change memory material. The better the amorphous structure stability and thermal stability, the longer the data retention. To obtain better amorphous structure stability and thermal stability, the phase change memory material may be required to have a higher crystallization temperature.

[0082] The switching ratio of phase change memory is determined by the resistance window of the phase change memory material. The resistance window refers to the resistivity difference between the amorphous state and the crystalline state. The resistivity difference between the amorphous state and the crystalline state is large, and the resistance window is large to ensure a large switching ratio, so that data can be read accurately and quickly during the read operation.

[0083] Still refer to Figure 4 As shown, an embodiment of the present disclosure provides a memory system, which includes: a memory 210 and a controller 220 coupled to the memory 210; the controller 220 is configured to: send a first command, and the information of the first command includes a first target address and a first address offset; the memory 210 is configured to: receive the first command, output first target data corresponding to the first target address; and pre-read second target data corresponding to the second target address; the second target address is determined based on the first target address and the first address offset, and is different from the first target address; the controller 220 is also configured to: receive the first target data.

[0084] Here, the memory system 200 may include one or more memories 210. The controller 220 may send a first command (or a second command) to the memory 210 via a command address bus, and the memory 210 may output first target data (or a second target data, a third target data) to the controller 220 via a data bus.

[0085] In some embodiments, the first command includes a first read command and a first pre-read command, and the memory 210 is configured to: output first target data corresponding to the first target address according to the first read command; and pre-read second target data corresponding to the second target address according to the first pre-read command.

[0086] In some embodiments, the memory 210 includes: a memory cell array 211 and a first data buffer 212 and a second data buffer 213 coupled to the memory cell array 211; the memory 210 is configured to: read the first target data corresponding to the first target address in the memory cell array 211 into the first data buffer 212; and output the first target data in the first data buffer 212; and pre-read the second target data corresponding to the second target address in the memory cell array 211 into the second data buffer 213.

[0087] An embodiment of the present disclosure further provides an electronic device, which includes: the memory system in the above technical solution and a host coupled to the memory system.

[0088] Here, the electronic device may include a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a memory therein.

[0089] Here, the host may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host may be configured to send data to or receive data from a memory system.

[0090] Here, the controller is coupled to the memory and the host and is configured to control the memory. The controller can manage data stored in the memory and communicate with the host.

[0091] refer to Fig. 9 , Fig. 9 A flowchart of a method for operating a memory provided in an embodiment of the present disclosure.

[0092] like Fig. 9 As shown, an embodiment of the present disclosure provides a method for operating a memory, and the method includes:

[0093] Step S301: receiving a first command, wherein information of the first command includes a first target address and a first address offset;

[0094] Step S302: outputting first target data corresponding to the first target address;

[0095] Step S303: pre-reading second target data corresponding to the second target address; the second target address is determined based on the first target address and the first address offset, and is different from the first target address.

[0096] In some embodiments, the memory includes: a storage cell array and a first data buffer coupled to the storage cell array; step S302 includes: reading the first target data corresponding to the first target address in the storage cell array into the first data buffer; and outputting the first target data in the first data buffer.

[0097] In some embodiments, the memory includes: a memory cell array and a second data buffer coupled to the memory cell array; step S302 includes: outputting first target data corresponding to a first target address pre-stored in the second data buffer.

[0098] In some embodiments, the memory includes: a memory cell array and a second data buffer coupled to the memory cell array; step S303 includes: pre-reading second target data corresponding to the second target address in the memory cell array into the second data buffer.

[0099] In some embodiments, the memory is further configured to: receive a second command, the second command including a second target address and a second address offset; output second target data corresponding to the second target address pre-stored in a second data buffer; and pre-read third target data corresponding to the third target address in the storage cell array into the second data buffer; the third target address is determined based on the second target address and the second address offset, and is different from the second target address.

[0100] In some embodiments, step S303 is performed simultaneously with step S302; or, step S303 is performed after step S302.

[0101] In some embodiments, the first command includes a first read command and a first pre-read command, and the memory is configured to: output first target data corresponding to the first target address according to the first read command; and pre-read second target data corresponding to the second target address according to the first pre-read command.

[0102] An embodiment of the present disclosure also provides an operating method of a memory system, the memory system comprising: a memory and a controller coupled to the memory; the operating method comprises: the controller sends a first command, the information of the first command comprises a first target address and a first address offset; the memory receives the first command; outputs first target data corresponding to the first target address; and pre-reads second target data corresponding to the second target address; the second target address is determined based on the first target address and the first address offset, and is different from the first target address; the controller receives the first target data.

[0103] refer to Fig.10 , Fig.10 Schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure. Fig.10 As shown, an embodiment of the present disclosure provides a computer-readable storage medium, and the computer-readable storage medium 400 stores a computer program 410. When the computer program 410 is executed, the memory operation method in the above technical solution can be implemented.

[0104] Here, the computer-readable storage medium may include: random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, read-only compact disks (CD-ROMs), or any other form of program code medium known in the technical field.

[0105] The disclosed embodiment provides a memory and a memory system. The memory is configured to: receive a first command, the information of the first command includes a first target address and a first address offset; output first target data corresponding to the first target address; and pre-read second target data corresponding to the second target address; the second target address is determined based on the first target address and the first address offset, and is different from the first target address. In the disclosed embodiment, after receiving the first command, the memory can output the first target data corresponding to the first target address, and pre-read the second target data corresponding to the second target address; in this way, after receiving the first command, the memory can read and output the first target data, and pre-read the second target data, so as to shorten the subsequent reading delay of the second target data.

[0106] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0107] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory is configured as: receiving a first command, wherein information of the first command includes a first target address and a first address offset; outputting first target data corresponding to the first target address; and Pre-reading second target data corresponding to the second target address; The second target address is determined based on the first target address and the first address offset, and is different from the first target address.

2. The memory according to claim 1, characterized in that: The memory comprises: a memory cell array and a first data buffer coupled to the memory cell array; The outputting the first target data corresponding to the first target address includes: reading first target data corresponding to the first target address in the storage cell array into the first data buffer; and The first target data in the first data buffer is output.

3. The memory according to claim 1, characterized in that: The memory comprises: a memory cell array and a second data buffer coupled to the memory cell array; The outputting the first target data corresponding to the first target address includes: The first target data corresponding to the first target address pre-stored in the second data buffer is output.

4. The memory according to claim 2 or 3, characterized in that: The memory comprises: a memory cell array and a second data buffer coupled to the memory cell array; The pre-reading of the second target data corresponding to the second target address includes: Pre-reading second target data corresponding to the second target address in the storage cell array into the second data buffer.

5. The memory according to claim 4, characterized in that: The memory is further configured to: receiving a second command, wherein information of the second command includes a second target address and a second address offset; Outputting the second target data corresponding to the second target address pre-stored in the second data buffer; as well as Pre-reading third target data corresponding to a third target address in the storage cell array into the second data buffer; The third target address is determined based on the second target address and the second address offset, and is different from the second target address.

6. The memory according to claim 1, characterized in that: Pre-reading the second target data corresponding to the second target address and outputting the first target data corresponding to the first target address are performed simultaneously; or, Pre-reading the second target data corresponding to the second target address is performed after outputting the first target data corresponding to the first target address.

7. The memory according to claim 1, characterized in that: The first command includes a first read command and a first pre-read command, and the memory is configured as follows: According to the first read command, output first target data corresponding to the first target address; as well as Pre-read second target data corresponding to the second target address according to the first pre-read command.

8. A memory system, characterized in that: The memory system comprises: the memory according to any one of claims 1 to 7 and a controller coupled to the memory; The controller is configured to: send a first command, wherein information of the first command includes a first target address and a first address offset; The memory is configured to: receive the first command; output first target data corresponding to the first target address; and pre-read second target data corresponding to a second target address; the second target address is determined based on the first target address and the first address offset and is different from the first target address; The controller is further configured to: receive the first target data.

9. The memory system according to claim 8, characterized in that: The first command includes a first read command and a first pre-read command, and the memory is configured as follows: According to the first read command, output first target data corresponding to the first target address; as well as Pre-read second target data corresponding to the second target address according to the first pre-read command.

10. The memory system according to claim 8, wherein: The memory comprises: a memory cell array and a first data buffer and a second data buffer coupled to the memory cell array; The memory is configured as: Reading first target data corresponding to the first target address in the storage cell array into the first data buffer; and outputting the first target data in the first data buffer; Pre-reading second target data corresponding to the second target address in the storage cell array into the second data buffer.

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