Bridge chip, storage device with bridge chip and conversion method

Abstract

The invention provides a bridging chip, a storage device with the bridging chip and a conversion method, the bridging chip is respectively connected with host equipment and a storage unit, and is used for enabling the host equipment to communicate with the storage unit, the chip comprises a communication unit, a data processing unit and a storage unit, the communication unit is connected with the host equipment through a bus interface, and the data processing unit is connected with the storage unit. Receiving first data sent by the host device, the first data being data conforming to a first protocol format; the bridging unit is used for converting the first data sent by the communication unit into target data according to the first protocol and the second protocol, and the target data is data conforming to a second protocol format; the output interface is used for outputting the target data to the storage unit, the problem that in the prior art, a single solid state disk is not universal with storage devices of other specifications due to elimination of the single solid state disk can be solved by using the bridging chip, universality of the storage devices of different specifications is achieved, and the application range of the storage devices of different specifications is widened.

Description

Technical Field

[0001] The present disclosure relates to the field of computer processing technology, and in particular to a bridge chip, a storage device having the bridge chip, and a conversion method. Background Art

[0002] With the continuous innovation of technology, Solid State Drives (SSD) are gradually being phased out due to rising costs, but end users and the market still have a large demand for this low-capacity storage device.

[0003] There are other types of storage devices on the market that can replace solid-state drives, such as Universal Flash Storage (UFS), but they are not universal because of their different specification requirements. Summary of the invention

[0004] The present disclosure provides a bridge chip, a storage device having the bridge chip, and a conversion method, so as to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a bridge chip is provided, wherein the bridge chip is connected to a host device and a storage unit respectively, and is used to enable communication between the host device and the storage unit. The chip comprises: a bus interface,

[0006] A communication unit, receiving first data sent by the host device through the bus interface, wherein the first data is data conforming to a first protocol format;

[0007] a bridging unit, configured to convert the first data sent by the communication unit into target data according to the first protocol and the second protocol, wherein the target data is data conforming to a format of the second protocol;

[0008] An output interface is used to output the target data to the storage unit.

[0009] In one possible implementation, the bridging unit includes: a parsing unit and a control unit, wherein:

[0010] The parsing unit is used to parse the first data according to the first protocol as second data;

[0011] The control unit is connected to the parsing unit, and is used to generate target data from the second data according to the second protocol.

[0012] In one possible implementation, the bridging unit further includes:

[0013] A first storage unit, connected to the communication unit and the parsing unit respectively, and used to store the first data sent by the communication unit;

[0014] The second storage unit is connected to the analyzing unit and the control unit respectively, and is used to store the second data.

[0015] In one embodiment, the chip further includes:

[0016] The processor is used to send a conversion instruction to the bridge unit, so that the bridge unit converts the first data into target data.

[0017] In one possible implementation, the conversion instruction includes a parsing instruction and a generating instruction.

[0018] The processor is specifically used to send a parsing instruction to the parsing unit to extract the first data from the first storage unit and parse it into second data, and store the second data in the second storage unit; and send a generation instruction to the control unit to extract the second data from the second storage unit and generate it as target data.

[0019] In one possible implementation, the first protocol includes a PCIE protocol and an NVME protocol, and the second protocol is a UFS protocol.

[0020] According to a second aspect of the present disclosure, a conversion method is provided, which is applied to a bridge chip, and the method includes:

[0021] Receiving first data sent by the host device, wherein the first data is data conforming to a first protocol format;

[0022] According to the first protocol and the second protocol, the first data is converted into target data and output to a storage unit, wherein the target data is data conforming to a format of the second protocol.

[0023] In one possible implementation, converting the first data into target data according to the first protocol and the second protocol includes: parsing the first data as second data based on a parsing instruction and the first protocol; and generating the second data as target data based on a generating instruction and the second protocol.

[0024] In one possible implementation, the first protocol includes a PCIE protocol and an NVME protocol, and the second protocol is a UFS protocol.

[0025] According to a third aspect of the present disclosure, a storage device having a bridge chip is provided, comprising the bridge chip described above and a storage unit connected to the bridge chip.

[0026] According to a fourth aspect of the present disclosure, a conversion device is provided, which is applied to a bridge chip, and the device includes:

[0027] A receiving module, configured to receive first data sent by the host device, wherein the first data is data conforming to a first protocol format;

[0028] The conversion module is used to convert the first data into target data according to the first protocol and the second protocol, and output the target data to a storage unit, wherein the target data is data conforming to the format of the second protocol.

[0029] In one possible implementation, the conversion module is specifically used to: parse the first data as second data based on a parsing instruction and the first protocol; and generate the second data as target data based on a generating instruction and the second protocol.

[0030] According to a fifth aspect of the present disclosure, there is provided an electronic device, including:

[0031] at least one processor; and

[0032] a memory communicatively connected to the at least one processor; wherein,

[0033] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0034] According to a sixth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method described in the present disclosure.

[0035] The present invention discloses a bridge chip, a storage device having the bridge chip, and a conversion method. The bridge chip is connected to a host device and a storage unit respectively, and is used to enable the host device to communicate with the storage unit. The chip includes: a bus interface, a communication unit, a bridge unit, and an output interface. The communication unit receives first data sent by the host device through the bus interface, wherein the first data is data that conforms to a first protocol format; the bridge unit is used to convert the first data sent by the communication unit into target data according to the first protocol and a second protocol, wherein the target data is data that conforms to a second protocol format; the output interface is used to output the target data to the storage unit. The present application can solve the problem of incompatibility with other storage devices of other specifications caused by the elimination of a single solid-state hard disk in the prior art by using a bridge chip, thereby achieving the versatility of storage devices of different specifications and improving its application scope.

[0036] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:

[0038] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0039] Figure 1 The structure of a bridge chip provided by the embodiment of the present disclosure is shown in FIG. Figure 1 ;

[0040] Figure 2 The structure of a bridge chip provided by the embodiment of the present disclosure is shown in FIG. Figure 2 ;

[0041] Figure 3 The structure of a bridge chip provided by the embodiment of the present disclosure is shown in FIG. Figure 3 ;

[0042] Figure 4 The structure of a bridge chip provided by the embodiment of the present disclosure is shown in FIG. Figure 4 ;

[0043] Figure 5 A schematic diagram of a conversion method provided by an embodiment of the present disclosure is shown;

[0044] Figure 6 A schematic structural diagram of a conversion device provided by an embodiment of the present disclosure is shown;

[0045] Figure 7 A schematic diagram of the structure of a storage device with a bridge chip according to an embodiment of the present disclosure is shown;

[0046] Figure 8 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0047] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0048] At present, low-capacity M.2PCIe SSDs are gradually being phased out due to rising costs. Major mainstream SSD manufacturers are expected to stop supplying 128GB / 256GB low-capacity M.2PCIe SSDs in the next few years, but end users and machines whose mass production projects have not yet been terminated still have a great demand for M.2 low-capacity storage devices. UFS is also increasingly used in personal notebook computers, educational notebooks, etc., but because UFS is a ball grid array (BGA) package, it is directly soldered on the motherboard, which not only brings certain difficulties to the analysis of problems in the notebook R&D and testing phase, but also is not conducive to the asynchronous verification and import of UFS, and also increases the customer's after-sales maintenance costs and the inconvenience of end users' use. It is not convenient to plug, replace and expand the capacity. Therefore, the existing technology is to modularize UFS into an M.2 storage device to achieve reuse with M.2PCIe SSD.

[0049] Among them, M.2 is a hard disk interface that is compatible with Serial Advanced Technology Attachmentsata (SATA) mode and Non-Volatile Memory Express (NVMe) mode; the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) is an interface that is directly connected to the central processing unit (CPU), and can be plugged with various expansion cards such as graphics cards, sound cards, and network cards.

[0050] However, since PCIe SSD and UFS are storage devices with different protocol specifications, PCIe SSD is used to transmit data through 4 LANE channels, and UFS is used to transmit data through 2 LANE channels, they cannot be used interchangeably. Therefore, this embodiment proposes a bridge chip that enables PCIE SSD and UFS to be used interchangeably without making any interface changes to UFS.

[0051] Figure 1 A schematic diagram of a bridge chip provided in an embodiment of the present disclosure Figure 1,like Figure 1 As shown, the bridge chip 10 is connected to the host device 20 and the storage unit 30 respectively, and is used to enable the host device 20 to communicate with the storage unit 30, wherein the bridge chip 10 includes: a bus interface 110, a communication unit 120, a bridge unit 130 and an output interface 140, wherein,

[0052] The communication unit 120 receives first data sent by the host device through the bus interface 110, wherein the first data is data conforming to a first protocol format;

[0053] The bridge unit 130 is used to convert the first data sent by the communication unit 120 into target data according to the first protocol and the second protocol, wherein the target data is data conforming to the format of the second protocol;

[0054] The output interface 140 is used to output the target data to the storage unit.

[0055] The host device may be an electronic device such as a notebook, a computer, or a tablet, and the storage unit may be a storage device with a storage function, such as a solid state drive SSD, a universal flash storage UFS, etc. Exemplarily, the solid state drive may be a low-capacity M.2PCIe SSD, and the communication unit may be configured to meet any communication protocol in the prior art and may receive data sent by the host device. The first data may be data that conforms to the first protocol format.

[0056] Specifically, the bridge chip in this embodiment is connected to the host device and the storage unit respectively, and the communication unit in the bridge chip can be connected to the bus interface to receive the first data sent by the host device. Exemplarily, in the prior art, many host devices send first data that conforms to the PCIE protocol and the NVME protocol. The communication unit can send the received first data to the bridge unit, and the bridge unit can allow memory sharing between different devices and subsystems, perform format conversion, and finally output the target data after format conversion to the storage unit via the output interface. Exemplarily, the bridge unit in this embodiment can convert the first data that conforms to the PCIE protocol and the NVME protocol into target data that conforms to the UFS protocol.

[0057] The present application can solve the problem in the prior art that a single solid-state hard disk is not compatible with other storage devices due to the elimination of the single solid-state hard disk by using a bridge chip, thereby achieving the compatibility of storage devices of different specifications and improving the scope of application thereof.

[0058] Figure 2 A schematic diagram of a bridge chip provided in an embodiment of the present disclosure Figure 2 ,like Figure 2As shown, the bridge unit 130 includes: a parsing unit 131 and a control unit 132, wherein:

[0059] The parsing unit 131 is used to parse the first data according to the first protocol as second data;

[0060] The control unit 132 is connected to the parsing unit, and is used to generate target data from the second data according to the second protocol.

[0061] Since the received first data is data in a certain data format, the parsing unit is used to parse the format of the data format, and the control unit is used to generate data in the required format. Specifically, the bridge unit in this embodiment includes at least a parsing unit and a control unit, and the parsing unit parses the received first data based on the first protocol to obtain the second data, and the control unit generates the target data from the second data using the second protocol.

[0062] Figure 3 A schematic diagram of a bridge chip provided in an embodiment of the present disclosure Figure 3 ,like Figure 3 As shown, the bridging unit 130 also includes: a first storage unit 133, which is connected to the communication unit 120 and the parsing unit 131 respectively, and is used to store the first data sent by the communication unit 120; a second storage unit 134, which is connected to the parsing unit 131 and the control unit 132 respectively, and is used to store the second data.

[0063] The first storage unit 133 and the second storage unit 134 may be random access memory (RAM) or read-only memory (ROM). RAM is used to temporarily store data and can improve data access speed; ROM can store fixed data and programs.

[0064] Specifically, the first storage unit is connected to the communication unit and the parsing unit, respectively, and can store the first data after the communication unit sends the first data for subsequent calls. The second storage unit is connected to the parsing unit and the control unit, respectively, and is used to store the second data, also for the convenience of subsequent calls. It should be noted that the first storage unit can be the same as the second storage unit, or different.

[0065] Figure 4 A schematic diagram of a bridge chip provided in an embodiment of the present disclosure Figure 4 ,like Figure 4As shown, the chip further includes: a processor 150, which is used to send a conversion instruction to the bridge unit 130, so that the bridge unit 130 converts the first data into target data. It should be noted that the processor in this embodiment is connected to other units in the bridge chip. Figure 4 Not shown in FIG.

[0066] The conversion instruction may be an instruction for converting the first data into target data. Specifically, in this embodiment, according to the conversion instruction sent by the processor, the bridge unit is enabled to convert the first data into target data.

[0067] In an embodiment of the present disclosure, the conversion instruction includes a parsing instruction and a generating instruction. The processor is specifically used to send a parsing instruction to the parsing unit to extract the first data from the first storage unit and parse it into second data, and store the second data in the second storage unit; and to send a generating instruction to the control unit to extract the second data from the second storage unit and generate it as target data.

[0068] The parsing instruction may be an instruction for parsing the first data into the second data; and the generating instruction may be an instruction for generating the target data from the second data.

[0069] Specifically, in this embodiment, the processor sends a parsing instruction to the parsing unit, which can extract the first data from the first storage unit, parse the first data into second data according to the first protocol, and store the parsed second data in the second storage unit. In this embodiment, a generation instruction can also be sent to the control unit to extract the second data from the second storage unit and generate the second data into target data according to the second protocol.

[0070] Exemplarily, the storage unit is a UFS storage device, and the UFS storage device includes a unified storage host (UFS Host) and an internal storage device (UFS device), wherein the unified storage host (UFS Host) is responsible for managing and controlling the access and data transmission of the storage device, and the UFS Host includes a UFS host controller (UFS Controller) that supports high-speed data transmission and low power consumption. In this embodiment, the UFS Host can send a parsing instruction to the parsing unit, convert the first data into the second data according to the PCIE protocol and the NVME protocol, and then send a generation instruction to the UFS host controller to extract the second data, and then convert the second data into target data that complies with the UFS protocol.

[0071] This embodiment supports the PCIE to UFS function, which can support both PCIE SSD and M2 UFS at the same time, and is not affected by the platform used. UFS can be used on all platforms that support PCIE, meeting the mass production UFS replacement needs and reducing production costs. At the same time, the bridge chip proposed in this embodiment can not only avoid the risk of UFS line length not meeting the specifications due to the original wiring settings of the motherboard in the current design, but also can avoid occupying the M2 PIN pin, not considering the impact of the path capacitance, and not affecting factory production and service business and other fool-proof requirements.

[0072] Figure 5 This is a flow chart of a conversion method provided by an embodiment of the present disclosure. The method can be executed by a conversion device provided by an embodiment of the present disclosure. The device can be implemented in software and / or hardware. Applied to a bridge chip, the method includes:

[0073] S510. Receive first data sent by the host device, wherein the first data is data conforming to a first protocol format.

[0074] S520: Convert the first data into target data according to the first protocol and the second protocol, and output the target data to a storage unit, wherein the target data is data conforming to a format of the second protocol.

[0075] Among them, the first protocol includes the PCIE protocol and the NVME protocol, and the second protocol is the UFS protocol.

[0076] Among them, the first data in this embodiment can be data that complies with the PCIE protocol and the NVME protocol, and the target data is data that complies with the second protocol format.

[0077] In this embodiment, the received first data may be converted into target data according to the first protocol and the second protocol.

[0078] In the embodiment of the present disclosure, converting the first data into target data according to the first protocol and the second protocol includes: parsing the first data as second data based on a parsing instruction and the first protocol; and generating the second data as target data based on a generating instruction and the second protocol.

[0079] Specifically, this embodiment can parse the first data as the second data based on the first protocol after receiving the parsing instruction; and generate the second data as the target data based on the second protocol after receiving the generating instruction.

[0080] Figure 6 : is a structural schematic diagram of a conversion device provided by an embodiment of the present disclosure, the device specifically comprises:

[0081] The receiving module 610 is configured to receive first data sent by the host device, wherein the first data is data conforming to a first protocol format;

[0082] The conversion module 620 is used to convert the first data into target data according to the first protocol and the second protocol, and output the target data to a storage unit, wherein the target data is data conforming to the format of the second protocol.

[0083] In one possible implementation, the conversion module 620 is specifically used to: parse the first data as second data based on a parsing instruction and the first protocol; and generate the second data as target data based on a generating instruction and the second protocol.

[0084] In the embodiment of the present disclosure, the first protocol includes the PCIE protocol and the NVME protocol, and the second protocol is the UFS protocol.

[0085] Figure 7 is a schematic diagram of a structure of a storage device with a bridge chip provided by an embodiment of the present disclosure, such as Figure 7 As shown, the device comprises:

[0086] A bridge chip 710 and a storage unit 720 connected to the bridge chip.

[0087] Specifically, this embodiment integrates the bridge chip into the storage unit, and can directly use the UFS storage device on all platforms that support the PCIE function, thereby increasing the application scope of the UFS device.

[0088] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0089] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0090] like Figure 8As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0091] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0092] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the conversion method. For example, in some embodiments, the conversion method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the conversion method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the sound effect correction method in any other appropriate manner (e.g., by means of firmware).

[0093] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0094] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0095] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0096] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0097] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0098] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0099] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0100] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0101] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A bridge chip, characterized in that: The bridge chip is connected to the host device and the storage unit respectively, and is used to enable the host device and the storage unit to communicate with each other. The chip includes: a bus interface, a communication unit, a bridge unit and an output interface, wherein: A communication unit, receiving first data sent by the host device through the bus interface, wherein the first data is data conforming to a first protocol format; a bridging unit, configured to convert the first data sent by the communication unit into target data according to the first protocol and the second protocol, wherein the target data is data conforming to a format of the second protocol; An output interface is used to output the target data to the storage unit.

2. The chip according to claim 1, wherein: The bridge unit includes: a parsing unit and a control unit, wherein: The parsing unit is used to parse the first data according to the first protocol as second data; The control unit is connected to the parsing unit, and is used to generate target data from the second data according to the second protocol.

3. The chip according to claim 2, wherein: The bridging unit further comprises: A first storage unit, connected to the communication unit and the parsing unit respectively, and used to store the first data sent by the communication unit; The second storage unit is connected to the analyzing unit and the control unit respectively, and is used to store the second data.

4. The chip according to claim 3, wherein: The chip further comprises: The processor is used to send a conversion instruction to the bridge unit, so that the bridge unit converts the first data into target data.

5. The chip according to claim 4, wherein: The conversion instructions include parsing instructions and generating instructions. The processor is specifically configured to send a parsing instruction to the parsing unit to extract first data from the first storage unit, parse the first data into second data, and store the second data in the second storage unit; And sending a generation instruction to the control unit to extract the second data from the second storage unit to generate the target data.

6. The chip according to claim 5, wherein: The first protocol includes the PCIE protocol and the NVME protocol, and the second protocol is the UFS protocol.

7. A conversion method, applied to a bridge chip, characterized in that: The method comprises: Receiving first data sent by the host device, wherein the first data is data conforming to a first protocol format; According to the first protocol and the second protocol, the first data is converted into target data and output to a storage unit, wherein the target data is data conforming to a format of the second protocol.

8. The method according to claim 7, characterized in that The converting the first data into target data according to the first protocol and the second protocol includes: Parsing the first data based on the parsing instruction and the first protocol as second data; The second data is generated as target data based on the generation instruction and the second protocol.

9. The method according to claim 8, wherein: The first protocol includes the PCIE protocol and the NVME protocol, and the second protocol is the UFS protocol.

10. A storage device having a bridge chip, characterized in that: The invention comprises the bridge chip according to any one of claims 1 to 6 and a storage unit connected to the bridge chip.

Images