Data block cache updating method and device, equipment and storage medium

Abstract

The invention discloses a data block cache updating method and device, equipment and a storage medium, and relates to the technical field of processor cores, and the method comprises the steps: obtaining a data access request for a target chip, and entering a target cache line based on an access address in the data access request to carry out data matching, so as to judge whether the data access request is in a memory access hit or not; if the data access request does not have access hit, judging a data cache running state based on the number of hit identifiers in the target access identifier signal; if the running state of the data cache is a normal running state, determining a first target cache data block based on the lowest hit identifier in the target memory access identifier signal, and if the distance between the hit identifiers in the first target cache data block is smaller than a preset distance threshold value, determining a second target cache data block; and if yes, performing data replacement on the first target cache data block to complete cache data block updating, and performing cache identifier refreshing on each group of cache identifiers of the target chip. In this way, the cache hit rate of the data blocks can be increased.

Description

Technical Field

[0001] The present invention relates to the field of processor core technology, and in particular to a data block cache update method, device, equipment and storage medium. Background Art

[0002] In the field of chip technology development, the performance of processors is affected by two core factors: one is the processor clock frequency and computing throughput, and the other is the data access speed. Thanks to the continuous evolution of Moore's Law, the clock frequency and computing throughput of processors have enabled the core frequency of modern microprocessors to reach 3GHz. However, the data access speed is limited by the requirements of memory access timing, and it usually takes multiple processor clock cycles to complete the reading of data from the memory. Therefore, memory access latency has become a key bottleneck restricting the improvement of processor performance. In order to enhance the memory reading performance of the processor and alleviate the resulting performance limitations, the multi-level cache architecture has become a commonly used storage technology in microprocessor design. This architecture integrates multiple groups of high-speed and low-capacity storage units on the chip, and pre-loads part of the external memory data into these caches, thereby reducing the processor core's access requirements to the external memory, thereby improving the overall processing performance. However, due to the limited physical resources on the chip, the cache storage capacity that can be integrated on the chip is limited. Therefore, how to optimize the selection and replacement strategy of data in the on-chip cache and improve the hit rate of cache data is a problem that needs to be solved. Summary of the invention

[0003] In view of this, the purpose of the present invention is to provide a data block cache update method, device, equipment and storage medium, which can improve the cache hit rate of data blocks. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses a data block cache update method, comprising:

[0005] Obtaining a data access request for a target chip, and entering a target cache line to perform data matching based on an access address in the data access request, so as to determine whether the data access request is a memory hit according to a data matching result;

[0006] If the data access request does not have a memory access hit, determining a target memory access identification signal of the target cache line, and judging whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal;

[0007] If the data cache operation state is a normal operation state, determining a first target cache data block based on the hit flag of the lowest bit in the target memory access identification signal, and obtaining the distance between the hit flags in the first target cache data block;

[0008] If the distance is less than a preset distance threshold, the current data block in the data access request is used to replace the first target cache data block to complete the cache data block update, and the cache identifiers of each group of cache identifiers of the target chip are refreshed based on a preset shift register mechanism.

[0009] Optionally, after entering the target cache line to perform data matching based on the access address in the data access request to determine whether the data access request is a memory hit according to the data matching result, the method further includes:

[0010] If the data access request is a memory hit, the cache identifier corresponding to the cache data block with successful data matching is shifted left and the hit identifier is filled at the last position, and the cache identifiers corresponding to other cache data blocks are shifted left and the hit identifiers are filled at the last position.

[0011] Optionally, determining the target memory access identification signal of the target cache line, and judging whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal, includes:

[0012] Performing a bitwise OR operation on cache identifiers corresponding to cache data blocks of the target cache line to obtain a target memory access identifier signal;

[0013] Obtaining the number of hit identifiers in the target memory access identifier signal, and determining the ratio of the number of hit identifiers to the number of all identifiers in the target memory access identifier signal;

[0014] It is determined whether the quantity ratio is greater than a preset quantity ratio threshold to determine whether the data cache operation state is an initial filling state or a normal operation state.

[0015] Optionally, after judging whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifiers in the target memory access identification signal, the method further includes:

[0016] If the data cache operation state is a preset initial filling state, the current data block in the data access request is stored to the target location based on a preset data filling order, and cache identifiers of each group of cache identifiers of the target chip are refreshed based on a preset shift register mechanism.

[0017] Optionally, after obtaining the distance between the hit identifiers in the first target cache data block, the method further includes:

[0018] If the distance is greater than or equal to a preset distance threshold, selecting a cache data block with the highest identification bit of the hit identifier in the cache identifier from the cache data blocks of the target cache line to obtain a second target cache data block;

[0019] The second target cache data block is replaced with the current data block in the data access request to complete the cache data block update.

[0020] Optionally, the step of selecting, from the cache data blocks of the target cache line, a cache data block having a highest identification bit of a hit identifier in a cache identifier to obtain a second target cache data block includes:

[0021] Determine, among the cache data blocks of the target cache line, the cache data block with the highest identification bit of the hit identification in the cache identification as the candidate data block, and determine whether there is a cache data block whose cache identification does not contain the hit identification among the cache data blocks of the target cache line;

[0022] If there is no cache data block in each cache data whose cache identifier does not include a hit identifier, the to-be-selected data block is determined as the second target cache data block.

[0023] Optionally, after refreshing the cache identifiers of each group of cache identifiers of the target chip based on the preset shift register mechanism, the method further includes:

[0024] Reacquiring the data access request, and entering the access address in the data access request into the target cache line for data matching;

[0025] The cache identifier corresponding to the cache data block with successful data matching is shifted left and the hit identifier is filled at the last position. At the same time, the cache identifiers corresponding to other cache data blocks are shifted left and the hit identifier is filled at the last position.

[0026] In a second aspect, the present application discloses a data block cache updating device, comprising:

[0027] An access request judgment module is used to obtain a data access request for a target chip, and enter a target cache line for data matching based on an access address in the data access request, so as to judge whether the data access request is a memory hit according to a data matching result;

[0028] A cache state determination module, configured to determine a target memory access identification signal of the target cache line if the data access request does not hit a memory access, and determine whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal;

[0029] A hit identifier acquisition module, configured to determine a first target cache data block based on the hit identifier of the lowest bit in the target memory access identifier signal if the data cache operation state is a normal operation state, and acquire the distance between the hit identifiers in the first target cache data block;

[0030] A cache refresh module is used to replace the first target cache data block with the current data block in the data access request to complete the cache data block update if the distance is less than a preset distance threshold, and to refresh the cache identifiers of each group of cache identifiers of the target chip based on a preset shift register mechanism.

[0031] In a third aspect, the present application discloses an electronic device, comprising:

[0032] Memory, used to store computer programs;

[0033] The processor is used to execute the computer program to implement the aforementioned data block cache update method.

[0034] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, wherein the computer program implements the aforementioned data block cache update method when executed by a processor.

[0035] It can be seen that in the present application, a data access request for a target chip is obtained, and based on the access address in the data access request, the target cache line is entered for data matching, so as to determine whether the data access request is a memory access hit according to the data matching result; if the data access request does not have a memory access hit, the target memory access identification signal of the target cache line is determined, and the data cache operating state is determined to be an initial fill state or a normal operating state according to the number of hit identifiers in the target memory access identification signal; if the data cache operating state is a normal operating state, the first target cache data block is determined based on the hit identifier of the lowest bit in the target memory access identification signal, and the distance between the hit identifiers in the first target cache data block is obtained; if the distance is less than the preset distance threshold, the current data block in the data access request is used to replace the data of the first target cache data block to complete the cache data block update, and the cache identifiers of each group of cache identifiers of the target chip are refreshed based on the preset shift register mechanism. In this way, by constructing a cache identifier separately for each cache group in the cache module, and analyzing the data access probability of the data in the cache identifier based on the cache identifier, targeted data update and replacement can be performed. This can retain data with a high memory hit rate, that is, data access intensive, to a certain extent, effectively improving the cache hit rate for data-intensive and non-data-intensive computing tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 A flow chart of a data block cache update method disclosed in this application;

[0038] Figure 2 A schematic diagram of a specific data block cache update architecture disclosed in this application;

[0039] Figure 3 A flow chart of a specific data block cache update method disclosed in this application;

[0040] Figure 4 This is a schematic diagram of the structure of a data block cache update device disclosed in this application;

[0041] Figure 5 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] In the existing cache replacement strategy, the core idea of ​​the LRU (Least Recently Used) replacement mechanism is to give priority to replacing the data blocks that have not been used for the longest time in the cache module, so as to tend to retain the data that has been recently accessed. This strategy conforms to the principle of locality in computer science, that is, the data that has been recently accessed has a higher probability of being accessed again in the future. However, for computing tasks that continuously process new data, the LRU replacement mechanism will cause the cache hit rate to drop significantly, because these tasks frequently access new data, and the invalid data that the LRU replacement mechanism preferentially retains will take up too much cache space. On the other hand, the FIFO (First Input First Output, a first-in-first-out data structure) replacement strategy and the random replacement strategy do not consider the impact of the cache hit history on the replacement decision when selecting replacement data. The FIFO algorithm is based on the first-in-first-out principle and simply replaces the data block that enters the cache earliest, while the random replacement strategy randomly selects a data block for replacement. These two strategies fail to effectively improve the cache hit rate for data-intensive and non-data-intensive computing tasks. Therefore, this application will specifically introduce a data block cache update method that can effectively improve the cache hit rate for data-intensive and non-data-intensive computing tasks.

[0044] See also Figure 1As shown, the embodiment of the present application discloses a data block cache update method, including:

[0045] Step S11: obtaining a data access request for a target chip, and entering a target cache line to perform data matching based on an access address in the data access request, so as to determine whether the data access request is a memory hit according to a data matching result.

[0046] In this embodiment, it should be noted that an independent cache identification set is constructed for each cache group in the cache module. These identifications record in detail the behavior pattern of the cache line in the previous n accesses, including hits, misses, and refresh events. Through this mechanism, the access history of the cache line can be accurately captured, providing a basis for subsequent data analysis. The specific architecture is as follows: Figure 2 As shown. In the traditional set-associative cache structure, cache data is distinguished according to multiple cache lines, and multiple groups of cache data are stored in each cache line. When a memory access signal comes, it first enters the corresponding cache line according to the memory access address to perform data matching to determine whether the memory access signal matches the multiple groups of data in the memory access line. If the data match is successful, it is a memory access hit, and the data of the corresponding group in the memory access line is read. If the data does not match successfully, it is a memory access miss, and the memory access miss information is stored and a data request signal is sent to the advanced cache. When the advanced cache sends back a response signal, it also enters the corresponding cache line according to the memory access address to perform a refresh operation. At this time, one of the multiple groups of cache data in the cache line will be selected according to the corresponding cache replacement strategy, and it will be overwritten and refreshed. When the data refresh is completed, the stored memory access miss signal will be resent, and the corresponding cache line will be entered for secondary data matching and reading.

[0047] In this embodiment, the adaptability is optimized based on the traditional group-connected cache structure, the cache module is divided into a cache data module and a cache identification module, and a data update mechanism for the cache identification is added. That is, a data access request for the target chip is obtained, and the target cache line is entered for data matching based on the access address in the data access request, so as to determine whether the data access request is a memory access hit according to the data matching result. Specifically, when a memory access signal comes and enters the corresponding cache line according to the memory access address, the cache data module sends an identification refresh signal to each group of memory access identifications of the corresponding cache line in the cache identification module; when the memory access signal completes data matching in the corresponding cache line, the cache data module sends identification refresh data to each group of memory access identifications of the corresponding cache line in the cache identification module. When the matching result is a memory access hit, the group of memory access hits in the identification refresh data is 1, and the other groups are 0; when the matching result is a memory access miss, the identification refresh data is all 0. It should be noted here that in the present invention, the hit identifier is 1. In this embodiment, with Figure 2Taking the 4-way set-associated cache structure as an example, when cache line 3 receives a memory access signal, the cache data module sends a mark refresh signal to cache line 3 in the cache identification module; then, the cache data module completes the data matching work of cache line 3 and obtains a data matching result: if the matching result is a memory access miss, the cache data module sends a mark refresh data 4-bit 0000 to the cache identification module; if the matching result is a memory access hit and the hit group identification is 1, the cache data module sends a mark refresh data 4-bit 0100 to the cache identification module.

[0048] In this embodiment, the target cache line is entered for data matching based on the access address in the data access request to determine whether the data access request is a memory hit according to the data matching result, and further includes: if the data access request is a memory hit, the cache identifier corresponding to the cache data block with successful data matching is shifted left and filled with the hit identifier at the last position, and the cache identifiers corresponding to other cache data blocks are shifted left and filled with the hit identifier at the last position. Specifically, the memory access identifier refresh mechanism is a shift register mechanism, that is, the original memory access identifier is shifted left by one position and the highest bit is discarded, and the newly received identifier refresh data is filled to the lowest bit of each group of memory access identifiers. This mechanism can ensure that sufficient cache hit information is retained using the least identifier bit, that is, when a bit of each group of memory access identifiers corresponding to the cache line has a bit of 1, it indicates that the corresponding group of the memory access line has a memory hit, and if a bit of each group of memory access identifiers corresponding to the cache line is all 0, it indicates that the memory access line has a memory miss.

[0049] Step S12: If the data access request does not hit a memory access, determine the target memory access identification signal of the target cache line, and judge whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal.

[0050] In this embodiment, the target memory access identification signal of the target cache line is determined, and the data cache operation state is judged to be the initial filling state or the normal operation state according to the number of hit identifications in the target memory access identification signal, including: performing a bitwise OR operation on the cache identifications corresponding to each cache data block of the target cache line to obtain the target memory access identification signal; obtaining the number of hit identifications in the target memory access identification signal, and determining the number ratio of the number of hit identifications to the number of all identifications in the target memory access identification signal; judging whether the number ratio is greater than a preset number ratio threshold to determine whether the data cache operation state is the initial filling state or the normal operation state. This embodiment determines whether the current data access mode tends to be data-intensive or non-data-intensive computing tasks by identifying and processing each group of memory access identification information maintained in the cache identification module, and then selects a suitable cache replacement strategy in a targeted manner. Specifically, assuming that the cache identification module maintains n memory access information, the bit width of each memory access identification corresponding to each cache line of the cache identification module is n, and the bitwise OR operation of each group of cache identifications in the same cache line can obtain an n-bit wide comprehensive memory access identification signal with cache behavior granularity. Then, by identifying the number of 1s in the n-bit wide comprehensive memory access identification signal, it is determined whether the current cache module is in an initial filling state or a normal operating state.

[0051] In this embodiment, after judging whether the data cache operation state is the initial filling state or the normal operation state according to the number of hit identifiers in the target memory access identification signal, it also includes: if the data cache operation state is the preset initial filling state, the current data block in the data access request is stored to the target position based on the preset data filling order, and the cache identifiers of each group of cache identifiers of the target chip are refreshed based on the preset shift register mechanism. Specifically, if the number of 1s in the n-bit wide comprehensive memory access identification signal is less than n / 2, it means that the current cache module is in the initial filling state. At this time, the cache module has just started to work and there are still cache groups that have not been filled with valid data. Therefore, the dynamic data refresh mechanism at this time preferably refreshes sequentially, that is, fills each group in turn from low to high, to ensure that each group in the cache module is filled with valid data first, and improves the on-chip resource utilization.

[0052] Step S13: If the data cache operation state is a normal operation state, a first target cache data block is determined based on the hit flag of the lowest bit in the target memory access flag signal, and the distance between the hit flags in the first target cache data block is obtained.

[0053] In this embodiment, after obtaining the distance between the hit identifiers in the first target cache data block, it also includes: if the distance is greater than or equal to the preset distance threshold, then from each cache data block of the target cache line, select the cache data block with the highest identification bit of the hit identifier in the cache identifier to obtain the second target cache data block; use the current data block in the data access request to perform data replacement on the second target cache data block to complete the cache data block update. Specifically, the method of selecting the cache data block with the highest identification bit of the hit identifier in the cache identifier from each cache data block of the target cache line to obtain the second target cache data block includes: determining the cache data block with the highest identification bit of the hit identifier in the cache identifier among each cache data block of the target cache line as the to-be-selected data block, and judging whether there is a cache data block in each cache data of the target cache line that does not contain a hit identifier in the cache identifier; if there is no cache data block in each cache data that does not contain a hit identifier in the cache identifier, then determining the to-be-selected data block as the second target cache data block. In actual operation, if the number of 1s in the n-bit wide comprehensive memory access identification signal is greater than or equal to n / 2, it means that the current cache module is in normal operation, and each group in the cache module has valid data. When a cache miss occurs at this time, the corresponding memory access identification group will be found according to the lowest bit of 1 in the comprehensive memory access identification signal, and the distance relationship between the two 1s in the corresponding memory access identification group will be determined. If the distance is less than n / 2, the dynamic refresh mechanism will preferably retain the base of the new data. If the distance is greater than or equal to n / 2, the dynamic refresh mechanism will preferably refresh the base of the new data.

[0054] Step S14: If the distance is less than a preset distance threshold, the first target cache data block is replaced with the current data block in the data access request to complete the cache data block update, and cache identifiers of each group of cache identifiers of the target chip are refreshed based on a preset shift register mechanism.

[0055] In this embodiment, when the distance is less than the preset distance threshold, the dynamic refresh mechanism is selected to preferentially retain the new data base, and the group for data replacement will select the group with the highest 1 signal bit in the corresponding memory access identifier; if the dynamic refresh mechanism preferentially refreshes the new data base, the group for data replacement will select the group with the lowest 1 signal bit in the corresponding memory access identifier.

[0056] In this embodiment, after the cache identifiers of each group of cache identifiers of the target chip are refreshed based on the preset shift register mechanism, it also includes: re-acquiring the data access request, and the access address in the data access request enters the target cache line for data matching; the cache identifier corresponding to the cache data block with successful data matching is shifted left and filled with the hit identifier at the last position, and the cache identifiers corresponding to other cache data blocks are shifted left and filled with the hit identifier at the last position. In the actual operation process, when the data is refreshed, the last memory access miss signal will be received again, and this time the memory access must be a hit. Since the last data refresh selected group 0, each memory access identifier is shifted left by one position and the last position is filled with 1000.

[0057] Next, the above situation will be explained by a specific implementation case of a cache behavior in which a four-way set-connected cache structure and a cache identification module store 8 access information. Figure 3As shown. First, the first memory access request arrives. Since the cache module has not yet worked and there is no valid data, a memory access miss must occur. At the same time, since all memory access identifiers in the cache identification module that has not yet worked are 0, the calculated comprehensive memory access identifier signal is 0000_0000, where the number of 1s is less than 8 / 2=4. Therefore, the cache module is in the initial filling state at this time, and the data refresh is preferably filled in sequence. Therefore, the group for data refresh selects group 0, and each memory access identifier is shifted left by one bit and the last bit is filled with 0000. When the data is refreshed, the last memory access miss signal will be received again, and this time the memory access must be hit. Since the last data refresh selected group 0, each memory access identifier is shifted left by one bit and the last bit is filled with 1000. The second memory access request arrives. If this memory access request is a memory access miss, since the current calculated comprehensive memory access identifier signal is 0000_0001, where the number of 1s is less than 8 / 2=4, the cache module is still in the initial filling state at this time, and the data refresh is preferably filled in sequence. Therefore, the group selected for data refresh is group 1, and each memory access identifier is shifted left by one position and the last position is filled with 0000. When the data refresh is completed, the previous memory access miss signal will be received again, and this time the memory access must be hit. Since the last data refresh selected group 1, each memory access identifier is shifted left by one position and the last position is filled with 0100. If the memory access requests are all memory access misses in the initial filling state, the data is refreshed to group 3 in sequence. Next, if group 0 receives a memory access hit signal, the cache identification module receives the identification refresh data of 1000, and each memory access identifier is shifted left by one position and the last position is filled with 1000. Next, if a cache miss occurs in the cache line, since the currently calculated comprehensive memory access identification signal is 1010_1011, the number of 1s is 5, which is greater than 8 / 2=4, so the cache module is in normal operation at this time, and the lowest bit of 1 comes from group 0, so the distance between the two 1s in the memory access identification in group 0 is judged. Since the memory access identification in group 0 is 1000_0001, the distance between the two 1s is 6, which is greater than 8 / 2=4, so the dynamic refresh mechanism prefers the new data refresh system. And because the lowest bit of the 1 signal in the memory access identification in groups 0-3 is the 0th, 5th, 4th and 1st bit respectively, the group 0 with the lowest refresh value is given priority. At the same time, since it is a memory access miss, each memory access identification is shifted left by one bit and the last bit is filled with 0000. When the data is refreshed, the last memory access miss signal will be received again, and this time the memory access must be hit. Since the last data refresh selected group 0, each memory access identification is shifted left by one bit and the last bit is filled with 1000. Next, if group 0 receives a memory access hit signal, the cache identification module receives the identification refresh data 1000, and each memory access identification is shifted left by one bit and the last bit is filled with 1000.Next, if the cache line has a cache miss again, since the currently calculated comprehensive memory access identification signal is 0101_1011, the number of 1s is 5, which is greater than 8 / 2=4. Therefore, the cache module is in normal operation at this time, and the lowest bit of 1 comes from group 0, so the distance between the two 1s in the memory access identification in group 0 is judged. Since the memory access identification in group 0 is 0000_1011, the distance between the two 1s is 0, which is less than 8 / 2=4, so the dynamic refresh mechanism prefers to retain the base for new data. And because the lowest bit of the 1 signal in the memory access identification in groups 0-3 is the 0th bit, no 1, the 6th bit and the 4th bit, respectively, the group 2 with the highest refresh value is given priority. However, it is worth noting that since there is no 1 in group 1 directly, the priority of group 1 is higher than that of group 2, so the group that is finally refreshed is group 1. At the same time, since it is a memory access miss, each memory access identification is shifted left by one bit and the last bit is filled with 0000. When the data is refreshed, the previous memory access miss signal will be received again, and the memory access must be hit this time. Since the last data refresh selected group 1, each memory access identifier is shifted left by one bit and the last bit is filled with 0100. The subsequent operations are also carried out in sequence.

[0058] It can be seen that in this embodiment, a data access request for a target chip is obtained, and based on the access address in the data access request, the target cache line is entered for data matching, so as to determine whether the data access request is a memory hit according to the data matching result; if the data access request does not have a memory hit, the target memory access identification signal of the target cache line is determined, and the data cache operating state is determined to be an initial fill state or a normal operating state according to the number of hit identifiers in the target memory access identification signal; if the data cache operating state is a normal operating state, the first target cache data block is determined based on the hit identifier of the lowest bit in the target memory access identification signal, and the distance between the hit identifiers in the first target cache data block is obtained; if the distance is less than the preset distance threshold, the first target cache data block is replaced with the current data block in the data access request to complete the cache data block update, and the cache identifiers of each group of cache identifiers of the target chip are refreshed based on the preset shift register mechanism. In this way, by constructing a cache identifier separately for each cache group in the cache module, and analyzing the data access probability of the data in the cache identifier based on the cache identifier, targeted data update and replacement can be performed. This can retain data with a high memory hit rate, that is, data access intensive, to a certain extent, effectively improving the cache hit rate for data-intensive and non-data-intensive computing tasks.

[0059] refer to Figure 4 The embodiment of the present application also discloses a data block cache updating device, including:

[0060] An access request judgment module 11 is used to obtain a data access request for a target chip, and enter a target cache line for data matching based on an access address in the data access request, so as to judge whether the data access request is a memory hit according to a data matching result;

[0061] A cache state determination module 12, configured to determine a target memory access identification signal of the target cache line if the data access request does not hit a memory access, and determine whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal;

[0062] A hit identifier acquisition module 13 is used to determine a first target cache data block based on the hit identifier of the lowest bit in the target memory access identifier signal if the data cache operation state is a normal operation state, and obtain the distance between the hit identifiers in the first target cache data block;

[0063] The cache refresh module 14 is used to replace the first target cache data block with the current data block in the data access request to complete the cache data block update if the distance is less than a preset distance threshold, and refresh the cache identifiers of each group of cache identifiers of the target chip based on a preset shift register mechanism.

[0064] It can be seen that by constructing a cache identifier separately for each cache group in the cache module, and performing targeted data update and replacement based on the data access probability of the data in the cache identifier by identifying and analyzing the cache identifier, data with a high memory hit rate, that is, data access intensive, can be retained to a certain extent, thereby effectively improving the cache hit rate of data-intensive and non-data-intensive computing tasks.

[0065] In some specific embodiments, the data block cache updating device may further include:

[0066] The first identifier filling module is used to shift the cache identifier corresponding to the cache data block with successful data matching to the left and fill the hit identifier at the last position if the data access request hits the memory access, and at the same time shift the cache identifiers corresponding to other cache data blocks to the left and fill the hit identifier at the last position.

[0067] In some specific embodiments, the cache status determination module 12 may specifically include:

[0068] an identification calculation unit, used for performing a bitwise OR operation on the cache identification corresponding to each cache data block of the target cache line to obtain a target memory access identification signal;

[0069] An identification number determination unit, used to obtain the number of hit identifications in the target memory access identification signal, and determine the ratio of the number of hit identifications to the number of all identifications in the target memory access identification signal;

[0070] The operation status judgment unit is used to judge whether the quantity ratio is greater than a preset quantity ratio threshold to determine whether the data cache operation status is an initial filling state or a normal operation state.

[0071] In some specific embodiments, the data block cache updating device may further include:

[0072] The second identification filling module is used to store the current data block in the data access request to the target position based on the preset data filling order if the data cache operation state is a preset initial filling state, and refresh the cache identification of each group of cache identifications of the target chip based on the preset shift register mechanism.

[0073] In some specific embodiments, the data block cache updating device may further include:

[0074] a distance judgment module, configured to select, from the cache data blocks of the target cache line, a cache data block with the highest identification bit of the hit identification in the cache identification to obtain a second target cache data block if the distance is greater than or equal to a preset distance threshold;

[0075] The data replacement module is used to use the current data block in the data access request to perform data replacement on the second target cache data block to complete the cache data block update.

[0076] In some specific embodiments, the distance determination module may specifically include:

[0077] a data block determination unit, configured to determine, among the cache data blocks of the target cache line, a cache data block having a highest identification bit of a hit identification in a cache identification as a candidate data block, and to determine whether there is a cache data block whose cache identification does not contain a hit identification among the cache data blocks of the target cache line;

[0078] The data block determining unit is configured to determine the candidate data block as the second target cache data block if there is no cache data block in each cache data whose cache identifier does not include a hit identifier.

[0079] In some specific embodiments, the data block cache updating device may further include:

[0080] A data matching module, used to reacquire the data access request, and enter the access address in the data access request into the target cache line for data matching;

[0081] The third identifier filling module is used to shift the cache identifier corresponding to the cache data block with successful data matching to the left and fill the hit identifier at the last position, and at the same time shift the cache identifiers corresponding to other cache data blocks to the left and fill the hit identifier at the last position.

[0082] Furthermore, the present application also discloses an electronic device. Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0083] Figure 5 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data block cache update method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0084] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0085] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0086] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the data block cache update method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0087] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed data block cache update method. The specific steps of the method can refer to the corresponding contents disclosed in the aforementioned embodiments, and will not be repeated here.

[0088] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0089] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0090] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0091] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0092] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data block cache update method, characterized in that: include: Obtaining a data access request for a target chip, and entering a target cache line to perform data matching based on an access address in the data access request, so as to determine whether the data access request is a memory hit according to a data matching result; If the data access request does not have a memory access hit, determining a target memory access identification signal of the target cache line, and judging whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal; If the data cache operation state is a normal operation state, determining a first target cache data block based on the hit flag of the lowest bit in the target memory access identification signal, and obtaining the distance between the hit flags in the first target cache data block; If the distance is less than a preset distance threshold, the current data block in the data access request is used to replace the first target cache data block to complete the cache data block update, and the cache identifiers of each group of cache identifiers of the target chip are refreshed based on a preset shift register mechanism.

2. The data block cache update method according to claim 1, characterized in that: After entering the target cache line to perform data matching based on the access address in the data access request to determine whether the data access request is a memory hit according to the data matching result, the method further includes: If the data access request is a memory hit, the cache identifier corresponding to the cache data block with successful data matching is shifted left and the hit identifier is filled at the last position, and the cache identifiers corresponding to other cache data blocks are shifted left and the hit identifiers are filled at the last position.

3. The data block cache update method according to claim 1, characterized in that: The step of determining the target memory access identification signal of the target cache line and judging whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal includes: Performing a bitwise OR operation on cache identifiers corresponding to cache data blocks of the target cache line to obtain a target memory access identifier signal; Obtaining the number of hit identifiers in the target memory access identifier signal, and determining the ratio of the number of hit identifiers to the number of all identifiers in the target memory access identifier signal; It is determined whether the quantity ratio is greater than a preset quantity ratio threshold to determine whether the data cache operation state is an initial filling state or a normal operation state.

4. The data block cache update method according to claim 1, characterized in that: After judging whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifiers in the target memory access identification signal, the method further includes: If the data cache operation state is a preset initial filling state, the current data block in the data access request is stored to the target location based on a preset data filling order, and cache identifiers of each group of cache identifiers of the target chip are refreshed based on a preset shift register mechanism.

5. The data block cache update method according to claim 1, characterized in that: After obtaining the distance between the hit identifiers in the first target cache data block, the method further includes: If the distance is greater than or equal to a preset distance threshold, selecting a cache data block with the highest identification bit of the hit identifier in the cache identifier from the cache data blocks of the target cache line to obtain a second target cache data block; The second target cache data block is replaced with the current data block in the data access request to complete the cache data block update.

6. The data block cache update method according to claim 5, characterized in that: The step of selecting, from the cache data blocks of the target cache line, a cache data block having a highest identification bit of a hit identification in a cache identification to obtain a second target cache data block comprises: Determine, among the cache data blocks of the target cache line, the cache data block with the highest identification bit of the hit identification in the cache identification as the candidate data block, and determine whether there is a cache data block whose cache identification does not contain the hit identification among the cache data blocks of the target cache line; If there is no cache data block in each cache data whose cache identifier does not include a hit identifier, the to-be-selected data block is determined as the second target cache data block.

7. The data block cache updating method according to any one of claims 1 to 6, characterized in that: After refreshing the cache identifiers of each group of cache identifiers of the target chip based on the preset shift register mechanism, the method further includes: Reacquiring the data access request, and entering the access address in the data access request into the target cache line for data matching; The cache identifier corresponding to the cache data block with successful data matching is shifted left and the hit identifier is filled at the last position. At the same time, the cache identifiers corresponding to other cache data blocks are shifted left and the hit identifier is filled at the last position.

8. A data block cache update device, characterized in that: include: An access request judgment module is used to obtain a data access request for a target chip, and enter a target cache line for data matching based on an access address in the data access request, so as to judge whether the data access request is a memory hit according to a data matching result; A cache state determination module, configured to determine a target memory access identification signal of the target cache line if the data access request does not hit a memory access, and determine whether the data cache operation state is an initial filling state or a normal operation state according to the number of hit identifications in the target memory access identification signal; A hit identifier acquisition module, configured to determine a first target cache data block based on the hit identifier of the lowest bit in the target memory access identifier signal if the data cache operation state is a normal operation state, and acquire the distance between the hit identifiers in the first target cache data block; A cache refresh module is used to replace the first target cache data block with the current data block in the data access request to complete the cache data block update if the distance is less than a preset distance threshold, and to refresh the cache identifiers of each group of cache identifiers of the target chip based on a preset shift register mechanism.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the data block cache updating method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the data block cache update method according to any one of claims 1 to 7.

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