System loading method, device and electronic equipment

Abstract

The application provides a loading method, device and electronic equipment of a system, the system comprising a programmable chip and a first memory, the loading method comprising: when the system enters an initialization state, controlling the programmable chip to enter a simulated memory state; when the system completes the initialization state, sending a program loading instruction to the programmable chip; according to the program loading instruction, controlling the programmable chip to cache program data in the first memory and load the program data to the system. By simulating the first memory supported by the first processor through the programmable chip, completing interface configuration, and loading the program data to the system, the support range of the processor boot device is expanded, and the application is suitable for providing a wider range of boot FLASH memories for a specific processor and expanding the support range.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer data processing, and particularly relates to a system loading method and device and electronic equipment. BACKGROUND

[0002] Part of the processor adopts QSPI (Queued Serial Peripheral Interface, a kind of serial peripheral interface technology) interface boot mode, but because the command word or access timing of QSPI FLASH (full name Quad Serial Peripheral Interface Flash, a kind of high-speed serial flash memory) device of different manufacturers is different, therefore the boot program built in the processor is usually only adapted to the FLASH (full name Flash EEPROM, flash memory) of specific model, because the types of domestic QSPI FLASH are less at present, and part of its command word is incompatible with imported products, therefore when domestic design is carried out, the FLASH memory available for selection is very few, and its cost, delivery time, etc. often bring constraints to product development.

[0003] With the increasing demand of weapon equipment development domestication, when the processor using QSPI interface boot mode is used in the project, it is urgent to need a FLASH memory support range expansion method to support more range of domestic FLASH chips.

[0004] Therefore, when the processor adopts QSPI interface boot mode, the FLASH memory available for selection is very few, how to expand the support range of FLASH memory is a technical problem to be solved. SUMMARY

[0005] In a first aspect, the present application provides a system loading method, the system comprising a programmable chip and a first memory, the system loading method comprising: when the system enters an initialization state, controlling the programmable chip to enter an analog memory state; when the system completes the initialization state, sending a program loading instruction to the programmable chip; according to the program loading instruction, controlling the first memory to cache program data, and loading the program data to the system.

[0006] In a second aspect, the present application provides a system loading device, comprising: a control module, configured to control the programmable chip to enter an analog memory state when the system enters an initialization state; a processor transceiver module, configured to send a program loading instruction to the programmable chip when the system completes the initialization state; a loading module, configured to control the first memory to cache program data according to the program loading instruction, and load the program data to the system.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor and a memory, the memory storing programs or instructions executable on the processor, and the programs or instructions, when executed by the processor, implement the steps of the loading method of the system of any of the above embodiments.

[0008] The present application has the following beneficial effects:

[0009] As can be seen from the above solution, the present application provides a loading method of a system, wherein a programmable chip simulates a first memory supported by the programmable chip according to a first processor initialization flow, when the system is initialized, the programmable chip first completes interface configuration, and according to a processor loading instruction, performs command analysis, caches program data stored in the first memory to an internal part, and then loads the program data to the system. The present application realizes expansion of a support range of a processor boot device, is suitable for providing a wider range of boot FLASH memory for a specific processor, expands the support range, and realizes sharing of a FPGA (Field Programmable Gate Array) configuration FLASH and a processor boot FLASH memory, which solves the problem of selection of a domestic device, and effectively reduces product cost. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 Fig. 1 shows a flowchart of a loading method of a system according to an embodiment of the present application;

[0011] Figure 2 Fig. 2 shows another flowchart of a loading method of a system according to an embodiment of the present application;

[0012] Figure 3 Fig. 3 shows a third flowchart of a loading method of a system according to an embodiment of the present application;

[0013] Figure 4 Fig. 4 shows a fourth flowchart of a loading method of a system according to an embodiment of the present application;

[0014] Figure 5 Fig. 5 shows a structural schematic block diagram of a programmable chip according to an embodiment of the present application;

[0015] Figure 6 Fig. 6 shows a structural schematic block diagram of a loading device of a system according to an embodiment of the present application;

[0016] Figure 7 Fig. 7 shows a structural schematic block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0018] like Figure 1 As shown, the present invention provides a system loading method, the system including a programmable chip and a first memory, the system loading method including:

[0019] Step 102: When the system enters the initialization state, control the programmable chip to enter the analog memory state;

[0020] Step 104: When the system completes the initialization process, send a program loading instruction to the programmable chip;

[0021] Step 106: According to the program loading instruction, control the programmable chip to cache the program data in the first memory and load the program data into the system.

[0022] This invention provides a system loading method. The system includes a first processor. When the system enters the initialization state, a programmable chip is controlled to enter a simulated memory state. That is, during the processor loading program initialization phase, the programmable chip simulates the first memory supported by the first processor according to its initialization process. When the system completes the initialization state, the programmable chip first completes interface configuration and performs command parsing according to the program loading instructions of the first processor. Based on the program loading instructions, the programmable chip is controlled to cache the program data stored in the first memory into the dual-port RAM (Random Access Memory) in the programmable chip and load the program data into the system. By simulating the first memory it supports through the programmable chip, and caching the program data stored in the first memory into the programmable chip after entering the simulated memory state, and then loading the program data into the system, the range of supported processor boot devices is expanded. This method is suitable for providing a wider range of boot FLASH memory for specific processors, expanding their support range. It also enables the sharing of FPGA (Field Programmable Gate Array) chip configuration FLASH and processor boot FLASH programs, solving the problem of difficult selection of domestically produced devices while effectively reducing product costs.

[0023] The system comprises a first processor having a QSPI boot interface, the programmable chip is an FPGA chip, the first memory is a FLASH memory, and the first memory comprises a FLASH program. In the above embodiment, further, when the system enters an initialization state, the programmable chip is controlled to enter an emulated memory state, comprising: when the system enters the initialization state, the programmable chip is controlled to enter the emulated memory state according to a preset initialization process.

[0024] In this embodiment, when the system enters the initialization state, the programmable chip enters the emulated memory state according to the preset initialization process, that is, emulates the first memory supported by the first processor to complete interface configuration. By controlling the programmable chip to enter the emulated memory state according to the preset initialization process, the interface configuration can be completed, the command sent by the system can be parsed, and the program data can be loaded to the system, thereby effectively expanding the support range of the processor booting the FLASH memory.

[0025] The specific principle that the programmable chip enters the emulated memory state according to the preset initialization process is that, according to the interface timing requirements of the first processor for the FLASH memory and the parsing of the command word, the program data in the externally expanded FLASH memory is read through a data preloading manner, and the first processor is made to believe that the read data is the FLASH memory supported by the first processor according to the timing and result required by the first processor.

[0026] In the above embodiment, further, as shown in Figure 2 According to the program loading instruction, the first memory is controlled to cache the program data and load the program data to the system, comprising:

[0027] Step 202: In an idle period, the programmable chip is controlled to cache the program data in the first memory according to the read timing in the program loading instruction;

[0028] Step 204: After the idle period ends, the programmable chip is controlled to send the cached program data to the system according to the read timing.

[0029] In this embodiment, in the idle period, the programmable chip is controlled to cache the program data in the first memory according to the read timing in the program loading instruction, that is, the QSPI idle period (DUMMY Cycle) is utilized, the program data is preloaded and cached according to the read timing of the newly expanded FLASH, and the program data is cached in the programmable chip; after the idle period ends, the program data is preloaded, the programmable chip is controlled to send the cached program data to the system according to the read timing, and the loading is completed until the loading of the FLASH program is completed.

[0030] In the above embodiment, further, when the system enters the initialization state, the control programmable chip enters the simulation memory state according to the preset initialization process: the control programmable chip is loaded to start the programmable chip.

[0031] In this embodiment, when the system is initialized, the control programmable chip is loaded to start the programmable chip, specifically, the programmable chip is loaded from address 0. It ensures that the programmable chip can be normally started and configured.

[0032] In the above embodiment, further, after the control programmable chip is loaded to start the programmable chip, it further includes: according to the startup process of the system, the control programmable chip is controlled to perform the first communication mode conversion.

[0033] In this embodiment, according to the startup process of the system, the control programmable chip is controlled to perform the first communication mode conversion, that is, the programmable chip is initialized to the single-wire SPI mode (Serial Peripheral Interface, SPI mode), to realize the parsing of the command issued by the system. This ensures the stability of the communication and prepares for the subsequent data loading.

[0034] Specifically, since the QSPI interface can work in different modes such as single-wire SPI and four-wire QSPI, the first processor built-in loading program will configure the single QSPI controller of the first processor to the single-wire SPI mode. Therefore, in the initial stage of the programmable chip, in order to normally parse the command of the first processor, the programmable chip needs to be initialized to the single-wire SPI mode.

[0035] In the above embodiment, further, as shown in Figure 3 According to the startup process of the system, after the control programmable chip is controlled to perform the first communication mode conversion, it further includes:

[0036] Step 302: the system sends an idle cycle instruction to the programmable chip;

[0037] Step 304: the programmable chip performs the second communication mode conversion according to the idle cycle instruction.

[0038] In this embodiment, after the programmable chip receives the idle cycle instruction issued by the system, it starts to perform the second communication mode conversion on the programmable chip, that is, the programmable chip is updated from the single-wire SPI mode to the four-wire QSPI mode. The four-wire QSPI mode can support more efficient data transmission and improve the performance of the system.

[0039] It can be understood that, in order to normally parse the command of the first processor, the programmable chip needs to be initialized to the four-wire QSPI mode, which can more efficiently perform data transmission and improve the performance of the system.

[0040] In the above embodiments, after the programmable chip performs a second communication mode conversion according to the idle cycle instruction, it further includes: initializing the first memory.

[0041] In this embodiment, the first memory is initialized according to the first processor's QSPI boot process and the selected FLASH type. If QSPI FLASH is used, its interface bit width, read latency, etc. are configured.

[0042] After the first processor of the system completes the initialization of its QSPI interface, the programmable chip changes the communication mode through programming. Then, the first processor completes its configuration according to the corresponding command of the selected QSPI FLASH chip, so that it can adapt to subsequent read and write operations.

[0043] In the above embodiments, further, as Figure 4 As shown, after sending the program loading instruction to the programmable chip, the following steps are included:

[0044] Step 402: The programmable chip parses the program loading instructions;

[0045] Step 404: If the program loading instruction is a boot instruction, remap the system addresses.

[0046] In this embodiment, the programmable chip parses the program loading instructions. If the program loading instruction is a boot instruction, the system address is remapped. The boot instruction signifies the start of the boot phase. The system parses commands according to a preset command table. Each command corresponds to a specific operation or function. When 0xB is parsed, it marks the start of the boot phase.

[0047] Specifically, the system's processor address starts from 0. The programmable chip remaps this address to the boot base address by adding a boot offset address. By adding a boot offset address, the programmable chip remaps the first processor address from 0 to the boot base address. This ensures that the first processor can correctly access and configure the FLASH memory without conflicting with the programmable chip's configuration, thus guaranteeing the system's stability and reliability.

[0048] like Figure 5 The diagram shows a schematic of the programmable chip 520. In a specific embodiment of the loading method for the system provided by this invention, the programmable chip is connected to a first processor 510 and a first memory 530, respectively. The first processor has a QSPI boot interface, the programmable chip is an FPGA chip, and the first memory is a FLASH memory including a FLASH program. The programmable chip includes a dual-port RAM, a FLASH read / write module, and a QSPI command parsing module.

[0049] For the first processor with QSPI boot interface, its boot loading process can be generally divided into three stages:

[0050] First stage: QSPI FLASH initialization;

[0051] The first processor initializes the configuration of the first memory, such as interface bit width, idle cycle number setting, etc.

[0052] Second stage: Boot program loading stage.

[0053] Third stage: Boot program execution, loading and executing application program.

[0054] The following takes the first processor with QSPI boot interface, boot FLASH memory selecting general parallel FLASH and sharing with FPGA chip configuration FLASH as an example for detailed description.

[0055] The starting flow of the first processor is shown in Table 1.

[0056] Table 1 QSPI starting flow of the first processor

[0057] Step Processor CPU issues command 1 Chip pull low 2 SCK = 25M 3 Send FLASH write enable command in single line mode 06H 4 SCK = 12.5M 5 Send "switch to quad mode" command in single line mode 61H + 1FH 6 Quad mode set to fast read, 10 DUMMY 81H + AFH 7 Read data 0BH + address (from 0 address) 8 Receive 256 bytes 9 Address + 100H, repeat steps 7-9 18 times

[0058] Since the boot FLASH memory and the FPGA chip configuration FLASH program are both loaded from the 0 address by default, in order to realize their sharing, the FLASH address needs to be remapped by the FPGA chip, and the QSPI command (i.e. program loading command) parsing flow is as follows:

[0059] 1. Initialization stage

[0060] 1) Complete FPGA loading from 0 address;

[0061] 2) According to the processor starting flow, initialize to single line SPI mode;

[0062] 3) Wait for the four-line command to be converted to four-line QSPI mode;

[0063] 4) After receiving the set idle (DUMMY) cycle command, allow QSPI output.

[0064] 2. Boot stage

[0065] 1) According to the QSPI command parsing of Table 2, initiate corresponding data transmission. Among them, 0xB command corresponds to boot stage, and the processor address starts from 0, and the FPGA chip remaps it to boot base address (such as 0x400000) by increasing the boot offset address;

[0066] 2) FLASH read-write module completes FLASH data reading and writes into the cache dual-port RAM according to the transmission command and general FLASH access timing;

[0067] 3) After the idle period, data is read from the cache according to the QSPI read timing, and data loading is realized.

[0068] Table 2: Transmission command of FLASH memory

[0069]

[0070] The transmission request of the FLASH memory is shown in Table 2, and the corresponding transmission request is initiated by analyzing the command in the table.

[0071] 3. Boot program execution stage

[0072] 1) The boot program uses a custom FLASH read command (0xC) to realize remaining program data reading, and the reading address is the actual address (no address remapping is required). The remaining address space after FPGA chip configuration storage is used as the program data storage of the first processor, and the address mapping is used to ensure that no storage space conflict occurs, thereby realizing the sharing of the two.

[0073] 2) Repeat reading until loading is completed;

[0074] 3) Execute the application program.

[0075] 4. Other FLASH read-write access

[0076] 1) Read operation: read transmission is initiated by a read FLASH command; the FLASH read-write module preloads data to the cache; after the idle period, read data is obtained from the dual-port RAM according to the QSPI timing and is output;

[0077] 2) Erase operation: erase transmission is initiated by a custom erase command (0x10), and the FLASH read-write module completes actual erasing according to the actual selected FLASH chip.

[0078] 3) Write operation: the write operation is divided into two steps of write buffer (0x20) and program FLASH (0x21), that is, data is first written to the dual-port RAM for buffering, and then 0x21 is used to start programming;

[0079] 4) State register operation: FLASH BUSY state (FLASH busy state) acquisition or write protection and other operations can be realized by state register access.

[0080] According to one specific embodiment of the application, a processor boot FLASH memory support range expansion method is provided, and the specific steps are as follows:

[0081] 1) FPGA chip configuration loading from 0 address;

[0082] 2) After loading, the first processor is reset;

[0083] 3) According to the QSPI boot flow of the first processor and the selected FLASH memory, the first processor initializes the FLASH memory, such as QSPI FLASH, the interface bit width, read delay, etc. are configured;

[0084] The process of initializing the FLASH memory by the first processor is to configure the extended FLASH. If QSPI FLASH is used, it needs to be configured according to the processor boot flow, such as idle period, interface bit width, etc. According to the corresponding command of the selected QSPI FLASH chip, its configuration is completed to make it adapt to the subsequent read and write operations. If BPI FLASH is used, reset processing is performed to ensure that it is in read mode.

[0085] 4) The first processor reset signal is removed;

[0086] 5) The first processor boot command is parsed until initialization is completed;

[0087] 6) Enter the boot stage and respond to the FLASH read command of the first processor;

[0088] 7) The FPGA chip increases the offset address to remap the loading address to the location of the boot data;

[0089] 8) Use the idle period when reading through the QSPI boot interface to read the program data in the FLASH memory and cache it to the dual-port RAM;

[0090] The idle period refers to the time the first memory needs to wait before receiving the next command.

[0091] 9) After the DUMMY period ends, read data from the cache according to the QSPI read timing to realize data loading;

[0092] 10) After loading is completed, use the custom QSPI command to read, erase, program, get BUSY state, and write protect the program data in the FLASH memory through the FPGA chip and the dual-port RAM cache.

[0093] The loading method of the system provided by the embodiment relates to processor boot device support range expansion, is suitable for providing a wider range of boot FLASH memory for a specific processor, and expands the support range thereof.

[0094] As shown in Figure 6 The loading device 600 of the system provided by the embodiment includes a control module 610, a processor transceiver module 620, and a loading module 630.

[0095] The loading device of the system provided by the embodiment includes a control module, a processor transceiver module, and a loading module, wherein the programmable chip simulates the first memory supported thereby according to the first processor initialization flow, when the system is initialized, the programmable chip first completes interface configuration, and according to the processor loading instruction, performs command analysis, caches the program data stored in the first memory to the inside, and then loads the program data to the system.

[0096] As shown in Figure 7 The electronic device 700 provided by the embodiment includes a processor 710 and a memory 720.

[0097] The electronic device provided by the embodiment includes a processor and a memory, the memory stores a program or instruction executable on the processor, and the program or instruction is executed by the processor to implement the steps of the loading method of the system of any one of the above embodiments.

[0098] In order to meet the loading and booting requirements of the processor with the QSPI interface, the FPGA chip is used to expand the FLASH program, and the processor interacts with the FPGA chip, so that the FLASH program can use the general FLASH, including the QSPI FLASH, the SPI FLASH (Serial Peripheral Interface Flash, a non-volatile memory based on the serial peripheral interface protocol) or the parallel FLASH. When the FLASH program supporting the FPGA chip configuration is selected, the FPGA chip configuration FLASH memory and the first processor booting FLASH program can be shared.

[0099] In the loading program initialization stage of the first processor, the FPGA chip simulates the FLASH program supported by the processor according to the initialization flow of the FPGA chip, and completes the interface configuration, such as the SPI single-wire access to the QSPI four-wire access; after the initialization is completed, the FPGA chip responds to the FLASH read command of the processor, and uses the idle period of the QSPI to perform the data preloading and caching according to the read timing of the new expanded FLASH program; when the idle period is ended, the program data is outputted from the cache according to the QSPI command read timing issued by the processor during the data preloading, until the loading is completed, and the FLASH program loading is completed.

[0100] The booting FLASH program expansion method based on the FPGA chip effectively expands the support range of the processor booting FLASH program with the QSPI interface, and realizes the sharing of the FPGA chip configuration FLASH memory and the first processor booting FLASH program. While solving the selection problem of the domestic device, the product cost can also be effectively reduced.

[0101] The above is the preferred embodiment of the present application, and it should be pointed out that, for the ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A method of loading a system, characterized by, The system comprises a programmable chip and a first memory, and a loading method of the system comprises: When the system enters an initialization state, the programmable chip is controlled to enter an analog memory state; When the system completes the initialization state, a program loading instruction is sent to the programmable chip; According to the program loading instruction, the programmable chip is controlled to cache program data in the first memory and load the program data to the system.

2. The loading method of the system according to claim 1, characterized in that, When the system enters the initialization state, the programmable chip is controlled to enter the analog memory state according to a preset initialization process. When the system enters the initialization state, the programmable chip is controlled to enter the analog memory state according to a preset initialization process.

3. The loading method of the system according to claim 1, characterized in that, According to the program loading instruction, the programmable chip is controlled to cache program data in the first memory and load the program data to the system. In an idle period, the programmable chip is controlled to cache program data in the first memory according to a read timing sequence in the program loading instruction; After the idle period ends, the programmable chip is controlled to send the cached program data to the system according to the read timing sequence.

4. The loading method of the system according to claim 1, characterized by, The programmable chip is controlled to enter the analog memory state according to the preset initialization process. The programmable chip is controlled to load to start the programmable chip.

5. The loading method of the system according to claim 4, characterized in that, After the programmable chip is controlled to load to start the programmable chip, the following further comprises: According to a start process of the system, the programmable chip is controlled to perform a first communication mode conversion.

6. The loading method of the system according to claim 5, characterized in that, After the programmable chip is controlled to perform the first communication mode conversion according to the start process of the system, the following further comprises: The system sends an idle period instruction to the programmable chip; The programmable chip performs a second communication mode conversion according to the idle period instruction.

7. The loading method of the system according to claim 6, characterized in that, After the programmable chip performs the second communication mode conversion according to the idle period instruction, the following further comprises: The system initializes the first memory.

8. The loading method of the system according to claim 1, characterized by, After the program loading instruction is sent to the programmable chip, the following further comprises: The programmable chip parses the program loading instruction; If the program loading instruction is a boot instruction, the address of the system is remapped.

9. A system loading apparatus characterized by comprising: The system comprises a programmable chip and a first memory, and the loading device comprises: A control module is configured to control the programmable chip to enter an analog memory state when the system enters an initialization state; A processor transceiver module is configured to send a program loading instruction to the programmable chip when the system completes the initialization state; A loading module is configured to control the programmable chip to cache program data in the first memory and load the program data to the system according to the program loading instruction.

10. An electronic device, comprising: The system comprises a programmable chip and a first memory, and the loading device comprises: A processor and a memory, wherein the memory stores a program or an instruction executable on the processor, and the program or the instruction is executed by the processor to implement the steps of the loading method of the system according to any one of claims 1 to 8.

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