Method and device for realizing initialization of distributed configuration chip in chip system verification
By defining queue FIFO and objective functions in basic use cases, the distributed configuration initialization of the chip system is solved, and the efficiency and quality of chip system verification is improved.
Patent Information
- Application Number
- CN202510103375.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-13
AI Technical Summary
In the verification of chip systems, the traditional chip initialization configuration process is cumbersome and redundant, resulting in a decrease in verification rate and quality. Especially in different scenarios and test cases, page table space and addresses need to be frequently managed and allocated.
By defining a global queue FIFO and an objective function in the basic use cases, collecting and managing common initialization configuration items of the chip system, realizing distributed configuration chip initialization, simplifying the configuration process of scenario use cases.
This greatly simplifies the initial configuration process in chip system verification, improves verification efficiency and quality, allows free addition or deletion of configuration items, and adjusts their order without paying attention to storage space management and page table address allocation.
Smart Images
Figure CN119987878A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip verification, and relates to a method and device for implementing distributed configuration chip initialization in chip system verification. Background Art
[0002] In chip design, there are usually some initialization settings that can be configured at the factory, such as the size allocation of flash memory, the selection of clock sources, or whether certain modules should be enabled, etc. The purpose of this is to allow designers to distinguish different chip versions or models, or to provide customized configurations for different users, etc. This is a common design method in chip design. These configurations are usually flashed to flash or other non-volatile storage spaces before power-on, and are configured by DMA (Direct Memory Access) or CPU and other hosts after the chip is started. In the verification of the chip system, not only one initialization setting is configured, because there are corresponding different configurations in different scenarios, so all settings and their combinations need to be configured to cover the verification.
[0003] In the verification of the chip system, different scenarios may be implemented by corresponding test cases, and even by different verification personnel. However, the configuration initialization process is not only to configure the target address and data, but also to write the address and data of the configuration item into the page table in the format, allocate the page table address, and then write the data and page table to the corresponding storage space. In this way, after the chip is started, the host can correctly execute the configuration according to the preset. When there are multiple configuration items, there are also multiple data and page tables, and there is also a sequence, so it is necessary to manage the address and allocate the space of the page table space, address and data.
[0004] However, these allocations and managements need to be implemented by centralizing all configuration items, while the configuration items in different scenarios are distributed among different test cases or different verifiers. If the test case of each scenario manages the page table and data of its initialization configuration items, each test case is required to perform management and allocation operations. At the same time, if the configuration items of this scenario are added or deleted, the management and allocation of storage space will affect other test cases and scenarios because it is necessary to manage some common initialization configuration items on the system. Such processing is not only cumbersome but also redundant, which reduces the verification rate and quality. Summary of the invention
[0005] In response to the problems existing in the above-mentioned traditional technologies, the present invention proposes a method for implementing distributed configuration chip initialization in chip system verification and a device for implementing distributed configuration chip initialization in chip system verification, which can greatly improve the verification rate and quality of the chip system.
[0006] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a method for implementing distributed configuration chip initialization in chip system verification is provided, comprising the steps of: Call a global queue FIFO defined in the basic use case and define a target function; the queue FIFO is used to collect all configuration items in the chip system verification, and the function interface of the target function only retains the target address and data that need to be configured; Call the target function through the basic use case to configure the common initialization configuration items, collect the common initialization configuration items in the chip system, and push the target address and data that need to be configured for the common initialization configuration items into the queue FIFO; Call the target function through the basic use case to perform space allocation and page table address allocation according to the target address and data of the configuration item in the queue FIFO; The target function is called through the basic use case to flush the target address and data of the allocated configuration item into the corresponding storage space.
[0007] In one of the embodiments, if the scenario use case derived from the base use case does not require common initialization configuration items, then after overloading and rewriting the target function, a derivable derived task is executed; the derived task is left to the derived scenario use case to execute the overload to implement the initialization configuration items in the scenario where the derived scenario use case is located.
[0008] In one of the embodiments, the target function uniformly flushes the target address and data of the allocated configuration items into the corresponding storage space through the backdoor.
[0009] On the other hand, a device for implementing distributed configuration chip initialization in chip system verification is also provided, including: The initial definition module is used to call a global queue FIFO defined in the basic use case and define a target function; the queue FIFO is used to collect all configuration items in the chip system verification, and the function interface of the target function only retains the target address and data that need to be configured; The common collection module is used to call the target function to configure the common initialization configuration items through the basic use case, collect the common initialization configuration items in the chip system, and push the target address and data to be configured for the common initialization configuration items into the queue FIFO; Configuration allocation module, used to call the target function through the basic use case to perform space allocation and page table address allocation according to the target address and data of the configuration item in the queue FIFO; The resource flushing module is used to call the target function through the basic use case to flush the target address and data of the allocated configuration item into the corresponding storage space.
[0010] In one of the embodiments, the implementation device of the distributed configuration chip initialization in the above-mentioned chip system verification also includes a reload module, which is used to execute a derivable derived task after overloading and rewriting the target function when the scenario use case derived from the basic use case does not need a common initialization configuration item; the derived task is left to the derived scenario use case to execute the overload to implement the initialization configuration items in the scenario where the derived scenario use case is located.
[0011] One of the above technical solutions has the following advantages and beneficial effects: The implementation method and device of distributed configuration chip initialization in the above chip system verification, by defining a global queue FIFO and a target function in the basic use case, collaboratively realizes the collection of common initialization configuration items in the chip system, and pushes the target address and data required for the initialization configuration items into the queue FIFO, so that in the scenario use case, only the target address and data of the configuration items need to be paid attention to, and the number of initialization configuration items can be freely added or deleted, and the order can be adjusted at will, without paying attention to the storage space management of the configuration items themselves and the address allocation of the page table, nor is there any need to consider the impact on the common initialization configuration items. Therefore, the cumbersome configuration part can be unified in the basic use case to complete the execution, which greatly simplifies the process operation of the scenario use case on the initialization configuration items, thereby greatly improving the verification efficiency and quality of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0013] Figure 1 A schematic flow chart of a method for implementing distributed configuration chip initialization in chip system verification in one embodiment; Figure 2 A schematic diagram of the implementation principle of a method for implementing distributed configuration chip initialization in chip system verification in an embodiment, wherein (a) is a flowchart of a basic use case implementation, and (b) is a schematic diagram of pushing a target address and data into a queue FIFO; Figure 3 A schematic diagram of a module framework of an implementation device for distributed configuration chip initialization in chip system verification in an embodiment. DETAILED DESCRIPTION
[0014] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0015] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.
[0016] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.
[0017] This manual provides a distributed configuration chip initialization method. In the test cases of different scenarios, the respective verification personnel can only focus on the content of the configuration items in the scenario itself, and do not need to take into account the page table address management, storage space allocation, management and burning in the entire initialization setting. These will be completed uniformly in the background and will not be visible in the respective distributed test cases, making the initialization setting simple and convenient in the verification of the chip system.
[0018] In one embodiment, Figure 1 As shown, a method for implementing distributed configuration chip initialization in chip system verification is provided, which may include the following steps S10 to S16: S10, calling a global queue FIFO defined in the basic use case and defining a target function; the queue FIFO is used to collect all configuration items in the chip system verification, and the function interface of the target function only retains the target address and data that need to be configured; S12, calling the target function through the basic use case to configure the common initialization configuration items, collecting the common initialization configuration items in the chip system, and pushing the target address and data to be configured for the common initialization configuration items into the queue FIFO; S14, calling the target function through the basic use case to perform space allocation and page table address allocation according to the target address and data of the configuration item in the queue FIFO; S16, calling the target function through the basic use case to flush the target address and data of the allocated configuration item into the corresponding storage space.
[0019] It can be understood that in the design of the chip, the steps of configuring the initialization settings can be generally divided into three steps: first, determine the configuration items that need to be initialized; second, manage the addresses of each page table in order and allocate storage space, etc.; finally, flush the page table and data to the storage space according to the allocated address.
[0020] In this embodiment, a global FIFO (First Input First Output) is defined in the base test case (base_test), and the FIFO is used to collect all configuration items. Figure 2 As shown in (b), define an objective function to achieve Figure 2 In (a) "Configure initialization configuration items", the interface of the target function only retains the target address (addr) and data (data) that need to be configured. The target function implements pushing the target address and data into the queue FIFO. Figure 2 The target function add_init_cfg in (b) is used to push the target address addr0 and data data0 of the initialization configuration item into the queue FIFO. This is one of the push examples. The push of the target address and data of other initialization configuration items is understood in the same way.
[0021] Among them, the base case (base_test) is a general test case or basic framework that serves as the basis for other test cases or functional modules. It usually contains some general settings, initialization operations and basic test logic. Other specific test cases can inherit or be built based on this base case to achieve code reuse and ensure the consistency and standardization of the test. FIFO is a data structure, like a queue. It follows the principle that the first data in is taken out first. The data enters the queue from one end (the end of the queue) and is taken out from the other end (the head of the queue). It is similar to the queuing phenomenon in life. The first person in line is served first. In the verification of the chip system, FIFO can be used for scenarios such as caching data, processing message queues and task scheduling to ensure that data or tasks are processed in the order they arrive, avoiding data confusion or processing order errors. Global means that the scope of this FIFO data structure is the entire test case set or the scope of the relevant program module, rather than being limited to a specific function or class. In the verification project of the entire chip system, as long as it is within the corresponding scope, it can be accessed and operated anywhere, which facilitates the sharing and transmission of data between different parts.
[0022] Specifically, Figure 2 (a) shows the flowchart of the basic use case. First, configure the common initialization configuration items, collect the common initialization configuration items in the chip system, and push the target address and data that need to be configured into the queue FIFO. In this way, the target address and data that need to be configured for the initialization configuration items are pushed into the queue FIFO, while the initialization configuration items are written in the basic use case. In this way, distributed configuration is realized in the scenario use case, and the target addresses and data of all initialization configuration items are collected in the basic use case. Then, according to the contents of all configuration items in the queue FIFO and the available storage space of the entire chip system, reasonable page table addresses and data addresses can be allocated. The specific allocation method can be operated according to the actual chip requirements. Finally, the allocated target addresses and data are unified and then flushed into the corresponding storage space through the backdoor or other interface.
[0023] The implementation method of distributed configuration chip initialization in the above chip system verification is to define a global queue FIFO in the basic use case and define a target function to collaboratively realize the collection of common initialization configuration items in the chip system, and push the target address and data required for the initialization configuration items into the queue FIFO, thus realizing the distributed configuration chip initialization in scenario use cases (such as Figure 2In the use cases 0 to n in the example, you only need to pay attention to the target address and data of the configuration items. You can freely add or delete the number of initialization configuration items and adjust the order at will. You do not need to pay attention to the storage space management of the configuration items themselves and the address allocation of the page table, nor do you need to consider the impact on the public initialization configuration items. Therefore, the cumbersome configuration parts can be unified in the basic use cases to complete the execution, which greatly simplifies the process operation of the scenario use cases on the initialization configuration items, thereby greatly improving the verification efficiency and quality of the chip system.
[0024] In one embodiment, Figure 2 As shown, if the scenario use case derived from the base use case does not require common initialization configuration items, then after overloading and rewriting the target function, a derivable derived task is executed; the derived task is left to the derived scenario use case to execute the overload to implement the initialization configuration items in the scenario where the derived scenario use case is located.
[0025] It can be understood that in this embodiment, if the derived use case does not require a common initialization configuration item, the target function can also be overloaded and rewritten. Then, a derivable task is executed, and the task is left to the derived use case to perform overloading, and the content of the overloading implementation is to configure the initialization configuration item in the use case scenario; in this way, the target address and data of the initialization configuration item of the use case are also pushed into the queue FIFO, but the initialization configuration item is written in the derived scenario use case, so that distributed configuration is also realized in the scenario use case, but the target addresses and data of all initialization configuration items are collected in the basic use case, which is more flexible, thereby further improving the verification rate and quality of the chip system.
[0026] In one embodiment, the target function uniformly flushes the target address and data of the allocated configuration items into the corresponding storage space through the backdoor.
[0027] It can be understood that in this embodiment, a target function can be set to uniformly flash the target address and data of the assigned configuration items into the corresponding storage space through the backdoor, thereby eliminating the need for configuration of other interfaces. The target address and data are uniformly input into the corresponding storage space through the backdoor, and the verification personnel no longer need to consider the configuration of the flashing method, thereby further improving the verification rate of the chip system.
[0028] It should be understood that although Figure 1 and Figure 2 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 1 and Figure 2At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.
[0029] In one embodiment, Figure 3 As shown, a device 100 for implementing distributed configuration chip initialization in chip system verification is provided, which may include an initial definition module 11, a common collection module 13, a configuration allocation module 15, and a resource flushing module 17. Among them, the initial definition module 11 is used to call a global queue FIFO defined in the basic use case and define a target function; the queue FIFO is used to collect all configuration items in the chip system verification, and the function interface of the target function only retains the target address and data that need to be configured. The public collection module 13 is used to call the target function through the basic use case to configure the public initialization configuration items, collect the public initialization configuration items in the chip system, and push the target address and data that need to be configured for the public initialization configuration items into the queue FIFO. The configuration allocation module 15 is used to call the target function through the basic use case to perform space allocation and page table address allocation according to the target address and data of the configuration items in the queue FIFO. The resource flushing module 17 is used to call the target function through the basic use case to flush the target address and data of the allocated configuration items into the corresponding storage space.
[0030] The implementation device 100 of distributed configuration chip initialization in the above chip system verification, by defining a global queue FIFO and a target function in the basic use case, collaboratively realizes the collection of common initialization configuration items in the chip system, and pushes the target address and data required to be configured for the initialization configuration items into the queue FIFO, so that in the scenario use case, only the target address and data of the configuration items need to be paid attention to, and the number of initialization configuration items can be freely added or deleted, and the order can be adjusted at will, without paying attention to the storage space management of the configuration items themselves and the address allocation of the page table, nor is there any need to consider the impact on the common initialization configuration items. Therefore, the cumbersome configuration parts can be unified in the basic use case to complete the execution, which greatly simplifies the process operation of the scenario use case on the initialization configuration items, thereby greatly improving the verification efficiency and quality of the chip system.
[0031] In one embodiment, the implementation device 100 for distributed configuration chip initialization in the above-mentioned chip system verification may also include an overload module, which is used to execute a derivable derived task after overloading and rewriting the target function when the scenario use case derived from the basic use case does not require a common initialization configuration item; the derived task is left to the derived scenario use case to execute the overload to implement the initialization configuration items in the scenario where the derived scenario use case is located.
[0032] In one embodiment, the target function uniformly flushes the target address and data of the allocated configuration items into the corresponding storage space through the backdoor.
[0033] Regarding the specific limitations of the implementation device 100 for distributed configuration chip initialization in chip system verification, please refer to the corresponding limitations of the implementation method for distributed configuration chip initialization in chip system verification above, which will not be repeated here.
[0034] Each module in the above-mentioned distributed configuration chip initialization implementation device 100 in chip system verification can be implemented in whole or in part by software, hardware, or a combination thereof. The above-mentioned components can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the above-mentioned device in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules. The above-mentioned device can be, but is not limited to, various types of chip verification computers already available in the art.
[0035] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).
[0036] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0037] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.
Claims
1. A method for implementing distributed configuration chip initialization in chip system verification, characterized in that: Includes steps: Call a global queue FIFO defined in the basic use case and define a target function; the queue FIFO is used to collect all configuration items in the chip system verification, and the function interface of the target function only retains the target address and data that need to be configured; Call the target function to configure common initialization configuration items through basic use cases, collect common initialization configuration items in the chip system, and push the target address and data that need to be configured for the common initialization configuration items into the queue FIFO; Calling the target function through the basic use case to perform space allocation and page table address allocation according to the target address and data of the configuration item in the queue FIFO; The target function is called through the basic use case to flush the target address and data of the allocated configuration item into the corresponding storage space.
2. The method for implementing distributed configuration chip initialization in chip system verification according to claim 1, characterized in that: If the scenario use case derived from the basic use case does not require common initialization configuration items, then after overloading and rewriting the target function, a derivable derived task is executed; the derived task is left to the derived scenario use case to execute the overload to implement the initialization configuration items in the scenario where the derived scenario use case is located.
3. The method for implementing distributed configuration chip initialization in chip system verification according to claim 1 or 2, characterized in that: The target function uniformly flushes the target address and data of the allocated configuration items into the corresponding storage space through the backdoor.
4. A device for implementing distributed configuration chip initialization in chip system verification, characterized in that: include: The initial definition module is used to call a global queue FIFO defined in the basic use case and define a target function; The queue FIFO is used to collect all configuration items in the chip system verification, and the function interface of the target function only retains the target address and data that need to be configured; A common collection module, used to call the target function to configure common initialization configuration items through basic use cases, collect common initialization configuration items in the chip system, and push the target address and data required to be configured for the common initialization configuration items into the queue FIFO; A configuration allocation module, used to call the target function through a basic use case to perform space allocation and page table address allocation according to the target address and data of the configuration item in the queue FIFO; The resource flushing module is used to call the target function through the basic use case to flush the target address and data of the allocated configuration item into the corresponding storage space.
5. The device for implementing distributed configuration chip initialization in chip system verification according to claim 4, characterized in that: It also includes an overload module, which is used to execute a derivable derived task after overloading and rewriting the target function when the scenario use case derived from the basic use case does not require a common initialization configuration item; the derived task is left to the derived scenario use case to execute the overload, so as to realize the configuration of the initialization configuration items in the scenario where the derived scenario use case is located.
6. The device for implementing distributed configuration chip initialization in chip system verification according to claim 4 or 5, characterized in that: The target function uniformly flushes the target address and data of the allocated configuration items into the corresponding storage space through the backdoor.