Reset test method, device and equipment

Abstract

The invention provides a reset test method, device and equipment, relates to the technical field of computers, and aims to solve the problems of high cost and low efficiency when an RAID card performs a reset test for a reset scene in the related technology. The method comprises the steps that a target reset type number is acquired, and target reset information corresponding to the target reset type number is determined according to the corresponding relation between the reset type number and reset information; under the condition that the reset type in the target reset information is hard disk reset, sending the target reset information to the disk array to trigger the disk array to execute a hard disk reset process; under the condition that the reset type in the target reset information is host reset, whether execution needs to be carried out in an IO scene or not is determined, and the target reset information is sent to the disk array to trigger the disk array to execute a host reset process or execute a host reset process in IO processing.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a reset test method, device and equipment. Background Art

[0002] In chip design, reset operation is an important mechanism to ensure system stability and recovery capability and is widely used in various scenarios. RAID (disk array) cards support NVMe SSD mounting, which can realize normal interaction such as NVMe command execution and disk operation. During this process, some scenarios that require reset operation will appear. Therefore, during the R&D and testing phase, it is necessary to test the possible reset scenarios.

[0003] Related Technology The methods for testing reset scenarios in RAID cards usually include: constructing reset scenarios, writing reset scenarios and trigger codes; and artificially constructing different reset scenarios for testing from the hardware perspective and software logic level. However, these methods have limitations. For example, constructing different reset scenarios involves complex software logic, and the reset test logic coding is relatively large, which is costly, time-consuming, and inefficient. Reset scenarios involving hardware processing require artificial construction defects, which is costly. Summary of the invention

[0004] The embodiments of the present application provide a reset test method, device and equipment, aiming to solve the problems of high cost and low efficiency when a RAID card performs a reset test for a reset scenario in the related art.

[0005] A first aspect of an embodiment of the present application provides a reset test method, which is applied to a host, and the method includes: Obtaining a target reset type number, and determining target reset information corresponding to the target reset type number according to a correspondence between the reset type number and the reset information; When the reset type in the target reset information is hard disk reset, sending the target reset information to the disk array to trigger the disk array to execute the hard disk reset process; When the reset type in the target reset information is a host reset, determining whether it needs to be executed in an IO scenario; When the operation does not need to be performed in the IO scenario, the target reset information is sent to the disk array to trigger the disk array to perform the host reset process; When execution is required in an IO scenario, the IO execution logic is triggered, the IO execution process is recorded, and the target reset information is sent to the disk array during the IO execution process to trigger the disk array to execute the host reset process in the IO processing.

[0006] In an optional embodiment, the method further includes: Numbering the multiple reset types respectively to obtain multiple reset type numbers; The reset descriptions, the IO operations involved, and the disk operations involved of the respective reset types are used as the reset information of the respective reset types; According to the reset type numbers and reset information of each of the plurality of reset types, a corresponding relationship between the reset type numbers and the reset information is established.

[0007] In an optional implementation, obtaining the target reset type number includes: Obtaining a type of reset test, where the type of reset test includes: manual input and random generation; When the type of the reset test is the manual input, outputting prompt information of the range of reset type numbers, obtaining a first reset type number input by a user, and determining whether the first reset type number is within the range of the type numbers; If the first reset type number is not within the range of the reset type numbers, determining that the first reset type number is invalid, and outputting prompt information for re-entering the reset type number; If the first reset type number is within the range of the reset type numbers, determining the first reset type number as the target reset type number; In the case where the type of the reset test is the random generation, a second reset type number is randomly generated according to the range of the reset type number, and the second reset type number is determined as the target reset type number.

[0008] A second aspect of an embodiment of the present application provides a reset test method, which is applied to a disk array, and the method includes: Receive target reset information sent by the host; When the reset type in the target reset information is hard disk reset, executing the hard disk reset process; When the reset type in the target reset information is a host reset and it is not necessary to execute in an IO scenario, executing a host reset process; When the reset type in the target reset information is a host reset and it needs to be executed in an IO scenario, the host reset process in the IO processing is executed.

[0009] In an optional embodiment, the method further includes: Add target reset information to the message queue; The process of executing host reset includes: When the target reset information is detected in the message queue, waking up the reset processing thread through an interrupt processing program; fetching the target reset information from the message queue through the reset processing thread; Parsing the target reset information through the reset processing thread to obtain a parsing result; When the parsing result indicates that the reset type in the target reset information is a host reset and it does not need to be performed in an IO scenario, executing a host reset process; When the analysis result indicates that the reset type in the target reset information is a host reset and the reset needs to be performed in an IO scenario, the host reset process in the IO processing is performed.

[0010] In an optional implementation, before executing the host reset process, or before executing the host reset process in IO processing, at least one of the following is also included: When the IO operation involved in the target reset information is to stop the IO, stop the IO sent by the host to implement reset preprocessing; When the disk operation involved in the target reset information is a disk reset, resetting the downstream disk to implement reset preprocessing; In the case where the disk operation involved in the target reset information is flushing the cache, flushing the cache of the downstream disk to implement reset preprocessing; The target module is notified to save the currently stored data, wherein the target module is a module whose stored data is lost after power failure.

[0011] In an optional implementation, when the parsing result indicates that the reset type in the target reset information is a host reset and needs to be executed in an IO scenario, executing the host reset process in the IO processing includes: Receive IO requests sent by the host; In response to the parsing result that the reset type in the target reset information is a host reset and needs to be performed in an IO scenario, executing a host reset process in IO processing; After the host reset process in the IO processing is completed, an IO response to the IO request is generated and sent to the host.

[0012] A third aspect of an embodiment of the present application provides a reset test device, which is applied to a host, and the device includes: An acquisition module, used for acquiring a target reset type number, and determining the target reset information corresponding to the target reset type number according to a correspondence between the reset type number and the reset information; A first trigger module, configured to send the target reset information to the disk array when the reset type in the target reset information is hard disk reset, so as to trigger the disk array to execute the hard disk reset process; A determination module, used to determine whether it is necessary to execute in an IO scenario when the reset type in the target reset information is a host reset; A second trigger module is used to send the target reset information to the disk array to trigger the disk array to execute the host reset process when it is not necessary to execute in the IO scenario; The third trigger module is used to trigger the IO execution logic, record the IO execution process, and send the target reset information to the disk array during the IO execution process to trigger the disk array to execute the host reset process in the IO processing.

[0013] A fourth aspect of an embodiment of the present application provides a reset test device, which is applied to a disk array, and the device includes: A receiving module, used for receiving target reset information sent by the host; A first execution module, configured to execute a hard disk reset process when the reset type in the target reset information is a hard disk reset; A second execution module, configured to execute a host reset process when the reset type in the target reset information is a host reset and the process does not need to be executed in an IO scenario; The third execution module is used to execute the host reset process in the IO processing when the reset type in the target reset information is host reset and it needs to be executed in the IO scenario.

[0014] A fifth aspect of an embodiment of the present application provides an electronic device, including: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the reset test method of the first aspect or the second aspect of the embodiment of the present application when executing the computer program.

[0015] In this embodiment, by obtaining the target reset type number, and according to the correspondence between the reset type number and the reset information, determining the target reset information corresponding to the target reset type number, sending the target reset information to the disk array, and triggering the disk array to execute different reset processes according to the reset type in the target reset information. This replaces the specific reset scenario construction process with the reset type encoding and injection, greatly reducing costs and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a flowchart of the steps of the host side of the reset test method proposed in one embodiment of the present application; Figure 2 It is a flowchart of the steps of the disk array side of the reset test method proposed in one embodiment of the present application; Figure 3 is a common processing flow chart of a reset test method proposed in an embodiment of the present application; Figure 4 is a reset injection flow chart of a reset test method proposed in an embodiment of the present application; Figure 5 is a structural diagram of a reset test system proposed in an embodiment of the present application; Figure 6 It is a schematic diagram of an electronic device of the present application. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] The following technical terms appearing in this application are explained: Redundant Arrays of Independent Disks (RAID): It is composed of many independent disks, combined into a large-capacity disk group to provide data redundancy and performance improvement. RAID stores data on multiple hard disks in a specific way and provides fault tolerance at certain levels, thereby improving data reliability and access speed.

[0020] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, mainly used to expand the data throughput of the computer system bus and improve the communication speed of the device. There are corresponding hardware interfaces for the host and peripherals. Through the PCIe bus protocol and host PCIe implemented inside the PCIe hardware link, the data interaction between the host and peripherals is realized, and it has the characteristics of high-speed transmission, link abnormality recovery, power consumption management, etc.

[0021] NVMe (Peripheral Component Interconnect Express) is a host software application layer protocol running on top of the hardware PCIe protocol. It defines a set of management and IO request / response queue interfaces, which can enable the host to submit IO request commands to the device and process IO responses in a high-concurrency and asynchronous manner.

[0022] IO (Input Output), input and output streams.

[0023] SSD (Solid State Drive) is a hard disk made of solid-state electronic storage chip array.

[0024] Reference Figure 1 , Figure 1 1 is a flowchart of the steps of the host side of the reset test method proposed in an embodiment of the present application, including the following steps S11 to S15: Step S11: Acquire a target reset type number, and determine the target reset information corresponding to the target reset type number according to the corresponding relationship between the reset type number and the reset information.

[0025] The corresponding relationship between the reset type number and the reset information can be established through a data structure or a similar data storage method. The target reset type number is obtained from user input or other data sources. This number is a unique identifier of the reset type to be executed. The target reset information corresponding to the target reset type number can be determined by searching for the corresponding relationship.

[0026] Further, obtaining the target reset type number includes: Obtaining a type of reset test, where the type of reset test includes: manual input and random generation; When the type of the reset test is the manual input, outputting prompt information of the range of reset type numbers, obtaining a first reset type number input by a user, and determining whether the first reset type number is within the range of the type numbers; If the first reset type number is not within the range of the reset type numbers, determining that the first reset type number is invalid, and outputting prompt information for re-entering the reset type number; If the first reset type number is within the range of the reset type numbers, determining the first reset type number as the target reset type number; In the case where the type of the reset test is the random generation, a second reset type number is randomly generated according to the range of the reset type number, and the second reset type number is determined as the target reset type number.

[0027] By executing the test script, select the type of reset test, for example, 0: manual input, 1: random generation. When input 0 to select manual input, the prompt information of the range of reset type number is output, such as the number 0 to 7 needs to be entered. Then the first reset type number entered by the user is obtained. If the first reset type number is within the range of reset type numbers, then the input first reset type number is correct and is determined as the target reset type number; otherwise, the input first reset type number is invalid, and a prompt information for re-entering the reset type number is output.

[0028] When input 1 selects random generation, according to the random algorithm formula: the second reset type number = random.randint(x, y), x and y represent the upper and lower limits of the range of the reset type number, set x=0, y=total number of reset types. The second reset type number randomly generated by the random algorithm is the determined target reset type number. Supports manual input and random generation to trigger reset, which increases the flexibility of reset test.

[0029] Step S12: When the reset type in the target reset information is hard disk reset, the target reset information is sent to the disk array to trigger the disk array to execute the hard disk reset process.

[0030] Parse the determined target reset information and execute different processes according to the reset type. If the reset type is hard disk reset, trigger and send the target reset information to the disk array side through a standard transmission interface such as a serial port to execute the hard disk reset process.

[0031] Step S13: When the reset type in the target reset information is a host reset, determine whether it needs to be executed in an IO scenario.

[0032] Parse the determined target reset information and execute different processes according to the reset type. If the reset type is a host reset, select whether to perform a reset test during the IO process. This helps simulate complex situations that may be encountered in actual applications, especially when a reset request is encountered when the system is performing critical IO operations.

[0033] Step S14: When the process does not need to be executed in the IO scenario, the target reset information is sent to the disk array to trigger the disk array to execute the host reset process.

[0034] If you do not need to perform a reset test in an IO scenario, you can directly trigger the reset by writing a register or other means, and send the target reset information to the disk array side to trigger the disk array to execute the host reset process.

[0035] Step S15: When the operation needs to be executed in an IO scenario, the IO execution logic is triggered, the IO execution process is recorded, and the target reset information is sent to the disk array during the IO execution process to trigger the disk array to execute the host reset process in the IO processing.

[0036] If you choose to perform a reset test in an IO scenario, the IO execution logic will be triggered to record the IO execution process, including key indicators such as data flow, response time, and error rate. During the IO execution process, the reset will be triggered and the target reset information will be sent to the disk array side to trigger the host reset process in the disk array IO processing.

[0037] Furthermore, the method further comprises: Numbering the multiple reset types respectively to obtain multiple reset type numbers; The reset descriptions, the IO operations involved, and the disk operations involved of the respective reset types are used as the reset information of the respective reset types; According to the reset type numbers and reset information of each of the plurality of reset types, a corresponding relationship between the reset type numbers and the reset information is established.

[0038] According to the NVMe protocol and PCIe manual standards, there are multiple reset types for RAID cards. Different resets involve different related information such as IO and disk operations. Therefore, all reset types and related information are classified and numbered according to type to obtain multiple reset type numbers. The reset types are summarized as shown in Table 1.

[0039] Table 1 Summary of reset types

[0040] The reset descriptions, IO operations and disk operations of the respective reset types are used as reset information of the respective reset types, and can be saved in the form of an array. The number of each reset type is associated with its corresponding reset information by using program code or other methods to establish a mapping relationship. When needed, the reset information can be quickly obtained by inputting the number of the reset type.

[0041] The host side executes the test script, first enters and saves the reset type information according to the NVMe and PCIe standard protocol interfaces, and then obtains the target reset type number for testing. Targeted reset tests can be performed by manually entering the reset type number, and reset tests can also be performed by generating reset type numbers through random algorithms. Both can be freely selected through switches, and different processes are executed according to different reset types. Stress testing is also supported. Reset injection is based on the standard NVMe protocol and PCIe manual, and the system adaptability and portability are good; it can realize the free selection of reset types and scenarios for automated testing, and supports stress testing, which is highly efficient.

[0042] In this embodiment, by obtaining the target reset type number, and according to the correspondence between the reset type number and the reset information, determining the target reset information corresponding to the target reset type number, sending the target reset information to the disk array, and triggering the disk array to execute different reset processes according to the reset type in the target reset information. This replaces the specific reset scenario construction process with the reset type encoding and injection, greatly reducing costs and improving test efficiency.

[0043] Reference Figure 2 , Figure 2 1 is a flowchart of the steps of the disk array side of the reset test method proposed in an embodiment of the present application, including the following steps S21-S24: Step S21: receiving target reset information sent by the host.

[0044] The disk array receives the target reset information sent by the host. The target reset information is determined by the host through the target reset type number and is usually sent to the disk array in the form of a data packet or a command.

[0045] Step S22: When the reset type in the target reset information is hard disk reset, execute the hard disk reset process.

[0046] By parsing the received target reset information, the reset type and related information can be obtained, including at least the reset type, reset description, involved IO operations, and involved disk operations. If the reset type in the target reset information is a hard disk reset, the hard disk reset process is executed, and the SSD disk is directly operated to reset through the disk reset logic.

[0047] Step S23: When the reset type in the target reset information is a host reset and it is not necessary to execute in an IO scenario, execute the host reset process.

[0048] If the reset type in the target reset information is a host reset, and it does not need to be executed in the IO scenario, the host reset process is executed through the reset processing logic. At this time, the reset operation has nothing to do with the IO operation and can be reset directly.

[0049] Step S24: When the reset type in the target reset information is a host reset and it needs to be executed in an IO scenario, the host reset process in the IO processing is executed.

[0050] If the reset type in the target reset information is host reset, and it needs to be executed in the IO scenario, execute the host reset process in IO processing. It is necessary to perform the reset operation as safely as possible without affecting the current IO operation. For example, suspend or complete the current IO operation before the reset, or keep monitoring the IO operation during the reset process to ensure that the reset operation does not damage the data consistency.

[0051] Furthermore, the method further comprises: Add target reset information to the message queue; The process of executing host reset includes: When the target reset information is detected in the message queue, waking up the reset processing thread through an interrupt processing program; fetching the target reset information from the message queue through the reset processing thread; Parsing the target reset information through the reset processing thread to obtain a parsing result; When the parsing result indicates that the reset type in the target reset information is a host reset and it does not need to be performed in an IO scenario, executing a host reset process; When the analysis result indicates that the reset type in the target reset information is a host reset and the reset needs to be performed in an IO scenario, the host reset process in the IO processing is performed.

[0052] A message queue is a mechanism for passing messages between different threads or processes. It allows one thread (or process) to put a message into a queue, and another thread (or process) can take the message out of the queue for processing. Add the target reset information to the message queue, wake up the reset processing thread through the interrupt handler; take out the target reset information (message) from the message queue, parse the message content, obtain the reset type and related information, and call the corresponding reset processing logic based on this information, such as Figure 3 If the reset type is a host reset and does not need to be executed in the IO scenario, the host reset process is executed; if the reset type is a host reset and needs to be executed in the IO scenario, the host reset process in the IO processing is executed.

[0053] Furthermore, before executing the host reset process, or before executing the host reset process in IO processing, at least one of the following is also included: When the IO operation involved in the target reset information is to stop the IO, stop the IO sent by the host to implement reset preprocessing; When the disk operation involved in the target reset information is a disk reset, resetting the downstream disk to implement reset preprocessing; In the case where the disk operation involved in the target reset information is flushing the cache, flushing the cache of the downstream disk to implement reset preprocessing; The target module is notified to save the currently stored data, wherein the target module is a module whose stored data is lost after power failure.

[0054] After the reset thread wakes up, it will call the corresponding reset processing logic according to the corresponding reset type and information, and perform reset preprocessing and reset notification before executing the host reset process or before executing the host reset process in IO processing.

[0055] The main tasks of the preprocessing stage include the following: according to the reset type, determine whether it is necessary to stop the IO sent by the host, and determine whether it is necessary to reset the downstream disk or flush the cache of the disk. If the IO operation involved in the target reset information is to stop IO, stop the IO sent by the host; if the disk operation involved in the target reset information is disk reset, reset the downstream disk; if the disk operation involved in the target reset information is to flush the cache, flush the cache of the downstream disk to achieve reset preprocessing.

[0056] After the preprocessing is completed, a reset notification can be performed to notify important modules in the system and save some important variables. During the system reset process, internal storage spaces such as LMU and OCB will generally not lose power and data will not be lost, but data in the heap and stack will be lost, so relevant data needs to be saved. After that, the reset execution is performed to implement the execution process of different reset scenarios, as described in Table 1.

[0057] Further, when the analysis result indicates that the reset type in the target reset information is a host reset and needs to be executed in an IO scenario, the host reset process in the IO processing is executed, including: Receive IO requests sent by the host; In response to the parsing result that the reset type in the target reset information is a host reset and needs to be performed in an IO scenario, executing a host reset process in IO processing; After the host reset process in the IO processing is completed, an IO response to the IO request is generated and sent to the host.

[0058] Receive the IO request sent by the host, and in response to the analysis result that the reset type in the target reset information is host reset and needs to be executed in the IO scenario, execute the host reset process in the IO processing. The current IO operation can be paused or completed before the reset, and the host reset operation can be performed according to the specific requirements of the target reset information. After the host reset is completed, the corresponding IO response is generated according to the IO request and sent to the host. Combine the host reset with the IO processing to improve the reliability of the reset test.

[0059] In this embodiment, the target reset information sent by the host and determined by the target reset type number is received and parsed, and different reset processes are executed according to the reset type in the target reset information. The reset type and scenario can be freely selected for testing, and automated testing can be performed, and stress testing is supported, which is highly efficient.

[0060] Reference Figure 4 , Figure 4 1 is a reset injection flow chart of a reset test method proposed in an embodiment of the present application. Figure 4 As shown, the reset injection process is specifically as follows: Execute the test script and prompt to enter the reset information; enter the reset type, number, operation information, etc., and save them in the same array, with the number corresponding to the array subscript one by one; determine whether the information has been entered; if the information has not been entered, continue to enter; when the information is entered, prompt to enter the reset test type, 0: manual input, 1: random generation. After entering the reset test type, determine whether it is randomly generated; if it is randomly generated, execute the random algorithm to generate the reset type number = random.randint(x, y), x and y represent the upper and lower limits of the range, set x=0, y=the total number of reset types; according to the reset type number, find the corresponding reset information array and obtain the corresponding reset information. If it is not randomly generated, manually enter the reset type number; determine whether the reset type number is correct; if the reset type number is incorrect, manually enter the reset type number again; if the reset type number is correct, find the corresponding reset information array according to the reset type number and obtain the corresponding reset information. After obtaining the corresponding reset information, determine whether it is a direct hard disk reset process; if it is a direct hard disk reset process, the reset information is transmitted and triggered through the serial port; the reset information is transmitted to the RAID side disk reset logic. If it is not a direct hard disk reset process, determine whether it needs to be executed in the IO scenario; if it needs to be executed in the IO scenario, trigger the IO execution logic, record the IO execution process, and reset during the IO execution process; execute the reset, and execute the corresponding trigger method such as writing registers according to the reset information; if it does not need to be executed in the IO scenario, execute the reset, and execute the corresponding trigger method such as writing registers according to the reset information; reset trigger, and transmit it to the RAID side for processing.

[0061] In the embodiment, through the reset injection mechanism, reset triggering is supported by manual input and random generation, which can be selected according to needs, and stress testing is supported, which realizes the automated processing of the test and increases the flexibility of the reset test.

[0062] refer to Figure 5 , Figure 5 Schematic diagram of the structure of the reset test system proposed in one embodiment of the present application. Figure 5 As shown, the reset test system includes a reset injector and a RAID card.

[0063] The reset injector is mainly responsible for entering, summarizing and saving all reset type information according to the NVMe and PCIe standard protocol interfaces according to the standard NVMe protocol and PCIe manual, and using different reset triggering methods according to the reset type to trigger and transmit the reset information to the RAID card, and supports manual input and random generation of reset types. Specifically, through switch control, you can enter the type code such as 0: manual input; 1: random generation, and make a random selection. After that, different reset triggering methods will be used according to the reset type. For example, during the host reset process, the reset scenario will be triggered on the host side by executing scripts, and finally the reset type will be transmitted to the reset processing logic on the RAID side for processing, which can test specific reset scenarios and reset stress tests; another direct hard disk reset process, the reset type will trigger and transmit the reset information to the disk reset logic on the RAID side through standard transmission interfaces such as serial ports, directly operate the SSD disk for reset, and also support stress testing, etc.

[0064] The RAID card is mainly responsible for receiving the reset information transmitted by the reset injector on the host side, and executing the corresponding reset scenario processing logic according to different reset types. Specifically, for host reset, it can trigger interrupts and other methods to the public processing logic, which uses message queue transmission according to different reset types, and finally wakes up the reset processing logic thread to perform reset preprocessing, reset notification, and reset execution. During this process, different operations will be performed according to different reset types, such as stopping IO, resetting the SSD disk, or refreshing the cache. For hard disk reset, reset is performed directly according to the disk reset logic processing. Among them, for the host reset test, on the RAID side, each different reset type and related information will also be recorded, and the relevant interrupt processing functions and reset threads will be registered in the initialization stage for the reset processing closed loop.

[0065] The reset test system supports independent reset test scenarios, scenarios where reset is performed during NVMe IO processing, and reset scenarios for disks. Figure 1As shown in the ①->②->③ process in the figure, the reset scenario test can also be performed in the IO business process on the host side, as shown in the ④->⑤->⑥->①->②->③->⑦ process in the figure. The direct reset test for the hard disk is as follows Figure 1 As shown in the process of ①->⑧->⑨->⑩.

[0066] In the embodiment, based on the standard NVMe protocol and PCIe manual, different reset test scenarios such as NVMeCLR, PCIe FLR, etc. are counted, and the reset type encoding and injection method is used to replace the specific reset scenario construction process, which greatly reduces the cost and improves the efficiency. It supports manual input and random generation to trigger the reset, and the two can be selected and executed in parallel, and supports stress testing, realizes the automated processing of the test, and increases the flexibility of the reset test.

[0067] Based on the same inventive concept of steps S11 to S15, a reset test device is applied to a host, and the device includes: An acquisition module, used for acquiring a target reset type number, and determining the target reset information corresponding to the target reset type number according to a correspondence between the reset type number and the reset information; A first trigger module, configured to send the target reset information to the disk array when the reset type in the target reset information is hard disk reset, so as to trigger the disk array to execute the hard disk reset process; A determination module, used to determine whether it is necessary to execute in an IO scenario when the reset type in the target reset information is a host reset; A second trigger module is used to send the target reset information to the disk array to trigger the disk array to execute the host reset process when it is not necessary to execute in the IO scenario; The third trigger module is used to trigger the IO execution logic, record the IO execution process, and send the target reset information to the disk array during the IO execution process to trigger the disk array to execute the host reset process in the IO processing.

[0068] In an optional embodiment, the device further comprises: A construction module is used to number the multiple reset types respectively to obtain multiple reset type numbers; The reset descriptions, involved IO operations, and involved disk operations of each of the multiple reset types are used as reset information of each of the multiple reset types; and a corresponding relationship between the reset type number and the reset information is established according to the reset type number and reset information of each of the multiple reset types.

[0069] In an optional implementation, the acquisition module is specifically used to: Obtaining a type of reset test, where the type of reset test includes: manual input and random generation; When the type of the reset test is the manual input, outputting prompt information of the range of reset type numbers, obtaining a first reset type number input by a user, and determining whether the first reset type number is within the range of the type numbers; If the first reset type number is not within the range of the reset type numbers, determining that the first reset type number is invalid, and outputting prompt information for re-entering the reset type number; If the first reset type number is within the range of the reset type numbers, determining the first reset type number as the target reset type number; In the case where the type of the reset test is the random generation, a second reset type number is randomly generated according to the range of the reset type number, and the second reset type number is determined as the target reset type number.

[0070] Based on the same inventive concept of steps S21 to S24, a reset test device is applied to a disk array, and the device includes: A receiving module, used for receiving target reset information sent by the host; A first execution module, configured to execute a hard disk reset process when the reset type in the target reset information is a hard disk reset; A second execution module, configured to execute a host reset process when the reset type in the target reset information is a host reset and the process does not need to be executed in an IO scenario; The third execution module is used to execute the host reset process in the IO processing when the reset type in the target reset information is host reset and it needs to be executed in the IO scenario.

[0071] In an optional embodiment, the device further comprises: The first processing module is used to add target reset information to a message queue; when the target reset information is detected in the message queue, wake up the reset processing thread through an interrupt handler; take out the target reset information from the message queue through the reset processing thread; parse the target reset information through the reset processing thread to obtain a parsing result; if the parsing result is that the reset type in the target reset information is a host reset and it does not need to be executed in an IO scenario, execute the host reset process; if the parsing result is that the reset type in the target reset information is a host reset and it needs to be executed in an IO scenario, execute the host reset process in IO processing.

[0072] In an optional embodiment, the device further comprises: The second processing module is used for, when the IO operation involved in the target reset information is to stop IO, stopping the IO sent by the host to realize reset preprocessing; when the disk operation involved in the target reset information is disk reset, resetting the downstream disk to realize reset preprocessing; when the disk operation involved in the target reset information is to flush cache, flushing the cache of the downstream disk to realize reset preprocessing; notifying the target module to save the currently stored data, the target module is the module whose stored data is lost after power failure.

[0073] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0074] Based on the same inventive concept, another embodiment of the present application provides an electronic device, referring to Figure 6 , Figure 6 FIG. 1 is a schematic diagram of an electronic device shown in an embodiment of the present application. Figure 6 As shown, the electronic device 100 includes: a memory 110 and a processor 120. The memory 110 and the processor 120 are connected via a bus communication. A computer program is stored in the memory 110. The computer program can be run on the processor 120 to implement the steps in the reset test method disclosed in the embodiment of the present disclosure.

[0075] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0076] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0077] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0078] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0079] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0080] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0081] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0082] The above is a detailed introduction to a reset test method, device and equipment provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A reset test method, characterized in that: Applied to a host, the method comprises: Obtaining a target reset type number, and determining target reset information corresponding to the target reset type number according to a correspondence between the reset type number and the reset information; When the reset type in the target reset information is hard disk reset, sending the target reset information to the disk array to trigger the disk array to execute the hard disk reset process; When the reset type in the target reset information is a host reset, determining whether it needs to be executed in an IO scenario; When the operation does not need to be performed in the IO scenario, the target reset information is sent to the disk array to trigger the disk array to perform the host reset process; When execution is required in an IO scenario, the IO execution logic is triggered, the IO execution process is recorded, and the target reset information is sent to the disk array during the IO execution process to trigger the disk array to execute the host reset process in the IO processing.

2. The reset test method according to claim 1, characterized in that: The method further comprises: Numbering the multiple reset types respectively to obtain multiple reset type numbers; The reset descriptions, the IO operations involved, and the disk operations involved of the respective reset types are used as the reset information of the respective reset types; According to the reset type numbers and reset information of each of the plurality of reset types, a corresponding relationship between the reset type numbers and the reset information is established.

3. The reset test method according to claim 1 or 2, characterized in that: The obtaining of the target reset type number includes: Obtaining a type of reset test, where the type of reset test includes: manual input and random generation; When the type of the reset test is the manual input, outputting prompt information of the range of reset type numbers, obtaining a first reset type number input by a user, and determining whether the first reset type number is within the range of the type numbers; If the first reset type number is not within the range of the reset type numbers, determining that the first reset type number is invalid, and outputting prompt information for re-entering the reset type number; If the first reset type number is within the range of the reset type numbers, determining the first reset type number as the target reset type number; In the case where the type of the reset test is the random generation, a second reset type number is randomly generated according to the range of the reset type number, and the second reset type number is determined as the target reset type number.

4. A reset test method, characterized in that: Applied to a disk array, the method comprises: Receive target reset information sent by the host; When the reset type in the target reset information is hard disk reset, executing the hard disk reset process; When the reset type in the target reset information is a host reset and it is not necessary to execute in an IO scenario, executing a host reset process; When the reset type in the target reset information is a host reset and it needs to be executed in an IO scenario, the host reset process in the IO processing is executed.

5. The reset test method according to claim 4, characterized in that: The method further comprises: Add target reset information to the message queue; The process of executing host reset includes: When the target reset information is detected in the message queue, waking up the reset processing thread through an interrupt processing program; fetching the target reset information from the message queue through the reset processing thread; Parsing the target reset information through the reset processing thread to obtain a parsing result; When the parsing result indicates that the reset type in the target reset information is a host reset and it does not need to be performed in an IO scenario, executing a host reset process; When the analysis result indicates that the reset type in the target reset information is a host reset and the reset needs to be performed in an IO scenario, the host reset process in the IO processing is performed.

6. The reset test method according to claim 5, characterized in that: Before executing the host reset process, or before executing the host reset process in IO processing, at least one of the following is also included: When the IO operation involved in the target reset information is to stop the IO, stop the IO sent by the host to implement reset preprocessing; When the disk operation involved in the target reset information is a disk reset, resetting the downstream disk to implement reset preprocessing; In the case where the disk operation involved in the target reset information is flushing the cache, flushing the cache of the downstream disk to implement reset preprocessing; The target module is notified to save the currently stored data, wherein the target module is a module whose stored data is lost after power failure.

7. The reset test method according to any one of claims 4 to 6, characterized in that: When the analysis result indicates that the reset type in the target reset information is a host reset and the reset needs to be performed in an IO scenario, the host reset process in the IO processing is performed, including: Receive IO requests sent by the host; In response to the parsing result that the reset type in the target reset information is a host reset and needs to be performed in an IO scenario, executing a host reset process in IO processing; After the host reset process in the IO processing is completed, an IO response to the IO request is generated and sent to the host.

8. A reset test device, characterized in that: Applied to a host, the device comprises: An acquisition module, used for acquiring a target reset type number, and determining the target reset information corresponding to the target reset type number according to a correspondence between the reset type number and the reset information; A first trigger module, configured to send the target reset information to the disk array when the reset type in the target reset information is hard disk reset, so as to trigger the disk array to execute the hard disk reset process; A determination module, used to determine whether it is necessary to execute in an IO scenario when the reset type in the target reset information is a host reset; A second trigger module is used to send the target reset information to the disk array to trigger the disk array to execute the host reset process when it is not necessary to execute in the IO scenario; The third trigger module is used to trigger the IO execution logic, record the IO execution process, and send the target reset information to the disk array during the IO execution process to trigger the disk array to execute the host reset process in the IO processing.

9. A reset test device, characterized in that: Applied to a disk array, the device comprises: A receiving module, used for receiving target reset information sent by the host; A first execution module, configured to execute a hard disk reset process when the reset type in the target reset information is a hard disk reset; A second execution module, configured to execute a host reset process when the reset type in the target reset information is a host reset and the process does not need to be executed in an IO scenario; The third execution module is used to execute the host reset process in the IO processing when the reset type in the target reset information is host reset and it needs to be executed in the IO scenario.

10. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the reset test method described in any one of claims 1 to 3 or 4 to 7 when executing the computer program.

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