Logical address representation method and device, terminal equipment and readable storage medium

Abstract

The invention is suitable for the technical field of storage, and provides a logical address representation method and device, terminal equipment and a readable storage medium. The logical address representation method comprises the following steps: acquiring initial logical address information of the storage equipment; performing bit width optimization combination on the SLC / XLC MODE information and Row add information to obtain combined information; and combining the CH information, the LUN information, the Clst information and the combination information into target logic address information. According to the embodiment of the invention, the bit width optimization combination is performed on the SLC / XLC MODE information and the Row address information, and compared with the prior art, the bit width required by the SLC / XLC MODE information can be omitted, so that the total bit width of a logic address is reduced, the storage space is saved, the algorithm calculation overhead is reduced, and the performance of storage equipment is improved.

Description

Technical Field

[0001] The present application belongs to the field of storage technology, and in particular, relates to a method, apparatus, terminal device and readable storage medium for representing a logical address. Background Art

[0002] With the continuous development of storage technology, solid-state drives (SSDs) have become important storage devices in modern computer systems. In the use of SSDs, it is often necessary to access specific storage units to read or write data. In order to accurately locate these storage units, the SSD controller needs to generate a logical address that contains all the necessary information of the storage unit, such as SLC / XLC MODE information, channel number (CH), logical unit number (LUN), cluster address (Clst), and row address (Row address).

[0003] In the related art, the above information is usually directly combined to form a logical address. However, the logical address obtained by this combination has a large bit width, which will waste storage space, increase algorithm calculation overhead, and affect storage device performance. Summary of the invention

[0004] The embodiments of the present application provide a method, apparatus, terminal device and readable storage medium for representing a logical address, which can solve the problem that the logical address bit width of the storage device formed by the related technology is large, resulting in a waste of storage space, an increase in algorithm calculation overhead, and an impact on the performance of the storage device.

[0005] In a first aspect, an embodiment of the present application provides a method for representing a logical address, including:

[0006] Obtain the initial logical address information of the storage device, which includes SLC / XLC MODE information, CH information, LUN information, Clst information, and Row address information;

[0007] The SLC / XLC MODE information and the Row address information are combined by optimizing the bit width to obtain the combined information;

[0008] Combine CH information, LUN information, Clst information and combination information into target logical address information.

[0009] In some implementations of the first aspect, combining the CH information, the LUN information, the Clst information, and the combination information into the target logical address information includes:

[0010] Allocate 2 bits of bit width to CH information;

[0011] Allocate 2 bits of bit width to LUN information;

[0012] Allocate 2 bits of bit width to Clst information;

[0013] Allocate 26 bits of bit width for the combined information;

[0014] According to the allocated bit width, the CH information, LUN information, Clst information and combination information are combined into the target logical address information.

[0015] In some implementations of the first aspect, the SLC / XLC MODE information and the Row address information are combined in a bit width optimized manner to obtain combined information, including:

[0016] Setting a mark bit at the first preset position of the Row address information;

[0017] Determine the mark value of the mark bit according to the SLC / XLC MODE information;

[0018] Fill the tag value into the tag bit of the Row address information to obtain the combined information.

[0019] In some implementations of the first aspect, the SLC / XLC MODE information and the Row address information are combined in a bit width optimized manner to obtain combined information, including:

[0020] Encoding the SLC / XLC MODE information into a first SLC / XLC MODE binary sequence according to a first preset encoding rule;

[0021] The first SLC / XLC MODE binary sequence is embedded into the second preset position of the Row address information to obtain the combined information.

[0022] In some implementations of the first aspect, the SLC / XLC MODE information and the Row address information are combined in a bit width optimized manner to obtain combined information, including:

[0023] Encoding the SLC / XLC MODE information into a second SLC / XLC MODE binary sequence according to a second preset encoding rule;

[0024] Determine the total bit width of the Row address information, and determine the insertion position of the second SLC / XLC MODE binary sequence in the Row address information;

[0025] The second SLC / XLC MODE binary sequence is moved to the inserting position, and a mask operation is performed on the second SLC / XLC MODE binary sequence to obtain combined information.

[0026] In some implementations of the first aspect, combining the CH information, the LUN information, the Clst information, and the combination information into the target logical address information includes:

[0027] According to a preset format and a preset order, the CH information, the LUN information, the Clst information and the combination information are sequentially spliced ​​to obtain the target logical address information.

[0028] In some implementations of the first aspect, obtaining initial logical address information of a storage device includes:

[0029] The configuration information of the storage device is read through the control interface of the storage device to obtain the initial logical address information.

[0030] In a second aspect, an embodiment of the present application provides a device for representing a logical address, including:

[0031] An acquisition module is used to acquire initial logical address information of a storage device, where the initial logical address information includes SLC / XLC MODE information, CH information, LUN information, Clst information, and Row address information;

[0032] An optimization module, used for combining the SLC / XLC MODE information and the Row address information in a bit width optimized manner to obtain combined information;

[0033] The combination module is used to combine CH information, LUN information, Clst information and combination information into target logical address information.

[0034] In a third aspect, an embodiment of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned logical address representation method when executing the computer program.

[0035] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the above-mentioned logical address representation method are implemented.

[0036] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed on a terminal device, enables the terminal device to execute the above-mentioned method for representing a logical address.

[0037] The beneficial effect of the embodiment of the present application compared with the prior art is: the embodiment of the present application obtains the initial logical address information of the storage device, and optimizes the bit width of the SLC / XLC MODE information and the Row address information to obtain the combination information, and then combines the CH information, LUN information, Clst information and the combination information into the target logical address information. The embodiment of the present application optimizes the bit width of the SLC / XLC MODE information and the Row address information, and compared with the prior art, the bit width required for the SLC / XLC MODE information can be omitted, thereby reducing the total bit width of the logical address, thereby saving storage space, reducing algorithm calculation overhead, and improving storage device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 It is a schematic diagram of an implementation flow of a method for representing a logical address provided in an embodiment of the present application;

[0040] Figure 2 It is a structural diagram of a logical address representation device provided in an embodiment of the present application;

[0041] Figure 3 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of bit width optimization provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are protected by the present application.

[0044] It should be noted that the terms "include", "comprises" and "have" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, terminal, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. In the claims, specification and drawings of the present application, relational terms such as "first" and "second" are merely used to distinguish one entity / operation / object from another entity / operation / object, and do not necessarily require or imply any such real-time relationship or order between these entities / operations / objects.

[0045] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] With the continuous development of storage technology, solid-state drives (SSDs) have become important storage devices in modern computer systems. In the use of SSDs, it is often necessary to access specific storage units to read or write data. In order to accurately locate these storage units, the SSD controller needs to generate a logical address, which contains all the necessary information of the storage unit, such as the channel number (CH), logical unit number (LUN), cluster address (Clst), and row address (Row address).

[0047] In the related art, the above information is usually directly combined to form a logical address. However, the logical address obtained by this combination has a large bit width, which will waste storage space, increase algorithm calculation overhead, and affect storage device performance.

[0048] In view of this, the implementation method of the present application optimizes the bit width of the SLC / XLC MODE information and the Row address information, which can omit the bit width required for the SLC / XLC MODE information compared to the prior art, thereby reducing the total bit width of the logical address, thereby saving storage space, reducing algorithm calculation overhead, and improving storage device performance.

[0049] In order to illustrate the technical solution of the present application, a specific embodiment is provided below for illustration.

[0050] Figure 1The present invention provides a schematic diagram of a method for representing a logical address, which can be applied to a terminal device, such as a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, etc.

[0051] Based on this, specifically, the above-mentioned method for expressing the logical address may include the following steps S101 to S103.

[0052] Step S101, obtaining initial logical address information of a storage device.

[0053] The initial logical address information includes SLC / XLC MODE information, CH information, LUN information, Clst information, and Rowaddress information.

[0054] The SLC / XLC MODE information is used to indicate the mode information of the storage unit, that is, whether the storage unit is in SLC mode or XLC mode, where XLC indicates MLC / TLC / QLC.

[0055] The CH information is the channel number, which indicates the physical channel where the storage unit is located. There are usually multiple channels inside the SSD, and each channel can connect to multiple storage units.

[0056] LUN information is the logical unit number (Logical Unit Number), which indicates the logical unit where the storage unit is located. In an SSD, multiple physical storage units can be combined into one logical unit for unified management and access.

[0057] The Clst information is the cluster address, which indicates the cluster where the storage unit is located. A cluster is a logical structure inside the SSD, which is used to organize multiple storage units together for efficient access and management.

[0058] Row address information is the row address, which indicates the specific location of the storage unit in the cluster. Each cluster usually contains multiple rows of storage units, and each row of storage units contains multiple storage units.

[0059] In an implementation manner of the present application, the terminal device may obtain the initial logical address information of the storage unit through the internal register or interface of the storage device, including SLC / XLC MODE information, CH information, LUN information, Clst information, and Rowaddress information.

[0060] Step S102: optimizing the bit width of the SLC / XLC MODE information and the Row address information to obtain combined information.

[0061] In an implementation manner of the present application, the terminal device may merge the SLC / XLC MODE information into the Row address information according to a preset rule, thereby saving the bit width that the SLC / XLC MODE information should have occupied to reduce the total bit width.

[0062] For example, Figure 4 As shown, it is assumed that the particle type of the storage device is N38A particle. If the particle is in SLC mode, the Row address information corresponding to the SLC page address of the particle is 0~0x8FF, with a bit width of 14 bits, and the SLC / XLC MODE information of the particle is 0, with a bit width of 1 bit. In the related art, the Row address information in this mode is combined with the SLC / XLC MODE information to obtain the combined address information 0~0x8FF, whose bit width is 15 bits. In the embodiment of the present application, the Row address information in this mode is combined with the SLC / XLC MODE information to obtain the combined address information 0x3000~0x38FF, whose bit width is 14 bits, which is 1 bit less than the prior art.

[0063] If the particle is in XLC mode, the Row address information corresponding to the XLC page address of the particle is 0 to 0x23FF, with a bit width of 14 bits, and the SLC / XLC MODE information of the particle is 1, with a bit width of 1 bit. In the related art, the Row address information is combined with the SLC / XLC MODE information to obtain the combined address information 0 to 0x63FF, with a bit width of 15 bits. In the embodiment of the present application, the Row address information in this mode is combined with the SLC / XLC MODE information to obtain the combined address information 0 to 0x23FF, with a bit width of 14 bits, which is 1 bit less than the prior art.

[0064] It can be seen that the embodiment of the present application obtains combined information by merging the SLC / XLC MODE information into the Row address information, thereby saving the bit width that the SLC / XLC MODE information should have occupied, thereby reducing the total bit width.

[0065] Step S103, combining the CH information, LUN information, Clst information and combination information into target logical address information.

[0066] In an implementation manner of the present application, the terminal device may combine CH information, LUN information, Clst information and combination information in a preset order and format to obtain complete target logical address information so that the SSD controller can accurately locate the storage unit.

[0067] The beneficial effect of the embodiment of the present application compared with the prior art is: the embodiment of the present application obtains the initial logical address information of the storage device, and optimizes the bit width of the SLC / XLC MODE information and the Row address information to obtain the combination information, and then combines the CH information, LUN information, Clst information and the combination information into the target logical address information. The embodiment of the present application optimizes the bit width of the SLC / XLC MODE information and the Row address information, and compared with the prior art, the bit width required for the SLC / XLC MODE information can be omitted, thereby reducing the total bit width of the logical address, thereby saving storage space, reducing algorithm calculation overhead, and improving storage device performance.

[0068] In some implementations of the present application, after the CH information, the LUN information, the Clst information and the combination information are combined into the target logical address information, the steps S401 to S405 may be specifically included.

[0069] Step S401: Allocate 2 bits of bit width to CH information.

[0070] In the implementation manner of the present application, the terminal device may reserve 2 bits for the CH information in the total bit width of the target logical address information. Through these 2 bits, up to 4 different channels (00, 01, 10, 11 correspond to channels 0 to 3 respectively) can be represented to ensure that the CH information can be accurately represented in the target logical address information while saving the bit width as much as possible.

[0071] Step S402: Allocate 2 bits of bit width to the LUN information.

[0072] In the implementation manner of the present application, the terminal device may reserve 2 bits for LUN information in the total bit width of the target logical address information. Through these 2 bits, up to 4 different logical units (00, 01, 10, 11 correspond to logical units 0 to 3, respectively) may be represented, so as to ensure that the LUN information can be accurately represented in the target logical address information while saving the bit width as much as possible.

[0073] Step S403: allocate a 2-bit bit width to the Clst information.

[0074] In the implementation manner of the present application, the terminal device may reserve 2 bits for the Clst information in the total bit width of the target logical address information. Through these 2 bits, up to 4 different clusters (00, 01, 10, 11 correspond to clusters 0 to 3, respectively) may be represented to ensure that the Clst information can be accurately represented in the target logical address information while saving the bit width as much as possible.

[0075] Step S404: Allocate a bit width of 26 bits for the combined information.

[0076] In the implementation manner of the present application, the terminal device may reserve 26 bits for the combination information in the total bit width of the target logical address information. Through these 26 bits, a relatively large range can be represented (for example, for binary numbers, integers from 0 to 2^26-1 can be represented), so as to be applicable to large-capacity storage devices.

[0077] Step S405 , combining the CH information, LUN information, Clst information and combination information into target logical address information according to the allocated bit width.

[0078] In the implementation manner of the present application, the terminal device can arrange the CH information, LUN information, Clst information and combination information in the corresponding position of the target logical address information in sequence according to the allocated bit width. Of course, it can also be arranged in other arrangement orders, and the implementation manner of the present application is not limited to this. For example, the CH information (2 bits) can be placed first, followed by the LUN information (2 bits), followed by the Clst information (2 bits), and finally the combination information (26 bits), thereby forming a complete and compact target logical address information, which is convenient for the SSD controller to quickly locate the storage unit.

[0079] For example, assume that a storage unit of an SSD has the following information:

[0080] CH information: 01 (indicates the second channel)

[0081] LUN information: 01 (indicates the second logical unit)

[0082] Clst information: 00 (indicates the first cluster)

[0083] Combined information (obtained by optimizing the combination of SLC / XLC MODE information and Row address information): assumed to be 0x003FF0 (binary representation is 00000000 00111111 11110000).

[0084] This information can be combined into a target logical address information:

[0085] CH information (2 bits): 01; LUN information (2 bits): 01; Clst information (2 bits): 00; combined information (26 bits): 0x003FF0. The target logical address information obtained by combining the above information is: 010100003FF0.

[0086] In some specific implementations of the present application, the above-mentioned bit width optimization combination of SLC / XLC MODE information and Row address information to obtain combined information may further include steps S501 to S503.

[0087] Step S501: Set a mark bit at a first preset position of Row address information.

[0088] In an implementation manner of the present application, the terminal device may first determine the total bit width of the Row address information, and reserve one or more bits at the beginning or a fixed position as a mark bit, and keep this preset position consistent in the entire data structure for subsequent processing and parsing.

[0089] Step S502: determine the flag value of the flag bit according to the SLC / XLC MODE information.

[0090] In the implementation manner of the present application, the terminal device can determine a corresponding tag value according to the specific value of the SLC / XLC MODE information (for example, using binary code to represent different storage modes). This tag value is a short and easy-to-distinguish binary sequence. Through the tag value, the storage mode used by the storage unit can be quickly identified to perform subsequent storage operations (such as reading, writing, and erasing, etc.).

[0091] Step S503, fill the tag value into the tag bit of the Row address information to obtain the combination information.

[0092] In an implementation of the present application, the terminal device can directly write the determined tag value into the tag bit reserved for the Row address information, thereby obtaining combined information including SLC / XLC MODE information. At this time, the combined information includes both row address information and storage mode information. By integrating the row address information and storage mode information, a compact and easy-to-process data structure is formed, which helps to reduce the use of storage space and improve the efficiency of data processing.

[0093] In some specific implementations of the present application, the above-mentioned bit width optimization combination of SLC / XLC MODE information and Row address information to obtain combined information may specifically include step S601 and step S602.

[0094] Step S601: Encode SLC / XLC MODE information into a first SLC / XLC MODE binary sequence according to a first preset encoding rule.

[0095] The first preset encoding rule is a rule for converting storage mode information into a binary sequence, and this rule defines how to map different storage modes to different binary sequences.

[0096] In an implementation of the present application, the terminal device may first determine the possible values ​​of the storage mode information (such as SLC and TLC). Then, according to the first preset coding rule, each storage mode is mapped to a unique binary sequence, and the length of the binary sequence is ensured to be as short as possible to reduce the use of storage space. For example, it may be specified that SLC is mapped to 00 and TLC is mapped to 01. By encoding, the storage mode information is converted into a binary sequence, which is convenient for subsequent embedding into the row address information.

[0097] Step S602: embed the first SLC / XLC MODE binary sequence into the second preset position of the Row address information to obtain combined information.

[0098] In an embodiment of the present application, the terminal device can determine one or more reserved positions (second preset positions) in the row address information, and the second preset position is sufficient to accommodate the binary sequence of the storage mode information. Then, the first SLC / XLC MODE binary sequence is inserted into the second preset position. And when inserting, byte alignment, bit filling or shifting operations are performed to ensure the correctness and readability of the combined information. By embedding, the storage mode information and the row address information are integrated together to form a compact and easy-to-process data structure, which helps to reduce the use of storage space and improve the efficiency of data processing.

[0099] In some implementations of the present application, the above-mentioned bit width optimization combination of the SLC / XLC MODE information and the Row address information to obtain the combined information may specifically include steps S701 to S703.

[0100] Step S701: Encode the SLC / XLC MODE information into a second SLC / XLC MODE binary sequence according to a second preset encoding rule.

[0101] The second preset encoding rule is a rule for converting storage mode information into a binary sequence, which defines how to map different storage modes to different binary sequences and may be the same as or different from the first preset encoding rule.

[0102] In an embodiment of the present application, the terminal device may first determine the possible values ​​of the storage mode information (such as SLC and TLC). Then, according to the second preset coding rule, each storage mode is mapped to a unique binary sequence. The length of this binary sequence is determined according to the number of storage modes and the required uniqueness. For example, if there are only two storage modes (SLC and TLC) and a 4-bit binary number is required to represent them (in order to leave room or consider future scalability), then it can be specified that SLC is mapped to 0000 and TLC is mapped to 0001. Through encoding, the storage mode information is converted into a binary sequence for subsequent insertion into the row address information.

[0103] Step S702: determine the total bit width of the Row address information, and determine the insertion position of the second SLC / XLC MODE binary sequence in the Row address information.

[0104] In an implementation manner of the present application, the terminal device may first obtain the total bit width of the row address information (i.e., the length of the row address information, in bits). Then, based on the alignment of the data, the compatibility of the system, and the convenience of subsequent processing, determine the position of the row address information into which the binary sequence of the storage mode information should be inserted. This position may be the beginning (highest or lowest bit), the end, or a certain position in the middle of the row address information. This ensures that the binary sequence of the storage mode information can be correctly embedded in the row address information and does not destroy the integrity and readability of the row address information.

[0105] Step S703: Move the second SLC / XLC MODE binary sequence to the insertion position, and perform a mask operation on the second SLC / XLCMODE binary sequence to obtain combination information.

[0106] In an embodiment of the present application, the terminal device may first move the binary sequence of the storage mode information to the insertion position. If the insertion position is not the original position of the binary sequence, a shift operation (such as left shift or right shift) is performed. Then, a mask operation is performed on the binary sequence of the storage mode information.

[0107] Specifically, some bits of a mask value (a binary number with the same length as the binary sequence of the storage mode information) can be set to 1 (indicating that these bits will be retained or modified), and other bits can be set to 0 (indicating that these bits will be ignored or remain unchanged). In this step, the mask value is designed to retain only the valid bits in the binary sequence of the storage mode information and set other bits to 0 (or other settings as needed). Finally, the binary sequence of the storage mode information that has undergone the mask operation is combined with the rest of the row address information to form the final combined information.

[0108] It should be understood that in the implementation of the present application, the mask operation refers to formatting or adjusting the binary sequence of the storage mode information to ensure that it is correctly embedded in the row address information. Therefore, the mask operation here can include a combination of multiple bit operations such as shift, bit AND, bit OR, etc.

[0109] For example, assuming that the row address information of a flash array is 8 bits (i.e., 256 rows), and there are two storage modes: SLC and TLC. The storage mode information can be encoded, inserted, and masked in the following manner:

[0110] The second preset coding rule: SLC is mapped to 0000, and TLC is mapped to 0001.

[0111] Insertion position: Assume that the lowest 4 bits of the row address information are selected as the insertion position (ie, the area for the mask operation).

[0112] Original row address information: 10000000 (indicating row 128).

[0113] Storage mode information (assuming TLC): 0001.

[0114] The terminal device can encode the storage mode information into a binary sequence 0001, and determine the insertion position as the lowest 4 bits of the row address information. Then move the binary sequence 0001 of the storage mode information to the insertion position and perform a mask operation on it (in fact, in this example, since the insertion position is empty, no additional mask operation is required, and the binary sequence of the storage mode information only needs to be directly inserted). However, in order to illustrate the concept of mask operation, it can be assumed that there is a mask value 11110000 (where the upper 4 bits are 1, indicating that these bits will be retained; the lower 4 bits are 0, indicating that these bits will be replaced by the binary sequence of the storage mode information). Then, perform a bitwise AND operation on the original row address information and the mask value. Finally, the binary sequence 0001 of the storage mode information is combined with the upper 4 bits 1000 of the original row address information to obtain the combined information 10000001.

[0115] The implementation method of the present application correctly embeds the binary sequence of storage mode information into the row address information through shift and mask operations, forming a compact and easy-to-process data structure, which helps to reduce the use of storage space and improve the efficiency of data processing.

[0116] In some specific implementations of the present application, the above-mentioned combining of CH information, LUN information, Clst information and combination information into target logical address information may specifically include the following steps:

[0117] According to a preset format and a preset order, the CH information, the LUN information, the Clst information and the combination information are sequentially spliced ​​to obtain the target logical address information.

[0118] In an embodiment of the present application, after obtaining CH information, LUN information, Clst information and combination information, the terminal device can determine the preset format and preset order of the target logical address information, specifically including defining the length, arrangement order and separator of the information field, etc., to provide a clear structure and order for the combination information, and ensure the consistency and readability of the target logical address information. Then, according to the preset order, the CH information, LUN information, Clst information and combination information are spliced ​​together in sequence. Specifically, each information field can be converted into binary or hexadecimal form, and arranged and combined according to the preset format. Finally, the spliced ​​information field is converted into the final target logical address information format, and further processing or formatting can be performed to ensure that the target logical address information meets the requirements of the storage system.

[0119] For example, it is assumed that the CH information is 2 bytes (16 bits), the LUN information is 4 bytes (32 bits), the Clst information is 4 bytes (32 bits), and the combined information is 8 bytes (64 bits). The preset format can be defined as: CH information (2 bytes) + LUN information (4 bytes) + Clst information (4 bytes) + combined information (8 bytes). The preset order is from left to right (or from large address to small address, depending on the byte order of the system). When splicing, each information field can be regarded as a binary string or hexadecimal number and spliced ​​according to the preset format.

[0120] In some specific implementations of the present application, the above-mentioned acquisition of the initial logical address information of the storage device may specifically include the following steps:

[0121] The configuration information of the storage device is read through the control interface of the storage device to obtain the initial logical address information.

[0122] In an embodiment of the present application, the terminal device may first determine the control interface for communicating with the storage device. This generally involves understanding the model, specifications, and communication protocol of the storage device. Then, a command to read the configuration information is sent to the storage device through the control interface. Specifically, it may include constructing an appropriate command format and sending it to the control interface of the storage device. Then, the configuration information returned by the storage device is received and parsed, and operations such as parsing binary data, extracting key fields, and verifying data integrity may be performed. In the process of parsing the configuration information, the fields related to the initial logical address information are identified and extracted, thereby obtaining the initial logical address information of the storage device.

[0123] Figure 2A schematic diagram of the structure of a logical address representation device provided in an embodiment of the present application is shown. The logical address representation device 2 may be configured on a terminal device. Specifically, the logical address representation device 2 may include:

[0124] The acquisition module 201 is used to acquire the initial logical address information of the storage device, wherein the initial logical address information includes SLC / XLC MODE information, CH information, LUN information, Clst information, and Row address information;

[0125] The optimization module 202 is used to optimize the bit width of the SLC / XLC MODE information and the Row address information to obtain combined information;

[0126] The combining module 203 is used to combine the CH information, the LUN information, the Clst information and the combined information into target logical address information.

[0127] The beneficial effect of the embodiment of the present application compared with the prior art is: the embodiment of the present application obtains the initial logical address information of the storage device, and optimizes the bit width of the SLC / XLC MODE information and the Row address information to obtain the combination information, and then combines the CH information, LUN information, Clst information and the combination information into the target logical address information. The embodiment of the present application optimizes the bit width of the SLC / XLC MODE information and the Row address information, and compared with the prior art, the bit width required for the SLC / XLC MODE information can be omitted, thereby reducing the total bit width of the logical address, thereby saving storage space, reducing algorithm calculation overhead, and improving storage device performance.

[0128] In some implementations of the present application, the above-mentioned combination module 203 is also used for:

[0129] Allocate a bit width of 2 bits for the CH information;

[0130] Allocating a bit width of 2 bits to the LUN information;

[0131] Allocate a bit width of 2 bits to the Clst information;

[0132] Allocating a bit width of 26 bits to the combined information;

[0133] The CH information, the LUN information, the Clst information and the combination information are combined into the target logical address information according to the allocated bit width.

[0134] In some implementations of the present application, the optimization module 202 is further used to:

[0135] Setting a mark bit at a first preset position of the Row address information;

[0136] Determine a flag value of the flag bit according to the SLC / XLC MODE information;

[0137] Fill the tag value into the tag bit of the Row address information to obtain the combination information.

[0138] In some implementations of the present application, the optimization module 202 is further used to:

[0139] Encoding the SLC / XLC MODE information into a first SLC / XLC MODE binary sequence according to a first preset encoding rule;

[0140] The first SLC / XLC MODE binary sequence is embedded into a second preset position of the Row address information to obtain the combined information.

[0141] In some implementations of the present application, the optimization module 202 is further used to:

[0142] Encoding the SLC / XLC MODE information into a second SLC / XLC MODE binary sequence according to a second preset encoding rule;

[0143] Determine the total bit width of the Row address information, and determine the insertion position of the second SLC / XLC MODE binary sequence in the Row address information;

[0144] The second SLC / XLC MODE binary sequence is moved to the insertion position, and a mask operation is performed on the second SLC / XLC MODE binary sequence to obtain the combination information.

[0145] In some implementations of the present application, the above-mentioned combination module 203 may also be used for:

[0146] According to a preset format and a preset order, the CH information, the LUN information, the Clst information and the combination information are sequentially spliced ​​to obtain the target logical address information.

[0147] In some implementations of the present application, the acquisition module 201 may be used to:

[0148] The configuration information of the storage device is read through the control interface of the storage device to obtain the initial logical address information.

[0149] like Figure 3FIG. 3 is a schematic diagram of a terminal device provided in an embodiment of the present application. The terminal device 3 may include: a processor 301, a memory 302, and a computer program 303 stored in the memory 302 and executable on the processor 301, such as a program for representing a logical address. When the processor 301 executes the computer program 303, the steps in the above-mentioned embodiments of the method for representing a logical address are implemented, such as Figure 1 Steps S101 to S103 are shown.

[0150] It should be noted that, for the convenience and brevity of description, the structure of the above-mentioned terminal device can also refer to the specific description of the structure in the method embodiment, which will not be repeated here.

[0151] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method for representing a logical address can be implemented.

[0152] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned logical address representation method when executing the computer program product.

[0153] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for expressing a logical address, characterized in that: include: Acquire initial logical address information of the storage device, wherein the initial logical address information includes SLC / XLC MODE information, CH information, LUN information, Clst information, and Row address information; The SLC / XLC MODE information and the Row address information are combined by optimizing the bit width to obtain combined information; The CH information, the LUN information, the Clst information and the combination information are combined into target logical address information.

2. The method for expressing a logical address according to claim 1, characterized in that: The combining the CH information, the LUN information, the Clst information and the combination information into the target logical address information includes: Allocate a bit width of 2 bits for the CH information; Allocating a bit width of 2 bits to the LUN information; Allocate a bit width of 2 bits to the Clst information; Allocating a bit width of 26 bits to the combined information; The CH information, the LUN information, the Clst information and the combination information are combined into the target logical address information according to the allocated bit width.

3. The method for expressing a logical address according to claim 1, wherein: The bit width-optimized combination of the SLC / XLC MODE information and the Row address information to obtain the combined information includes: Setting a mark bit at a first preset position of the Row address information; Determine a flag value of the flag bit according to the SLC / XLC MODE information; Fill the tag value into the tag bit of the Row address information to obtain the combination information.

4. The method for expressing a logical address according to claim 1, wherein: The bit width-optimized combination of the SLC / XLC MODE information and the Row address information to obtain the combined information includes: Encoding the SLC / XLC MODE information into a first SLC / XLC MODE binary sequence according to a first preset encoding rule; The first SLC / XLC MODE binary sequence is embedded into a second preset position of the Row address information to obtain the combined information.

5. The method for expressing a logical address according to claim 1, wherein: The bit width-optimized combination of the SLC / XLC MODE information and the Row address information to obtain the combined information includes: Encoding the SLC / XLC MODE information into a second SLC / XLC MODE binary sequence according to a second preset encoding rule; Determine the total bit width of the Row address information, and determine the insertion position of the second SLC / XLC MODE binary sequence in the Row address information; The second SLC / XLC MODE binary sequence is moved to the insertion position, and a mask operation is performed on the second SLC / XLC MODE binary sequence to obtain the combination information.

6. The method for expressing a logical address according to claim 1, wherein: The combining the CH information, the LUN information, the Clst information and the combination information into the target logical address information includes: According to a preset format and a preset order, the CH information, the LUN information, the Clst information and the combination information are sequentially spliced ​​to obtain the target logical address information.

7. The method for expressing a logical address according to claim 1, wherein: The obtaining of initial logical address information of the storage device includes: The configuration information of the storage device is read through the control interface of the storage device to obtain the initial logical address information.

8. A device for representing a logical address, characterized in that: include: An acquisition module is used to acquire initial logical address information of a storage device, wherein the initial logical address information includes SLC / XLC MODE information, CH information, LUN information, Clst information, and Row address information; An optimization module, used for performing bit width optimization combination of the SLC / XLC MODE information and the Row address information to obtain combination information; A combining module is used to combine the CH information, the LUN information, the Clst information and the combined information into target logical address information.

9. A terminal device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for representing a logical address as claimed in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for representing a logical address according to any one of claims 1 to 7 are implemented.

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