Cache block replacement method and device after cache access failure in a multi-core processor

Abstract

The present invention provides a cache block replacement method and apparatus after a cache access failure in a multi-core processor, which relates to the field of computer technologies. Among them, the cache block replacement method after a cache access failure in a multi-core processor includes: when a cache access fails, taking the status field of the cache block to be replaced at the current moment as the first status field; when the valid bit in the first status field is valid, in the first clock cycle of performing cache block replacement, by accessing the register storing the status field of the cache block to be replaced, reading the latest status field of the cache block to be replaced and taking it as the second status field; and determining whether to perform a data write-back operation on the cache block to be replaced according to the second status field. The present invention can reduce unnecessary data write-back during the cache block replacement process after a cache access failure in a multi-core processor, thereby improving the performance of the processor.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a cache block replacement method and device after high-speed cache access failure of a multi-core processor. Background Art

[0002] With the rapid progress of semiconductor technology, the processing speed and integration of microprocessors have been significantly improved, providing processor designers with more abundant transistor resources. This trend has promoted the development of multi-core processors and has become the mainstream direction of high-performance processor design. Multi-core processors integrate more and more processor cores on-chip to achieve higher parallel processing capabilities and computing efficiency. However, the storage system of multi-core processors faces unprecedented challenges. Due to the need to provide data services to multiple processor cores at the same time, the storage system is under tremendous pressure on access bandwidth. The read and write requests of multiple processor cores, as well as the additional transaction requests generated to maintain multi-core consistency, jointly exacerbate the "Memory Wall" problem, that is, the data access speed of the storage system cannot match the data processing speed of the processor, which seriously restricts the overall performance of the multi-core processor.

[0003] In order to improve the bandwidth resource utilization of multi-core processors, academia and industry have conducted extensive research and exploration. Bandwidth optimization technology has become the key to solving this problem, which can be divided into two categories: one is to directly improve data throughput by increasing the transmission bandwidth of the processor, including increasing the data transmission frequency and increasing the width of the data path; the other is to indirectly improve bandwidth utilization by reducing unnecessary data transmission of the processor, such as reducing data access and write-back operations, reducing the loss of consistency protocol transmission, increasing the proportion of valid data in transmission, and avoiding unnecessary consistency transaction transmission. In the existing cache block replacement method after the cache access of multi-core processors fails, there are unnecessary data write-back operations due to the concurrent characteristics of the cache access of multi-core processors. These additional write-back operations increase the data transmission burden of the processor, further exacerbating the impact of the "storage wall" problem on the performance of multi-core processors.

[0004] Therefore, how to reduce unnecessary data write-back during the cache block replacement process after the cache access failure of a multi-core processor, thereby improving the performance of the processor, is a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention provides a method and device for replacing cache blocks after cache access failure of a multi-core processor, so as to reduce unnecessary data write-back in the cache block replacement process after cache access failure of a multi-core processor, thereby improving the performance of the processor.

[0006] The present invention provides a cache block replacement method after a cache access miss in a multi-core processor, including the following steps.

[0007] In response to a cache access miss in any processor of the multi-core processor, obtain the status fields of each cache block of the processor; wherein, the status fields are implemented by registers, and the status fields include a valid bit indicating whether the corresponding cache block is valid, and a flag bit indicating whether the corresponding cache block is dirty; according to the status fields of each cache block of the processor, determine the cache block to be replaced, and use the status field of the cache block to be replaced at the current moment as the first status field; based on the miss request triggered by the access miss, instruct the lower-level storage system to return the backfill data of the cache block to be replaced; in the case where the valid bit in the first status field is valid, in the first clock cycle of performing cache block replacement, read the latest status field of the cache block to be replaced by accessing the register storing the status field of the cache block to be replaced, and use it as the second status field; according to the second status field, determine whether it is necessary to perform a data write-back operation on the cache block to be replaced; if it is necessary to perform a data write-back operation on the cache block to be replaced, then perform the data write-back operation; in the second clock cycle of performing the cache block replacement, write the backfill data into the cache block to be replaced.

[0008] According to the cache block replacement method after a cache access miss in a multi-core processor provided by the present invention, the determining whether it is necessary to perform a data write-back operation on the cache block to be replaced according to the second status field includes: in response to the valid bit in the second status field being valid and the flag bit being dirty, determining that it is necessary to perform a data write-back operation on the cache block to be replaced.

[0009] According to the cache block replacement method after a cache access miss in a multi-core processor provided by the present invention, the determining whether it is necessary to perform a data write-back operation on the cache block to be replaced according to the second status field includes: in response to the valid bit in the second status field being invalid, determining that it is not necessary to perform a data write-back operation on the cache block to be replaced.

[0010] According to the cache block replacement method after a cache access miss in a multi-core processor provided by the present invention, the determining whether it is necessary to perform a data write-back operation on the cache block to be replaced according to the second status field includes: in response to the valid bit in the second status field being valid and the flag bit in the second status field being clean, determining that it is not necessary to perform a data write-back operation on the cache block to be replaced.

[0011] A cache block replacement method after cache access failure of a multi-core processor provided by the present invention, where the access to the cache is to write data to the cache. After writing the backfill data to the cache block to be replaced, the method further includes: by accessing a register storing the status field of the cache block to be replaced, marking the valid bit of the cache block to be replaced as valid, and marking the identification bit of the cache block to be replaced as clean.

[0012] A cache block replacement method after cache access failure of a multi-core processor provided by the present invention, where the status field further includes a status bit for indicating whether the cache block to be replaced is in a shared state or an exclusive state; after writing the backfill data to the cache block to be replaced, the method further includes: in response to the access to the cache being to write data to the cache, by accessing a register storing the status field of the cache block to be replaced, marking the status bit as the exclusive state; or in response to the access to the cache being to read data from the cache, by accessing a register storing the status field of the cache block to be replaced, marking the status bit as the shared state.

[0013] The present invention further provides a cache block replacement device after cache access failure of a multi-core processor, including the following modules:

[0014] A first acquisition module, configured to, in response to an access miss of a cache of any processor in a multi-core processor, acquire status fields of respective cache blocks of the processor; wherein the status fields are implemented by registers, and the status fields include a valid bit indicating whether the corresponding cache block is valid, and a dirty flag indicating whether the corresponding cache block is dirty; a first determination module, configured to determine a cache block to be replaced according to the status fields of the respective cache blocks of the processor, and use the status field of the cache block to be replaced at the current moment as a first status field; a second acquisition module, configured to, based on a miss request triggered by the access miss, instruct a lower-level storage system to return the fill data of the cache block to be replaced; a third acquisition module, configured to, when the valid bit of the first status field is valid, in a first clock cycle of performing cache block replacement, read the latest status field of the cache block to be replaced by accessing the register storing the status field of the cache block to be replaced, and use it as a second status field; a second determination module, configured to determine whether a data write-back operation of the cache block to be replaced needs to be performed according to the second status field; a write-back module, configured to perform the data write-back operation if the data write-back operation of the cache block to be replaced needs to be performed; a write module, configured to, in a second clock cycle of performing the cache block replacement, write the fill data into the cache block to be replaced.

[0015] The present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the cache block replacement method after cache access miss of the multi-core processor as described in any one of the above is implemented.

[0016] The present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the cache block replacement method after cache access miss of the multi-core processor as described in any one of the above is implemented.

[0017] The present invention further provides a computer program product, including a computer program. When the computer program is executed by a processor, the cache block replacement method after cache access miss of the multi-core processor as described in any one of the above is implemented.

[0018] The cache block replacement method after cache access failure provided by the present invention, in the case of cache access failure of any processor in a multi-core processor, obtains the status fields of each cache block of the processor; determines the cache block to be replaced according to the status fields of each cache block of the processor, and uses the status field of the cache block to be replaced at the current moment as the first status field; based on the failure request triggered by the access failure, instructs the lower-level storage system to return the backfill data of the cache block to be replaced; since the status field is implemented by a register, there is no need to consider the problem that operations on the status fields of multiple cache accesses to the same way will jointly preempt the SRAM (Static Random-Access Memory) port, and the problem that operations on the status fields of cache accesses to the same way will jointly preempt the SRAM port with the tag access request (the status field and the tag are implemented by the same SRAM block). When the valid bit of the first status field is valid, in the first clock cycle of performing cache block replacement, by accessing the register storing the status field of the cache block to be replaced, the latest status field of the cache block to be replaced is read and used as the second status field; according to the second status field that can accurately reflect the status of the cache block to be replaced at this time, it is accurately determined whether it is necessary to perform the data write-back operation of the cache block to be replaced. Therefore, it is possible to avoid writing back the data of the cache block to be replaced that has been invalidated, or the data of the cache block to be replaced that is valid but clean, during the cache block replacement process after cache access failure in a multi-core processor. Since unnecessary data write-back is reduced, the performance of the processor can be effectively improved. Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 is a flowchart of the cache block replacement method after cache access failure of the multi-core processor provided by the present invention.

[0021] Figure 2 is a structural diagram of the multi-core processor cache.

[0022] Figure 3 is a structural diagram of the cache block replacement device after cache access failure of the multi-core processor provided by the present invention.

[0023] Figure 4 is a structural diagram of the electronic device provided by the present invention. Detailed implementation manners

[0024] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0025] The following combines Figure 1 - Figure 2 to describe the cache block replacement method after a cache access miss in a multi-core processor of the present invention.

[0026] Figure 1 is a schematic flowchart of the cache block replacement method after a cache access miss in a multi-core processor provided by the present invention. As Figure 1 shown, this method is executed by a multi-core processor and includes the following:[[]]END]]

[0027] Step 101: In response to a cache access miss for any one of the processors in the multi-core processor, obtain the status fields of each cache block of the processor.

[0028] A cache access miss, also known as a cache miss, refers to a situation where the central processing unit fails to find the required data when attempting to read or write data from the cache. When a cache access miss occurs, the data block needs to be read from the lower-level storage system (i.e., the lower-level cache or the main memory) and placed in the cache for subsequent access.

[0029] As Figure 2 shown, a cache block includes: a tag field (Tag), a data field (Data), and a status field (Meta).

[0030] Among them, the tag field is used to store the high bits of the cache block address for Tag comparison to determine whether the cache is hit.

[0031] Among them, the status field includes a valid bit, an identification bit, and a status bit.

[0032] The valid bit is used to indicate whether the corresponding cache block is valid. When initializing, the value of the valid bit is set to invalid. Generally, binary 0 represents invalid and 1 represents valid.

[0033] The identification bit is used to indicate whether the corresponding cache block is dirty or clean. For example, binary 0 represents clean and 1 represents dirty. In the technical terms of computer science and computer architecture, when the data in a cache block has been modified and this modification has not been written back to a lower-level storage (such as main memory), the cache block is said to be "dirty". When the data in a cache block is exactly the same as the data in the main memory and has not been modified in the cache, the cache block is said to be "clean".

[0034] The status bit is used to indicate the status category of the corresponding cache block in the cache, including two states: shared (abbreviated as SHD) and exclusive (abbreviated as EXC). Both of these two states are regarded as valid states.

[0035] When the status bit is SHD (for example, binary 01), it means that the corresponding cache block is in a shared state in the cache. When the processor core reads this block, it can directly hit; if it needs to write to this block, it needs to invalidate the copies in other processor cores first to obtain the exclusive state before writing.

[0036] When the status bit is EXC (for example, binary 10), it means that the corresponding cache block is in an exclusive state in the cache. The processor can directly hit when reading and writing this block.

[0037] In the prior art, the status field, tag field, and data field of the cache block are all implemented using static random-access memory (SRAM). Therefore, multiple operations that simultaneously access the status field of the same cache line will jointly preempt the SRAM port, thereby affecting the execution efficiency of access requests. If the status field and the tag are implemented using the same SRAM block, it will also cause the operations of accessing the status field of the same cache line and the tag access requests to jointly preempt the SRAM port.

[0038] In the present invention, the status field is implemented using registers so that the operations of accessing the status field of the cache block do not affect the execution efficiency of access requests for random-access memory. Since the tag field and the data field have a large number of bits, they are implemented using random-access memory to save chip area.

[0039] Step 102: Determine the cache block to be replaced according to the status fields of each cache block of the processor, and use the status field of the cache block to be replaced at the current moment as the first status field.

[0040] The organizational structure of the cache is as Figure 2As shown, the cache block adopts a multi-way set associative structure. Both direct mapping and fully associative mapping can be regarded as special cases of this structure: direct mapping is equivalent to one-way set associative mapping, while fully associative mapping is equivalent to set associative mapping with the number of cache lines of the cache.

[0041] When a memory access instruction accesses the cache, it needs to read out the states of the cache blocks in each way to determine whether there is a hit. If there is no hit, according to the states, ages and other information of the cache blocks in each way, the cache replacement algorithm is used to determine which cache block in which way to replace, and the replacement way information such as the state field and tag field of the cache block to be replaced is stored in the memory access miss queue (Miss Queue) together with the miss access request. Among them, memory access instructions mainly refer to instructions for reading data from the cache (Load instructions) and instructions for writing data to the cache (Store instructions).

[0042] When determining the cache block to be replaced, it can be selected according to a preset replacement policy. The preset replacement policies include random replacement policy (Random), least recently used replacement policy (Least Recently Used, LRU), least frequently used replacement policy (Least Frequently Used, LFU), and first in first out replacement policy (First In First Out, FIFO), etc. According to the selected replacement policy, the corresponding replacement block in the cache is determined, and the state field of the replacement block is obtained.

[0043] Step 103: Based on the miss request triggered by the memory access miss, instruct the lower-level storage system to return the fill data of the cache block to be replaced.

[0044] In the specific implementation process, the memory access miss queue is responsible for sending the miss request to the lower-level storage system. The lower-level storage system searches for and returns the data that misses the memory access miss, and uses it as the fill data of the cache block to be replaced.

[0045] Step 104: When the valid bit of the first state field is valid, in the first clock cycle of performing cache block replacement, read the latest state field of the cache block to be replaced by accessing the register storing the state field of the cache block to be replaced, and use it as the second state field.

[0046] In the related art, in the case of a cache access miss, according to the cache replacement policy, the cache block to be replaced is determined, and the state field of the cache block to be replaced is obtained. After the miss request enters the memory access miss queue (Miss Queue), the state field of the cache block to be replaced is no longer read. If the valid bit of the state field of the cache block to be replaced obtained at this time is valid, this policy may lead to the following two situations.

[0047] In the first case, when the cache block to be replaced is in a valid and clean state, there is no need to perform a write-back operation on it, but an unnecessary write-back operation is still performed.

[0048] During the process of waiting to obtain the backfill data, the cache block to be replaced may be marked as dirty due to the execution of other store instructions. Therefore, when getting the backfill data and preparing to perform the cache block replacement operation, since the system cannot determine whether the cache block to be replaced has been modified by a store instruction, even if the cache block to be replaced is in a valid and clean state at this time, to ensure data consistency, it is necessary to perform the write-back operation on the cache block to be replaced, which results in wasting the storage bandwidth of the processor and affecting the processor performance.

[0049] In the second case, when the cache block to be replaced is in an invalid state, there is no need to perform a write-back operation on it, but an unnecessary write-back operation is still performed.

[0050] During the process of waiting to obtain the backfill data, the cache block to be replaced may be marked as invalid due to an external coherence request sent by other processor cores to maintain cache coherence. When getting the backfill data and preparing to perform the cache block replacement operation, since the system cannot determine whether the cache block to be replaced is still in a valid state or is marked as invalid due to an external coherence request, therefore, even if the cache block to be replaced is already in an invalid state at this time, to ensure data consistency, it is necessary to perform the write-back operation on the cache block to be replaced, which also wastes the storage bandwidth of the processor and affects the processor performance.

[0051] Since in the present invention, the status field of the cache block is implemented through a register, multiple reads of the status information will not cause port contention for other normal cache access requests. In the first clock cycle of performing the cache block replacement, if the valid bit of the first status field is valid, by accessing the register storing the status field of the cache block to be replaced, a second status field that can accurately reflect the state of the cache block to be replaced at this time is obtained. In the subsequent steps, it is possible to accurately determine whether it is necessary to perform the write-back operation on the cache block to be replaced based on the second status field, so as to avoid wasting the storage bandwidth of the processor.

[0052] If the valid bit of the first status field is invalid, the above steps and subsequent steps 105 and 106 do not need to be performed, and directly jump to step 107.

[0053] Step 105: Determine whether it is necessary to perform the data write-back operation on the cache block to be replaced according to the second status field.

[0054] In some embodiments, when the valid bit in the second status field is valid and the identification bit in the second status field is clean, it is determined that there is no need to perform a data write-back operation on the cache block to be replaced, and only the valid bit of the cache block to be replaced needs to be marked as invalid.

[0055] In some embodiments, when the valid bit in the second status field is valid and the identification bit is dirty, it can be accurately known that during the process of waiting to obtain the backfill data, the cache block to be replaced is marked as dirty due to the execution of other store instructions. Therefore, it can be accurately determined that a data write-back operation on the cache block to be replaced needs to be performed.

[0056] In some embodiments, when the valid bit in the second status field is invalid, it can be accurately known that during the process of waiting to obtain the backfill data, the cache block to be replaced is marked as invalid due to an external coherence request for maintaining cache coherence sent by other processor cores. Therefore, it can be accurately determined that there is no need to perform a data write-back operation on the cache block to be replaced. Thus, unnecessary write-backs to invalid cache blocks are avoided.

[0057] Step 106: If a data write-back operation on the cache block to be replaced needs to be performed, then perform the data write-back operation.

[0058] When performing the data write-back operation, it can be carried out according to a preset write-back policy. The write-back policy may include immediate write-back, deferred write-back, etc., depending on the system design and implementation.

[0059] Step 107: In the second clock cycle of performing cache block replacement, write the backfill data into the cache block to be replaced.

[0060] In the specific implementation process, after writing the backfill data into the cache block to be replaced, the following operations also need to be performed.

[0061] By accessing the register storing the status field of the cache block to be replaced, mark the valid bit of the cache block to be replaced as valid, and mark the corresponding identification bit of the cache block to be replaced as clean. Subsequently, when the data in the cache block to be replaced is modified, mark the identification bit as dirty.

[0062] In the case where the access to the cache is a write operation to the cache (i.e., a store instruction access), mark the status bit as the exclusive state by accessing the register storing the status field of the cache block to be replaced.

[0063] In the case where the access to the cache is a read operation from the cache (i.e., a load instruction access), mark the status bit as the shared state by accessing the register storing the status field of the cache block to be replaced.

[0064] The cache block replacement device after cache access failure of the multi-core processor provided by the present invention will be described below. The cache block replacement device after cache access failure of the multi-core processor described below can be correspondingly referred to the cache block replacement method after cache access failure of the multi-core processor described above.

[0065] Figure 3 It is a schematic structural diagram of the cache block replacement device after cache access failure of the multi-core processor provided by the present invention. As Figure 3 shown, the device 300 includes the following modules.

[0066] The first acquisition module 310 is configured to, in response to a cache access failure for any processor in the multi-core processor, acquire the status fields of each cache block of the processor; wherein, the status field is implemented by a register, and the status field includes a valid bit indicating whether the corresponding cache block is valid, and a flag bit indicating whether the corresponding cache block is dirty.

[0067] The first determination module 320 is configured to determine a cache block to be replaced according to the status fields of each cache block of the processor, and use the status field of the cache block to be replaced at the current moment as the first status field.

[0068] The second acquisition module 330 is configured to, based on the failure request triggered by the access failure, instruct the lower-level storage system to return the backfill data of the cache block to be replaced.

[0069] The third acquisition module 340 is configured to, when the valid bit in the first status field is valid, in the first clock cycle of performing cache block replacement, read the latest status field of the cache block to be replaced by accessing the register storing the status field of the cache block to be replaced, and use it as the second status field.

[0070] The second determination module 350 is configured to determine whether it is necessary to perform a data write-back operation on the cache block to be replaced according to the second status field.

[0071] The write-back module 360 is configured to perform the data write-back operation if it is necessary to perform a data write-back operation on the cache block to be replaced.

[0072] The write module 370 is configured to write the backfill data into the cache block to be replaced in the second clock cycle of performing the cache block replacement.

[0073] Figure 4 It exemplifies a schematic structural diagram of an electronic device, as Figure 4As shown in the figure, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communications interface 420, and the memory 430 complete their mutual communication through the communication bus 440. The processor 410 may call the logical instructions in the memory 430 to execute a cache block replacement method after a cache access miss in a multi-core processor. The method includes: in response to a cache access miss for any processor in the multi-core processor, obtaining the status fields of each cache block of the processor; wherein, the status fields are implemented using registers, and the status fields include a valid bit indicating whether the corresponding cache block is valid, and a dirty flag indicating whether the corresponding cache block is dirty; determining a cache block to be replaced according to the status fields of each cache block of the processor, and using the status field of the cache block to be replaced at the current moment as a first status field; based on the miss request triggered by the access miss, instructing the lower-level storage system to return the fill data of the cache block to be replaced; in the case where the valid bit in the first status field is valid, in the first clock cycle of performing cache block replacement, reading the latest status field of the cache block to be replaced by accessing the register storing the status field of the cache block to be replaced, and using it as a second status field; determining whether to perform a data write-back operation on the cache block to be replaced according to the second status field; if it is necessary to perform a data write-back operation on the cache block to be replaced, then performing the data write-back operation; in the second clock cycle of performing the cache block replacement, writing the fill data into the cache block to be replaced.

[0074] In addition, when the logical instructions in the above-mentioned memory 430 are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, may be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0075] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the cache block replacement method after a cache access failure provided by each of the above methods. The method includes: in response to a cache access failure for any processor in a multi-core processor, obtaining status fields of each cache block of the processor; wherein, the status fields are implemented by registers, and the status fields include a valid bit indicating whether the corresponding cache block is valid, and a flag bit indicating whether the corresponding cache block is dirty; determining a cache block to be replaced according to the status fields of each cache block of the processor, and using the status field of the cache block to be replaced at the current moment as a first status field; based on the failure request triggered by the access failure, instructing the lower-level storage system to return the backfill data of the cache block to be replaced; in the case where the valid bit in the first status field is valid, in the first clock cycle of performing cache block replacement, reading the latest status field of the cache block to be replaced by accessing the register storing the status field of the cache block to be replaced, and using it as a second status field; determining whether a data write-back operation for the cache block to be replaced needs to be performed according to the second status field; if a data write-back operation for the cache block to be replaced needs to be performed, performing the data write-back operation; in the second clock cycle of performing the cache block replacement, writing the backfill data into the cache block to be replaced.

[0076] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a cache block replacement method after a cache access failure of a multi-core processor provided by the above various methods. The method includes: in response to a cache access failure of any processor in the multi-core processor, obtaining status fields of each cache block of the processor; wherein, the status fields are implemented by registers, and the status fields include a valid bit indicating whether the corresponding cache block is valid, and a flag bit indicating whether the corresponding cache block is dirty; determining a cache block to be replaced according to the status fields of each cache block of the processor, and using the status field of the cache block to be replaced at the current moment as a first status field; based on a failure request triggered by the access failure, instructing a lower-level storage system to return the backfill data of the cache block to be replaced; when the valid bit in the first status field is valid, in the first clock cycle of performing cache block replacement, reading the latest status field of the cache block to be replaced by accessing the register storing the status field of the cache block to be replaced, and using it as a second status field; determining whether a data write-back operation of the cache block to be replaced needs to be performed according to the second status field; if the data write-back operation of the cache block to be replaced needs to be performed, performing the data write-back operation; in the second clock cycle of performing the cache block replacement, writing the backfill data into the cache block to be replaced.

[0077] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0078] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on such an understanding, the above technical solutions, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for replacing cache blocks after a multi-core processor cache access failure, characterized in that: include: In response to an access failure to a cache of any processor in the multi-core processor, a status field of each cache block of the processor is obtained; wherein the status field is implemented using a register, and the status field includes a valid bit indicating whether the corresponding cache block is valid, and a flag bit indicating whether the corresponding cache block is dirty; Determine a cache block to be replaced according to the status field of each cache block of the processor, and use the status field of the cache block to be replaced at the current moment as the first status field; Based on the invalidation request triggered by the access invalidation, instruct the lower storage system to return the backfill data of the cache block to be replaced; When the valid bit of the first status field is valid, in the first clock cycle of executing cache block replacement, by accessing the register storing the status field of the cache block to be replaced, the latest status field of the cache block to be replaced is read and used as the second status field; Determining whether it is necessary to perform a data write-back operation on the to-be-replaced cache block according to the second status field; If it is necessary to perform a data write-back operation on the cache block to be replaced, perform the data write-back operation; In the second clock cycle of executing the cache block replacement, the backfill data is written into the cache block to be replaced.

2. The method for replacing cache blocks after cache access failure of a multi-core processor according to claim 1, characterized in that: The determining, according to the second status field, whether it is necessary to perform a data write-back operation on the cache block to be replaced includes: In response to the valid bit in the second status field being valid and the flag bit being dirty, it is determined that a data write-back operation of the to-be-replaced cache block needs to be performed.

3. The method for replacing cache blocks after cache access failure of a multi-core processor according to claim 1, characterized in that: The determining, according to the second status field, whether it is necessary to perform a data write-back operation on the cache block to be replaced includes: In response to the valid bit in the second status field being invalid, it is determined that there is no need to perform a data write-back operation on the to-be-replaced cache block.

4. The method for replacing cache blocks after cache access failure of a multi-core processor according to claim 1, characterized in that: The determining, according to the second status field, whether it is necessary to perform a data write-back operation on the cache block to be replaced includes: In response to the valid bit of the second status field being valid and the flag bit of the second status field being clean, it is determined that there is no need to perform a data write-back operation on the cache block to be replaced.

5. The method for replacing cache blocks after cache access failure of a multi-core processor according to claim 1, characterized in that: The access to the cache is to write data to the cache. After writing the backfill data into the cache block to be replaced, the method further includes: By accessing the register storing the status field of the cache block to be replaced, the valid bit of the cache block to be replaced is marked as valid, and the identification bit of the cache block to be replaced is marked as clean.

6. The method for replacing cache blocks after cache access failure of a multi-core processor according to claim 1, characterized in that: The state field also includes a state bit, and the state bit is used to indicate whether the cache block to be replaced is in a shared state or an exclusive state; After writing the backfill data into the cache block to be replaced, the method further includes: In response to the access to the cache being to write data to the cache, the status bit is marked as an exclusive state by accessing a register storing a status field of the cache block to be replaced; or In response to the access to the cache being to read data from the cache, the state bit is marked as a shared state by accessing a register storing a state field of the cache block to be replaced.

7. A cache block replacement device for a multi-core processor after cache access failure, characterized in that: include: A first acquisition module is configured to acquire, in response to an access failure to a cache of any processor in the multi-core processor, a status field of each cache block of the processor; wherein the status field is implemented using a register, and the status field includes a valid bit indicating whether the corresponding cache block is valid, and a flag bit indicating whether the corresponding cache block is dirty; A first determining module, configured to determine a cache block to be replaced according to the status fields of each cache block of the processor, and use the status field of the cache block to be replaced at a current moment as a first status field; A second acquisition module, configured to instruct a lower-layer storage system to return backfill data of the cache block to be replaced based on the failure request triggered by the access failure; A third acquisition module is used for, when the valid bit of the first status field is valid, in a first clock cycle of executing cache block replacement, accessing a register storing the status field of the cache block to be replaced, reading the latest status field of the cache block to be replaced as the second status field; A second determination module, configured to determine whether a data write-back operation of the to-be-replaced cache block needs to be performed according to the second status field; A write-back module, configured to perform a data write-back operation on the cache block to be replaced if the data write-back operation needs to be performed; The writing module is used to write the backfill data into the to-be-replaced cache block in the second clock cycle of executing the cache block replacement.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method for replacing a cache block after a cache access failure of a multi-core processor as claimed in any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the cache block replacement method after a cache access failure of a multi-core processor as claimed in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the cache block replacement method after a cache access failure of a multi-core processor as claimed in any one of claims 1 to 6 is implemented.

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