DMA controller, data transmission method, equipment and medium

Abstract

The invention relates to a DMA (direct memory access) controller, a data transmission method, equipment and a medium, the DMA controller comprises a core module and a register module, the core module comprises at least one DMA core, and the DMA core adopts an eight-level assembly line sub-module. The data processing module is respectively used for recording channel start transmission preparation, importing configuration information corresponding to the channel into the assembly line, sending a reading request for a reading address through a bus according to the reading address, receiving returned target data and importing the target data into the assembly line according to the width of the reading data; and sending a write-in request and a write-in data width to the write-in address through the bus according to the write-in address, sending the target data through the bus to perform write-in, receiving write-in completion information through the bus to generate update information, and sending the update information to the register module. According to the technical scheme provided by the invention, a built-in FIFO is not needed, and the area is reduced while the transmission speed is met, so that the power consumption and the cost are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data transmission, and in particular to a DMA controller, a data transmission method, a device and a medium. Background Art

[0002] With the continuous development of computer technology, the amount of data that needs to be processed in a short period of time is increasing. At the same time, people's requirements for data transmission speed are also increasing. DMA (Direct Memory Access) is a transmission mechanism for data transmission between external devices and memory, which can realize data transmission without passing through the central processing unit (CPU).

[0003] In the related art, DMA uses FIFO (First Input First Output) to improve the transmission speed. When there is a multi-channel demand, the area required for data transmission increases because the FIFO volume is proportional to the number of channels, which increases power consumption and cost significantly. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a DMA controller, a data transmission method, a device and a medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a DMA controller, including:

[0006] A core module and a register module, wherein the core module includes at least one DMA core, and the DMA core includes a first pipeline submodule, a second pipeline submodule, a third pipeline submodule, a fourth pipeline submodule, a fifth pipeline submodule, a sixth pipeline submodule, a seventh pipeline submodule and an eighth pipeline submodule;

[0007] The first pipeline submodule is used to obtain a transmission request from a requester and record a channel corresponding to the transmission request;

[0008] The second pipeline submodule is used to import the configuration information corresponding to the channel into the pipeline according to the recorded channel; the configuration information includes a read address, a write address, a read data width, a write data width, and a current transmission count value;

[0009] The third pipeline submodule is used to send a read request for the read address through a bus according to the read address;

[0010] The fourth pipeline submodule is used to receive the target data returned in response to the read request, and import the target data into the pipeline according to the read data width;

[0011] The fifth pipeline submodule is used to send a write request for the write address and the write data width through a bus according to the write address;

[0012] The sixth pipeline submodule is used to send the target data through a bus for writing;

[0013] The seventh pipeline submodule is used to receive write completion information through a bus;

[0014] The eighth pipeline sub-module is used to generate update information and send it to the register module.

[0015] In a second aspect, an embodiment of the present disclosure provides a data transmission method, including:

[0016] Obtaining a transmission request from a requesting party, and recording a channel corresponding to the transmission request;

[0017] According to the recorded channel, the configuration information corresponding to the channel is imported into the pipeline; the configuration information includes a read address, a write address, a read data width, a write data width, and a current transmission count value;

[0018] According to the read address, sending a read request for the read address through a bus;

[0019] receiving target data returned in response to the read request, and importing the target data into the pipeline according to the read data width;

[0020] According to the write address, sending a write request for the write address and the write data width through a bus;

[0021] Sending the target data via a bus for writing;

[0022] receiving write completion information via the bus;

[0023] Generates update information to update register configuration.

[0024] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: a processor; a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the data transmission method described in the second aspect above.

[0025] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the data transmission method described in the second aspect is implemented.

[0026] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages: the DMA controller adopts a pipeline design to perform overlapping operations of multiple DMA transfers, does not require a built-in FIFO, and while meeting the transmission speed, reduces the area, thereby reducing power consumption and cost, and can fully utilize the bus channels, thereby improving the utilization rate of the bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0029] Figure 1 A schematic diagram of a DMA controller provided by an embodiment of the present disclosure;

[0030] Figure 2 A schematic diagram of a workflow of a core module provided in an embodiment of the present disclosure;

[0031] Figure 3 A schematic diagram of another DMA controller provided by an embodiment of the present disclosure;

[0032] Figure 4 A schematic diagram of a peripheral selection and arbitration module provided by an embodiment of the present disclosure;

[0033] Figure 5 A schematic diagram of a core module provided by an embodiment of the present disclosure;

[0034] Figure 6 A schematic diagram of water flow monitoring provided by an embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of bus monitoring provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0037] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0038] Figure 1 A schematic diagram of a DMA controller provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the DMA controller provided by the embodiment of the present disclosure includes: a core module and a register module.

[0039] The core module includes at least one DMA core, and the DMA core includes a first pipeline submodule, a second pipeline submodule, a third pipeline submodule, a fourth pipeline submodule, a fifth pipeline submodule, a sixth pipeline submodule, a seventh pipeline submodule, and an eighth pipeline submodule. The DMA core adopts a pipeline design, including 8 pipeline submodules, so that multiple instructions overlap and operate to achieve quasi-parallel processing during program execution, and is specifically used for overlapping operations of multiple DMA transmissions in this embodiment.

[0040] In this embodiment, the first pipeline submodule is used to obtain the transmission request of the requester and record the channel corresponding to the transmission request. Optionally, for multiple data transmission requesters, the channel corresponding to the transmission request of each requester is determined, wherein the requester can be a peripheral device to realize data transfer between the peripheral device and the memory, and the memory to the peripheral device, or it can be a memory to realize data transfer from the memory to the memory.

[0041] The second pipeline submodule is used to import the configuration information corresponding to the channel into the pipeline according to the recorded channel, wherein the configuration information includes the read address, the write address, the read data width, the write data width, and the current transmission count value.

[0042] The third pipeline sub-module is used to send a read request for the read address through the bus according to the read address.

[0043] The fourth pipeline submodule is used to receive the target data returned in response to the read request, and import the target data into the pipeline according to the read data width.

[0044] The fifth pipeline sub-module is used to send a write request and a write data width to the write address through the bus according to the write address.

[0045] The sixth pipeline submodule is used to send target data through the bus for writing.

[0046] The seventh pipeline sub-module is used to receive write completion information through the bus.

[0047] The eighth pipeline sub-module is used to generate update information and send it to the register module.

[0048] As an example, multiple data transmission requesters include the first requester to the eighth requester, and the transmission requests correspond to the first channel to the eighth channel respectively. The transmission request of each requester is processed by each pipeline sub-module in the core module. For example, at a certain moment, the first pipeline sub-module obtains the transmission request of the first requester, and records the first channel corresponding to the transmission request of the first requester, and starts the transmission preparation; the second pipeline sub-module imports the configuration information corresponding to the second channel into the pipeline according to the recorded second channel, and the configuration information includes the read address, write address, read data width, write data width, and the current transmission count value; the third pipeline sub-module sends a read request to the read address corresponding to the third channel through the bus; the fourth pipeline sub-module receives the target data returned in response to the read request for the read address corresponding to the fourth channel, And the target data is imported into the pipeline according to the read data width; the fifth pipeline sub-module sends a write request and a write data width for the write address through the bus according to the write address corresponding to the fifth channel; the sixth pipeline sub-module sends the target data corresponding to the sixth channel through the bus for writing; the seventh pipeline sub-module receives write completion information through the bus, and the write completion information is returned after the write completion of the target data corresponding to the seventh channel is sent through the bus; the eighth pipeline sub-module generates update information in response to the completion of the eighth transfer request and sends it to the register module, thereby processing the data transmission requests of eight channels at the same time.

[0049] Compared with the traditional DMA method of using FIFO to speed up the transmission speed, the FIFO volume is proportional to the number of channels when there is a multi-channel demand, which leads to an increase in the area for data transmission, and a large increase in power consumption and cost. In this embodiment, the DMA controller adopts a pipeline design to perform overlapping operations of multiple DMA transmissions to realize DMA parallel processing. It does not require a built-in FIFO, and reduces the area while meeting the transmission speed, thereby reducing power consumption and cost.

[0050] In one embodiment of the present disclosure, the third pipeline sub-module is specifically used to send a read request for a read address through the ar channel of an AXI (Advanced Xtensible Interface, a bus protocol) bus; the fourth pipeline sub-module is specifically used to receive target data returned in response to the read request through the r channel of the AXI bus; the fifth pipeline sub-module is specifically used to send a write request and a write data width for a write address through the aw channel of the AXI bus; the sixth pipeline sub-module is specifically used to send target data through the w channel of the AXI bus; and the seventh pipeline sub-module is specifically used to receive write completion information through the b channel of the AXI bus.

[0051] Reference Figure 2 , Figure 2 , each pipeline submodule is shown in the figure, wherein the first pipeline submodule receives the request information and starts the transmission preparation, the second pipeline submodule loads the information of the register of the corresponding channel and temporarily stores it, the third pipeline submodule sends the read address according to the temporarily stored information, specifically, sends a read request for the read address in the ar channel of the AXI bus, the fourth pipeline submodule waits for and receives the read data, specifically, waits for the r channel of the AXI bus to return the data, the fifth pipeline submodule sends the write address according to the temporarily stored information, specifically, sends a write request for the write address through the aw channel of the AXI bus, the sixth pipeline submodule sends the read data, specifically, sends it through the w channel of the AXI bus, the seventh pipeline submodule waits for the write response information of the write completion, specifically, waits for the b channel of the AXI bus to return the write completion information, and the eighth pipeline submodule updates the information and sends it to the register, for example, sends the transmission address superimposed after the transmission is completed and the number of transmissions reduced by one to the register for the user to read.

[0052] Therefore, in the pipeline process, the called information loading channel, AXI ar channel, AXI r channel, AXI aw channel, AXI w channel, AXI b channel, and information return channel are independent of each other in hardware design, which can ensure the independence of each stage of the pipeline without interfering with each other. In addition, the above-mentioned pipeline design enables the DMA controller to fully utilize the 5 channels of the AXI bus under multi-channel transmission conditions. The theoretical maximum data transmission efficiency can reach five times that of the existing solution. Compared with the existing solution that only one data channel of the bus can be used, it solves the technical problems of large bandwidth waste and performance loss in the AXI bus, and improves the utilization rate of the bus.

[0053] Based on the above embodiments, Figure 3 A schematic diagram of another DMA controller provided by an embodiment of the present disclosure is shown in FIG. Figure 3As shown, the DMA controller includes: a core module, a register module, and a peripheral selection and arbitration module.

[0054] Among them, the peripheral selection and arbitration module includes a peripheral signal selection matrix and a channel priority arbitration matrix. The peripheral signal selection matrix is ​​used to obtain the transmission request of the peripheral, and determine the channel corresponding to each peripheral transmission request according to the channel matching information configured by the register module, and transmit the transmission request to the channel priority arbitration matrix through the corresponding channel; the channel priority arbitration matrix is ​​used to send the transmission request corresponding to each channel to the core module in the order of priority according to the channel priority configured by the register module.

[0055] As an example, Figure 4 As shown, the request signals of peripherals 1 to n are transmitted to the peripheral signal selection matrix after crossing the clock. The peripheral signal selection matrix connects the request signals to the corresponding channels 0 to n according to the channel matching information. The channel priority arbitration matrix sends the transmission requests corresponding to each channel to the core module according to the order of channel priority from high to low, or according to the order of channel sequence from low to high. Among them, the request signal includes a read ready signal and a write ready signal.

[0056] In this embodiment, the core module further includes a delay device and a comparator, and at least one DMA core uses a master DMA core and a slave DMA core, such as Figure 5 shown.

[0057] The input content of the main DMA core includes arbitration information, bus return information, and register change information, and the output content includes a first bus operation output and a first register change output; the first bus operation output and the first register change output are outputs of the core module.

[0058] The input content from the DMA core includes arbitration information passing through the delay device, bus return information passing through the delay device, and register change information passing through the delay device, and the output content includes a second bus operation output and a second register change output.

[0059] The comparator is used to detect the first bus operation output through the second bus operation output and / or detect the first register change output through the second register change output.

[0060] The logic of the master DMA core and the slave DMA core is the same, and the slave DMA core is delayed compared to the master DMA core. Optionally, the delay device is specifically used to delay the arbitration information, bus return information, and register change information by 3 cycles to reduce the susceptibility of common mode failure to the clock power supply. Figure 5As shown, the interface of the main DMA core is directly connected to the outside, and the interface of the slave DMA core is not directly connected to the outside. The output of the slave DMA core is connected to the comparator and compared with the output of the main DMA core for consistency. When the comparison result of the comparator is abnormal, exception processing is performed, such as performing a reset operation. Thus, the security of the DMA controller is improved, and under the architecture of dual DMA cores, compared with the FIFO solution, power consumption and cost can be reduced more.

[0061] In this embodiment, the DMA controller further includes:

[0062] The first watchdog module is used to start timing when any pipeline sub-module is enabled, stop timing when the task of the pipeline sub-module is completed and released, and clear the counter; wherein, if the timing duration is greater than or equal to the preset duration, an alarm signal is triggered to perform alarm processing.

[0063] As an example, Figure 6 As shown in the figure, an independent pipeline watchdog is set on each pipeline of the DMA core for monitoring. If the timing time before the release of the pipeline task of this level is greater than or equal to the preset time, it is determined that the timing has timed out, and an alarm signal is triggered at this time. The alarm processing includes DMA error interrupt processing, notification system error detection module, etc., to remind the user or process.

[0064] In this embodiment, the DMA controller further includes: a second watchdog module, the second watchdog module includes a read channel checker and a read channel watchdog, a write channel checker and a write channel watchdog.

[0065] Optionally, a read channel checker is used to monitor the ar channel and the r channel; and a read channel watchdog is used to start timing when the first access times between the ar channel and the r channel do not match, and to stop timing and clear the counter when the first access times match. If the duration of the read channel watchdog timing is greater than or equal to a preset duration, an alarm signal is triggered to perform alarm processing.

[0066] Optionally, a write channel checker is used to monitor the aw channel, the w channel and the b channel; and a write channel watchdog is used to start timing when the second access times among the aw channel, the w channel and the b channel do not match each other, and to stop timing and clear the counter when the second access times match each other. If the duration of the write channel watchdog timing is greater than or equal to the preset duration, an alarm signal is triggered to perform alarm processing.

[0067] like Figure 7As shown, the second watchdog module is used to monitor and time the input and output of the DMA bus, and the monitoring types include read channel monitoring and write channel monitoring. The access number matching between channels, for example, refers to the same access number. If the duration of the mismatch between the access numbers between the channels is greater than or equal to the preset duration, it is determined that the timing has timed out, and an alarm signal is triggered at this time. The alarm processing includes DMA error interrupt processing, notification system error detection module, etc., to remind the user or perform processing.

[0068] The DMA controller of the disclosed embodiment can be applied to automotive-grade microprocessors to achieve highly secure direct memory access.

[0069] Based on the above embodiments, the embodiments of the present disclosure further provide a data transmission method. The method provided by the embodiments of the present disclosure can be performed by a data transmission device, which can be implemented by software and / or hardware and can be integrated on any electronic device with computing capabilities. The data transmission method provided by the embodiments of the present disclosure may include the following steps:

[0070] Obtain the transmission request from the requester and record the channel corresponding to the transmission request;

[0071] According to the recorded channels, the configuration information corresponding to the channels is imported into the pipeline; the configuration information includes the read address, the write address, the read data width, the write data width, and the current transmission count value;

[0072] According to the read address, a read request for the read address is sent through the bus;

[0073] receiving target data returned in response to a read request, and importing the target data into a pipeline according to a read data width;

[0074] According to the write address, a write request for the write address and a write data width are sent through the bus;

[0075] Send the target data over the bus for writing;

[0076] receiving write completion information via the bus;

[0077] Generates update information to update register configuration.

[0078] Therefore, compared with the DMA transmission of the FIFO solution, the lack of FIFO reduces a large number of SRAM blocks of the FIFO, thereby reducing the area and power consumption, and achieving high-security direct memory access, which can detect errors more accurately and quickly, further improving the security of data transmission.

[0079] Based on the above embodiments, the embodiments of the present disclosure also propose a data transmission device, which includes: a first processing module, a second processing module, a third processing module, a fourth processing module, a fifth processing module, a sixth processing module, a seventh processing module, and an eighth processing module.

[0080] A first processing module is used to obtain a transmission request from a requesting party and record a channel corresponding to the transmission request;

[0081] The second processing module is used to import the configuration information corresponding to the channel into the pipeline according to the recorded channel; the configuration information includes a read address, a write address, a read data width, a write data width, and a current transmission count value;

[0082] A third processing module, configured to send a read request for the read address through a bus according to the read address;

[0083] a fourth processing module, configured to receive target data returned in response to the read request, and to import the target data into the pipeline according to the read data width;

[0084] A fifth processing module, used for sending a write request and a write data width for the write address through a bus according to the write address;

[0085] a sixth processing module, configured to send target data via a bus for writing;

[0086] A seventh processing module, configured to receive write completion information via a bus;

[0087] An eighth processing module is used to generate update information to update register configuration.

[0088] The data transmission device provided in the embodiment of the present disclosure can execute any data transmission method provided in the embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method. For the contents not described in detail in the embodiment of the device of the present disclosure, reference can be made to the description in any method embodiment of the present disclosure.

[0089] The present disclosure also provides an electronic device, which includes one or more processors and a memory. The processor may be a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions. The memory may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on a computer-readable storage medium, and the processor may run the program instructions to implement the method of the above embodiment of the present disclosure and / or other desired functions. Various contents such as input signals, signal components, noise components, etc. may also be stored in the computer-readable storage medium.

[0090] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected through a bus system and / or other forms of connection mechanisms. In addition, the input device may also include, for example, a keyboard, a mouse, etc. The output device may output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and a remote output device connected thereto, etc. In addition, according to the specific application, the electronic device may also include any other appropriate components such as a bus, an input / output interface, etc.

[0091] In addition to the above methods and devices, the embodiments of the present disclosure may also be a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes any method provided by the embodiments of the present disclosure.

[0092] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0093] In addition, the embodiments of the present disclosure may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes any method provided by the embodiments of the present disclosure.

[0094] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0095] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0096] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A DMA controller, characterized in that: include: A core module and a register module, wherein the core module includes at least one DMA core, and the DMA core includes a first pipeline submodule, a second pipeline submodule, a third pipeline submodule, a fourth pipeline submodule, a fifth pipeline submodule, a sixth pipeline submodule, a seventh pipeline submodule and an eighth pipeline submodule; The first pipeline submodule is used to obtain a transmission request from a requester and record a channel corresponding to the transmission request; The second pipeline submodule is used to import the configuration information corresponding to the channel into the pipeline according to the recorded channel; the configuration information includes a read address, a write address, a read data width, a write data width, and a current transmission count value; The third pipeline submodule is used to send a read request for the read address through a bus according to the read address; The fourth pipeline submodule is used to receive the target data returned in response to the read request, and import the target data into the pipeline according to the read data width; The fifth pipeline submodule is used to send a write request for the write address and the write data width through a bus according to the write address; The sixth pipeline submodule is used to send the target data through a bus for writing; The seventh pipeline submodule is used to receive write completion information through a bus; The eighth pipeline sub-module is used to generate update information and send it to the register module.

2. The DMA controller according to claim 1, wherein: Also includes: A peripheral selection and arbitration module, wherein the peripheral selection and arbitration module comprises a peripheral signal selection matrix and a channel priority arbitration matrix; The peripheral signal selection matrix is ​​used to obtain the transmission request of the peripheral, and determine the channel corresponding to each transmission request of the peripheral according to the channel matching information configured by the register module, and transmit the transmission request to the channel priority arbitration matrix through the corresponding channel; The channel priority arbitration matrix is ​​used to send the transmission request corresponding to each channel to the core module in the order of priority according to the channel priority configured by the register module.

3. The DMA controller according to claim 1, wherein: The third pipeline submodule is specifically used to send a read request for the read address through the ar channel of the AXI bus; The fourth pipeline submodule is specifically used to receive the target data returned in response to the read request through the r channel of the AXI bus; The fifth pipeline submodule is specifically used to send a write request for the write address and the write data width through the aw channel of the AXI bus; The sixth pipeline submodule is specifically used to send the target data through the w channel of the AXI bus; The seventh pipeline sub-module is specifically used to receive write completion information through the b channel of the AXI bus.

4. The DMA controller according to claim 1, wherein: The core module also includes: a delay device and a comparator; the at least one DMA core uses a master DMA core and a slave DMA core; The input content of the main DMA core includes arbitration information, bus return information, and register change information, and the output content includes a first bus operation output and a first register change output; the first bus operation output and the first register change output are used as outputs of the core module; The input content from the DMA core includes the arbitration information passed through the delay device, the bus return information passed through the delay device, and the register change information passed through the delay device, and the output content includes the second bus operation output and the second register change output; The comparator is used for detecting the first bus operation output through the second bus operation output and / or detecting the first register change output through the second register change output.

5. The DMA controller according to claim 1, wherein: Also includes: A first watchdog module is used to start timing when any pipeline sub-module is enabled, stop timing when the task of the pipeline sub-module is completed and released, and clear the counter; If the timing duration is greater than or equal to the preset duration, an alarm signal is triggered to perform alarm processing.

6. The DMA controller according to claim 3, wherein: Also includes: A second watchdog module, the second watchdog module comprising a read channel checker and a read channel watchdog; The read channel checker is used to monitor the ar channel and the r channel; The read channel watchdog is used to start timing when the first access times between the ar channel and the r channel do not match, and stop timing and clear the counter when the first access times match; If the duration of the read channel watchdog timing is greater than or equal to a preset duration, an alarm signal is triggered to perform alarm processing.

7. The DMA controller according to claim 6, wherein: The second watchdog module also includes: Write channel checker and write channel watchdog; The write channel checker is used to monitor the aw channel, the w channel and the b channel; The write channel watchdog is used to start timing when the second access times between the aw channel, the w channel and the b channel do not match each other, and stop timing and clear the counter when the second access times match each other; If the duration of the write channel watchdog timing is greater than or equal to a preset duration, an alarm signal is triggered to perform alarm processing.

8. A data transmission method, characterized in that: Applied to the DMA controller as claimed in claim 1, the method comprises: Obtaining a transmission request from a requesting party, and recording a channel corresponding to the transmission request; According to the recorded channel, the configuration information corresponding to the channel is imported into the pipeline; the configuration information includes a read address, a write address, a read data width, a write data width, and a current transmission count value; According to the read address, sending a read request for the read address through a bus; receiving target data returned in response to the read request, and importing the target data into the pipeline according to the read data width; According to the write address, sending a write request for the write address and the write data width through a bus; Sending the target data via a bus for writing; receiving write completion information via the bus; Generates update information to update register configuration.

9. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method of claim 8.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to claim 8 is implemented.

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