Data reading method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a data reading method and device, electronic equipment and a storage medium, and relates to the field of data reading. The method is applied to the embedded storage device and comprises the steps that a current open type multi-block read command sent by a host is received, the preset read data length of the embedded storage device is obtained, and if the current open type multi-block read command is not first-time data reading, the preset read data length of the embedded storage device is obtained; if yes, the preset read data length is set to be the accumulated data transmission length of the DMA module after data transmission of the last multi-block read command is completed, target data reading operation is executed, target data is cached in an RAM cache, and the target data in the RAM cache is transmitted to a host through the DMA module. Through the preset read data length of the embedded storage device, under the condition that the length of the data actually requested by the host is smaller than or equal to the preset read data length, the read command delay time can be shortened, and the processing overhead of the embedded storage device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of data reading, and in particular to a data reading method, device, electronic equipment and storage medium. Background Art

[0002] Open-Ended Multiple-Block Read (OMBR) is the most basic read type in the embedded Multi Media Card (eMMC) device protocol. After the host sends a read command, the embedded storage device prepares data according to the read command address and transmits it to the host. According to the eMMC protocol, open-ended multiple-block read does not define the number of blocks for reading multiple blocks. The device will continuously transmit data blocks until it receives a stop transmission command (StopCommand, CMD12) to complete this read command request.

[0003] In this context, based on the characteristics of open multi-block read, the embedded storage device will continuously prepare data and transmit it to the host. The embedded storage device always prepares read data according to its own random access memory (RAM) cache size. The delay of transmitting data is equal to the time to read data from Nand flash memory to RAM cache. Regardless of the size of the data block requested by the host, its read command delay time is the same. When the host requests a smaller data block, it will cause its read command delay to be higher. Summary of the invention

[0004] In view of this, an object of the embodiments of the present invention is to provide a data reading method, device, electronic device and storage medium to at least partially improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows: In a first aspect, an embodiment of the present invention provides a data reading method, which is applied to an embedded storage device, and the method includes: Receive a current open multi-block read command sent by the host, and obtain a preset read data length of the embedded storage device, if the current open multi-block read command is not the first data read, then the preset read data length is set to the data transmission length accumulated by the DMA module after the previous multi-block read command completes the data transmission; According to the current open multi-block read command and the preset read data length, a target data read operation is performed, the target data is cached in a RAM cache, and the target data in the RAM cache is transmitted to the host through a DMA module.

[0006] Optionally, the method further comprises: After the DMA module completes the current data transmission, if no stop transmission command is received from the host, the preset read data length is set to the capacity of the embedded storage device, and the next target data is read. After the stop transmission command is received from the host, the accumulated data transmission length of the DMA module is obtained, and the accumulated data transmission length is used as the preset read data length of the next multi-block read command.

[0007] Optionally, the step of transmitting the target data in the RAM cache to the host through the DMA module includes: Set the data transmission direction, starting address, block size and number of blocks of the DMA module; The target data is transferred from the RAM cache to the host through the DMA module starting from the start address according to the block size and the number of blocks.

[0008] Optionally, after the step of performing a target data read operation according to the current open multi-block read command and the preset read data length and caching the target data in a RAM cache, the method further comprises: According to the current open multi-block read command and the preset read data length, a predicted target data pre-reading operation is performed to obtain the predicted target data; After the DMA module completes the transmission of the target data and does not receive a stop transmission command sent by the host, the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module.

[0009] Optionally, caching the predicted target data in the RAM cache, and transmitting the predicted target data in the RAM cache to the host through the DMA module, includes: In the case where the data size of the predicted target data is less than or equal to the RAM cache, all of the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module; When the data size of the predicted target data is larger than the RAM cache, caching the first predicted target data of the RAM cache size into the RAM cache; In the process of transmitting the first predicted target data in the RAM cache to the host through the DMA module, sending a data request for the second predicted target data remaining from the predicted target data to the flash memory so that the flash memory is ready for the second predicted target data; After the first predicted target data in the RAM cache is transmitted through the DMA module, the second predicted target data is cached in the RAM cache, and the second predicted target data is transmitted to the host through the DMA module.

[0010] Optionally, the method further comprises: If the subsequent actual access data is smaller than the data size of the predicted target data, the predicted target data that has been read and cached in the RAM cache is cleared.

[0011] Optionally, the method further comprises: If the current open multi-block read command is the first data read, the preset read data length is set to be less than or equal to the capacity of the RAM cache.

[0012] In a second aspect, an embodiment of the present invention provides a data reading device, which is applied to an embedded storage device, and the device includes: A command acquisition unit, used for receiving a current open multi-block read command sent by a host, and acquiring a preset read data length of the embedded storage device, if the current open multi-block read command is not the first data read, then the preset read data length is set to the data transmission length accumulated by the DMA module after the previous multi-block read command completes the data transmission; The data reading unit is used to perform a target data reading operation according to the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transmit the target data in the RAM cache to the host through the DMA module.

[0013] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements any of the above-described methods when executing the program.

[0014] In a fourth aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, wherein the computer program implements any of the above-described methods when executed by a processor.

[0015] A data reading method, device, electronic device and storage medium provided by an embodiment of the present invention can reduce the read command delay time and significantly reduce the processing overhead of the embedded storage device by presetting the read data length and dynamically tracking the actual transmission length of the previous open multi-block read command and using it as the preset read data length of the next multi-block read command.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic structural block diagram of an electronic device provided by an embodiment of the present invention; Figure 2 A schematic structural block diagram of an embedded storage device provided by an embodiment of the present invention; Figure 3 A schematic diagram of a flow chart of a data reading method provided by an embodiment of the present invention; Figure 4 Another schematic diagram of a flow chart of a data reading method provided by an embodiment of the present invention; Figure 5 A schematic diagram of a DMA module transmitting data provided by an embodiment of the present invention; Figure 6 A schematic structural block diagram of a data reading device provided in an embodiment of the present invention.

[0019] Icons: 100 - electronic device; 101 - memory; 102 - communication interface; 103 - processor; 104 - bus; 300 - embedded storage device; 310 - DMA module; 320 - RAM cache; 400 - data reading device; 410 - command acquisition unit; 420 - data reading unit. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0023] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0024] OMBR is the most basic read type in the embedded multimedia card embedded storage device protocol. After the host sends a read command, the embedded storage device prepares data according to the read command address and transmits it to the host. According to the eMMC protocol, open multi-block read does not define the number of blocks for reading multi-block operations. The device will continuously transmit data blocks until it receives a stop transmission command to complete this read command request.

[0025] In this context, embedded storage devices usually prepare the data to be read based on the capacity of their own random access memory (RAM) cache. This means that no matter how many data blocks the host requests, the device will read the data from the NAND flash into the RAM cache and then transmit it to the host. Since this process is subject to the size of the RAM cache and the time required to read data from the NAND flash, the delay in transmitting data is always equal to the time required to read data from the NAND flash to the RAM cache. Therefore, the delay time of the read command depends largely on the hardware characteristics rather than the specific data block size requested by the host. Although this mechanism simplifies the design of the read command, it may also cause unnecessary data delays and additional resource consumption.

[0026] Based on the above situation, an embodiment of the present invention provides a data reading method, device, electronic device and storage medium, which presets the read data length and dynamically tracks the actual transmission length of the previous open multi-block read command, and uses it as the preset read data length of the next multi-block read command, so that when the actual request length is less than or equal to the preset read data length, the read command delay time can be reduced, and the processing overhead of the embedded storage device can be significantly reduced.

[0027] To implement the process steps and functions of each example of the present invention, please refer to Figure 1 , Figure 1 A schematic structural block diagram of an electronic device provided in an embodiment of the present invention. The electronic device 100 may be an embedded storage device, including a memory 101 and a processor 103, wherein the memory 101 and the processor 103 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components may be electrically connected to each other via one or more communication buses 104 or signal lines. The memory 101 may be used to store software programs and modules, and the processor 103 executes the software programs and modules stored in the memory 101, thereby performing various functional applications and data processing.

[0028] The electronic device 100 may be, but is not limited to, a personal computer (PC), a server, a distributed computer, etc. It is understandable that the electronic device 100 is not limited to a physical server, but may also be a virtual machine on a physical server, a virtual machine built on a cloud platform, etc., which can provide the same functions as the server or virtual machine. The operating system of the electronic device 100 may be, but is not limited to, a Windows system, a Linux system, etc.

[0029] Among them, the memory 101 can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc.

[0030] The communication connection between the electronic device 100 and an external device is achieved through at least one communication interface 102 (which can be wired or wireless).

[0031] The processor 103 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the embodiment of the present invention can be completed by the hardware integrated logic circuit in the processor 103 or the instructions in the form of software. The processor 103 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0032] Understandably, Figure 1 The structure shown is for illustration only. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0033] The following is an exemplary description of the data reading method provided by the embodiment of the present invention. Figure 2 , 3 , Figure 2 A schematic structural block diagram of an embedded storage device provided by an embodiment of the present invention, Figure 3 A flow chart of a data reading method provided by an embodiment of the present invention is shown in FIG. 1 . The method is applied to an embedded storage device 300. The method includes: Figure 3 The following steps are shown: S210: Receive the current open multi-block read command sent by the host, and obtain the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the accumulated data transmission length of the DMA module after the previous multi-block read command completes the data transmission.

[0034] Among them, the open multi-block read command is a read instruction in the eMMC protocol, which allows the host to read multiple data blocks continuously without sending a separate command for each block. After the host sends this command, it can continue to read data until the stop transmission command is sent. The preset read data length can be set when the embedded storage device is initially powered on, and can also be modified after each open multi-block read command is executed.

[0035] For the preset read data length, if the current open multi-block read command is not the first data read (ie, the open multi-block read command has been used to read data before), then the preset read data length is the accumulated data transmission length of the DMA module 310 after the previous multi-block read command is completed.

[0036] S220: Execute a target data read operation according to the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transmit the target data in the RAM cache to the host through the DMA module.

[0037] The embedded storage device reads a corresponding number of data blocks from a storage medium (such as a flash memory chip) as target data according to a preset read data length, and caches the target data in a RAM cache 320, and transmits the target data in the RAM cache to the host through a DMA module. The DMA module is used to efficiently transmit data in the RAM cache to the host. The DMA module allows data to be directly transmitted between the storage device and the host without the intervention of the CPU, thereby improving transmission efficiency and reducing the burden on the CPU.

[0038] The method uses the preset read data length stored in the embedded storage device. When the length of the data actually requested by the host is less than or equal to the preset read data length, it is only necessary to prepare the data according to the preset read data length, and there is no need to prepare the read data according to the cache size itself. This can reduce the read command delay time and significantly reduce the processing overhead of the embedded storage device.

[0039] In a data reading, the preset read data length may be smaller than the data actually required to be read. After the DMA module completes the current data transmission, it is necessary to continue to read the target data. The method may also include: after the DMA module completes the current data transmission, if the stop transmission command sent by the host is not received, the preset read data length is set to the capacity of the embedded storage device, and the next target data reading is performed until the stop transmission command sent by the host is received, and the accumulated data transmission length of the DMA module is obtained, and the accumulated data transmission length is used as the preset read data length of the next multi-block read command.

[0040] After the DMA module completes the current data transmission, if it does not receive the stop transmission command sent by the host, it means that the data of the current open multi-block read command has not been read completely. When reading the target data for the next time, the preset read data length is first set to the capacity of the embedded storage device. When the current open multi-block read command reads data subsequently, the preset read data length will be the capacity of the embedded storage device. After the data reading of the current open multi-block read command is completed, that is, the host sends a stop transmission command, the DMA module will record the total data length transmitted by this open multi-block read command, and use the total data length transmitted as the preset read data length of the next multi-block read command.

[0041] For example, see Figure 4 , the data reading process of an open multi-block read command provided by an embodiment of the present invention includes: S1: Set the read data length of the multi-block read command to the preset read data length.

[0042] Among them, if this read command is not the first open multi-block read command after the embedded storage device is powered on, the preset read data length is the actual transmission length of the previous open multi-block read command. If it is the first open multi-block read command, the preset read data length is the storage capacity of the embedded storage device.

[0043] In a possible implementation, if the current open multi-block read command is the first data read, the preset read data length is set to be less than or equal to the capacity of the RAM cache. For example, if the capacity of the RAM cache is 2GB, the preset read data length is set to 1GB. When the open multi-block read command is the first data read, if the data actually required to be read is less than 1GB, the data read does not need to read 2GB of data into the RAM cache, which can improve the data reading efficiency.

[0044] S2: Read data from the flash memory into the RAM cache according to the adjusted read data length.

[0045] S3: CPU configures the DMA module to start data transmission.

[0046] The steps of transmitting data by the DMA module may include: Set the data transfer direction, starting address, block size, and number of blocks for the DMA module.

[0047] The target data is transferred from the RAM cache to the host through the DMA module starting from the starting address according to the block size and the number of blocks.

[0048] See also Figure 5After the data is read into the RAM cache, the CPU completes the data transfer from the RAM cache data to the eMMC hardware interface by configuring the DMA module, and transmits the data to the host side eMMC interface through the eMMC BUS. Among them, the core parameters of the CPU configuration DMA module include: DMA direction: RAM cache to eMMC hardware interface; DMA start address: physical address of RAM cache; DMA Block size: usually sector size, such as 512 bytes; DMA Block number: number of data blocks to be transferred this time.

[0049] S4: Wait for DMA module transfer to complete or terminate.

[0050] The DMA module transfer completion indicates that the data in the RAM cache has been transferred to the host, but the stop transfer command sent by the host has not been received. The DMA module transfer abort indicates that the stop transfer command sent by the host has been received.

[0051] S5: If the DMA module transfer is completed and the host does not send a stop transfer command, the accumulated data transfer length of the DMA module is updated, and the starting address of the next read data is updated. The read data length is restored to the default data length of the open read command, that is, the capacity of the embedded storage device, and steps S2 to S4 are repeated until the DMA module transfer is terminated.

[0052] S6: If the DMA module transmission is terminated, the host sends a stop transmission command, accumulates the data length of this DMA transmission, and the accumulated value is the actual read data length of this open multi-block read command. The preset read data length is set to the actual read data length, and the next open multi-block read command uses the preset read data length to read data. The processing of this open multi-block read command ends.

[0053] After the target data is cached in the RAM cache, the DMA module will transfer the data to the host. During this period, the embedded storage device does not do anything else. In order to further speed up the data reading speed, the data required by the host can be prepared during this period. Based on this, in a possible implementation, after executing the target data reading operation according to the current open multi-block read command and the preset read data length, and caching the target data in the RAM cache, the method may also include: According to the current open multi-block read command and the preset read data length, a predicted target data pre-reading operation is performed to obtain the predicted target data.

[0054] After the DMA module completes the target data transmission and does not receive a stop transmission command sent by the host, the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module.

[0055] The embedded storage device performs predictive read operations based on the current multi-block read command and the preset read data length. By analyzing the current read mode and historical data access mode, it reads the data that may be needed in advance to optimize the subsequent read efficiency. After the DMA module completes the transmission of the target data once, it checks whether the stop transmission command sent by the host is received. If the stop transmission command is not received, the previous predicted target data is directly cached in RAM. The predicted target data in the RAM cache is transferred to the host again through the DMA module to ensure that the host can seamlessly obtain the required data.

[0056] There are multiple situations in which the predicted target data is cached in the RAM cache and the predicted target data in the RAM cache is transmitted to the host through the DMA module. The data size of the predicted target data may be smaller than the size of the RAM cache or may be larger than the size of the RAM cache. Based on this situation, the predicted target data is cached in the RAM cache and the steps of transmitting the predicted target data in the RAM cache to the host through the DMA module may include: When the data size of the predicted target data is less than or equal to the RAM cache, all the predicted target data are cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module.

[0057] When the data size of the predicted target data is larger than the RAM cache, the first predicted target data of the RAM cache size is cached in the RAM cache.

[0058] In the process of transferring the first predicted target data in the RAM cache to the host through the DMA module, a data request for the remaining second predicted target data of the predicted target data is sent to the flash memory so that the flash memory is ready for the second predicted target data.

[0059] After the first predicted target data in the RAM cache is transmitted through the DMA module, the second predicted target data is cached in the RAM cache, and the second predicted target data is transmitted to the host through the DMA module.

[0060] If the data size of the predicted target data is less than or equal to the size of the RAM cache, all the predicted target data are directly read into the RAM cache, and the DMA module is directly used to transfer the predicted target data in the RAM cache to the host.

[0061] If the size of the predicted target data is larger than the RAM cache, it needs to be transferred in segments. First, the first predicted target data with a size equal to the RAM cache size is loaded into the RAM cache. Then, two operations are performed simultaneously. The DMA module transfer is started to transfer the first predicted target data from the RAM cache to the host. At the same time, a read request for the second predicted target data is sent to the flash memory. The data is prepared in advance using the time difference of the DMA module transfer. When the first predicted target data transfer is completed, the second predicted target data is immediately loaded into the RAM cache and the DMA module is used again to transfer the second predicted target data to the host.

[0062] In order to release RAM cache resources, the method may further include: if the subsequent actual access data is smaller than the data size of the predicted target data, clearing the predicted target data that has been read and cached in the RAM cache.

[0063] When the DMA module is performing data transmission, a stop transmission command sent by the host is received before the data transmission in the RAM cache is completed. After the read command is stopped, there is still read predicted target data in the RAM cache, and the data needs to be cleared.

[0064] Further, see Figure 6 The embodiment of the present invention further provides a data reading device, which is applied to an embedded storage device. The data reading device 400 includes: The command acquisition unit 410 is used to receive the current open multi-block read command sent by the host and obtain the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the data transmission length accumulated by the DMA module after the previous multi-block read command completes the data transmission.

[0065] The data reading unit 420 is used to perform a target data reading operation according to the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transmit the target data in the RAM cache to the host through the DMA module.

[0066] In summary, the embodiments of the present invention provide a data reading method, device, electronic device and storage medium, which preset the read data length and dynamically track the actual transmission length of the previous open multi-block read command, and use it as the preset read data length of the next multi-block read command, so that when the actual request length is less than or equal to the preset read data length, the read command delay time can be reduced, and the processing overhead of the embedded storage device can be significantly reduced; after reading data from the flash memory to the RAM cache, the target data is predicted and prepared, so the speed of reading data from the flash memory next time can be accelerated.

[0067] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a module, a program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0068] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0069] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a computer-readable storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0070] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0071] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A data reading method, characterized in that: Applied to an embedded storage device, the method comprises: Receive a current open multi-block read command sent by the host, and obtain a preset read data length of the embedded storage device, if the current open multi-block read command is not the first data read, then the preset read data length is set to the data transmission length accumulated by the DMA module after the previous multi-block read command completes the data transmission; According to the current open multi-block read command and the preset read data length, a target data read operation is performed, the target data is cached in a RAM cache, and the target data in the RAM cache is transmitted to the host through a DMA module.

2. The method according to claim 1, characterized in that The method further comprises: After the DMA module completes the current data transmission, if no stop transmission command is received from the host, the preset read data length is set to the capacity of the embedded storage device, and the next target data is read. After the stop transmission command is received from the host, the accumulated data transmission length of the DMA module is obtained, and the accumulated data transmission length is used as the preset read data length of the next multi-block read command.

3. The method according to claim 2, characterized in that The step of transmitting the target data in the RAM cache to the host through the DMA module comprises: Set the data transmission direction, starting address, block size and number of blocks of the DMA module; The target data is transferred from the RAM cache to the host through the DMA module starting from the start address according to the block size and the number of blocks.

4. The method according to claim 1, characterized in that: After the step of performing a target data read operation according to the current open multi-block read command and the preset read data length and caching the target data in a RAM cache, the method further includes: According to the current open multi-block read command and the preset read data length, a predicted target data pre-reading operation is performed to obtain the predicted target data; After the DMA module completes the transmission of the target data and does not receive a stop transmission command sent by the host, the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module.

5. The method according to claim 4, characterized in that The step of caching the predicted target data into the RAM cache, and transmitting the predicted target data in the RAM cache to the host through the DMA module, comprises: In the case where the data size of the predicted target data is less than or equal to the RAM cache, all of the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module; When the data size of the predicted target data is larger than the RAM cache, caching the first predicted target data of the RAM cache size into the RAM cache; In the process of transmitting the first predicted target data in the RAM cache to the host through the DMA module, sending a data request for the second predicted target data remaining from the predicted target data to the flash memory so that the flash memory is ready for the second predicted target data; After the first predicted target data in the RAM cache is transmitted through the DMA module, the second predicted target data is cached in the RAM cache, and the second predicted target data is transmitted to the host through the DMA module.

6. The method according to claim 5, characterized in that The method further comprises: If the subsequent actual access data is smaller than the data size of the predicted target data, the predicted target data that has been read and cached in the RAM cache is cleared.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: If the current open multi-block read command is the first data read, the preset read data length is set to be less than or equal to the capacity of the RAM cache.

8. A data reading device, characterized in that: Applied to an embedded storage device, the device comprises: A command acquisition unit, used for receiving a current open multi-block read command sent by a host, and acquiring a preset read data length of the embedded storage device, if the current open multi-block read command is not the first data read, then the preset read data length is set to the data transmission length accumulated by the DMA module after the previous multi-block read command completes the data transmission; The data reading unit is used to perform a target data reading operation according to the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transmit the target data in the RAM cache to the host through the DMA module.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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