Data Reading Method, Device, Electronic Device and Storage Medium

Abstract

Embodiments of the present invention provide a data reading method, apparatus, electronic device, and storage medium, which relate to the field of data reading. The method is applied to an embedded storage device and includes: receiving a current open multi-block read command sent by a host and obtaining a preset read data length of the embedded storage device. If the current open multi-block read command is not the first data reading, the preset read data length is set to the cumulative data transmission length of the DMA module after the previous multi-block read command completes data transmission. Then, perform a target data reading operation, cache the target data in the RAM cache, and transmit the target data in the RAM cache to the host through the DMA module. By means of the preset read data length of the embedded storage device, when the length of the data actually requested by the host is less than or equal to the preset read data length, the read command delay time can be reduced, and the processing overhead of the embedded storage device can be decreased.

Description

Technical Field

[0001] The present invention relates to the field of data reading, and in particular, to a data reading method, device, electronic device and storage medium. Background Art

[0002] Open-Ended Multiple-Block Read (OMBR) is the most basic read type in the Embedded Multi Media Card (eMMC) device protocol. After the host sends a read command, the embedded storage device prepares data according to the read command address and transfers it to the host. According to the eMMC protocol, the number of blocks for the open-ended multiple-block read is not defined, and the device will continuously transfer data blocks until it receives a stop transfer command (Stop Command, CMD12) to complete the current read command request.

[0003] In this context, based on the characteristics of open-ended multiple-block read, the embedded storage device will continuously prepare data and transfer it to the host. The embedded storage device always prepares read data according to the size of its own Random Access Memory (RAM) cache. The latency of data transfer is equal to the time it takes to read data from Nand flash into the RAM cache. Regardless of the size of the data block requested by the host, the read command latency time is the same. When the host requests a small data block, it will result in a relatively high read command latency. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of the present invention is to provide a data reading method, device, electronic device and storage medium to at least partially improve the above problems.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a data reading method applied to an embedded storage device. The method includes:

[0007] Receiving a current open-ended multiple-block read command sent by the host, and obtaining a preset read data length of the embedded storage device. If the current open-ended multiple-block read command is not the first data reading, the preset read data length is set to the cumulative data transfer length of the DMA module after the previous multiple-block read command completes data transfer;

[0008] Performing a target data reading operation according to the current open-ended multiple-block read command and the preset read data length, caching the target data in the RAM cache, and transferring the target data in the RAM cache to the host through the DMA module.

[0009] Optionally, the method further includes:

[0010] After the DMA module completes the current data transfer, if a stop transfer command sent by the host is not received, the preset read data length is set to the capacity size of the embedded storage device, and the next target data reading is performed until a stop transfer command sent by the host is received, and the cumulative data transfer length of the DMA module is obtained, and the cumulative data transfer length is used as the preset read data length for the next multi-block read command.

[0011] Optionally, the step of transferring the target data in the RAM cache to the host through the DMA module includes:

[0012] Set the data transfer direction, start address, block size, and number of blocks of the DMA module;

[0013] Through the DMA module, starting from the start address, according to the block size and the number of blocks, transfer the target data from the RAM cache to the host.

[0014] Optionally, after the step of performing a target data reading operation according to the current open multi-block read command and the preset read data length, and caching the target data in the RAM cache, the method further includes:

[0015] Perform a predicted target data pre-reading operation according to the current open multi-block read command and the preset read data length to obtain predicted target data;

[0016] After the DMA module finishes transferring the target data and a stop transfer command sent by the host is not received, cache the predicted target data into the RAM cache, and transfer the predicted target data in the RAM cache to the host through the DMA module.

[0017] Optionally, the step of caching the predicted target data into the RAM cache and transferring the predicted target data in the RAM cache to the host through the DMA module includes:

[0018] When the data volume size of the predicted target data is less than or equal to the RAM cache, all the predicted target data is cached into the RAM cache, and the predicted target data in the RAM cache is transferred to the host through the DMA module;

[0019] When the data volume size of the predicted target data is greater than the RAM cache, the first predicted target data with the size of the RAM cache is cached into the RAM cache;

[0020] During the process of transmitting the first predicted target data in the RAM cache to the host through the DMA module, a data request for the remaining second predicted target data of the predicted target data is sent to the flash memory to enable the flash memory to prepare the second predicted target data;

[0021] After the transmission of the first predicted target data in the RAM cache through the DMA module is completed, the second predicted target data is cached in the RAM cache, and the second predicted target data is transmitted to the host through the DMA module.

[0022] Optionally, the method further includes:

[0023] If the subsequent actual access data is less than the data volume size of the predicted target data, the predicted target data cached in the RAM cache that has been read is cleared.

[0024] Optionally, the method further includes:

[0025] If the current open multi-block read command is the first data read, the preset read data length is set to be less than or equal to the capacity size of the RAM cache.

[0026] In a second aspect, an embodiment of the present invention provides a data reading device, which is applied to an embedded storage device. The device includes:

[0027] A command acquisition unit, configured to receive a current open multi-block read command sent by a host and acquire a preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the cumulative data transmission length of the DMA module after the previous multi-block read command completes data transmission;

[0028] A data reading unit, configured to perform a target data reading operation according to the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transmit the target data in the RAM cache to the host through the DMA module.

[0029] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the program, the method described in any one of the above is implemented.

[0030] In a fourth aspect, an embodiment of the present invention provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method described in any one of the above is implemented.

[0031] A data reading method, device, electronic device, and storage medium provided by an embodiment of the present invention preset a read data length and dynamically track the actual transmission length of the previous open multi-block read command, and use it as the preset read data length of the next multi-block read command. Thus, when the actual request length is less than or equal to the preset read data length, the read command delay time can be reduced, and the processing overhead of the embedded storage device can be significantly reduced.

[0032] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0034] Figure 1 A schematic structural block diagram of an electronic device provided by an embodiment of the present invention;

[0035] Figure 2 A schematic structural block diagram of an embedded storage device provided by an embodiment of the present invention;

[0036] Figure 3 A schematic flow chart of a data reading method provided by an embodiment of the present invention;

[0037] Figure 4 Another schematic flow chart of a data reading method provided by an embodiment of the present invention;

[0038] Figure 5 A schematic diagram of data transmission by a DMA module provided by an embodiment of the present invention;

[0039] Figure 6 A schematic structural block diagram of a data reading device provided by an embodiment of the present invention.

[0040] Icons: 100 - Electronic device; 101 - Memory; 102 - Communication interface; 103 - Processor; 104 - Bus; 300 - Embedded storage device; 310 - DMA module; 320 - RAM cache; 400 - Data reading device; 410 - Command acquisition unit; 420 - Data reading unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

[0042] Therefore, the detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but is merely representative of selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0043] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings. At the same time, in the description of the present invention, terms such as "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0044] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0045] OMBR is the most basic read type in the embedded multimedia card embedded storage device protocol. After the host sends a read command, the embedded storage device prepares data according to the read command address and transfers it to the host. According to the eMMC protocol, the number of blocks for the open multi-block read to read multiple blocks is undefined, and the device will continuously transfer data blocks until it receives a stop transfer command to complete the current read command request.

[0046] In this context, an embedded storage device typically prepares the data to be read based on its own Random Access Memory (RAM) cache capacity. This means that regardless of the number of data blocks requested by the host, the device will read the data from the NAND flash into the RAM cache and then transfer it to the host. Since this process is limited by the size of the RAM cache and the time required to read data from the NAND flash, the latency of data transfer is always equal to the time required to read data from the NAND flash into the RAM cache. Therefore, the latency of the read command depends to a large extent on the hardware characteristics rather than the specific data block size requested by the host. Although this mechanism simplifies the design of the read command, it may also result in unnecessary data latency and additional resource consumption.

[0047] Based on the above situation, the embodiments of the present invention provide a data reading method, device, electronic device and storage medium. By presetting the read data length and dynamically tracking the actual transmission length of the previous open multi-block read command and using it as the preset read data length of the next multi-block read command, the latency of the read command can be reduced when the actual request length is less than or equal to the preset read data length, significantly reducing the processing overhead of the embedded storage device.

[0048] To implement the process steps and functions of the various examples of the present invention, please refer to Figure 1 , Figure 1 which is a schematic structural block diagram of an electronic device provided by an embodiment of the present invention. The electronic device 100 may be an embedded storage device, including a memory 101 and a processor 103, and the memory 101 and the processor 103 are directly or indirectly electrically connected to each other to achieve data transmission or interaction. For example, these components may be electrically connected to each other through one or more communication buses 104 or signal lines. The memory 101 may be used to store software programs and modules, and the processor 103 may execute various functional applications and data processing by executing the software programs and modules stored in the memory 101.

[0049] The electronic device 100 may be, but is not limited to, a personal computer (PC), a server, a distributed computer, etc. It can be understood that the electronic device 100 is not limited to a physical server, but may also be a virtual machine on a physical server, a virtual machine built on a cloud platform, etc., which can provide the same functions as the server or virtual machine. The operating system of the electronic device 100 may be, but is not limited to, the Windows system, the Linux system, etc.

[0050] Among them, the memory 101 can be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electric Erasable Programmable Read-Only Memory (EEPROM), etc.

[0051] The communication connection between the electronic device 100 and an external device is realized through at least one communication interface 102 (which can be wired or wireless).

[0052] The processor 103 may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the embodiments of the present invention can be completed by the integrated logic circuit in hardware or instructions in software form in the processor 103. The processor 103 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0053] It can be understood that Figure 1 The structure shown is only schematic, and the electronic device 100 may further include more or fewer components than those shown Figure 1 in it, or have a configuration different from that shown Figure 1 in it. Figure 1 Each component shown in it can be implemented by hardware, software, or a combination thereof.

[0054] Next, an exemplary description will be given of the data reading method provided in the embodiments of the present invention. Refer to Figure 2 、 3 , Figure 2 which is a schematic structural block diagram of an embedded storage device provided in the embodiments of the present invention. Figure 3Schematic flowchart of a data reading method provided by an embodiment of the present invention. This method is applied to an embedded storage device 300 and includes the following steps as Figure 3 shown:

[0055] S210: Receive the current open multi-block read command sent by the host, and obtain the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data reading, the preset read data length is set to the cumulative data transfer length of the DMA module after the previous multi-block read command completes data transfer.

[0056] Among them, the open multi-block read command is a read instruction in the eMMC protocol, which allows the host to continuously read multiple data blocks without sending a separate command for each block. After the host sends this command, it can continuously read data until a stop transfer command is sent. The preset read data length can be set when the embedded storage device is initially powered on, and can also be modified after each execution of the open multi-block read command.

[0057] For the preset read data length, if the current open multi-block read command is not the first data reading (that is, the open multi-block read command has been used for data reading before), then the preset read data length is the cumulative data transfer length of the DMA module 310 after the previous multi-block read command is completed.

[0058] S220: According to the current open multi-block read command and the preset read data length, perform a target data reading operation, cache the target data in the RAM cache, and transfer the target data in the RAM cache to the host through the DMA module.

[0059] The embedded storage device reads a corresponding number of data blocks from the storage medium (such as a flash chip) as the target data according to the preset read data length, and caches the target data in the RAM cache 320, and transfers the target data in the RAM cache to the host through the DMA module. The DMA module is used to efficiently transfer the data in the RAM cache to the host. The DMA module allows data to be directly transferred between the storage device and the host without the intervention of the CPU, thereby improving the transfer efficiency and reducing the burden on the CPU.

[0060] This method, through the preset read data length stored in the embedded storage device, when the length of the data actually requested by the host is less than or equal to the preset read data length, only needs to prepare data according to the preset read data length, instead of preparing read data according to its own cache size, which can reduce the read command delay time and significantly reduce the processing overhead of the embedded storage device.

[0061] During a data read, the preset read data length may be less than the data that actually needs to be read. After the DMA module completes the current data transfer, it is necessary to continue reading the target data. This method may further include: after the DMA module completes the current data transfer, if it does not receive a stop transfer command sent by the host, set the preset read data length to the capacity of the embedded storage device, and perform the next target data read until it receives a stop transfer command sent by the host, obtain the cumulative data transfer length of the DMA module, and use the cumulative data transfer length as the preset read data length for the next multi-block read command.

[0062] After the DMA module completes the current data transfer, if it does not receive a stop transfer command sent by the host, it means that the data of the current open multi-block read command has not been completely read. When performing the next target data read, first set the preset read data length to the capacity of the embedded storage device. When reading the subsequent data of this open multi-block read command, the preset read data length will always be the capacity of the embedded storage device. After the data of the current open multi-block read command is read, that is, when the host sends a stop transfer command, the DMA module will record the total data length transmitted by this open multi-block read command, and use this total data length as the preset read data length for the next multi-block read command.

[0063] Exemplarily, refer to Figure 4 , the data reading process of an open multi-block read command provided by an embodiment of the present invention includes:

[0064] S1: Set the read data length of the multi-block read command to the preset read data length.

[0065] Among them, if this read command is not the first open multi-block read command after the power-on of the embedded storage device, the preset read data length is the actual transmission length of the previous open multi-block read command; if it is the first open multi-block read command, the preset read data length is the storage capacity of the embedded storage device.

[0066] In a possible implementation manner, if the current open multi-block read command is the first data read, the preset read data length is set to be less than or equal to the capacity of the RAM cache. For example, the capacity of the RAM cache is 2GB, and the preset read data length is set to 1GB. When the open multi-block read command is the first data read, if the data that actually needs to be read this time is less than 1GB, then it is not necessary to read 2GB of data into the RAM cache this time, which can improve the data reading efficiency.

[0067] S2: Read data from the flash memory into the RAM cache according to the adjusted read data length.

[0068] S3: The CPU configures the DMA module to start data transfer.

[0069] Among them, the steps for the DMA module to transfer data may include:

[0070] Set the data transfer direction, starting address, block size, and number of blocks of the DMA module.

[0071] Starting from the starting address through the DMA module, transfer the target data from the RAM cache to the host according to the block size and the number of blocks.

[0072] See Figure 5 , after the data is read into the RAM cache, the CPU completes the data transfer from the RAM cache to the eMMC hardware interface by configuring the DMA module, and transfers the data to the host-side eMMC interface through the eMMC BUS. Among them, the core parameters for the CPU to configure the DMA module include: DMA direction: from the RAM cache to the eMMC hardware interface; DMA starting address: the physical address of the RAM cache; DMA Block size: usually the sector size, such as 512 bytes; DMA Block number: the number of data blocks to be transferred this time.

[0073] S4: Wait for the DMA module to complete or abort the transfer.

[0074] The completion of the DMA module transfer indicates that the data in the RAM cache has been transferred to the host, but no stop transfer command sent by the host has been received. The abortion of the DMA module transfer indicates that a stop transfer command sent by the host has been received.

[0075] S5: If the DMA module transfer is completed and the host has not sent a stop transfer command, update the cumulative data transfer length of the DMA module this time, and update the starting address for the next data read. The data read length is restored to the default data length of the open read command, that is, the capacity of the embedded storage device, and continue to repeat steps S2~S4 until the DMA module transfer is aborted.

[0076] S6: If the DMA module transfer is aborted and the host sends a stop transfer command, accumulate the data transfer length of this DMA transfer. The accumulated value is the actual read data length of this open multi-block read command. Set the preset read data length to this actual read data length, and the next open multi-block read command will use this preset read data length for data reading. The processing of this open multi-block read command ends.

[0077] After caching the target data in the RAM cache, the DMA module transfers the data to the host. During this period, the embedded storage device does nothing else. To further accelerate the data reading speed, the data required by the host can be prepared during this period. Based on this, in a possible implementation, after the step of performing the target data reading operation according to the current open multi-block read command and the preset read data length and caching the target data in the RAM cache, the method may further include:

[0078] Perform a predicted target data pre-reading operation according to the current open multi-block read command and the preset read data length to obtain predicted target data.

[0079] After the DMA module finishes transferring the target data and has not received a stop transfer command sent by the host, cache the predicted target data in the RAM cache, and transfer the predicted target data in the RAM cache to the host through the DMA module.

[0080] The embedded storage device performs a predictive reading operation according to the current multi-block read command and the preset read data length, and by analyzing the current reading mode and the historical data access mode, reads in advance the data that may be required to optimize the subsequent reading efficiency. After the DMA module completes a transfer of target data, check whether a stop transfer command sent by the host is received. If the stop transfer command is not received, directly cache the previous predicted target data in the RAM. Then transfer the predicted target data in the RAM cache to the host through the DMA module again to ensure that the host can seamlessly obtain the required data.

[0081] There are various situations where the predicted target data is cached in the RAM cache and the predicted target data in the RAM cache is transferred to the host through the DMA module. The data volume size of the predicted target data may be smaller than the size of the RAM cache or may be larger than the size of the RAM cache. Based on this situation, the step of caching the predicted target data in the RAM cache and transferring the predicted target data in the RAM cache to the host through the DMA module may include:

[0082] When the data volume size of the predicted target data is less than or equal to the RAM cache, all the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transferred to the host through the DMA module.

[0083] When the data volume size of the predicted target data is greater than the RAM cache, cache the first predicted target data with the size of the RAM cache in the RAM cache.

[0084] During the process of transmitting the first predicted target data in the RAM cache to the host through the DMA module, a data request for the remaining second predicted target data of the predicted target data is sent to the flash memory to enable the flash memory to prepare the second predicted target data.

[0085] After the transmission of the first predicted target data in the RAM cache through the DMA module is completed, the second predicted target data is cached in the RAM cache, and the second predicted target data is transmitted to the host through the DMA module.

[0086] If the data volume size of the predicted target data is less than or equal to the size of the RAM cache, all the predicted target data is directly read into the RAM cache, and the predicted target data in the RAM cache is directly transmitted to the host using the DMA module.

[0087] If the data volume size of the predicted target data is greater than the RAM cache, segmented transmission is required. First, the first predicted target data with a size equal to the RAM cache size is loaded into the RAM cache. Next, two operations are performed simultaneously. The DMA module is started to transmit the first predicted target data from the RAM cache to the host, and at the same time, a read request for the second predicted target data is sent to the flash memory to prepare the data in advance using the time difference of the DMA module transmission. After the transmission of the first predicted target data is completed, the second predicted target data is immediately loaded into the RAM cache, and the second predicted target data is transmitted to the host using the DMA module again.

[0088] To release the RAM cache resources, the method may further include: if the subsequent actual access data is less than the data volume size of the predicted target data, the predicted target data read and cached in the RAM cache is cleared.

[0089] When the DMA module is performing data transmission and a stop transmission command sent by the host is received before the data in the RAM cache is completely transmitted, after stopping the current read command, there is still the read predicted target data in the RAM cache, and this data needs to be cleared.

[0090] Further, referring to Figure 6 , an embodiment of the present invention further provides a data reading device, which is applied to an embedded storage device. The data reading device 400 includes:

[0091] A command acquisition unit 410, configured to receive a current open multi-block read command sent by the host and acquire a preset read data length of the embedded storage device. If the current open multi-block read command is not the first data reading, the preset read data length is set to the cumulative data transmission length of the DMA module after the previous multi-block read command completes data transmission.

[0092] The data reading unit 420 is configured to perform a target data reading operation according to the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transmit the target data in the RAM cache to the host through the DMA module.

[0093] In summary, a data reading method, apparatus, electronic device, and storage medium provided by an embodiment of the present invention preset the read data length and dynamically track the actual transmission length of the previous open multi-block read command, and use it as the preset read data length of the next multi-block read command. Therefore, when the actual request length is less than or equal to the preset read data length, the read command delay time can be reduced, and the processing overhead of the embedded storage device can be significantly reduced; by predicting and preparing the target data after reading data from the flash memory into the RAM cache, the speed of reading data from the flash memory next time can be increased.

[0094] In the embodiments provided by the present invention, it should be understood that the disclosed apparatus and method can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of apparatuses, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0095] In addition, the functional modules in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

[0096] When a function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0097] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0098] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes that fall within the meaning and scope of the equivalent elements of the claims in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. A data reading method, characterized in that Applied to an embedded storage device, the method includes: Receiving a current open multi-block read command sent by a host, and obtaining a preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the cumulative data transfer length of the DMA module after the previous multi-block read command completes data transfer; According to the current open multi-block read command and the preset read data length, performing a target data read operation, caching the target data in the RAM cache, and transferring the target data in the RAM cache to the host through the DMA module; Wherein, after the step of performing a target data read operation according to the current open multi-block read command and the preset read data length and caching the target data in the RAM cache, performing a predicted target data pre-read operation according to the current open multi-block read command and the preset read data length to obtain predicted target data; after the DMA module completes the transfer of the target data and before receiving a stop transfer command sent by the host, when the data volume of the predicted target data is less than or equal to the RAM cache, all of the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transferred to the host through the DMA module; when the data volume of the predicted target data is greater than the RAM cache, the first predicted target data with the size of the RAM cache is cached in the RAM cache; during the process of transferring the first predicted target data in the RAM cache to the host through the DMA module, sending a data request for the remaining second predicted target data of the predicted target data to the flash memory so that the flash memory prepares the second predicted target data; after the first predicted target data in the RAM cache is transferred through the DMA module, caching the second predicted target data in the RAM cache and transferring the second predicted target data to the host through the DMA module.

2. The method according to claim 1, wherein The method further includes: After the DMA module completes the current data transfer, if a stop transfer command sent by the host is not received, setting the preset read data length to the capacity size of the embedded storage device, performing the next target data read until a stop transfer command sent by the host is received, obtaining the cumulative data transfer length of the DMA module, and using the cumulative data transfer length as the preset read data length for the next multi-block read command.

3. The method according to claim 2, characterized in that The step of transferring the target data in the RAM cache to the host through the DMA module includes: Setting the data transfer direction, start address, block size, and number of blocks of the DMA module; Starting from the start address through the DMA module, transferring the target data from the RAM cache to the host according to the block size and the number of blocks.

4. The method according to claim 1, wherein The method further includes: If the amount of data actually accessed subsequently is less than the amount of data of the predicted target data, the predicted target data cached in the RAM cache that has been read is cleared.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: If the current open multi-block read command is the first data read, the preset read data length is set to be less than or equal to the capacity of the RAM cache.

6. A data reading device, characterized in that, Applied to an embedded storage device, the device includes: A command acquisition unit, configured to receive a current open multi-block read command sent by a host and obtain a preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the cumulative data transfer length of the DMA module after the previous multi-block read command completes data transfer; A data reading unit, configured to perform a target data reading operation according to the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transfer the target data in the RAM cache to the host through the DMA module; and further configured to, after the step of performing the target data reading operation according to the current open multi-block read command and the preset read data length and caching the target data in the RAM cache, perform a predicted target data pre-reading operation according to the current open multi-block read command and the preset read data length to obtain predicted target data; after the DMA module completes the transfer of the target data and without receiving a stop transfer command sent by the host, when the amount of data of the predicted target data is less than or equal to the RAM cache, all the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transferred to the host through the DMA module; when the amount of data of the predicted target data is greater than the RAM cache, the first predicted target data of the size of the RAM cache is cached in the RAM cache; during the process of transferring the first predicted target data in the RAM cache to the host through the DMA module, a data request for the second predicted target data remaining of the predicted target data is sent to the flash memory to make the flash memory ready for the second predicted target data; after the transfer of the first predicted target data in the RAM cache through the DMA module is completed, the second predicted target data is cached in the RAM cache, and the second predicted target data is transferred to the host through the DMA module.

7. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, wherein, When the processor executes the program, the method according to any one of claims 1 to 5 is implemented.

8. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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