Serial port communication transmission method and device with high baud rate tolerance

Abstract

The invention discloses a serial port communication transmission method and system with high baud rate tolerance. The method comprises the following steps: S1, monitoring a serial port communication line until a level change from logic '1' to logic '0' is detected, and detecting a start bit of a data frame through a triple acknowledgement mechanism; s2, after the transmission of the data bits and the optional parity check bits is completed, continuously monitoring the serial port communication line until the level change from the logic '0' to the logic '1' is detected, and confirming a stop bit for detecting a data frame through triple sampling; and S3, after the stop bit of the data frame is ended, returning to the step S1 to detect the start bit of the next frame of data. According to the invention, by adopting a triple acknowledgement mechanism and a triple sampling acknowledgement method, the start bit and the stop bit of the data frame can be accurately detected, accurate receiving of data can be kept even under the conditions of Baud rate change and noise interference, and an efficient and reliable serial port communication solution is provided for users.

Description

Technical Field

[0001] The invention relates to a serial communication transmission method with high baud rate tolerance, and also relates to a corresponding serial communication device, belonging to the technical field of digital communication. Background Art

[0002] In a serial communication system, ensuring reliable signal transmission is crucial to maintaining data accuracy and system performance. However, the existing technology has some defects in the implementation of serial communication, which can have a significant adverse effect on the quality of communication. For example, existing filter circuit designs are mainly used to eliminate fixed-length glitch noise, but when faced with a changing baud rate signal, these circuits often cannot effectively filter out shorter glitch noise. These glitch noises that are not completely filtered out may be generated at the edge of the signal, thereby affecting the synchronization and stability of the signal, resulting in missynchronization and misreception near the edge of the data bit. This will not only cause data errors or losses, but also reduce the reliability of communication.

[0003] In addition, serial communication systems usually lack effective detection mechanisms for bus noise and stop bits. Without proper noise detection, the performance of serial communication systems in high noise environments will be affected, increasing the risk of data transmission errors. At the same time, inaccurate stop bit detection may lead to data frame recognition errors, resulting in data frame loss or errors when continuously receiving data. These problems further aggravate the instability of data transmission and affect the performance of the entire serial communication system. On the other hand, the design of the start bit is very critical to ensure the correct reception of the data frame. An unreasonable start bit design may cause synchronization problems when continuously receiving data, such as failure to correctly receive the next frame of data or sampling point jump, thereby affecting the integrity and accuracy of the data. In addition, the existing technology cannot adapt to changes in baud rate, resulting in signal synchronization and stability being affected when the baud rate changes, which in turn leads to data transmission delays or packet loss, affecting the real-time and reliability of communication. At the same time, the deficiencies of the existing technology in filtering and synchronization may cause the device to require more energy to handle noise and errors, increasing the power consumption of the device, especially in mobile or battery-powered devices.

[0004] In the Chinese patent application with application number 202111041666.8, a method and system for correcting the baud rate of a serial port are disclosed. The correction method is used to correct the baud rate of the serial port to obtain a target baud rate, including: presetting a set containing several baud rate values; performing a screening step for each baud rate value in the set: setting the baud rate of the serial port to a baud rate value; if test data is received, detecting the test data; if the test data meets the preset detection requirements, recording the baud rate value; and correcting the target baud rate according to all recorded baud rate values. The correction method performs targeted corrections to the frequency deviation by training the baud rate value sequence, increases the tolerance of the communication module to the MCU serial port frequency deviation, and realizes automated and efficient serial port baud rate correction. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a serial communication transmission method with high baud rate tolerance.

[0006] Another technical problem to be solved by the present invention is to provide a serial communication device for implementing the above serial communication transmission method.

[0007] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, there is provided a serial communication transmission method with high baud rate tolerance, comprising the following steps:

[0009] S1: Monitor the serial communication line until a level change from logic "1" to logic "0" is detected, and the start bit of the data frame is detected through a triple confirmation mechanism;

[0010] S2: After the data bits and the optional parity bit are transmitted, the serial communication line is continuously monitored until a level change from logic "0" back to logic "1" is detected, and the stop bit of the data frame is confirmed by triple sampling;

[0011] S3: After the stop bit of the data frame ends, return to step S1 to detect the start bit of the next frame of data.

[0012] Preferably, in step S1, the triple confirmation mechanism means that when detecting the start bit, three independent conditions need to be met: whether the detected start bit is a low level, whether the low level lasts for a sufficient time, and whether the start bit is detected within the expected time window; only when these three conditions are met at the same time, the start bit is confirmed and data reception continues.

[0013] Preferably, the first filter detects the falling edge of the start bit at a preset sampling point to ensure whether the detected start bit is a low level; the second filter detects the duration of the low level at subsequent sampling points to ensure whether the low level lasts for a sufficient time; the third filter continuously samples at the middle sampling point position of the start bit to ensure that the start bit is detected within the expected time window.

[0014] Preferably, the first filter uses sampling points related to the baud rate to determine the falling edge; and through three high-level samplings, it is ensured that at least three sampling points are covered in the idle high-level time of the previous frame of data.

[0015] Preferably, the second filter operates at the following three sampling points, requiring at least two sampling points to be logic "0", otherwise it will exit the current state and re-determine the start bit.

[0016] Preferably, the third filter continuously takes three sampling points at the middle sampling point position of the start bit for judgment, requiring at least two sampling points to be logic "0", otherwise it will exit the current state and re-judge the start bit.

[0017] Preferably, in step S2, the triple sampling confirmation refers to taking three sampling points in succession at the middle position of the stop bit duration; if all or at least two of the three sampling points are logic "1", it is considered that the stop bit has been collected.

[0018] Preferably, the first counter counts and samples according to the baud rate of the previous frame of data, and the second counter is cleared after detecting the falling edge of the next frame of data; after the previous frame of data is received, the two counters perform synchronous processing.

[0019] Preferably, in step S3, the detection of the start bit of the next frame of data begins immediately after the highest bit of the byte of the previous frame of data ends.

[0020] According to a second aspect of an embodiment of the present invention, there is provided a serial communication device, comprising a microcontroller, a serial interface connector and a power supply; wherein the microcontroller is connected to the serial interface connector for implementing the aforementioned serial communication transmission method.

[0021] Compared with the prior art, the present invention significantly improves the stability and reliability of the serial communication system under high baud rate conditions. By adopting a triple confirmation mechanism and a triple sampling confirmation method, the present invention can accurately detect the start bit and stop bit of the data frame, and can maintain accurate data reception even under conditions of baud rate changes and noise interference. The design of the dual counter further improves the system's adaptability to baud rate changes, ensuring accurate identification and processing of data frames. The improved next frame start bit detection method reduces the loss of data frames caused by baud rate mismatch and enhances the system's synchronization capability. In general, the present invention effectively solves the challenges of traditional serial communication technology under high baud rate and complex environment through its unique design and mechanism, and provides users with an efficient and reliable serial communication solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the format of the data frame in UART communication;

[0023] Figure 2 A flowchart of a serial communication transmission method provided by an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of determining a start position through a triple confirmation mechanism in an embodiment of the present invention;

[0025] Figure 4 A schematic diagram of determining a stop position by triple sampling in an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of advancing the start bit of the next frame in an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of an improved next frame start bit detection method in an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of the structure of a serial communication device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Serial communication refers to a communication method for data transmission through the serial port of a computer or other device, which allows data to be transmitted between a transmitter and a receiver in a serialized format. Serial communication can be implemented using a variety of different protocols and standards, and UART communication (universal asynchronous receive / transmit communication) is the most common implementation method. Below, taking UART communication as an example, the specific implementation steps of the serial communication transmission method provided by the embodiment of the present invention are described in detail.

[0031] First embodiment

[0032] In UART communication, data is transmitted in characters, and the transmission of each character is independent and does not need to rely on the clock synchronization between the sending and receiving devices. This means that the sending and receiving devices can have their own clock sources and can start sending data at any time.

[0033] On the other hand, data transmission in UART communication follows a specific communication protocol. This communication protocol defines the format of the data frame. Figure 1 As shown in FIG. 1 , a data frame generally includes the following parts: idle bit, start bit, data bit, optional parity bit, and stop bit. These components together ensure the correct transmission and reception of data.

[0034] Specifically, the transmission of a data frame starts with an idle bit, when the bus is in a logic "1" state, indicating that no data is being transmitted. Subsequently, the transmitting device sends a start bit of logic "0", marking the beginning of a new data frame. This is followed by data bits, which can be 4, 5, 6, 7 or 8 bits, which constitute the characters to be transmitted, usually encoded in ASCII code. The transmission of data bits starts with the lowest bit and relies on an external clock signal for synchronization. If a parity bit is included, it will be sent after the data bit to check the total number of "1"s in the data bit. Odd parity ensures that the total number of "1"s is an odd number, while even parity ensures that the total number of "1"s is an even number. Finally, the stop bit marks the end of the character data, ensuring that the receiving device can recognize the end of the data frame. After a frame of data transmission is completed, the appearance of the stop bit not only marks the end of the current data frame, but also provides the necessary time interval before starting the next frame of data transmission. This time interval is also called the minimum frame interval. Generally, the length of the stop bit can be configured as a high level of 1 bit, 1.5 bits or 2 bits. This design helps create clear boundaries between data frames and prevents the receiving device from confusing the boundaries between individual data frames in a continuous data stream.

[0035] Baud rate is an indicator of the data transmission rate of UART communication, which indicates the number of binary bits transmitted per second. For example, if the data transmission rate is 120 characters / second and each character is 10 bits, the baud rate of its transmission is 10×120=120 bits / second=1200 baud. In UART communication, as long as the receiving device can keep synchronization with the sending device within the transmission time of one character after receiving the start bit, the data can be received correctly. This character-by-character transmission method makes UART communication very effective when dealing with communication between devices with varying speeds or asynchronous clocks.

[0036] In one embodiment of the present invention, the time base of UART communication changes with the change of baud rate. When the baud rate changes, the length of each bit and the length of the start bit of frame synchronization will also change accordingly. For example, if the system clock frequency is 38.4MHz, and we want to establish a baud rate of 9600bps for serial communication, it is necessary to generate a suitable time base by frequency division. The specific calculation method is to divide the system clock frequency by the product of the baud rate and a fixed multiple (such as 16, but not limited to this), that is, div=Fsys / (bps*16)=38400000 / (9600*16)=250. This means that the system clock needs to be divided by 250 to generate a standard time base. Under this time base, the length of each bit is composed of 16 such reference time units, achieving 16 times oversampling. The reason for using 16 times oversampling here is that it can not only improve the sampling accuracy, but also ensure the reliability and accuracy of data transmission without increasing the complexity of the system.

[0037] In the UART communication protocol, accurately detecting the start bit of each frame of data is crucial to ensure the correct reception of the data. Since the baud rate of UART communication may change, traditional dual-edge filtering circuits (such as Chinese invention patent No. ZL201810999948.0, etc.) or capacitive filter circuits have limitations in filtering out glitch noise. These circuit designs can only filter out glitches of fixed length, but cannot adapt to the challenges brought by baud rate changes, which can easily lead to missynchronization and misreception problems caused by noise signals on the bus. Therefore, it is particularly important to develop a filtering sampling mechanism that can adapt to the baud rate changes of UART communication.

[0038] like Figure 2 As shown, the serial communication transmission method provided by the embodiment of the present invention at least includes the following steps:

[0039] S1: Monitor the serial communication line until a level change from logic "1" to logic "0" is detected, and the start bit of the data frame is detected through a triple confirmation mechanism;

[0040] S2: After the data bits and the optional parity bit are transmitted, the serial communication line is continuously monitored until a level change from logic "0" back to logic "1" is detected, and the stop bit of the data frame is confirmed by triple sampling;

[0041] S3: After the stop bit of the data frame ends, return to step S1 to detect the start bit of the next frame of data.

[0042] In one embodiment of the present invention, a specially designed triple confirmation mechanism is used for the start bit of a frame of data, aiming to improve the response speed of UART communication when facing an abnormal state, so that it can quickly exit the current receiving state and restart the detection of the start bit. This mechanism requires that the UART communication must successfully check the start bit in the bus before waking up the system.

[0043] To achieve this, 1 bit time needs to be divided into 16 sampling points, which is equivalent to 16 times oversampling. Such a design helps to improve sampling accuracy while reducing system complexity. On this basis, the triple confirmation mode requires that three independent conditions must be met when the start bit in UART communication is detected. If any of the conditions is not met, the system will immediately exit the current receiving process. For example, assume that the three conditions are whether the detected start bit is a low level, whether the low level lasts for a sufficient time, and whether the start bit is detected within the expected time window. Only when these three conditions are met at the same time will the system confirm the start bit and continue to receive data. This design significantly reduces missynchronization and misreception caused by noise, and also reduces the power consumption of the device because it avoids meaningless data processing for a long time.

[0044] like Figure 3 As shown, in the triple confirmation mechanism provided by the embodiment of the present invention, the coordinated work of the three filters is crucial for the accurate detection of the start bit:

[0045] First filter: Detect the falling edge of the start bit at the preset sampling point to ensure that the detected start bit is a low level. This step mainly uses the sampling points related to the baud rate to judge the falling edge. Through three high-level samplings, it is ensured that at least three sampling points are covered during the idle high-level time of the previous frame of data. The purpose of this mechanism is to ignore the detection of the start bit even in the presence of noise, thereby avoiding false wake-up.

[0046] Second filter: detect the duration of the low level at subsequent sampling points to ensure whether the low level lasts for a sufficient period of time. Specifically, operations are performed at the 2nd, 4th, and 6th sampling points, requiring at least two sampling points to be 0 (low level), otherwise the system will exit the current state and re-judge the start bit. The selection of these three specific sampling points is based on reducing the complexity of implementation while tolerating a certain degree of noise. If two of the three sampling points are 0 and one is 1, this indicates that the signal on the bus generally meets the requirements of the UART start bit, but there is too much noise. This noise signal is used to notify the user that although the signal on the bus generally meets the requirements of the UART start bit, there is still noise interference, but this will not affect the reception of subsequent data.

[0047] The third filter: continuously samples at the middle sampling point of the start bit to ensure that the start bit is detected within the expected time window. Specifically, the three consecutive sampling points of 7, 8, and 9 are detected, and at least two sampling points are required to be 0. Since the most stable part of the data is located in the middle of the bit, three sampling points are continuously taken at the middle sampling point of the start bit for judgment, and its rules are consistent with the second filter. Such a design helps to provide feedback when a noise signal is detected to ensure the accuracy of data reception.

[0048] Through this triple confirmation mechanism, UART communication can detect the start bit more accurately when facing baud rate changes and noise interference, thereby improving the reliability of data transmission. This design not only improves the robustness of the system, but also reduces communication errors caused by missynchronization and misreception, ensuring accurate data transmission.

[0049] On the other hand, in the UART communication protocol, accurate detection of the stop bit of a frame of data is crucial to identifying the end of a frame of data. In one embodiment of the present invention, the determination of the stop bit occurs at the middle position of its duration. Specifically, Figure 4 As shown in the figure, if all or at least two of the three sampling points in the middle position are logic "1", it is considered that the stop bit has been correctly captured. However, if a combination of two logic "0" and one logic "1" appears, such as 100, 010 or 001, this usually indicates the presence of noise interference, that is, a noise signal. This noise signal may cause communication errors, so the design must consider how to reduce its impact.

[0050] When the start bit appears during the stop bit, the counter may need to be resynchronized. In order to ensure the continuity and accuracy of UART communication, a dual counter design method is adopted in the embodiment of the present invention. Specifically, the first counter counts and samples according to the baud rate of the previous frame data, and the second counter is cleared after detecting the falling edge of the next frame data. Such a design allows the system to prepare for the arrival of the next frame data while receiving the current frame data. After the previous frame data is received, the two counters will be synchronized. This synchronization mechanism ensures the synchronization between the first counter and the second counter, so that the system can accurately process the current frame data and pre-process the next frame data in advance. The design of this dual counter improves the flexibility and efficiency of the UART receiver, ensuring that even in the case of noise interference or baud rate changes, the accurate identification and processing of the data frame can be maintained. In this way, the reliability of UART communication is significantly improved, reducing the risk of data errors and communication interruptions caused by noise.

[0051] The judgment mechanism for the stop bit of a frame of data in the embodiment of the present invention allows the user to clearly understand the state of the stop bit. Through the last judgment of the stop bit, data packets that do not conform to the frame format can be filtered out. For example, if a data frame does not detect a high level at the expected stop bit, then the data frame will be marked as an error and can be discarded by the system. In addition, by detecting the start bit of the next frame of data, the false reporting of frame errors can be further reduced. This mechanism ensures that only data frames that conform to the format will be received and processed, thereby improving the accuracy of the data and the reliability of communication.

[0052] When receiving multiple frames of data continuously, the present invention improves the tolerance of UART communication to baud rate changes by accurately formulating the actual detection timing. In UART communication, ensuring that the start bit of the next frame of data is correctly detected is crucial to maintaining the continuity and accuracy of the data stream. In one embodiment of the present invention, the sampling point position of the next frame of data is detected by the following mechanism. Specifically, in the case of continuous transmission, that is, the start bit of the next frame of data is sent immediately after the 1-bit stop bit. Since the crystal oscillators used by the transmitter and the receiver are often independent and have certain deviations, this may cause the baud rate of the transmitter to be faster than the baud rate of the receiver. For example Figure 5 As shown in the figure, if the receiving end starts to detect the start bit after the stop bit ends, it may miss the actual start bit because the start bit of the sending end may have arrived in advance. This will cause the loss of data frames and affect the integrity of communication.

[0053] In order to solve this problem, an improved next frame start bit detection method is proposed in the embodiment of the present invention. Figure 6 As shown, the embodiment of the present invention does not start detecting the start bit of the next frame of data after the stop bit of the previous frame of data ends, but starts detecting immediately after the highest bit of the byte of the previous frame of data (for a byte composed of 8 bits, the highest bit is data bit B7) ends. In this way, even if the baud rate of the sending end is faster than that of the receiving end, the receiving end can detect the start bit in time, thereby avoiding the loss of data frames caused by the start bit synchronization failure. This design improves the tolerance of the system to the baud rate change of the sending end. The inventor has confirmed through experiments that this tolerance can reach 11.1%. This means that as long as the deviation of the crystal oscillator of the opposite end is less than 11.1%, the receiving end can correctly receive the next frame of data, thereby reducing the loss of data frames caused by baud rate mismatch. For example, even if the baud rate of the sending end is slightly faster, as long as it is within the deviation range of 11.1%, the receiving end can still accurately synchronize and receive data.

[0054] In general, the above next frame start bit detection method effectively solves the start bit synchronization problem caused by crystal oscillator deviation by detecting the start bit in advance. Through this improvement, UART communication can work more stably and reliably in the face of crystal oscillator deviation, reducing the risk of data loss and improving communication quality.

[0055] In UART communication, noise is one of the main causes of data errors. By monitoring the noise level in real time, once excessive noise is detected, the system can flag and notify the user that there is a noise problem on the bus. For example, the filter can set a threshold, and when the error caused by noise exceeds this threshold in multiple consecutive samples, the system will record and prompt the excessive noise state. In this way, measures can be taken based on this information, such as adjusting the baud rate, improving the communication line, or taking other noise suppression measures to ensure the reliability of data transmission.

[0056] It should be noted that the serial communication transmission method provided in the embodiment of the present invention is not limited to use in UART communication. Other serial communication methods, such as USART, SPI, I2C, SMBus, CAN, etc. can be used in the present invention. These serial communication methods have their own characteristics and are suitable for different application scenarios and requirements. For example, UART and USART are generally used for low-speed serial communication due to their simplicity and flexibility; SPI, I2C, etc. are suitable for scenarios requiring higher data transmission rates or multi-device communication; CAN, etc. are suitable for long-distance communication and industrial applications.

[0057] Second embodiment

[0058] Based on the above first embodiment, the second embodiment of the present invention provides a serial communication device for implementing the above serial communication transmission method. Figure 7 As shown, the serial communication device at least includes:

[0059] Microcontroller (MCU): As the control center of the serial communication device, it handles data sending and receiving;

[0060] Serial interface connector: used to physically connect to another device;

[0061] Power supply: Provides power to the microcontroller.

[0062] Among them, the TX (transmit) pin of the microcontroller is directly connected to the TX pin of the serial interface connector, and the RX (receive) pin of the microcontroller is directly connected to the RX pin of the serial interface connector. The TX pin of the serial interface connector is connected to the RX pin of another device, and the RX pin of the serial interface connector is connected to the TX pin of another device. The power pin of the microcontroller is connected to the power supply to provide the required voltage for the entire serial communication device.

[0063] When the microcontroller needs to send data, the data is transmitted through the microcontroller's TX pin to the TX pin of the serial interface connector, and then connected to the RX pin of another device through the serial line. The receiving device transmits the signal received by its RX pin to the RX pin of its microcontroller, which then processes the data. Conversely, when the receiving device needs to send data, the same process is carried out in the opposite direction.

[0064] In addition, the serial communication device may also include a UART interface, a crystal oscillator and a filter circuit. The UART interface is integrated inside the microcontroller and is responsible for implementing the UART communication protocol. The crystal oscillator is responsible for providing a stable clock signal for generating the baud rate of the UART communication. The filter circuit is used to filter out the noise on the signal line to ensure the quality of communication. The UART interface converts the data into a serial signal that complies with the UART protocol according to the clock signal provided by the crystal oscillator, and sends it out through a serial interface connector. The received data enters the filter circuit through the serial interface connector, and after filtering out the noise, it is transmitted to the receiver of the UART interface.

[0065] It should be noted that the above embodiments are only examples, and the technical solutions of the various embodiments can be combined, all within the protection scope of the present invention.

[0066] The above is a detailed description of the serial communication transmission method and device with high baud rate tolerance provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A serial communication transmission method with high baud rate tolerance, characterized in that The steps include: S1: Monitor the serial communication line until a level change from logic "1" to logic "0" is detected, and the start bit of the data frame is detected through a triple confirmation mechanism; S2: After the data bits and optional parity bits are transmitted, the serial communication line is continuously monitored until a level change from logic "0" back to logic "1" is detected, and the stop bit of the data frame is detected by triple sampling; S3: After the stop bit of the data frame ends, return to step S1 to detect the start bit of the next frame of data.

2. The serial communication transmission method according to claim 1, wherein: In step S1, the triple confirmation mechanism means that when detecting the start bit, three independent conditions need to be met: whether the detected start bit is a low level, whether the low level lasts for a sufficient time, and whether the start bit is detected within the expected time window; only when these three conditions are met at the same time, the start bit is confirmed and data continues to be received.

3. The serial communication transmission method according to claim 2, wherein: The first filter detects the falling edge of the start bit at a preset sampling point to ensure that the detected start bit is a low level; the second filter detects the duration of the low level at subsequent sampling points to ensure that the low level lasts for a sufficient time; the third filter continuously samples at the middle sampling point position of the start bit to ensure that the start bit is detected within the expected time window.

4. The serial communication transmission method according to claim 3, wherein: The first filter uses sampling points related to the baud rate to judge the falling edge; through three high-level samplings, it is ensured that at least three sampling points are covered in the idle high-level time of the previous frame of data.

5. The serial communication transmission method according to claim 3, wherein: The second filter operates at the following three sampling points, requiring at least two sampling points to be logic "0", otherwise it will exit the current state and re-determine the start bit.

6. The serial communication transmission method according to claim 3, wherein: The third filter continuously takes three sampling points at the middle sampling point position of the start bit for judgment, requiring at least two sampling points to be logic "0", otherwise it will exit the current state and re-judge the start bit.

7. The serial communication transmission method according to claim 1, wherein: In step S2, the triple sampling confirmation means taking three sampling points in succession at the middle position of the stop bit duration; if all or at least two of the three sampling points are logic "1", it is considered that the stop bit has been collected.

8. The serial communication transmission method according to claim 7, wherein: The first counter counts and samples according to the baud rate of the previous frame of data, and the second counter is cleared after detecting the falling edge of the next frame of data; after the previous frame of data is received, the two counters are processed synchronously.

9. The serial communication transmission method according to claim 1, wherein: In step S3, the start bit of the next frame of data is detected immediately after the highest bit of the byte of the previous frame of data ends.

10. A serial communication device, characterized in that It comprises a microcontroller, a serial interface connector and a power supply; wherein the microcontroller is connected to the serial interface connector and is used to implement the serial communication transmission method according to any one of claims 1 to 9.

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