Wireless communication method
By adopting a wireless communication method between core-grade devices, and using effective signals and command/address/data signals to transmit under the control of clock signals, the problems of unreliable and inefficient wireless interconnection communication in the prior art SMIC equipment are solved, and efficient and reliable wireless interconnection communication with low latency and low power consumption are achieved.
Patent Information
- Application Number
- CN202510032663.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-08
- Publication Date
- 2025-05-13
AI Technical Summary
The existing inter-chip interconnection protocols have problems with complex systems and wired interconnection, which leads to unreliable and inefficient wireless interconnection communication between core-chip devices.
A wireless communication method is adopted to transmit efficient and reliable wireless interconnection communication with low latency and low power consumption through wireless communication between the master interface and the slave interface, using effective signals and command/address/data signals under the control of the clock signal.
This method can greatly reduce the delay of inter-chip transmission, realize high-efficiency and reliable wireless interconnection communication between core-grade devices with low latency, low power consumption, and simplify the complexity of inter-chip communication.
Smart Images
Figure CN119988282A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of communication interface technology, and in particular to a wireless communication method. Background Art
[0002] In the field of digital integrated circuits, processors using chiplet technology can reduce costs, shorten R&D cycles, and improve product performance in all aspects. For chiplet-level devices, the existing chiplet-level inter-chip interconnection protocol is not only complex and difficult to use, but also wired, with certain connection reliability issues. How to achieve reliable and efficient wireless interconnection and communication between chiplet-level devices has become an urgent problem to be solved. Summary of the invention
[0003] Based on the above situation of the prior art, the purpose of the embodiments of the present invention is to provide a wireless communication method that can achieve efficient and reliable wireless interconnection communication with low latency and low power consumption between chip-level devices.
[0004] To achieve the above object, according to one aspect of the present invention, a wireless communication method is provided, the method being used for wireless communication between a master interface and a slave interface; the method comprising:
[0005] During a period when the first valid signal is at a first level, the master interface sends a first command signal;
[0006] During the period when the first valid signal is at the second level, the master interface sends an address and / or data, wherein the address and / or data follows the first command signal and indicates operation information related to the first command signal;
[0007] During the period when the second valid signal is at the first level, the slave interface sends a second command signal;
[0008] During the period when the second valid signal is at the second level, the slave interface sends read data;
[0009] The master interface and the master device are located in a first bare core, the slave interface and the slave device are located in a second bare core, the master interface and the master device communicate via a first on-chip bus, and the slave interface and the slave device communicate via a second on-chip bus.
[0010] Further, the first command signal includes an on-chip bus write operation command and an on-chip bus read operation command; the second command signal includes a bus read / write completion confirmation command and a bus read / write error indication command;
[0011] In response to the on-chip bus write operation command or the on-chip bus read operation command, the slave interface sends a bus read / write completion confirmation command when the on-chip bus write operation ends or the read operation ends, and the slave interface sends a bus read / write error indication command when the on-chip bus write operation fails or the read operation fails.
[0012] Further, when the total number of read and write operation commands is equal to the total number of read and write confirmation commands, and the first on-chip bus is in an idle state, the master interface turns off the clock signal;
[0013] The read / write operation commands include an on-chip bus write operation command and an on-chip bus read operation command, and the read / write confirmation commands include a bus read / write completion confirmation command and a bus read / write error indication command.
[0014] Further, the master interface includes a first FIFO, and the slave interface includes a second FIFO; the first command signal includes a wait command; the second command signal includes a wait command;
[0015] During the period when the first valid signal is at the second level and the first FIFO is unloaded, the master interface sends a wait command;
[0016] During the period when the second valid signal is at the second level and the second FIFO is unloaded, the slave interface sends a wait command.
[0017] Further, the second command signal includes a back pressure start command and a back pressure end command;
[0018] During the period when the first valid signal is at the second level, when the second FIFO is greater than or equal to the full load threshold, the slave interface sends a back pressure start command; based on the back pressure start command, when the second FIFO is less than the full load threshold, the slave interface sends a back pressure end command;
[0019] In response to the back pressure start command, the first valid signal is converted from the second level to the first level, and the master interface sends a wait command; in response to the back pressure end command, the first valid signal is converted from the first level to the second level, and the master interface sends an address and / or data.
[0020] Further, the first command signal includes a back pressure start command and a back pressure end command;
[0021] During the period when the second valid signal is at the second level, when the first FIFO is greater than or equal to the full load threshold, the master interface sends a back pressure start command; based on the back pressure start command, when the first FIFO is less than the full load threshold, the master interface sends a back pressure end command;
[0022] In response to the backpressure start command, the second valid signal is converted from the second level to the first level, and the slave interface sends a wait command; in response to the backpressure end command, the second valid signal is converted from the first level to the second level, and the slave interface sends read data.
[0023] Further, the first command signal includes a bus read unit command;
[0024] In the INCR mode, in response to the on-chip bus read operation command, the slave interface sends a data exchange unit of read data based on each bus read unit command;
[0025] In the non-INCR mode, in response to the on-chip bus read operation command, the slave interface sends a predetermined amount of read data.
[0026] In summary, an embodiment of the present invention provides a wireless communication method, which is used for wireless communication between a master interface and a slave interface; the method includes: during a period when a first valid signal is at a first level, the master interface sends a first command signal; during a period when the first valid signal is at a second level, the master interface sends an address and / or data, the address and / or data follows the first command signal, indicating operation information related to the first command signal; during a period when a second valid signal is at a first level, the slave interface sends a second command signal; during a period when the second valid signal is at a second level, the slave interface sends read data. The technical solution provided by an embodiment of the present invention is used for wireless communication between a master interface and a slave interface of a chip-level device, and the number of interface signals is small, and the data to be transmitted does not need to be packaged, and can be a data stream of any length. At any clock time, as long as the data to be transmitted is received, it can be directly transmitted, which can greatly reduce the delay of inter-chip transmission and realize high-efficiency and reliable wireless interconnection communication with low latency and low power consumption between chip-level devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 is a schematic diagram of wireless communication using CWI interface signals according to an embodiment of the present invention;
[0028] Figure 2 is a timing diagram of a CWI interface write operation according to an embodiment of the present invention;
[0029] Figure 3 It is a timing diagram of a CWI interface read operation when the data transmission is of INCR type according to an embodiment of the present invention;
[0030] Figure 4 It is a timing diagram of a CWI interface read operation not considering the back pressure mechanism when the data transmission is of non-INCR type according to an embodiment of the present invention;
[0031] Figure 5This is a timing diagram of a CWI interface read operation taking into account a back pressure mechanism when data transmission is of a non-INCR type according to an embodiment of the present invention. DETAILED DESCRIPTION
[0032] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.
[0033] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in one or more embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
[0034] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings. An embodiment of the present invention provides a wireless communication method, which is used for wireless communication between a master interface and a slave interface, wherein the master interface and the slave interface are located in the same wireless interconnection interface system, and the wireless interconnection interface system is a chiplet wireless interconnection interface (CWI) system based on an on-chip bus, and the system includes, for example, a first bare core and a second bare core, the master interface and the master device are located in the first bare core, the slave interface and the slave device are located in the second bare core, the master interface and the master device communicate through the first on-chip bus, and the slave interface and the slave device communicate through the second on-chip bus, and the master interface and the slave interface can communicate wirelessly through the CWI wireless communication method provided by the embodiment of the present invention. In the embodiment of the present invention, the master device is, for example, a processor, including at least one processor core, for sending data control information; the slave device is, for example, a peripheral device, for responding to the control information of the master device and completing data transmission. The master interface also includes a master side FIFO and a master side register, and the master side register can be accessed through the first on-chip bus; the slave interface also includes a slave side FIFO and a slave side register, and the slave side register can be accessed through the slave side register write command and the slave side register read command of the CWI bus. The Chinese invention application with application number 2024103653465 provides a preferred structure of the above wireless interconnection interface system.
[0035] Figure 1 The schematic diagram of wireless communication using CWI interface signals in an embodiment of the present invention is shown. The CWI interface signals require a small number of signals and only require three types of interface signals, namely clock signals, valid signals, and command / address / data signals. The valid signals and command / address / data signals are transmitted under the control of the clock signal. The 1-bit valid signal is used to distinguish whether the command or address / data to be transmitted, which not only reduces the number of interfaces but also greatly simplifies the complexity of inter-chip communication. The data to be transmitted does not need to be packaged and can be a data stream of any length. At any time of the clock signal, as long as the data to be transmitted is received, it can be directly transmitted, which can greatly reduce the delay of inter-chip transmission.
[0036] Table 1 shows the interpretation of each type of interface signal in the CWI interface signal, and the 1-bit valid signal CWI_m2s_dvalid / CWI_s2m_dvalid is used to distinguish whether the command or address / data to be transmitted is a command. The valid signal CWI_m2s_dvalid / CWI_s2m_dvalid is a high level, indicating that CWI_m2s_data transmits address / data and CWI_s2m_data transmits data. The valid signal CWI_m2s_dvalid / CWI_s2m_dvalid is a low level, indicating that CWI_m2s_data transmits a command and CWI_s2m_data transmits a command. The interpretation of the command signal is shown in Table 2, which is the basic command used in the embodiment of the present invention. Other commands can be set according to actual usage requirements.
[0037] Table 1 CWI interface signal interpretation
[0038]
[0039] Table 2 Command signal interpretation
[0040]
[0041]
[0042] The wireless communication method provided by the embodiment of the present invention comprises the following steps:
[0043] S202 . When the first valid signal is at a first level, the master interface sends a first command signal.
[0044] S204: During the period when the first valid signal is at the second level, the master interface sends an address and / or data, where the address and / or data follows the first command signal, indicating operation information related to the first command signal.
[0045] The first valid signal is, for example, a valid signal CWI_m2s_dvalid from the master interface to the slave interface, and the first level may be a low level 0, and the second level may be a high level 1. During the period when the first valid signal is at the first level, that is, when the valid signal from the master interface to the slave interface is 0, it indicates that the command is sent from the master interface to the slave interface, and the master interface sends the first command signal to the slave interface through the command / address / data signal CWI_m2s_data. During the period when the first valid signal is at the second level, that is, when the valid signal from the master interface to the slave interface is 1, it indicates that the address / data is sent from the master interface to the slave interface, and the master interface sends the address and / or data to the slave interface through the command / address / data signal CWI_m2s_data, and the address and / or data sent by the master interface follow the first command signal, which is used to indicate the operation information related to the first command signal.
[0046] S206 . Send a second command signal from the interface while the second valid signal is at the first level.
[0047] S208 . Send read data from the interface while the second valid signal is at the second level.
[0048] The second valid signal is, for example, a valid signal CWI_s2m_dvalid from the interface to the main interface, and the first level may be a low level 0, and the second level may be a high level 1. During the period when the second valid signal is at the first level, that is, when the valid signal from the interface to the main interface is 0, it indicates that a command is sent from the interface to the main interface, and the second command signal is sent from the interface to the main interface via the command / address / data signal CWI_s2m_data. During the period when the second valid signal is at the second level, that is, when the valid signal from the interface to the main interface is 1, it indicates that an address / data is sent from the interface to the main interface, and data is sent from the interface to the main interface via the command / address / data signal CWI_s2m_data.
[0049] According to certain optional embodiments, the first command signal includes an on-chip bus write operation command and an on-chip bus read operation command; the second command signal includes a bus read / write completion confirmation command and a bus read / write error indication command. In response to the on-chip bus write operation command or the on-chip bus read operation command, the slave interface sends a bus read / write completion confirmation command at the end of the on-chip bus write operation or the end of the read operation, and sends a bus read / write error indication command when the on-chip bus write operation or the read operation is wrong. During the write operation or the read operation, the slave interface detects the end of the on-chip bus write operation or the end of the on-chip bus read operation, and sends a bus read / write completion confirmation command, and detects the on-chip bus write operation error or the on-chip bus read operation error, and sends a bus read / write error indication command.
[0050] According to some optional embodiments, when the total number of read / write operation commands is equal to the total number of read / write confirmation commands, and the first intra-chip bus is in an idle state, the master interface turns off the clock signal, wherein the read / write operation commands include intra-chip bus write operation commands and intra-chip bus read operation commands, and the read / write confirmation commands include bus read / write completion confirmation commands and bus read / write error indication commands. The master interface checks the read / write confirmation commands to confirm that the number of commands must be consistent with the number of sent commands, that is, the master interface counts the intra-chip bus write operation command BUS_WR and the intra-chip bus read operation command BUS_RD, and counts the bus read / write completion confirmation command BUS_ACK and the bus read / write error indication command BUS_NAK. When the two are consistent and the first intra-chip bus is in an idle state, the master interface turns off the clock signal.
[0051] According to some optional embodiments, the master interface includes a first FIFO, the slave interface includes a second FIFO; the first command signal includes a wait command; the second command signal includes a wait command. During the period when the first valid signal is at a second level and the first FIFO is unloaded, the master interface sends the wait command; during the period when the second valid signal is at a second level and the second FIFO is unloaded, the slave interface sends the wait command.
[0052] According to certain optional embodiments, the second command signal includes a backpressure start command and a backpressure end command; during the period when the first valid signal is at the second level, when the second FIFO is greater than or equal to the full load threshold, the slave interface sends a backpressure start command; based on the backpressure start signal, when the second FIFO is less than the full load threshold, the slave interface sends a backpressure end command; in response to the backpressure start command, the first valid signal is converted from the second level to the first level, and the master interface sends a wait command; in response to the backpressure end command, the first valid signal is converted from the first level to the second level, and the master interface sends an address and / or data. In data transmission, there may be a problem of mismatch between the processing speeds of the data sender and the receiver. In the embodiment of the present invention, a flow regulation mechanism is used to prevent data loss due to untimely processing. Both the CWI master interface and the CWI slave interface are provided with a cache FIFO (e.g., a first FIFO and a second FIFO), and flow regulation is performed considering the full and empty situations of the FIFO at the master interface and the FIFO at the slave interface. During the write operation, if the FIFO at the master interface is full, the master interface on-chip bus can be held without operation; if the FIFO at the master interface is empty, the master interface inserts a wait command WAIT, for example, the CWI interface bandwidth is greater than the on-chip bus interface bandwidth, resulting in an empty FIFO, or the master-side on-chip bus is busy and suspends sending data, resulting in an empty FIFO; if the FIFO at the slave interface is full, the slave interface can send a backpressure command (including the backpressure start command BP_START and the backpressure end command BP_STOP), and in response to the backpressure command, the master interface inserts a wait command WAIT, and the master interface suspends sending data, for example, the slave interface on-chip bus is busy, resulting in a full FIFO; if the FIFO at the slave interface is empty, the slave interface on-chip bus can be held without operation. Therefore, write operations can achieve flow regulation in the following three situations:
[0053] 1. The CWI interface bandwidth is greater than the on-chip bus interface bandwidth;
[0054] 2. The bus on the main interface chip is busy, and data transmission is suspended;
[0055] 3. The bus on the slave interface chip is busy, the CWI slave interface sends a back pressure command, and the master interface stops sending data.
[0056] Figure 2 FIG. 1 shows a timing diagram of a CWI interface write operation according to an embodiment of the present invention. Figure 2The upper timing diagram shows the signal transmission timing diagram from the master interface to the slave interface, and the lower timing diagram shows the signal transmission timing diagram from the slave interface to the master interface. Figure 2 As shown, at the start and end of the transmission, the CWI bus is in an idle state (idle command IDLE), and the master interface can turn off the clock to save power. Specifically, the master interface can count the read and write operation commands (including the on-chip bus write operation command BUS_WR and the on-chip bus read operation command BUS_RD), and count the read and write confirmation commands (including the bus read and write completion confirmation command BUS_ACK and the bus read and write error indication command BUS_NAK). If the total number of the two is the same, and the on-chip bus of the current master interface (such as the first on-chip bus) has no request, the clock signal can be turned off. The master interface / slave interface outputs a 1-bit first valid signal / second valid signal (CWI_m2s_dvalid / CWI_s2m_dvalid) to distinguish whether the command or address / data to be transmitted is a command. At the start of the transmission, the first valid signal CWI_m2s_dvalid is at a low level, indicating that the command (such as the idle command IDLE, the on-chip bus write operation command BUS_WR, etc.) is transmitted through CWI_m2s_data.
[0057] like Figure 2 As shown, the master interface sends a first command signal on-chip bus write operation command BUS_WR ( Figure 2 In the upper timing diagram, the first yellow BUS_WR of CWI_m2s_data is shown. At this time, the first valid signal CWI_m2s_dvalid is at a low level, indicating that CWI_m2s_data is transmitting a command. Then, the operation information related to the on-chip bus write operation command BUS_WR is sent, including the target address (ADDR0-ADDR3) and data (WDATA0-WDATA3). At this time, the first valid signal CWI_m2s_dvalid is at a high level, indicating that CWI_m2s_data is transmitting an address / data. The slave interface detects the end command of the on-chip bus write operation of the master interface, and sends the bus read and write completion confirmation command BUS_ACK ( Figure 2 The first green BUS_ACK of CWI_s2m_data in the timing diagram at the bottom implements the transaction confirmation mechanism.
[0058] The master interface continues to send the first command signal on-chip bus write operation command BUS_WR ( Figure 2In the upper timing diagram, the second yellow BUS_WR of CWI_m2s_data is sent, and then the operation information related to the on-chip bus write operation command BUS_WR is sent, including the target address (ADDR0-ADDR3) and data (WDATA0-WDATA3). However, at the same time, the CWI master interface receives the back pressure start command BP_START from the slave interface, so the master interface inserts the wait command WAIT () between sending the target address (ADDR0-ADDR3) and data (WDATA0-WDATA3). Figure 2 The first green WAIT of CWI_m2s_data in the timing diagram at the top waits until the CWI master interface receives the back pressure end command BP_STOP, and the master interface continues to send the unfinished target address (ADDR0-ADDR3) and data (WDATA0-WDATA3), thereby realizing the flow regulation mechanism. If the CWI interface bandwidth is greater than the on-chip bus interface bandwidth or the first on-chip bus is busy and stops sending data, the wait command WAIT ( Figure 2 In the upper timing diagram, the second green WAIT of CWI_m2s_data indicates that the master interface suspends data transmission, thereby realizing the flow regulation mechanism. When the master interface completes the write operation, the slave interface detects again that the write operation of the master interface on-chip bus is completed, and the slave interface sends the bus read and write completion confirmation command BUS_ACK ( Figure 2 The second green BUS_ACK of CWI_s2m_data in the timing diagram at the bottom). After the master interface completes the transmission, it enters the idle state again (idle command IDLE). During the above write operation, the slave interface keeps transmitting commands, so the second valid signal CWI_s2m_dvalid is always at a low level.
[0059] According to some optional embodiments, the first command signal includes a backpressure start command and a backpressure end command; during the period when the second valid signal is at the second level, when the first FIFO is greater than or equal to the full load threshold, the master interface sends a backpressure start command; based on the backpressure start command, when the first FIFO is less than the full load threshold, the master interface sends a backpressure end command; in response to the backpressure start command, the second valid signal is converted from the second level to the first level, and the slave interface sends a wait command; in response to the backpressure end command, the second valid signal is converted from the first level to the second level, and the slave interface sends read data. Both the CWI master interface and the CWI slave interface are provided with a cache FIFO (e.g., a first FIFO and a second FIFO), and flow regulation is performed considering the full and empty situations of the FIFO at the master interface and the FIFO at the slave interface. During the read operation, if the FIFO at the master interface is full, the master interface sends a back pressure command (back pressure start command BP_START and back pressure end command BP_STOP), and the slave interface inserts a wait command WAIT to pause and return read data. For example, the master interface on-chip bus is busy, causing the FIFO to be full; if the master interface FIFO is empty, the master interface on-chip bus is held and does not operate; if the slave interface FIFO is full, the slave interface on-chip bus is held and does not operate; if the slave interface FIFO is empty, the slave interface inserts a wait command WAIT, for example, the CWI interface bandwidth is greater than the on-chip bus interface bandwidth, causing the FIFO to be empty, or the slave interface on-chip bus is busy and pauses to return read data, causing the FIFO to be empty. Therefore, the read operation can achieve flow regulation in the following three situations:
[0060] 1. The CWI interface bandwidth is greater than the on-chip bus interface bandwidth;
[0061] 2. The bus in the slave interface chip is busy, so the data reading is paused and returned;
[0062] 3. The bus on the master interface chip is busy, the CWI master interface sends a back pressure command, and the slave interface pauses and returns read data.
[0063] According to certain optional embodiments, the first command signal includes a bus read unit command; in INCR mode, in response to the on-chip bus read operation command, the slave interface sends a data exchange unit of read data based on each bus read unit command, and the data exchange unit is, for example, Transfer, which refers to the transmission of a single data item, that is, a data transmission unit completed within a single bus cycle, which may be a single transmission unit of address, data or control information; in non-INCR mode, in response to the on-chip bus read operation command, the slave interface sends a predetermined amount of read data. During a read operation, data transmission can be divided into an incremental transfer (INCR) type and a non-INCR type. Depending on the type of data transmission, the read operation flow regulation mechanism is different.
[0064] INCR type read operation traffic regulation mechanism: The INCR type transmits data in one unit each time as a Transfer, supports the first two types of traffic regulation, and does not need to consider the back pressure mechanism.
[0065] Non-INCR type read operation flow regulation mechanism: Non-INCR type data transmission includes one or more Burst transmissions each time, and the slave interface reads data in fixed quantities. Burst transmission refers to the transmission of one or more data in a single bus transaction, allowing multiple data with adjacent addresses to be transmitted in a continuous time. Multiple data transmissions are achieved by sending the start address and control information (such as burst length, etc.), without sending a separate address for each data. A burst transmission can include one or more transfers. The first two flow regulation mechanisms are supported, and whether a back pressure mechanism is needed should be discussed separately based on the on-chip bus type and the FIFO size at the master interface.
[0066] For example, for the AHB bus, non-INCR transmits one burst at a time. If the FIFO size at the master interface supports a complete burst data storage, the CWI bus does not need to consider the back pressure mechanism; if the FIFO at the master interface does not support a complete burst data storage, the CWI bus needs to consider the back pressure mechanism. The CWI master interface sends a back pressure command, and the slave interface inserts a wait command WAIT to pause and return read data. For the AXI bus, non-INCR transmits one to multiple bursts at a time. When transmitting one burst, its back pressure mechanism is the same as the above AHB bus; when transmitting multiple bursts, due to the FIFO size limit at the master interface, the back pressure mechanism generally needs to be considered.
[0067] Figure 3 FIG. 1 shows a timing diagram of a CWI interface read operation when data transmission is of INCR type according to an embodiment of the present invention. Figure 3 The upper timing diagram shows the signal transmission timing diagram from the master interface to the slave interface, and the lower timing diagram shows the signal transmission timing diagram from the slave interface to the master interface. The situation of clock signal shutdown is the same as Figure 2 The transmission starts, the first valid signal CWI_m2s_dvalid is at a low level, indicating a CWI_m2s_data transmission command (such as an idle command IDLE, an on-chip bus write operation command BUS_WR, etc.); the master interface sends an on-chip bus write operation command BUS_WR ( Figure 3The first yellow BUS_WR of CWI_m2s_data in the timing diagram at the top) is then sent to the operation information related to the on-chip bus write operation command BUS_WR, including the target address (ADDR0-ADDR3) and data (WDATA0-WDATA3). At this time, the first valid signal CWI_m2s_dvalid is at a high level, indicating that CWI_m2s_data transmits the address / data; the slave interface detects that the on-chip bus write operation of the master interface is completed, and the slave interface sends the bus read and write completion confirmation command BUS_ACK ( Figure 3 The first green BUS_ACK of CWI_s2m_data in the timing diagram at the bottom realizes the transaction confirmation; the master interface then sends the on-chip bus read operation command BUS_RD ( Figure 3 In the upper timing diagram, the first yellow BUS_RD of CWI_m2s_data is sent, and then the operation information related to the on-chip bus read operation command BUS_RD and the target address (ADDR0-ADDR3) are sent. In INCR mode, the data exchange unit is a Transfer, so every time the master interface sends a bus read unit command BUS_GET, the slave interface replies with a Transfer read data (RDATA0-RDATA3). The master interface inserts a wait command WAIT in the bus read unit command BUS_GET, waiting for the slave interface to return the read data; if the slave interface on-chip bus is busy or waiting for the bus read unit command BUS_GET, the wait command WAIT can be inserted to achieve traffic regulation. The slave interface detects that the on-chip bus read operation of the master interface is completed, and the slave interface sends a bus read and write completion confirmation command BUS_ACK ( Figure 3 In the lower timing diagram, the second green BUS_ACK of CWI_s2m_data is used to confirm the transaction. Finally, the master interface notifies the slave interface bus read unit command BUS_GET to end through the idle command IDLE. During the above read operation, the second valid signal CWI_s2m_dvalid is high only when the slave interface returns the read data.
[0068] Figure 4 FIG. 1 shows a timing diagram of a CWI interface read operation not considering the back pressure mechanism when the data transmission is of non-INCR type according to an embodiment of the present invention. Figure 4 The upper timing diagram shows the signal transmission timing diagram from the master interface to the slave interface, and the lower timing diagram shows the signal transmission timing diagram from the slave interface to the master interface. The situation of clock signal shutdown is the same as Figure 2 The transmission starts, the first valid signal CWI_m2s_dvalid is at a low level, indicating a CWI_m2s_data transmission command (such as an idle command IDLE, an on-chip bus write operation command BUS_WR, etc.); the master interface sends an on-chip bus write operation command BUS_WR ( Figure 4 The first yellow BUS_WR of CWI_m2s_data in the timing diagram at the top) is then sent to the operation information related to the on-chip bus write operation command BUS_WR, including the target address (ADDR0-ADDR3) and data (WDATA0-WDATA3). At this time, the first valid signal CWI_m2s_dvalid is at a high level, indicating that CWI_m2s_data transmits the address / data; the slave interface detects that the on-chip bus write operation of the master interface is completed, and the slave interface sends the bus read and write completion confirmation command BUS_ACK ( Figure 4 The first green BUS_ACK of CWI_s2m_data in the timing diagram at the bottom confirms the transaction. The master interface then sends the on-chip bus read operation command BUS_RD ( Figure 4 In the timing diagram at the top, the first yellow BUS_RD of CWI_m2s_data is sent, and then the operation information related to the on-chip bus read operation command BUS_RD and the target address (ADDR0-ADDR3) are sent. In non-INCR mode, one to multiple Bursts are transmitted, and the slave interface returns the read data (RDATA0-RDATA3, RDATA0-RDATA3); the master interface inserts the wait command WAIT to wait for the slave interface to return the read data; if the on-chip bus of the slave interface is busy, the slave interface can also insert the wait command WAIT; the slave interface detects that the master interface bus read operation is completed, and the slave interface sends the bus read and write completion confirmation command BUS_ACK ( Figure 4 The second green BUS_ACK of CWI_s2m_data in the timing diagram at the bottom realizes transaction confirmation. During the above read operation, the second valid signal CWI_s2m_dvalid is high only when the read data is returned from the interface.
[0069] Figure 5 FIG. 1 shows a timing diagram of a CWI interface read operation taking into account a back pressure mechanism when data transmission is of a non-INCR type according to an embodiment of the present invention. Figure 5 The upper timing diagram shows the signal transmission timing diagram from the master interface to the slave interface, and the lower timing diagram shows the signal transmission timing diagram from the slave interface to the master interface. The situation of clock signal shutdown is the same as Figure 2 The implementation of the on-chip bus write operation command BUS_WR and the on-chip bus read operation command BUS_RD is the same as Figure 4 The CWI master interface sends a back pressure start command BP_START, and the CWI slave interface inserts a wait command WAIT ( Figure 5 In the second green WAIT of CWI_s2m_data in the timing diagram at the bottom, the read data is returned temporarily until the master interface sends the back pressure end command BP_STOP, and the slave interface continues to send the unfinished read data to achieve flow regulation.
[0070] In summary, an embodiment of the present invention relates to a wireless communication method, which is used for wireless communication between a master interface and a slave interface; the method includes: during a period when a first valid signal is at a first level, the master interface sends a first command signal; during a period when the first valid signal is at a second level, the master interface sends an address and / or data, the address and / or data follows the first command signal, indicating operation information related to the first command signal; during a period when a second valid signal is at a first level, the slave interface sends a second command signal; during a period when the second valid signal is at a second level, the slave interface sends read data. The technical solution provided by an embodiment of the present invention is used for wireless communication between a master interface and a slave interface of a chip-level device, with a small number of interface signals, and the data to be transmitted does not need to be packaged, and can be a data stream of any length. At any clock time, as long as the data to be transmitted is received, it can be directly transmitted, which can greatly reduce the delay of inter-chip transmission and realize high-efficiency and reliable wireless interconnection communication with low latency and low power consumption between chip-level devices.
[0071] It should be understood that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present invention (including claims) is limited to these examples; under the idea of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of one or more embodiments of the present invention as described above, which are not provided in detail for the sake of simplicity. The above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the scope of protection of the present invention. In addition, the claims attached to the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the attached claims, or the equivalent forms of such scope and boundaries.
Claims
1. A wireless communication method, characterized in that: The method is used for wireless communication between a master interface and a slave interface; the method comprises: During the period when the first valid signal is at the first level, the master interface sends a first command signal; During the period when the first valid signal is at the second level, the master interface sends an address and / or data, wherein the address and / or data follows the first command signal and indicates operation information related to the first command signal; During the period when the second valid signal is at the first level, the slave interface sends a second command signal; During the period when the second valid signal is at the second level, the slave interface sends read data; The master interface and the master device are located in a first bare core, the slave interface and the slave device are located in a second bare core, the master interface and the master device communicate via a first on-chip bus, and the slave interface and the slave device communicate via a second on-chip bus.
2. The method according to claim 1, characterized in that The first command signal includes an on-chip bus write operation command and an on-chip bus read operation command; the second command signal includes a bus read / write completion confirmation command and a bus read / write error indication command; In response to the on-chip bus write operation command or the on-chip bus read operation command, the slave interface sends a bus read / write completion confirmation command when the on-chip bus write operation ends or the read operation ends, and the slave interface sends a bus read / write error indication command when the on-chip bus write operation fails or the read operation fails.
3. The method according to claim 2, characterized in that When the total number of read and write operation commands is equal to the total number of read and write confirmation commands and the first on-chip bus is in an idle state, the master interface turns off the clock signal; The read / write operation commands include an on-chip bus write operation command and an on-chip bus read operation command, and the read / write confirmation commands include a bus read / write completion confirmation command and a bus read / write error indication command.
4. The method according to claim 1, characterized in that The master interface includes a first FIFO, and the slave interface includes a second FIFO; the first command signal includes a wait command; the second command signal includes a wait command; During the period when the first valid signal is at the second level and the first FIFO is unloaded, the master interface sends a wait command; During the period when the second valid signal is at the second level and the second FIFO is unloaded, the slave interface sends a wait command.
5. The method according to claim 4, characterized in that The second command signal includes a back pressure start command and a back pressure end command; During the period when the first valid signal is at the second level, when the second FIFO is greater than or equal to the full load threshold, the slave interface sends a back pressure start command; based on the back pressure start command, when the second FIFO is less than the full load threshold, the slave interface sends a back pressure end command; In response to the back pressure start command, the first valid signal is converted from the second level to the first level, and the master interface sends a wait command; In response to the back pressure end command, the first valid signal is converted from a first level to a second level, and the master interface sends an address and / or data.
6. The method according to claim 4, characterized in that The first command signal includes a back pressure start command and a back pressure end command; During the period when the second valid signal is at the second level, when the first FIFO is greater than or equal to the full load threshold, the master interface sends a back pressure start command; based on the back pressure start command, when the first FIFO is less than the full load threshold, the master interface sends a back pressure end command; In response to the back pressure start command, the second valid signal is converted from the second level to the first level, and the slave interface sends a wait command; In response to the backpressure end command, the second valid signal is converted from a first level to a second level, and the slave interface sends read data.
7. The method according to claim 2, characterized in that: The first command signal includes a bus read unit command; In the INCR mode, in response to the on-chip bus read operation command, the slave interface sends a data exchange unit of read data based on each bus read unit command; In the non-INCR mode, in response to the on-chip bus read operation command, the slave interface sends a predetermined amount of read data.