Standard backboard for expansion bus of high-speed serial computer

Abstract

The invention provides a high-speed serial computer expansion bus standard backboard which is characterized in that multiple layers of circuit boards are arranged, a plurality of through silicon vias are formed in the multiple layers of circuit boards, the multiple layers of circuit boards are vertically and electrically connected through the through silicon vias to form a three-dimensional topological structure, and the three-dimensional topological structure comprises a first circuit board layer, a second circuit board layer and a third circuit board layer; the first circuit board layer is provided with a plurality of expansion card slots, the second circuit board layer is used for transmitting and processing serial signals, the third circuit board layer is used for providing a power supply, the multi-layer circuit board is further provided with a chip stacking module and a chip mounting part which are electrically connected with the multi-layer circuit board, and the chip mounting part is used for mounting the chip stacking module. According to the multi-layer circuit board, vertical electric connection of all the circuit board layers of the multi-layer circuit board is achieved through the silicon through holes, the transmission path of serial signals is greatly shortened, delay and attenuation of the serial signals are reduced, and stable and high-speed circulation of the high-speed serial signals is powerfully guaranteed.

Description

Technical Field

[0001] The invention relates to the technical field of computers, and in particular to a high-speed serial computer expansion bus standard backplane. Background Art

[0002] The computer expansion bus standard backplane is a key component in the computer system. It is equipped with a series of slots, interfaces and circuit connections to connect the computer and various expansion devices. The computer expansion bus standard backplane is mainly used to enable different devices to be easily inserted into the computer system, such as: graphics card, network card, sound card, storage device, etc.

[0003] At present, the computer expansion bus standard backplane is mainly the parallel computer expansion bus standard backplane, and the parallel computer expansion bus standard backplane adopts a two-dimensional planar circuit board design. Due to space limitations, the number of circuits and chips that can be arranged is relatively limited, and it is difficult to integrate more functional modules in a limited space, resulting in certain limitations on the overall function and performance, and unable to meet the growing demand for high integration of complex systems. For example: for some high-performance computing systems that require a large number of chips and complex circuits, the two-dimensional planar circuit board cannot accommodate enough chips, resulting in difficulty in improving system performance. In addition, electromagnetic interference is easily generated between parallel signals, resulting in damage to signal integrity, affecting the accuracy and reliability of data transmission. Summary of the invention

[0004] The present invention provides a high-speed serial computer expansion bus standard backplane to solve the problems in the prior art that a large number of chips cannot be accommodated due to space limitations, and electromagnetic interference is easily generated between parallel signals, resulting in damage to signal integrity and affecting the accuracy and reliability of data transmission.

[0005] The present invention provides a high-speed serial computer expansion bus standard backplane, comprising:

[0006] A multi-layer circuit board, wherein the multi-layer circuit board is provided with a plurality of through silicon vias, and the multi-layer circuit board is vertically electrically connected through the through silicon vias to form a three-dimensional topological structure, wherein the three-dimensional topological structure comprises a first circuit board layer, a second circuit board layer and a third circuit board layer, wherein the first circuit board layer is provided with a plurality of expansion card slots, the second circuit board layer is used for transmitting and processing serial signals, and the third circuit board layer is used for providing power;

[0007] A chip stacking module, the chip stacking module is electrically connected to the multi-layer circuit board, the chip stacking module comprises a plurality of chips, the plurality of chips are stacked on each other through three-dimensional integration to form the chip stacking module, and adjacent chips are connected through micro bumps;

[0008] A chip mounting portion, wherein the chip mounting portion is disposed on one side of the multi-layer circuit board, the chip mounting portion is used to mount the chip stacking module, the chip mounting portion is provided with a ball grid array packaging unit, and the chip stacking module is electrically connected to the multi-layer circuit board through the ball grid array packaging unit.

[0009] According to the high-speed serial computer expansion bus standard backplane provided by the present invention, the first circuit board layer and the second circuit board layer are vertically electrically connected through the through silicon via, or the first circuit board layer and the third circuit board layer are vertically electrically connected through the through silicon via, or the second circuit board layer and the third circuit board layer are vertically electrically connected through the through silicon via, or the first circuit board layer, the second circuit board layer and the third circuit board layer are vertically electrically connected through the through silicon via.

[0010] According to the high-speed serial computer expansion bus standard backplane provided by the present invention, the three-dimensional topological structure is a reconfigurable topological structure, and the three-dimensional topological structure includes a switchable interconnection channel and a switch element, the switchable interconnection channel is connected to the switch element, and the switch element is used to control the conduction and disconnection of the switchable interconnection channel, the switchable interconnection channel includes a microstrip line, and the expansion card slot is electrically connected to the silicon through-hole through the microstrip line.

[0011] According to the high-speed serial computer expansion bus standard backplane provided by the present invention, a thermal conductive gel and a microchannel liquid cooling plate are provided on the top of the chip stacking module, the microchannel liquid cooling plate is connected to the chip stacking module through the thermal conductive gel, a plurality of microchannels are provided on the interface between the microchannel liquid cooling plate and the chip stacking module, a cooling liquid inlet and a cooling liquid outlet are respectively provided at both ends of the microchannel liquid cooling plate, and the cooling liquid inlet, the microchannel and the cooling liquid outlet are connected.

[0012] According to the high-speed serial computer expansion bus standard backplane provided by the present invention, the cooling liquid inlet is provided with a diverter plate, and the diverter plate distributes the cooling liquid to the microchannel, and the cooling liquid outlet is provided with a collecting device, and the collecting device collects the cooling liquid flowing out of the microchannel.

[0013] According to the high-speed serial computer expansion bus standard backplane provided by the present invention, the serial signal is transmitted through the SerDes communication protocol.

[0014] According to the high-speed serial computer expansion bus standard backplane provided by the present invention, the high-speed serial computer expansion bus standard backplane also includes an optical wiring structure, the optical wiring structure includes an optical transmitting module, an optical receiving module and an optical waveguide layer, the optical transmitting module and the optical receiving module are arranged opposite to each other and are respectively arranged on the sides of the multi-layer circuit board, the optical waveguide layer is arranged between the second circuit board layer and the third circuit board layer, and an insulating layer is arranged between the optical waveguide layer and the second circuit board layer, the optical transmitting module converts the serial signal into a corresponding optical signal, the optical waveguide layer is used to transmit the optical signal, and the optical receiving module is used to convert the optical signal into the serial signal.

[0015] According to the high-speed serial computer expansion bus standard backplane provided by the present invention, the three-dimensional topological structure includes a plurality of distributed signal exchange nodes, and the plurality of distributed signal exchange nodes are interconnected through the optical waveguide layer, and the distributed signal exchange nodes are used for routing and exchanging the serial signals.

[0016] According to the high-speed serial computer expansion bus standard backplane provided by the present invention, the chip stacking module is provided with an intermediate layer, the intermediate layer is provided with a plurality of micro vias, and the chip is connected to the optical waveguide layer through the micro vias.

[0017] The present invention also provides a computer device, comprising the high-speed serial computer expansion bus standard backplane.

[0018] The present invention provides a high-speed serial computer expansion bus standard backplane, which is provided with a multi-layer circuit board and a plurality of silicon-through holes (TSVs) on the multi-layer circuit board. The multi-layer circuit board forms a three-dimensional topological structure through the TSVs. The three-dimensional topological structure includes a first circuit board layer, a second circuit board layer and a third circuit board layer. The first circuit board layer is provided with a plurality of expansion card slots. The second circuit board layer is used for transmitting and processing serial signals. The third circuit board layer is used for providing power. A chip stacking module electrically connected to the multi-layer circuit board is also provided. The chip stacking module includes a plurality of chips. The plurality of chips are stacked on each other through three-dimensional integration to form the chip stacking module. Adjacent chips are connected through micro-bumps. A large number of chips can be accommodated in a limited space. A chip mounting portion is provided on one side of the multilayer circuit board, and the chip mounting portion is used to mount the chip stacking module. The chip mounting portion is provided with a ball grid array packaging unit, and the chip stacking module is electrically connected to the multilayer circuit board through the ball grid array packaging unit. The present invention constructs a three-dimensional topological structure through silicon vias, and each layer has a clear division of labor, wherein the second circuit board layer is used for high-speed transmission and processing of serial signals. In addition, the vertical electrical connection of each circuit board layer achieved by the silicon via greatly shortens the transmission path of the serial signal, reduces the delay and attenuation of the serial signal, and effectively guarantees the stable transmission of the high-speed serial signal. Therefore, the present invention not only reduces the interference of the serial signal, but also improves the integration, thereby providing a reliable environment for high-speed serial signal transmission and ensuring the high-speed circulation of the serial signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 It is a structural schematic diagram of a high-speed serial computer expansion bus standard backplane provided by an embodiment of the present invention;

[0021] Figure 2 It is a structural schematic diagram of a multi-layer circuit board of a high-speed serial computer expansion bus standard backplane provided by an embodiment of the present invention;

[0022] Figure 3 The diagram is a schematic diagram of an optical wiring structure of a high-speed serial computer expansion bus standard backplane provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The present invention provides a high-speed serial computer expansion bus standard backplane, comprising:

[0025] A multi-layer circuit board, wherein the multi-layer circuit board is provided with a plurality of through silicon vias, and the multi-layer circuit board is vertically electrically connected through the through silicon vias to form a three-dimensional topological structure, wherein the three-dimensional topological structure comprises a first circuit board layer, a second circuit board layer and a third circuit board layer, wherein the first circuit board layer is provided with a plurality of expansion card slots, the second circuit board layer is used for transmitting and processing serial signals, and the third circuit board layer is used for providing power;

[0026] A chip stacking module, the chip stacking module is electrically connected to the multi-layer circuit board, the chip stacking module comprises a plurality of chips, the plurality of chips are stacked on each other through three-dimensional integration to form the chip stacking module, and adjacent chips are connected through micro bumps;

[0027] A chip mounting portion, wherein the chip mounting portion is disposed on one side of the multi-layer circuit board, the chip mounting portion is used to mount the chip stacking module, the chip mounting portion is provided with a ball grid array packaging unit, and the chip stacking module is electrically connected to the multi-layer circuit board through the ball grid array packaging unit.

[0028] Among them, the first circuit board layer and the second circuit board layer are vertically electrically connected through the silicon via, or the first circuit board layer and the third circuit board layer are vertically electrically connected through the silicon via, or the second circuit board layer and the third circuit board layer are vertically electrically connected through the silicon via, or the first circuit board layer, the second circuit board layer and the third circuit board layer are vertically electrically connected through the silicon via.

[0029] Among them, the three-dimensional topological structure is a reconfigurable topological structure, and the three-dimensional topological structure includes a switchable interconnection channel and a switch element, the switchable interconnection channel is connected to the switch element, and the switch element is used to control the conduction and disconnection of the switchable interconnection channel, the switchable interconnection channel includes a microstrip line, and the expansion card slot is electrically connected to the silicon through-hole through the microstrip line.

[0030] Wherein, the top of the chip stacking module is provided with a thermally conductive gel and a microchannel liquid cooling plate, the microchannel liquid cooling plate is connected to the chip stacking module through the thermally conductive gel, a plurality of microchannels are arranged on the interface between the microchannel liquid cooling plate and the chip stacking module, a coolant inlet and a coolant outlet are arranged at both ends of the microchannel liquid cooling plate, and the coolant inlet, the microchannel and the coolant outlet are connected. In addition, the coolant inlet is provided with a diverter plate, which distributes the coolant to the microchannel, and the coolant outlet is provided with a collector, which collects the coolant flowing out of the microchannel.

[0031] Wherein, the serial signal is transmitted through the SerDes communication protocol.

[0032] Wherein, the high-speed serial computer expansion bus standard backplane also includes an optical wiring structure, the optical wiring structure includes an optical transmitting module, an optical receiving module and an optical waveguide layer, the optical transmitting module and the optical receiving module are arranged relative to each other and are respectively arranged on the side of the multi-layer circuit board, the optical waveguide layer is arranged between the second circuit board layer and the third circuit board layer, and an insulating layer is arranged between the optical waveguide layer and the second circuit board layer, the optical transmitting module converts the serial signal into a corresponding optical signal, the optical waveguide layer is used to transmit the optical signal, and the optical receiving module is used to convert the optical signal into the serial signal. In addition, the three-dimensional topological structure includes a plurality of distributed signal exchange nodes, and the plurality of distributed signal exchange nodes are interconnected through the optical waveguide layer, and the distributed signal exchange nodes are used for routing and exchanging the serial signal. The chip stacking module is also provided with an intermediate layer, and the intermediate layer is provided with a plurality of micro vias, and the chip is connected to the optical waveguide layer through the micro vias.

[0033] The present invention also provides a computer device, comprising the high-speed serial computer expansion bus standard backplane.

[0034] The present invention provides a high-speed serial computer expansion bus standard backplane, which is provided with a multi-layer circuit board and a plurality of silicon-through holes (TSVs) on the multi-layer circuit board. The multi-layer circuit board forms a three-dimensional topological structure through the TSVs. The three-dimensional topological structure includes a first circuit board layer, a second circuit board layer and a third circuit board layer. The first circuit board layer is provided with a plurality of expansion card slots. The second circuit board layer is used for transmitting and processing serial signals. The third circuit board layer is used for providing power. A chip stacking module electrically connected to the multi-layer circuit board is also provided. The chip stacking module includes a plurality of chips. The plurality of chips are stacked on each other through three-dimensional integration to form the chip stacking module. Adjacent chips are connected through micro-bumps. A large number of chips can be accommodated in a limited space. A chip mounting portion is provided on one side of the multilayer circuit board, and the chip mounting portion is used to mount the chip stacking module. The chip mounting portion is provided with a ball grid array packaging unit, and the chip stacking module is electrically connected to the multilayer circuit board through the ball grid array packaging unit. The present invention constructs a three-dimensional topological structure through silicon vias, and each layer has a clear division of labor, wherein the second circuit board layer focuses on high-speed transmission and processing of serial signals. In addition, the vertical electrical connection of each circuit board layer achieved by the silicon via greatly shortens the transmission path of the serial signal, reduces the delay and attenuation of the serial signal, and effectively guarantees the stable transmission of the high-speed serial signal. Therefore, the present invention not only reduces the interference of the serial signal, but also improves the integration, thereby providing a reliable environment for high-speed serial signal transmission and ensuring the high-speed circulation of the serial signal.

[0035] In this embodiment, please refer to Figure 1 , Figure 2 and Figure 3 , which are respectively a structural schematic diagram of a high-speed serial computer expansion bus standard backplane 1 provided in an embodiment of the present invention, a structural schematic diagram of a multi-layer circuit board 10 of a high-speed serial computer expansion bus standard backplane 1 provided in an embodiment of the present invention, and a schematic diagram of an optical wiring structure 40 of a high-speed serial computer expansion bus standard backplane 1 provided in an embodiment of the present invention.

[0036] Specifically, in this embodiment, Figure 1 and Figure 2As shown, an embodiment of the present invention provides a high-speed serial computer expansion bus standard backplane 1, including a multilayer circuit board 10, wherein the multilayer circuit board 10 is provided with a plurality of silicon through vias, and the multilayer circuit board 10 is vertically electrically connected through the silicon through vias to form a three-dimensional topological structure 100, wherein the three-dimensional topological structure 100 includes a first circuit board layer 1001, a second circuit board layer 1002 and a third circuit board layer 1003, wherein the first circuit board layer 1001 is provided with a plurality of expansion card slots, the second circuit board layer 1002 is used for transmitting and processing serial signals, and the third circuit board layer 1003 is used for providing power, wherein the serial signal is transmitted through the SerDes communication protocol, and the full name of the SerDes communication protocol is the Serializer / Deserializer communication protocol. The multilayer circuit board 10 of the present invention realizes the vertical transmission of high-speed serial signals by adopting the three-dimensional topological structure 100 formed by vertical interconnection of silicon through vias, thereby greatly shortening the signal transmission distance and improving the transmission efficiency.

[0037] In this embodiment, the through silicon via includes an insulating layer and a barrier layer. The insulating layer is used to isolate the conductive material in the through silicon via from the surrounding silicon or other conductive layers to prevent leakage and short circuit. The formation of the through silicon via mainly includes the following processes:

[0038] First, the position and shape of the silicon through hole are determined on the multi-layer circuit board 10 by using the photolithography technology, specifically including: coating a photoresist on the surface of the laminated structure of the multi-layer circuit board 10, exposing the area where the silicon through hole is to be formed through the photolithography mask, and then etching the multi-layer circuit board 10 by deep reactive ion etching (DRIE) to form the silicon through hole penetrating the corresponding circuit board layer;

[0039] On the inner wall of the formed through silicon via, an insulating layer is deposited by a chemical vapor deposition (CVD) process. The thickness of the insulating layer is between 200 and 500 nanometers. Its function is to isolate the conductive material in the through silicon via from the surrounding silicon or other conductive layers to prevent leakage and short circuit.

[0040] Next, a barrier layer is deposited on the insulating layer by a physical vapor deposition (PVD) process to prevent the subsequent conductive material from diffusing into the surrounding material. In this embodiment, the conductive material is copper, and a thin copper seed layer is deposited on the barrier layer to prepare for the subsequent electroplating filling.

[0041] Then, copper is filled into the TSV using the copper electroplating method. In an electroplating solution containing copper ions, the copper seed layer is used as an electrode. The copper ions are reduced and evenly fill the TSV by precisely controlling the electroplating current, time and solution composition.

[0042] In this embodiment, specifically, a number of expansion card slots are distributed in an array on the surface of the first circuit board layer 1001, and the spacing between adjacent expansion card slots is designed based on the size and heat dissipation requirements of the corresponding expansion cards, and is preferably 15-25 mm, thereby ensuring that each expansion card can work stably and does not interfere with each other. In addition, the pin layout of the expansion card slot is vertically electrically connected to the signal line of the second circuit board layer 1002 through silicon vias, thereby ensuring the high efficiency of signal transmission. In addition, the three-dimensional topological structure 100 formed by vertical interconnection of silicon vias by the multi-layer circuit board 10 can connect chips, modules or circuit elements on different layers, thereby realizing vertical transmission of high-speed serial signals, greatly shortening the signal transmission distance, and improving the transmission efficiency.

[0043] In this embodiment, the first circuit board layer 1001 and the second circuit board layer 1002 are vertically electrically connected through the through silicon via. Specifically, the expansion card slot of the first circuit board layer 1001 guides the serial signal to the top of the through silicon via through a microstrip line. The top of the through silicon via is metallized to ensure electrical contact with the microstrip line. The filled metal material at the bottom of the through silicon via is electrically connected to the second circuit board layer 1002 through the microstrip line to achieve vertical transmission of the serial signal.

[0044] The first circuit board layer 1001 and the third circuit board layer 1003 are vertically electrically connected through the silicon vias. Specifically, on the power plane of the third circuit board layer 1003, the power is led out to the top of the silicon vias, and is conducted to the power pin of the first circuit board layer 1001 through the metal material in the silicon vias. In addition, an insulating layer is arranged around the silicon vias to isolate the silicon vias from the second circuit board layer 1002, so as to prevent the signals transmitted by the first circuit board layer 1001 and the third circuit board layer 1003 from interfering with the signals of the second circuit board layer 1002. For large current requirements, the density of silicon vias can be increased in the corresponding area, and at the same time, it is ensured that the layout of these silicon vias in the third circuit board layer 1003 complies with the power integrity principle to avoid the problems of power supply noise and excessive voltage drop. Then, the grounding requirements of the first circuit board layer 1001 are connected to the ground layer of the third circuit board layer 1003 through silicon vias. By increasing the number of grounding silicon vias and optimizing their layout, a good grounding loop is formed, the grounding impedance is reduced, and electromagnetic interference is reduced.

[0045] The second circuit board layer 1002 is vertically electrically connected to the third circuit board layer 1003 through the through silicon via. Specifically, the second circuit board layer 1002 is connected to the top of the through silicon via through a microstrip line, and the bottom of the through silicon via is connected to the corresponding power plane and ground layer of the third circuit board layer 1003. In addition, the first circuit board layer 1001, the second circuit board layer 1002 and the third circuit board layer 1003 are vertically electrically connected through the through silicon via, and their structure is similar to the above structure. The above structure can be adjusted accordingly and connected, and no further details are given.

[0046] In this embodiment, the three-dimensional topological structure 100 is a reconfigurable topological structure. The three-dimensional topological structure 100 includes a switchable interconnection channel and a switch element. The switchable interconnection channel is connected to the switch element. The switch element is used to control the conduction and disconnection of the switchable interconnection channel. The switchable interconnection channel includes a microstrip line. The expansion card slot is electrically connected to the silicon through-hole through the microstrip line. Specifically, in this embodiment, the switchable interconnection channel is an optical interconnection channel. The switch element is a thermo-optical switch. The optical interconnection channel is controlled by the thermo-optical switch. For example, the thermo-optical switch changes the refractive index of its own waveguide material by changing the temperature, thereby guiding the optical signal to propagate along different paths. Different optical interconnection channels in the multi-layer circuit board 10 can be connected to different chips or circuit board layers. The three-dimensional topological structure 100 is dynamically adjusted by switching the thermo-optical switch, so that the originally unconnected signal lines are connected to change the original three-dimensional topological structure 100 according to actual needs.

[0047] In this embodiment, if Figure 1 As shown, an embodiment of the present invention provides a high-speed serial computer expansion bus standard backplane 1 also including a chip stacking module 20, wherein the chip stacking module 20 is electrically connected to the multi-layer circuit board 10, wherein the chip stacking module 20 includes a plurality of chips, wherein the plurality of chips are stacked on each other through three-dimensional integration to form the chip stacking module 20, wherein adjacent chips are connected through micro-bumps, and furthermore, a chip mounting portion 30 is provided, wherein the chip mounting portion 30 is provided on one side of the multi-layer circuit board 10, wherein the chip mounting portion 30 is used to mount the chip stacking module 20, wherein the chip mounting portion 30 is provided with a ball grid array packaging unit, wherein the chip stacking module 20 is electrically connected to the multi-layer circuit board 10 through the ball grid array packaging unit, and specifically, a plurality of high-speed serial communication chips are stacked together, wherein each chip is responsible for processing signals in different directions or channels, and adjacent chips are interconnected through short-distance micro-bumps to form a compact chip stacking module 20, which can not only increase the serial signal transmission rate but also save space, thereby accommodating a large number of chips in a limited space.

[0048] In this embodiment, it is optimal that a thermally conductive gel and a microchannel liquid cooling plate are provided on the top of the chip stacking module 20, the microchannel liquid cooling plate is connected to the chip stacking module 20 through the thermally conductive gel, a plurality of microchannels are provided on the interface between the microchannel liquid cooling plate and the chip stacking module 20, a coolant inlet and a coolant outlet are provided at both ends of the microchannel liquid cooling plate, and the coolant inlet, the microchannel and the coolant outlet are connected. In addition, a flow divider is provided at the coolant inlet, and the flow divider distributes the coolant to the microchannel, and a flow collecting device is provided at the coolant outlet, and the flow collecting device collects the coolant flowing out of the microchannel. It is optimal that a plurality of microchannels are etched on the surface where the microchannel liquid cooling plate connects to the chip stacking module 20, and the shape of the microchannel is trapezoidal, and the trapezoidal microchannel is conducive to the flow distribution of the coolant, thereby ensuring the flow rate and heat exchange efficiency of the coolant.

[0049] In addition, the diverter plate is connected to the coolant inlet by a threaded connection, which is convenient for disassembly and maintenance. A sealing gasket is added at the connection part to ensure that the coolant does not leak. When the coolant flows in, the diverter plate divides the coolant into multiple small streams. According to the Bernoulli principle and the continuity equation of fluid mechanics, the diverter plate is used to make each stream have a similar flow rate and pressure before entering the microchannel, thereby achieving uniform distribution of the coolant in each microchannel. For example, for coolant with a faster flow rate, the diverter plate is used to slow down and divert it, ensuring that each microchannel can obtain an appropriate amount of coolant.

[0050] In this embodiment, a collecting device is installed at the coolant outlet, and is used to collect the coolant flowing out of the microchannel. The collecting device includes a collecting chamber and an outlet pipe. The collecting chamber is used to accommodate the coolant flowing out of each microchannel, and fully mix it in the collecting chamber to balance the pressure. The inner wall of the collecting chamber is smoothed to reduce the flow resistance of the coolant. The outlet pipe is connected to the collecting chamber by threads, and a sealing ring is provided to ensure the sealing. After the coolant flowing out of the microchannel enters the collecting chamber, due to the large cross-sectional area of ​​the collecting chamber, the flow rate of the coolant is reduced, and the pressure tends to be balanced. In the collecting chamber, the coolant is gradually collected to the outlet pipe through natural diffusion and the guidance of the guide structure, wherein the guide structure is a guide groove arranged in the collecting chamber, and the guide groove is used to guide the coolant to flow to the outlet pipe, avoiding the formation of a dead zone or vortex in the collecting chamber, and ensuring that the coolant can be efficiently collected and flowed out.

[0051] In this embodiment, if Figure 1 and Figure 3As shown, the high-speed serial computer expansion bus standard backplane 1 also includes an optical wiring structure 40, and the optical wiring structure 40 includes an optical transmitting module 400, an optical receiving module 401 and an optical waveguide layer 402. The optical transmitting module 400 and the optical receiving module 401 are arranged relatively to each other and are respectively arranged on the sides of the multi-layer circuit board 10, the optical waveguide layer 402 is arranged between the second circuit board layer 1002 and the third circuit board layer 1003, and an insulating layer is arranged between the optical waveguide layer 402 and the second circuit board layer 1002, the optical transmitting module 400 converts the serial signal into a corresponding optical signal, the optical waveguide layer 402 is used to transmit the optical signal, and the optical receiving module 401 is used to convert the optical signal into the serial signal.

[0052] In this embodiment, specifically, a first electrical interface matching the optical transmitter module 400 is provided on the side of the multi-layer circuit board 10, and the optical transmitter module 400 is electrically connected to the second circuit board layer 1002 through the first electrical interface. The optical transmitter module 400 receives a serial signal from the second circuit board layer 1002 and converts the serial signal into a corresponding optical signal. In addition, the optical receiving module 401 is connected to the multi-layer circuit board 10 through the second electrical interface, and is located on the other side of the multi-layer circuit board 10 and is arranged opposite to the optical transmitter module 400 to ensure that the optical signal transmitted through the optical waveguide layer 402 can be accurately received. The second electrical interface is electrically connected to the second circuit board layer 1002, and is used to transmit the restored serial signal to the subsequent circuit for processing.

[0053] In this embodiment, the optical waveguide layer 402 is located between the second circuit board layer 1002 and the third circuit board layer 1003, and serves as a channel for optical signal transmission. In order to prevent signal interference between the optical waveguide layer 402 and the second circuit board layer 1002, an insulating layer is provided between the optical waveguide layer 402 and the second circuit board. The optical waveguide layer 402 includes a straight waveguide, a curved waveguide, a branch waveguide and a coupler. The straight waveguide is used to realize long-distance straight-line transmission of the optical signal. The curved waveguide is used to change the propagation direction of the optical signal. In order to reduce the loss, the bending radius is usually greater than a certain value. For example, in a silicon-based optical waveguide, the bending radius needs to be greater than 50 microns. The branch waveguide is used to divide one optical signal into multiple channels, or to realize the merging of multiple optical signals. The coupler is used to realize the coupling of optical signals between different waveguides, so as to ensure that the optical signal can be accurately and efficiently transmitted to the target location.

[0054] In addition, the three-dimensional topological structure 100 includes a plurality of distributed signal exchange nodes, and the plurality of distributed signal exchange nodes are interconnected through the optical waveguide layer 402. The distributed signal exchange nodes are used for routing and exchanging the serial signals. Specifically, when a serial signal arrives at a distributed signal exchange node, the serial signal is first parsed and information such as the destination address of the serial signal is extracted. Then, the next hop node of the serial signal is determined according to a pre-set routing table or a dynamically calculated routing strategy. For example, if a routing algorithm based on the shortest path is used to calculate the path length from the current node to all possible destination nodes, the next hop node corresponding to the shortest path is selected. Then, the serial signal is temporarily stored in a buffer and waits for a suitable time to be sent to the next hop node. Finally, the sending order of the serial signal is arranged according to the communication status between nodes and the bandwidth usage, so as to ensure that the signal can be efficiently and orderly transmitted to the target node through the optical waveguide layer 402.

[0055] In this embodiment, if Figure 1 As shown, the chip stacking module 20 is also provided with an intermediate layer 200, and a plurality of micro vias are provided on the intermediate layer 200. The chip is connected to the optical waveguide layer 402 through the micro vias. The intermediate layer 200 not only provides physical support and electrical connection, but also performs certain preprocessing and adaptation on the signal to ensure efficient communication between the chip and the optical waveguide layer 402. The intermediate layer 200 reduces the transmission delay and loss of the signal by optimizing the signal transmission path.

[0056] The present invention further provides a computer device, including the high-speed serial computer expansion bus standard backplane 1, the specific structure of which is as described above and will not be described in detail.

[0057] The present invention provides a high-speed serial computer expansion bus standard backplane 1, which is provided with a multi-layer circuit board 10 and a plurality of silicon through holes (TSVs) on the multi-layer circuit board 10. The multi-layer circuit board 10 forms a three-dimensional topological structure 100 through the TSVs. The three-dimensional topological structure 100 includes a first circuit board layer 1001, a second circuit board layer 1002 and a third circuit board layer 1003. The first circuit board layer 1001 is provided with a plurality of expansion card slots. The second circuit board layer 1002 is used for transmitting and processing serial signals. The third circuit board layer 1003 is used for providing power. A chip stacking module 20 electrically connected to the multi-layer circuit board 10 is also provided. The chip stacking module 20 includes a plurality of chips. The plurality of chips are stacked on each other through three-dimensional integration to form the chip stacking module 20. Adjacent chips are connected through micro-bumps. A chip mounting portion 30 is provided on one side of the multi-layer circuit board 10, and the chip mounting portion 30 is used to mount the chip stacking module 20. The chip mounting portion 30 is provided with a ball grid array packaging unit, and the chip stacking module 20 is electrically connected to the multi-layer circuit board 10 through the ball grid array packaging unit. The present invention constructs a three-dimensional topological structure 100 through silicon vias, and each layer has a clear division of labor, wherein the second circuit board layer 1002 focuses on high-speed transmission and processing of serial signals. In addition, the vertical electrical connection of each circuit board layer achieved by the silicon via greatly shortens the transmission path of the serial signal, reduces the delay and attenuation of the serial signal, and effectively guarantees the stable transmission of the high-speed serial signal. Therefore, the present invention not only reduces the interference of the serial signal, but also improves the integration, thereby providing a reliable environment for high-speed serial signal transmission and ensuring the high-speed circulation of the serial signal.

[0058] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0059] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed serial computer expansion bus standard backplane, characterized in that: include: A multi-layer circuit board, wherein the multi-layer circuit board is provided with a plurality of through silicon vias, and the multi-layer circuit board is vertically electrically connected through the through silicon vias to form a three-dimensional topological structure, wherein the three-dimensional topological structure comprises a first circuit board layer, a second circuit board layer and a third circuit board layer, wherein the first circuit board layer is provided with a plurality of expansion card slots, the second circuit board layer is used for transmitting and processing serial signals, and the third circuit board layer is used for providing power; A chip stacking module, the chip stacking module is electrically connected to the multi-layer circuit board, the chip stacking module comprises a plurality of chips, the plurality of chips are stacked on each other through three-dimensional integration to form the chip stacking module, and adjacent chips are connected through micro bumps; A chip mounting portion, wherein the chip mounting portion is disposed on one side of the multi-layer circuit board, the chip mounting portion is used to mount the chip stacking module, the chip mounting portion is provided with a ball grid array packaging unit, and the chip stacking module is electrically connected to the multi-layer circuit board through the ball grid array packaging unit.

2. The high-speed serial computer expansion bus standard backplane according to claim 1, characterized in that: The first circuit board layer is vertically electrically connected to the second circuit board layer through the silicon via, or the first circuit board layer is vertically electrically connected to the third circuit board layer through the silicon via, or the second circuit board layer is vertically electrically connected to the third circuit board layer through the silicon via, or the first circuit board layer, the second circuit board layer and the third circuit board layer are vertically electrically connected through the silicon via.

3. The high-speed serial computer expansion bus standard backplane according to claim 1, characterized in that: The three-dimensional topological structure is a reconfigurable topological structure, and the three-dimensional topological structure includes a switchable interconnection channel and a switch element, the switchable interconnection channel is connected to the switch element, the switch element is used to control the conduction and disconnection of the switchable interconnection channel, the switchable interconnection channel includes a microstrip line, and the expansion card slot is electrically connected to the silicon through-hole through the microstrip line.

4. The high-speed serial computer expansion bus standard backplane according to claim 1, characterized in that: A thermally conductive gel and a microchannel liquid cooling plate are provided on the top of the chip stacking module. The microchannel liquid cooling plate is connected to the chip stacking module through the thermally conductive gel. A plurality of microchannels are provided on the interface between the microchannel liquid cooling plate and the chip stacking module. A cooling liquid inlet and a cooling liquid outlet are respectively provided at both ends of the microchannel liquid cooling plate. The cooling liquid inlet, the microchannel and the cooling liquid outlet are connected.

5. The high-speed serial computer expansion bus standard backplane according to claim 4, characterized in that: The coolant inlet is provided with a flow divider, and the flow divider distributes the coolant to the microchannel. The coolant outlet is provided with a flow collecting device, and the flow collecting device collects the coolant flowing out of the microchannel.

6. The high-speed serial computer expansion bus standard backplane according to claim 1, characterized in that: The serial signal is transmitted via the SerDes communication protocol.

7. The high-speed serial computer expansion bus standard backplane according to claim 1, characterized in that: The high-speed serial computer expansion bus standard backplane also includes an optical wiring structure, which includes an optical transmitting module, an optical receiving module and an optical waveguide layer. The optical transmitting module and the optical receiving module are arranged opposite to each other and are respectively arranged on the sides of the multi-layer circuit board. The optical waveguide layer is arranged between the second circuit board layer and the third circuit board layer, and an insulating layer is arranged between the optical waveguide layer and the second circuit board layer. The optical transmitting module converts the serial signal into a corresponding optical signal, the optical waveguide layer is used to transmit the optical signal, and the optical receiving module is used to convert the optical signal into the serial signal.

8. The high-speed serial computer expansion bus standard backplane according to claim 7, characterized in that: The three-dimensional topological structure includes a plurality of distributed signal exchange nodes, the plurality of distributed signal exchange nodes are interconnected through the optical waveguide layer, and the distributed signal exchange nodes are used for routing and exchanging the serial signals.

9. The high-speed serial computer expansion bus standard backplane according to claim 7, characterized in that: The chip stacking module is provided with an intermediate layer, the intermediate layer is provided with a plurality of micro vias, and the chip is connected to the optical waveguide layer through the micro vias.

10. A computer device, characterized in that: A high-speed serial computer expansion bus standard backplane comprising any one of claims 1-9.

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