A system architecture design method, device and equipment for two-node interaction and a medium

Abstract

The application discloses a system architecture design method and device for double-node interaction, equipment and medium, relates to the field of integrated circuits, and comprises the following steps: configuring corresponding communication bus modules for a first node and a second node in double nodes respectively; the communication bus module comprises a universal serial bus function based on integrated logic; the communication bus modules of the double nodes are connected with respective video graphics array modules, management component transmission protocol modules, data access interaction modules and general expansion control interfaces; the respective video graphics array modules of the double nodes are connected with respective image coding and decoding modules; the bandwidth of the communication bus module is calculated according to the bus characteristics of the communication bus module, and the bandwidth of the storage space is calculated according to the storage characteristics of the storage space, so as to meet the bandwidth requirement of the double nodes. The application effectively solves the problem of high cost of the multi-node server, greatly improves the utilization rate of the baseboard management controller, and realizes simultaneous online control management of the multi-node server host.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a system architecture design method and device for double-node interaction, equipment and a medium. BACKGROUND

[0002] A BMC (Baseboard Management Controller) undertakes the functions of server control and remote monitoring in a system. In a traditional multi-node server, each node (host) needs a separate BMC for management control. When the number of nodes is large, a large number of BMCs are needed, which leads to a high cost of the multi-node server.

[0003] In summary, how to realize simultaneous online control and management of multi-node server hosts, improve the utilization rate of the BMC, and reduce enterprise costs is an important technical problem to be solved in the field. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a system architecture design method and device for double-node interaction, which can realize simultaneous online control and management of multi-node server hosts, improve the utilization rate of the system, and reduce enterprise costs. The specific solutions are as follows:

[0005] In a first aspect, the present application discloses a system architecture design method for double-node interaction, comprising:

[0006] A corresponding communication bus module is configured for each of the first node and the second node in the double nodes; wherein the communication bus module comprises a universal serial bus function based on a preset integrated logic;

[0007] The communication bus module of the double nodes is connected to the respective video graphics array module, management component transmission protocol module, data access interaction module and universal expansion control interface, and the respective video graphics array module of the double nodes is connected to the respective image encoding and decoding module;

[0008] The bandwidth of the communication bus module is calculated according to the bus characteristics of the communication bus module, and the bandwidth of the storage space is calculated according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the double nodes.

[0009] Optionally, the bandwidth of the communication bus module is calculated according to the bus characteristics of the communication bus module, comprising:

[0010] The first bandwidth requirement of the video graphics array module for the communication bus module is determined;

[0011] determining a second bandwidth requirement of the communication bus module for the universal serial bus function;

[0012] determining a bus standard of the communication bus module according to the first bandwidth requirement and the second bandwidth requirement, and determining a coding rule corresponding to the bus standard;

[0013] calculating a bandwidth of the communication bus module according to the bus standard and the coding rule.

[0014] Optionally, data generated by the image coding and decoding module in the process of image coding and image decoding and data generated by the video graphics array module in the process of processing video are stored in the same block of storage space.

[0015] Optionally, the bandwidth of the storage space is calculated according to the storage characteristics of the storage space, comprising:

[0016] determining a third bandwidth requirement of the video graphics array module for the storage space according to the maximum resolution of the video graphics array module, the picture transmission rate and the bit number occupied by the pixel;

[0017] calculating a fourth bandwidth requirement of the image coding and decoding module for the storage space according to the third bandwidth requirement; wherein the fourth bandwidth requirement is related to the data reading rate of the image coding and decoding module;

[0018] determining a minimum compression ratio of the image coding and decoding module, and calculating a fifth bandwidth requirement of the image coding and decoding module for the storage space according to the fourth bandwidth requirement and the minimum compression ratio of the image coding and decoding module;

[0019] calculating a sixth bandwidth requirement of the system for the storage space according to the first data transmission rate and the data transmission bit width when the storage space interacts with the target network controller;

[0020] determining a data bus width of the storage space according to the third bandwidth requirement, the fourth bandwidth requirement, the fifth bandwidth requirement and the sixth bandwidth requirement;

[0021] calculating the bandwidth of the storage space according to the data bus width of the storage space, the second data transmission rate of the storage space and the minimum working efficiency of the storage space.

[0022] Optionally, the universal expansion control interfaces of the two nodes are respectively connected to the universal serial bus interfaces of the two nodes, so as to communicate with the corresponding external devices through the universal serial bus interfaces.

[0023] Optionally, the system architecture design method for the two nodes to interact further comprises:

[0024] The serial peripheral interface of the dual nodes is connected with the target network controller through the bus master interface of each node, and the serial peripheral interface of the dual nodes is connected with the four-wire serial peripheral interface and the integrated circuit bus of each node through the bus slave interface of each node.

[0025] Optionally, the system architecture design method for dual node interaction further includes:

[0026] The low-pin-count bus of the dual nodes is connected with the target network controller through the virtual universal asynchronous receiver transmitter of each node, and the low-pin-count bus of the dual nodes is connected with the target network controller through the virtual universal asynchronous receiver transmitter of each node.

[0027] In a second aspect, the present application discloses a system architecture design device for dual node interaction, comprising:

[0028] The node communication bus configuration module is configured to configure a corresponding communication bus module for each of the first node and the second node in the dual nodes, wherein the communication bus module comprises a universal serial bus function based on a preset integrated logic implementation.

[0029] The multi-module connection management module is configured to control the communication bus module of the dual nodes to connect the video graphics array module, the management component transmission protocol module, the data access interaction module, and the universal expansion control interface, and to control the video graphics array module of the dual nodes to connect the image encoding and decoding module.

[0030] The storage bandwidth adaptation module is configured to calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and to calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirement of the dual nodes.

[0031] In a third aspect, the present application discloses an electronic device, comprising:

[0032] The memory is configured to save the computer program.

[0033] The processor is configured to execute the computer program to implement the system architecture design method for dual node interaction disclosed above.

[0034] In a fourth aspect, the present application discloses a computer readable storage medium configured to save a computer program, wherein the computer program is executed by a processor to implement the system architecture design method for dual node interaction disclosed above.

[0035] As can be seen, this application proposes a system architecture design method for dual-node interaction, including: configuring corresponding communication bus modules for the first and second nodes in the dual-node system; wherein, the communication bus modules of the dual nodes each include a universal serial bus function implemented based on preset integrated logic; controlling the communication bus modules of the dual nodes to connect to their respective video graphics array modules, management component transmission protocol modules, data access interaction modules, and universal extended control interfaces, and controlling the respective video graphics array modules of the dual nodes to connect to their respective image encoding and decoding modules; calculating the bandwidth of the communication bus modules based on their bus characteristics, and calculating the bandwidth of the storage space based on its storage characteristics, so that the bandwidth of the communication bus modules and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes. It is evident that this application integrates the universal serial bus function implemented by the second communication bus module in the conventional technology into the first communication bus module, thereby reducing the number of communication bus modules used and effectively solving the problem of high cost of multi-node servers. Furthermore, this application connects the video graphics array module, management component transmission protocol module, data access interaction module, and general-purpose extended control interface to the communication bus module controlling the dual nodes, thereby achieving centralized management and control of multiple modules on the dual nodes. This significantly improves the utilization rate of the baseboard management controller. In addition, this application calculates the bandwidth of the communication bus module and the bandwidth of the storage space to ensure that they meet the bandwidth requirements of the dual nodes, guaranteeing stable and efficient data transmission. Finally, this application connects the video graphics array modules of each dual node to the image encoding / decoding module, and combines this with the communication bus module to connect the aforementioned key modules, enabling technicians to perform real-time online management and control of the video, data, and other aspects of the dual nodes, achieving simultaneous online control and management of the multi-node server host. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of a single-node scheme for a traditional baseboard management controller system.

[0038] Figure 2 This is a schematic diagram of a single-node related module structure of a traditional baseboard management controller system.

[0039] Figure 3 This application discloses a flowchart of a system architecture design method for dual-node interaction.

[0040] Figure 4A system architecture diagram of a two-node interaction disclosed in the present application;

[0041] Figure 5 A related module structure diagram of a two-node interaction disclosed in the present application;

[0042] Figure 6 A system architecture design device structure diagram of a two-node interaction disclosed in the present application;

[0043] Figure 7 An electronic device structure diagram disclosed in the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0045] The BMC undertakes the functions of server control and remote monitoring in the system. In a traditional multi-node server, each node needs a separate baseboard management controller for management control. When the number of nodes is large, more baseboard management controllers are needed, resulting in a high cost of the multi-node server.

[0046] Therefore, the embodiments of the present application propose a system architecture design scheme of a two-node interaction, which can realize simultaneous online control management of a multi-node server host, improve system utilization, and reduce enterprise costs.

[0047] The embodiments of the present application disclose a system architecture design method of a two-node interaction, as shown in the figure, the method comprises: Figure 5

[0048] Step S11: configuring a corresponding communication bus module for each of the first node and the second node in the two nodes; wherein the communication bus module comprises a universal serial bus function based on a preset integrated logic.

[0049] Figure 1 ​A single-node (server) scheme diagram of a traditional baseboard management controller system is provided. A server is connected to a baseboard management controller system through a Peripheral Component Interconnect Express (PCIe) interface. The baseboard management controller system has two PCIe modules, which are connected to different functional modules. On one hand, an AXI routing is connected through an Advanced eXtensible Interface Master (Axi Master) and an Advanced eXtensible Interface Slave (Axi Slave) interface. A Management Component Transport Protocol (Mctp), a data access interaction module, and a Video Graphics Array (Vga) are connected through the AXI routing. A Joint Photographic Experts Group (Jpeg) is connected through the Vga. Data in the Jpeg and the Vga is stored in a Double Data Rate (Ddr).

[0050] Figure 2A single node (server) of a traditional baseboard management controller system LPC (Linear Predictive Coding) and eSPI (Enhanced Serial Peripheral Interface module) related module structure diagram is provided. The server is connected with other modules as the core equipment of the whole system. The universal asynchronous receiver-transmitter (UART) includes universal asynchronous receiver-transmitter 10 and universal asynchronous receiver-transmitter , which is used to realize asynchronous serial communication. The low pin count bus (LPC Bus) is connected with the universal asynchronous receiver-transmitter through the LPC control signal, and is bidirectionally connected with the server. The Uart router is located between the universal asynchronous receiver-transmitter and the universal asynchronous receiver-transmitter 10, and plays a role of data routing. The universal asynchronous receiver-transmitter input and output port is connected with the universal asynchronous receiver-transmitter 10 and the universal asynchronous receiver-transmitter 1-4, and provides data input and output functions. The enhanced serial peripheral interface (eSPI) is connected with the four-channel serial peripheral interface through the advanced high-performance bus master interface, and is connected with the server, two virtual universal asynchronous receiver-transmitters and the network control port through the advanced high-performance bus slave interface. The four-channel serial peripheral interface (QSPI) is connected with the enhanced serial peripheral interface, which is used for serial data communication. The network control port is connected with the enhanced serial peripheral interface through the advanced high-performance bus slave interface, and is connected with two virtual universal asynchronous receiver-transmitters. It should be pointed out that the number of interfaces, module composition, DDR bandwidth and PCIe bus rate in the current baseboard management controller architecture scheme cannot meet the needs of double-node management. In order to solve this problem, the baseboard management controller architecture is redesigned in the embodiment, and the functional modules and interfaces required for double-node management are added, and the DDR bandwidth and PCIe bus bandwidth are also improved, and the previous design content is reused as much as possible, so as to meet all the functional and performance requirements of double-node management, and save the corresponding manufacturing cost.

[0051] Therefore, the application respectively configures the corresponding communication bus module for the first node and the second node in the double nodes (that is Figure 4The communication bus module includes a universal serial bus function based on a preset integrated logic. That is, the universal serial bus function realized by the second communication bus module in the prior art is integrated into the first communication bus module, so as to reduce the number of communication bus modules, and effectively solve the problem of high cost of the multi-node server.

[0052] Step S12: Control the communication bus modules of the two nodes to connect the respective video graphics array modules, management component transmission protocol modules, data access interaction modules and general expansion control interfaces, and control the respective video graphics array modules of the two nodes to connect the respective image encoding and decoding modules.

[0053] Referring to FIG. 6, in this embodiment, the communication bus modules of the two nodes are connected to the respective video graphics array modules, management component transmission protocol modules, data access interaction modules and general expansion control interfaces through the respective AXI routes, and the respective video graphics array modules of the two nodes are connected to the respective image encoding and decoding modules. Figure 4 In this way, the two modules do not need to be respectively configured with independent storage chips or storage areas, so that the hardware procurement cost and the complexity of the circuit board design are effectively reduced. In addition, after the image encoding and decoding are completed, the video graphics array modules can directly read data from the shared storage space for subsequent video processing, without going through complicated cross-storage area transmission, so that the real-time performance of data processing is significantly improved.

[0054] Referring to FIG. 6, in this embodiment, the communication bus modules of the two nodes are connected to the respective video graphics array modules, management component transmission protocol modules, data access interaction modules and general expansion control interfaces through the respective AXI routes, and the respective video graphics array modules of the two nodes are connected to the respective image encoding and decoding modules. Figure 4 Referring to FIG. 6, in this embodiment, the general expansion control interfaces of the two nodes are connected to the respective universal serial bus interfaces (USB3.0 physical layer modules and USB2.0 device control modules) to communicate with external devices through the respective universal serial bus interfaces.

[0055] Figure 5 Referring to FIG. 6, the serial peripheral interfaces (enhanced serial peripheral interface 0 and enhanced serial peripheral interface 1) of the two nodes are connected to the target network controller (network interface controller 400) through the respective bus master interfaces (advanced high-performance bus slave interfaces), and the serial peripheral interfaces of the two nodes are connected to the respective four-wire serial peripheral interfaces (four-channel serial peripheral interface 0 and four-channel serial peripheral interface 1) and integrated circuit buses (integrated circuit bus 1) through the respective bus slave interfaces.The low-pin-count buses (low-pin-count bus 0 and low-pin-count bus 1) of the two nodes are connected to the respective universal asynchronous receiver-transmitters (universal asynchronous receiver-transmitter 10, universal asynchronous receiver-transmitter 20, universal asynchronous receiver-transmitter 30 and universal asynchronous receiver-transmitter 40) through the respective universal asynchronous receiver-transmitters (universal asynchronous receiver-transmitter 10, universal asynchronous receiver-transmitter 20, universal asynchronous receiver-transmitter 30 and universal asynchronous receiver-transmitter 40). , universal asynchronous receiver-transmitter 11, universal asynchronous receiver-transmitter ) and the respective routes (universal asynchronous receiver-transmitter route 0 and universal asynchronous receiver-transmitter route 1), connecting the low-pin-count bus of the dual nodes to the target network controller through the respective virtual universal asynchronous receiver-transmitters (2 virtual universal asynchronous receiver-transmitters). It can be seen that, on the basis of the single-node scheme, the application additionally adds a set of LPC1, eSPI1 modules and is mounted on the same Nic400 bus, adding AXI Route1, , UART11 and GPIO function multiplexing module, the added module and the AXI Route0, , UART10 and GPIO function in the single-node scheme are consistent. LPC0, eSPI0, QSPI0, UART10, for supporting the first node data processing, LPC1, eSPI1, QSPI1, UART11, for supporting the second node data processing.

[0056] In this way, the single BMC can simultaneously process the data of the LPC and eSPI interfaces of the dual-node host. Through the above connection mode, the needs of the dual-node interface are met. The enhanced serial peripheral interface of the dual nodes is directly connected to the network interface controller 400, providing a dedicated high-speed data channel for the two nodes, so that each node can independently and quickly interact with the network, reduce transmission delay, meet the real-time data transmission needs of the dual nodes, and ensure efficient data throughput of the dual nodes in a complex network environment.

[0057] Step S13: Calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth needs of the dual nodes.

[0058] In this embodiment, the first bandwidth requirement of the video graphics array module to the communication bus module is determined, the second bandwidth requirement of the universal serial bus function to the communication bus module is determined, the bus standard of the communication bus module is determined according to the first bandwidth requirement and the second bandwidth requirement, and the encoding rule corresponding to the bus standard is determined, and then the bandwidth of the communication bus module is calculated according to the bus standard and the encoding rule.

[0059] For example, the first bandwidth requirement of the VGA module to the PCIE module is (first bandwidth requirement), the bandwidth requirement of the USB module to the PCIe is (second bandwidth requirement), and the PCIe2.0 protocol supports Each lane supports the transmission of 5 gigabits per second. This is because the PCIe 2.0 physical layer protocol uses... The encoding scheme requires sending 10 bits for every 8 bits transmitted. The extra 2 bits are not meaningful information to the upper layers; therefore, each lane in the PCIe 2.0 protocol supports: rate ( That is, the available bandwidth of PCIe gen2 is only The bandwidth requirement of a USB module for PCIe is... The VGA module requires PCIe bandwidth of At this point, the requirement for USB and VGA modules to share a single PCIe interface cannot be met, therefore the PCIe bus needs to be upgraded. For this reason, this embodiment upgrades PCIe from PCIe gen2 to PCIe gen3 (the bus standards corresponding to different levels are not the same). Protocol support This means that each lane supports the transmission of 8 gigabits per second. The physical layer protocol used in PCIe 3.0 is... The encoding scheme requires sending 130 bits for every 128 bits transmitted. Therefore, each lane in the PCIe 3.0 protocol supports: The rate (bandwidth is approximately) This satisfies the need for dual-node management.

[0060] In this embodiment, the third bandwidth requirement of the video graphics array module for storage space is determined based on the maximum resolution, image transmission rate, and number of bits per pixel of the video graphics array module. The fourth bandwidth requirement of the image codec module for storage space is calculated based on the third bandwidth requirement. The fourth bandwidth requirement is related to the data read rate of the image codec module. The minimum compression ratio of the image codec module is determined, and the fifth bandwidth requirement of the image codec module for storage space is calculated based on the fourth bandwidth requirement and the minimum compression ratio of the image codec module. The sixth bandwidth requirement of the system for storage space is calculated based on the first data transmission rate and data transmission bit width when the storage space interacts with the target network controller. The data bus width of the storage space is determined based on the third, fourth, fifth, and sixth bandwidth requirements. Finally, the bandwidth of the storage space is calculated based on the data bus width, the second data transmission rate of the storage space, and the minimum operating efficiency of the storage space.

[0061] For example, VGA's DDR operations include writing and reading images, within the maximum resolution supported by VGA. At 60 frames per second and 32 bpp per pixel, the required DDR bandwidth for a VGA is: (third bandwidth requirement). Further, Jpeg reads image from DDR and writes compressed image to DDR at maximum resolution , 60 frames per second, 32bpp per pixel, Jpeg reads data bandwidth is: (fourth bandwidth requirement). Further, Jpeg compression ratio is between , according to the minimum compression ratio , compressed bandwidth is: (fifth bandwidth requirement). Further, the system operates on DDR mainly for system and application running, and interacts with DDR through Nic400, and the bandwidth requirement is: (sixth bandwidth requirement). According to the above calculation, the total bandwidth requirement of the BMC system is: . The minimum efficiency of the DDR module is: . According to the calculation, under the condition of maintaining the DDR bus width of 16 (bits), the minimum requirement , can meet the bandwidth requirement: . According to the production process selection and back-end layout and wiring, it is ensured that the DDR can reach 2667Mbps after production to meet the system requirements. DDR4 has the highest speed of 2667MHz under the existing process, and the modules interacting with DDR include VGA, Jpeg and Nic400. After each module is expanded to double nodes, the bandwidth requirement of the double-node system to DDR is about: , so the single-node DDR solution cannot meet the bandwidth requirements of two groups of VGA and Jpeg in the double-node system, and therefore the DDR bandwidth needs to be improved. The DDR process continues to use DDR4, and the rate can reach 2667MB / s, and the DDR external interface is upgraded from 16 bits to 32 bits, at this time the DDR bandwidth is: , which meets the bandwidth requirements of the double-node system.

[0062] In this embodiment, the original path is merged into one path to reduce the number of PCIe eps used under the premise of ensuring normal function implementation, thereby saving hardware resources. The is split into two IPs in the form of a pcie IP and a remaining logic IP (Intellectual Property) for integration into the system. Through the design of a new server management architecture, it is possible to support the management of two hosts by a single BMC. The function modules of each host management application apply a group of PCIe buses respectively, and share double data rate random access memory. The eSPI and LPC interfaces are expanded, and related function interfaces UART and virtual UART are combined into the baseboard management controller architecture, which can support the management requirements of double nodes.

[0063] In addition, the embodiment can also dynamically adjust the working frequency and power consumption of each module according to the real-time load condition of the system, and maximize the reduction of system energy consumption on the premise of ensuring that the system performance is not affected. In addition, the embodiment can also design a real-time communication priority scheduling algorithm. The system allocates different priorities to various data according to the data transmission requirements and real-time requirements of different modules. For example, the highest priority is given to the real-time video data transmitted by the video graphics array module, so as to preferentially guarantee the timeliness of data transmission and avoid video lag; and a lower priority is set for the transmission of some non-critical system configuration data. As can be seen, this priority scheduling technology can effectively optimize the bandwidth utilization of the communication bus, thereby improving the overall real-time performance of the system.

[0064] It can be seen that the application proposes a system architecture design method for double-node interaction, which comprises: configuring corresponding communication bus modules for the first node and the second node in the double nodes respectively; wherein the communication bus modules of the double nodes respectively comprise a universal serial bus function based on a preset integrated logic; controlling the communication bus modules of the double nodes to connect respective video graphics array modules, management component transmission protocol modules, data access interaction modules and general expansion control interfaces, and controlling the respective video graphics array modules of the double nodes to connect respective image encoding and decoding modules; calculating the bandwidth of the communication bus modules according to the bus characteristics of the communication bus modules, and calculating the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus modules and the bandwidth of the storage space meet the bandwidth requirements of the double nodes. It can be seen that the application integrates the universal serial bus function realized by the second communication bus module in the traditional technology into the first communication bus module, thereby reducing the number of communication bus modules used, effectively solving the problem of high cost of multi-node servers. Further, the application controls the communication bus modules of the double nodes to connect the video graphics array modules, the management component transmission protocol modules, the data access interaction modules and the general expansion control interfaces, thereby realizing centralized management and control of the multi-modules of the double nodes. In this way, the utilization rate of the baseboard management controller is greatly improved. In addition, the application calculates the bandwidth of the communication bus modules and the bandwidth of the storage space to ensure that they meet the bandwidth requirements of the double nodes, thereby ensuring stable and efficient data transmission. Finally, the application connects the respective video graphics array modules of the double nodes to the image encoding and decoding modules, and connects the communication bus modules to the above-mentioned key modules, so that the technician can perform online management and control of the video, data and other aspects of the double nodes in real time, thereby realizing simultaneous online control and management of the multi-node server host.

[0065] Correspondingly, the application also discloses a system architecture design device for double-node interaction, as shown in Figure 6 The device comprises:

[0066] The node communication bus configuration module 11 is configured to configure a corresponding communication bus module for each of the first node and the second node in the dual node, wherein the communication bus module comprises a universal serial bus function based on a preset integrated logic;

[0067] The multi-module connection management module 12 is configured to control the communication bus module of the dual node to connect the video graphics array module, the component transmission protocol module, the data access interaction module and the universal expansion control interface, and control the video graphics array module of the dual node to connect the image encoding and decoding module.

[0068] The storage bandwidth adaptation module 13 is configured to calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirement of the dual node.

[0069] The more specific working processes of the above-mentioned modules can refer to the corresponding contents disclosed in the foregoing embodiments, and will not be described here in detail.

[0070] It can be seen that the application provides a system architecture design device for double-node interaction, which comprises: a node communication bus configuration module 11, configured to configure a corresponding communication bus module for a first node and a second node in the double nodes respectively; wherein the communication bus modules of the double nodes respectively comprise a universal serial bus function based on a preset integrated logic; a multi-module connection management module 12, configured to control the communication bus modules of the double nodes to connect respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal expansion control interfaces, and control the respective video graphics array modules of the double nodes to connect respective image encoding and decoding modules; and a storage bandwidth adaptation module 13, configured to calculate the bandwidth of the communication bus modules according to the bus characteristics of the communication bus modules, and calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus modules and the bandwidth of the storage space meet the bandwidth requirements of the double nodes. It can be seen that the application integrates the universal serial bus function realized by the second communication bus module in the traditional technology into the first communication bus module, thereby reducing the number of communication bus modules used and effectively solving the problem of high cost of multi-node servers. Further, the application controls the communication bus modules of the double nodes to connect the video graphics array modules, the management component transmission protocol modules, the data access interaction modules and the universal expansion control interfaces, thereby realizing centralized management and control of the multi-modules of the double nodes, which greatly improves the utilization rate of the baseboard management controller. In addition, the application calculates the bandwidth of the communication bus modules and the bandwidth of the storage space to ensure that they meet the bandwidth requirements of the double nodes and guarantee stable and efficient data transmission. Finally, the application connects the respective video graphics array modules of the double nodes to the image encoding and decoding modules, and connects the communication bus modules to the above-mentioned key modules, so that the technician can perform online management and control of the video, data and other aspects of the double nodes in real time, thereby realizing simultaneous online control and management of the multi-node server host.

[0071] Further, the application embodiment also provides an electronic device. Figure 7 The electronic device 20 structure diagram shown in FIG. 1 is not considered as any limitation on the use range of the application.

[0072] Figure 7 The electronic device 20 structure diagram provided by the application embodiment. The electronic device 20, specifically can include: at least one processor 21, at least one memory 22, display screen 23, input and output interface 24, communication interface 25, power supply 26 and communication bus 27. Wherein, the memory 22 is used for storing computer program, computer program is loaded and executed by the processor 21, to realize the related steps in the double-node interaction system architecture design method disclosed by any preceding embodiment. In addition, the electronic device 20 in the embodiment specifically can be electronic computer.

[0073] In this embodiment, the power supply 26 is configured to provide operating voltage for each hardware device on the electronic device 20; the communication interface 25 is configured to create a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 25 can be any communication protocol applicable to the technical solution of the present application, which will not be specifically limited herein; the input / output interface 24 is configured to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application requirements, which will not be specifically limited herein.

[0074] In addition, the memory 22 as a carrier for storing resources can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include a computer program 221, and the storage mode can be temporary storage or permanent storage. In addition to the computer program 221 capable of being used to complete the system architecture design method of the double-node interaction executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 221 can further include a computer program capable of being used to complete other specific work.

[0075] Further, the embodiment of the present application further discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to implement the system architecture design method of the double-node interaction disclosed above.

[0076] The specific steps of the method can refer to the corresponding content disclosed in the foregoing embodiments, which will not be described here.

[0077] Further, the embodiment of the present application further discloses a computer program product, including computer programs / instructions, which are executed by a processor to implement the steps of the random number generation method disclosed above.

[0078] The embodiments in the present application are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant part can refer to the method part.

[0079] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of the two. In order to clearly show the interchangeability of hardware and software, the components and steps of each example have been described in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0080] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. The storage medium can be coupled to the processor such that the processor can read information from, and write information to, the storage medium.

[0081] Finally, it should be noted that the terms "first", "second", and the like, herein do not denote any order, quantity, combination, or importance, but rather are used to distinguish one element from another, and do not imply or require any such actual relationship or order. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0082] The above provides a detailed introduction to the system architecture design method, device, equipment, and storage medium of a dual-node interaction system provided by the present application. The principles and implementation modes of the present application are described in the above examples, and the above example descriptions are only used to help understand the method and core idea of the present application. Meanwhile, for those skilled in the art, the specific implementation mode and application range will be changed according to the idea of the present application. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method for designing a system architecture of a two-node interaction, characterized in that, The method comprises: configuring a corresponding communication bus module for the first node and the second node in the dual nodes respectively; wherein the communication bus module comprises a universal serial bus function based on a preset integrated logic; controlling the communication bus module of the dual nodes to connect respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal expansion control interfaces, and controlling the respective video graphics array modules of the dual nodes to connect respective image encoding and decoding modules; calculating the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculating the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes.

2. The system architecture design method of two-node interaction according to claim 1, characterized in that, The method of calculating the bandwidth of the communication bus module according to the bus characteristics of the communication bus module comprises: determining the first bandwidth requirement of the video graphics array module for the communication bus module; determining the second bandwidth requirement of the universal serial bus function for the communication bus module; determining the bus standard of the communication bus module according to the first bandwidth requirement and the second bandwidth requirement, and determining the encoding rule corresponding to the bus standard; calculating the bandwidth of the communication bus module according to the bus standard and the encoding rule.

3. The system architecture design method of dual-node interaction according to claim 1, wherein, The data generated by the image encoding and decoding module in the process of image encoding and decoding and the data generated by the video graphics array module in the process of processing video are stored in the same block of storage space.

4. The system architecture design method of dual-node interaction according to claim 3, characterized in that, The method of calculating the bandwidth of the storage space according to the storage characteristics of the storage space comprises: determining the third bandwidth requirement of the video graphics array module for the storage space according to the maximum resolution, picture transmission rate and pixel bit number of the video graphics array module; calculating the fourth bandwidth requirement of the image encoding and decoding module for the storage space according to the third bandwidth requirement; wherein the fourth bandwidth requirement is related to the data reading rate of the image encoding and decoding module; determining the minimum compression ratio of the image encoding and decoding module, and calculating the fifth bandwidth requirement of the image encoding and decoding module for the storage space according to the fourth bandwidth requirement and the minimum compression ratio of the image encoding and decoding module; calculating the sixth bandwidth requirement of the system for the storage space according to the first data transmission rate and data transmission bit width when the storage space interacts with a target network controller; determining the data bus width of the storage space according to the third bandwidth requirement, the fourth bandwidth requirement, the fifth bandwidth requirement and the sixth bandwidth requirement; calculating the bandwidth of the storage space according to the data bus width of the storage space, the second data transmission rate of the storage space and the minimum working efficiency of the storage space.

5. The system architecture design method of dual node interaction according to claim 1, wherein, The universal expansion control interfaces of the dual nodes are respectively connected to the universal serial bus interfaces of the dual nodes, so as to communicate with the corresponding external devices through the universal serial bus interfaces.

6. The system architecture design method of dual-node interaction according to claim 4, wherein, The method further comprises: The serial peripheral interface of the dual node is connected with the target network controller through the bus master interface of each bus, and the serial peripheral interface of the dual node is connected with the four-wire serial peripheral interface and the integrated circuit bus through the bus slave interface of each bus.

7. The system architecture design method of dual node interaction according to claim 4, wherein, Also included are: The low-pin bus of the dual node is connected with the target network controller through the virtual universal asynchronous receiver transmitter of each bus, and the low-pin bus of the dual node is connected with the target network controller through the virtual universal asynchronous receiver transmitter of each bus.

8. A system architecture design device of two-node interaction, characterized in that, Including: The node communication bus configuration module is configured to configure a corresponding communication bus module for each of the first node and the second node in the dual node, wherein the communication bus module includes a universal serial bus function based on a preset integrated logic implementation; The multi-module connection management module is configured to control the communication bus module of the dual node to connect the video graphics array module, the management component transmission protocol module, the data access interaction module and the universal expansion control interface, and to control the video graphics array module of the dual node to connect the image encoding and decoding module of each node; The storage bandwidth adaptation module is configured to calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and to calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual node.

9. An electronic device, comprising: Including: A memory for storing a computer program; A processor for executing the computer program to implement the system architecture design method of the dual node interaction according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A memory for storing a computer program; wherein the computer program is executed by a processor to implement the system architecture design method of the dual node interaction according to any one of claims 1 to 7. A memory for storing a computer program; wherein the computer program is executed by a processor to implement the system architecture design method of the dual node interaction according to any one of claims 1 to 7.

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