Asynchronous signal capturing method for improving utilization efficiency of hardware resources

Abstract

The invention relates to an asynchronous signal capturing method for improving the utilization efficiency of hardware resources, which comprises the following steps of: judging capturing starting time by utilizing an adjustable fixed-length data segment power average value and a single sampling point which slides forwards each time, and maintaining capturing to ending by utilizing an average power state of two data segments with adjacent time; the processing process accurately and efficiently obtains an effective sample point set to save system storage resources, the data segment power average value algorithm is optimized and designed to save hardware implementation resources, and the cache space is circularly used in the whole capture process to improve the utilization rate of hardware resources.

Description

Technical Field

[0001] The present invention relates to the technical field related to digital communication, and in particular to an asynchronous signal capture method for improving the utilization efficiency of hardware resources. Background Art

[0002] Asynchronous signals are those signals that are not controlled by the same clock signal and may come from different clock domains or external devices. In FPGA design, the processing of asynchronous signals is an important and complex task, because improper processing may lead to system instability, data errors and even system crashes.

[0003] When processing asynchronous signals, special attention should be paid to signal synchronization, stability, and potential metastable issues. Since asynchronous signals may come from different clock domains or external devices, their arrival time and frequency may not be controlled by the FPGA internal clock, so processing is relatively complex.

[0004] In the process of capturing existing asynchronous signals, a large amount of hardware system resources are wasted, resulting in poor resource utilization efficiency.

[0005] In view of the above-mentioned defects, the designers have actively carried out research and innovation in order to create an asynchronous signal capture method that improves the efficiency of hardware resource utilization and makes it more valuable for industrial use. Summary of the invention

[0006] To solve the above technical problems, an object of the present invention is to provide an asynchronous signal capture method for improving the utilization efficiency of hardware resources.

[0007] To achieve the above object, the present invention adopts the following technical solution:

[0008] An asynchronous signal capture method for improving hardware resource utilization efficiency comprises the following steps in sequence:

[0009] Step S1: After receiving the trigger prediction command, first calculate the data segment DP m Power average, calculate the sum of the squared amplitudes of single sample points in sequence and input the result into the 0th register of the long N sliding data delay. Before each new sample point is input, move each stored data to the adjacent next delay register position, until the squared amplitude of the N-1th sample point is calculated for the first time, and the N squared amplitude sets are obtained for the first time after inputting the sliding data delay 0th register. From this point on, the earliest sample point will be shifted out after each new sample point is input, and the most recent N sets of values ​​will always be retained; then calculate the total power sum of the data segment, and finally right shift log2N=M bits to obtain the average power d a ;

[0010] Among them, single sample point IQs i =a i +b ij;

[0011] The square of the single sample point amplitude P(i) = a i 2 +b i 2 ;

[0012] Long N data segment power average

[0013] d a It is the average power parameter that captures the decision input of the whole process;

[0014] Step S2: At the beginning of the prediction period, after obtaining the first data segment DP0, use the power average d a (0) and the predicted expected power threshold Q p Compare, let Q p is 20% Rmax, Rmax is the maximum square amplitude of a single sample point, if d a (0) Greater than or equal to Q p , then the first data segment DP0 is judged to be valid and capture begins; if d a (0) Less than Q p , wait until the second data segment DP1, use the power average d a (1) and the expected power threshold Q p Compare, if d a (1) Greater than or equal to Q p , determine that the second data segment DP1 is the capture start segment; if d a (r-1) is still less than Q p , waiting for data segment r, using power average d a (r) and the expected power threshold Q p Compare, when d a (r) greater than or equal to Q p , data segment r is the first captured data segment DC0, otherwise wait for data segment r+1, repeat comparison and judgment; when the capture condition is met, start to capture the NL sample point set including the current data segment;

[0015] Step S3, enter the capture period, the first captured data segment is DC0, the second segment is DC1, ..., the last captured data segment is DC NL-1 , capture NL data segments and record and track the capture status of each segment; for the kth captured data segment DC k , calculate the power average d a (k), compare the power average d a (k) and capture the expected power threshold Q c , 20% Rmax, if d a (k) greater than or equal to Q c , record the kth capture state T kNormally 0, if d a (k) is less than Q c , remember T k Exception 1, calculate and record each capture state;

[0016] Among them, starting from the second capture state T1, tracking and judging two consecutive capture states T k and T k+1 , a total of NL-1 judgments are required.

[0017] As a further improvement of the present invention, in step S2, Q p The upper limit is 35% Rmax.

[0018] As a further improvement of the present invention, in step S3, if the capture status is abnormal for two consecutive times, the currently captured data segment will be abandoned, the capture will be stopped and the pre-judgment will be re-entered, and the capture will be maintained in other cases.

[0019] As a further improvement of the present invention, in step S3, Q c The lower limit is 5% Rmax.

[0020] As a further improvement of the present invention, before the captured data is stored in the memory, the ADC sampling data is first written into a depth 2N buffer. The capture trigger command makes the full write pointer valid. If one sample point is written per clock, the pointer always points to the cache address corresponding to the current write count modulo 2N counter value.

[0021] As a further improvement of the present invention, during the prediction period, at least a length N+M+3 cache containing the current length N data segment DP is required. m And M+3 clock calculation delays are introduced, including 1 level of multiplication, 1 level of IQ square addition, M level of data segment accumulation, and 1 level of comparison delay.

[0022] As a further improvement of the present invention, during capture, if the capture rate is 1 sample point per clock, when N≥8, N+M+3 base 2 requires 2N caches B0 and B1, which cache 1 data segment and M+3 state calculation delay write samples respectively; the capture start command makes the capture read pointer valid, which always points to the cache address corresponding to the current read position modulo 2N counter value.

[0023] As a further improvement of the present invention, when the capture starts, the capture read pointer points to the first position of the first capture data segment DC0, which is cached in B1 at position n, denoted as CP n , the capture transfer is completed when the read pointer cycles to the capture read counter of NL-1.

[0024] As a further improvement of the present invention, the write pointer continuously loops to write into the 2N cache during the whole capture process, while the read pointer continuously loops to read from the start to the completion of the capture.

[0025] By means of the above scheme, the present invention has at least the following advantages:

[0026] The present invention utilizes the power average value of an adjustable fixed-length data segment and each forward sliding single sample point to determine the capture start time, and uses the average power state of two temporally adjacent data segments to maintain capture until the end. This processing procedure accurately and efficiently obtains a valid sample point set to save system storage resources. The optimized design of the data segment power average value algorithm saves hardware implementation resources, and the cache space is cyclically used throughout the capture process to improve hardware resource utilization.

[0027] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a schematic diagram of the whole process of capturing the present invention;

[0030] Figure 2 1 is a schematic diagram of a flow chart of calculating the average power value of N=8 data segments in the first embodiment of the present invention;

[0031] Figure 3 is a schematic diagram of the state transition of sampling NL data capture in the first embodiment of the present invention;

[0032] Figure 4 It is a schematic diagram of the relationship between the 2N cache space access pointer and the capture state in the first embodiment of the present invention. DETAILED DESCRIPTION

[0033] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, rather than all the embodiments. The components of the embodiment of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiment of the present invention provided in the drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected embodiment of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0035] Example

[0036] like Figure 1 to Figure 4 As shown,

[0037] An asynchronous signal capture method for improving hardware resource utilization efficiency comprises the following steps in sequence:

[0038] Step S1: After receiving the trigger prediction command, first calculate the data segment DP m Power average, calculate the sum of the squared amplitudes of single sample points in sequence and input the result into the 0th register of the long N sliding data delay. Before each new sample point is input, move each stored data to the adjacent next delay register position, until the squared amplitude of the N-1th sample point is calculated for the first time, and the N squared amplitude sets are obtained for the first time after inputting the sliding data delay 0th register. From this point on, the earliest sample point will be shifted out after each new sample point is input, and the most recent N sets of values ​​will always be retained; then calculate the total power sum of the data segment, and finally right shift log2N=M bits to obtain the average power d a ;

[0039] Among them, single sample point IQs i =a i +b i j;

[0040] The square of the single sample point amplitude P(i) = a i 2 +b i 2 ;

[0041] Long N data segment power average

[0042] d a It is the average power parameter that captures the decision input of the entire process.

[0043] During the prediction period, at least N+M+3 buffers are required to contain the current N-length data segment DP. mAnd M+3 clock calculation delays are introduced, including 1 level of multiplication, 1 level of IQ square addition, M level of data segment accumulation, and 1 level of comparison delay.

[0044] Step S2: At the beginning of the prediction period, after obtaining the first data segment DP0, use the power average d a (0) and the predicted expected power threshold Q p Compare, let Q p is 20% Rmax, Rmax is the maximum square amplitude of a single sample point, if d a (0) Greater than or equal to Q p , then the first data segment DP0 is judged to be valid and capture begins; if d a (0) Less than Q p , wait until the second data segment DP1, use the power average d a (1) and the expected power threshold Q p Compare, if d a (1) Greater than or equal to Q p , determine that the second data segment DP1 is the capture start segment; if d a (r-1) is still less than Q p , waiting for data segment r, using power average d a (r) and the expected power threshold Q p Compare, when d a (r) greater than or equal to Q p , data segment r is the first captured data segment DC0, otherwise wait for data segment r+1, repeat comparison and judgment; when the capture condition is met, start grabbing the NL sample point set including the current data segment.

[0045] In step S2, Q p The upper limit is 35% Rmax.

[0046] Step S3, enter the capture period, the first captured data segment is DC0, the second segment is DC1, ..., the last captured data segment is DC NL-1 , capture NL data segments and record and track the capture status of each segment; for the kth captured data segment DC k , calculate the power average d a (k), compare the power average d a (k) and capture the expected power threshold Q c , 20% Rmax, if d a (k) greater than or equal to Q c , record the kth capture state T k Normally 0, if d a (k) is less than Q c , remember T k Exception 1, calculate and record each capture state;

[0047] Among them, starting from the second capture state T1, tracking and judging two consecutive capture states T k and T k+1 , a total of NL-1 judgments are required.

[0048] In step S3, if the capture status is abnormal for two consecutive times, the currently captured data segment will be abandoned, the capture will be stopped and the prediction will be re-entered. In other cases, the capture will be maintained.

[0049] In step S3, Q c The lower limit is 5% Rmax.

[0050] During capture, if the capture rate is 1 sample point per clock, when N≥8, N+M+3 base 2 requires 2N caches B0 and B1 to cache 1 data segment and M+3 state calculation delay write samples respectively; the capture start command makes the capture read pointer valid, which always points to the cache address corresponding to the current read position modulo 2N counter value.

[0051] When the capture starts, the capture read pointer points to the first position of the first capture data segment DC0, which is cached in B1 at position n, denoted as CP n , the capture transfer is completed when the read pointer cycles to the capture read counter of NL-1.

[0052] Before the captured data is stored in the memory, the ADC sampling data is first written into the depth 2N buffer. The capture trigger command makes the full write pointer valid. If one sample point is written per clock, the pointer always points to the cache address corresponding to the current write count modulo 2N counter value.

[0053] During the capture process, the write pointer continuously loops to write to the 2N cache, while the read pointer continuously loops to read from the start to the completion of the capture.

[0054] The first embodiment of the present invention:

[0055] If the capture ADC sampling length NL baseband samples, the samples are vector IQ signals, N is a base 2 integer, L is a positive integer, the entire capture is as follows Figure 1 It includes two stages: prediction and capture.

[0056] like Figure 1 After receiving the trigger prediction command, the data segment DP is first calculated m Power average. Calculate the sum of the squared amplitudes of the single sample points in sequence and input the result into the 0th register of the long N sliding data delay. Move each stored data to the next adjacent delay register position before each new sample point is input, until the squared amplitude of the N-1th sample point is calculated for the first time. After inputting the 0th register of the sliding data delay, the first N squared amplitude sets are obtained. From this point on, the earliest sample point will be removed after each new sample point is input, and the most recent N sets of values ​​will always be retained. Then calculate the total power sum of the data segment, and finally right shift log2N=M bits to obtain the average power da .

[0057] like Figure 2 As shown:

[0058] Single sample point IQ s i =a i +b i j;

[0059] The square of the single sample point amplitude P(i) = a i 2 +b i 2 ;

[0060] Long N data segment power average d a It is the average power parameter that captures the decision input of the entire process.

[0061] Implement calculation d a The module requires 2 real number multiplications, N-1 additions, and 2N-3 delay registers. Sharing the computing module can save hardware resources.

[0062] At the beginning of the prediction period, after obtaining the first data segment DP0, the power average d a (0) and the predicted expected power threshold Q p Compare, let Q p is 20% Rmax, Rmax is the maximum square amplitude of a single sample point, if d a (0) Greater than or equal to Q p , then the first data segment DP0 is judged to be valid and capture begins; if d a (0) Less than Q p , wait until the second data segment DP1, use the power average d a (1) and the expected power threshold Q p Compare, if d a (1) Greater than or equal to Q p , determine that the second data segment DP1 is the capture start segment; if d a (r-1) is still less than Q p , waiting for data segment r, using power average d a (r) and the expected power threshold Q p Compare, when d a (r) greater than or equal to Q p , data segment r is the first captured data segment DC0, otherwise wait for data segment r+1 and repeat the comparison and judgment.

[0063] Q p The upper limit can be set within the range of 35% Rmax. The higher it is, the greater the average signal amplitude is, the more accurate the starting point of the captured data is, the lower the probability of misjudgment is, but the probability of missed judgment is higher.

[0064] When the capture condition is met, the NL sample point set including the current data segment is captured.

[0065] Entering the capture period, the first captured data segment is DC0, the second segment is DC1, ..., and the last captured data segment is DC NL-1 , capture NL data segments and record and track the capture status of each segment. For the kth captured data segment DC k ,like Figure 2 Calculate the power average d a (k), compare the power average d a (k) and capture the expected power threshold Q c , 20%Rmax, if d a (k) greater than or equal to Q c , record the kth capture state T k Normally 0, if d a (k) is less than Q c , remember T k Exception 1, calculate and record each capture state.

[0066] Starting from the second capture state T1, the tracking judgment is two consecutive capture states T k and T k+1 , a total of NL-1 judgments are required.

[0067] like Figure 3 As shown in the figure, if the capture status is abnormal for two consecutive times, the currently captured data segment will be abandoned, the capture will be stopped and the prediction will be re-entered. In other cases, the capture will be maintained. c The lower limit can be set within a range of up to 5% Rmax. The lower the limit, the smaller the average signal amplitude, the higher the capture efficiency, the shorter the capture cycle, and the better the signal integrity.

[0068] Before the captured data is stored in the memory, the ADC sampling data is first written into the depth 2N buffer. The capture trigger command makes the full write pointer valid. If one sample point is written per clock, the pointer always points to the cache address corresponding to the current write count modulo 2N counter value.

[0069] During the prediction period, at least N+M+3 buffers are required to contain the current N-length data segment DP. m And M+3 clock calculation delays are introduced, including 1 level of multiplication, 1 level of IQ square addition, M level of data segment accumulation, and 1 level of comparison delay.

[0070] During capture, if the capture rate is 1 sample per clock, when N≥8, N+M+3 base 2 requires 2N caches B0 and B1, caching 1 data segment and M+3 state calculation delay write samples respectively. The capture start command makes the capture read pointer valid, which always points to the cache address corresponding to the current read position modulo 2N counter value. For example, when starting capture, the capture read pointer points to the first position of the first capture data segment DC0, which is cached in B1 at position n and recorded as CP n The capture transfer is completed when the read pointer cycles to the capture read counter of NL-1.

[0071] like Figure 4 During the whole process of capture, the write pointer continuously writes to the 2N cache in a loop, while the read pointer continuously reads in a loop from the start to the completion of capture. In this way, the shared cache space saves hardware resources and has a very high utilization rate.

[0072] The present invention proposes an asynchronous signal capture method for improving the efficiency of hardware resource utilization after ADC sampling of radio frequency measurement. The power average value of a data segment with an adjustable fixed length and a single sample point sliding forward each time are used to determine the capture start time, and the average power state of two temporally adjacent data segments is used to maintain the capture until the end. This processing process accurately and efficiently obtains a valid sample point set to save system storage resources, the data segment power average value algorithm is optimized and designed to save hardware implementation resources, and the cache space is cyclically used throughout the capture process to improve the utilization of hardware resources.

[0073] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly referring to the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0074] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection, it can be a mechanical connection, it can be an electrical connection, it can be a direct connection, it can be indirectly connected through an intermediate medium, and it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. An asynchronous signal capture method for improving hardware resource utilization efficiency, characterized in that: The following steps are included in sequence: Step S1: After receiving the trigger prediction command, first calculate the data segment DP m Power averaging, calculate the sum of the squared amplitudes of single sample points in sequence and input the result into the 0th register of the long N sliding data delay. Each stored data is moved to the next adjacent delay register position before each new sample point is input, until the squared amplitude of the N-1th sample point is calculated for the first time, and the N squared amplitude sets are obtained for the first time after inputting the sliding data delay 0th register. From this point on, the earliest sample point will be removed after each new sample point is input, and the most recent N sets of values ​​will always be retained; Then calculate the total power sum of the data segment, and finally right shift log2N=M bits to get the average power d a ; Among them, single sample point IQ s i =a i +b i j; The square of the single sample point amplitude P(i) = a i 2 +b i 2 ; Long N data segment power average d a It is the average power parameter that captures the decision input of the whole process; Step S2: At the beginning of the prediction period, after obtaining the first data segment DP0, use the power average d a (0) and the predicted expected power threshold Q p Compare, let Q p is 20% Rmax, Rmax is the maximum square amplitude of a single sample point, if d a (0) Greater than or equal to Q p , then the first data segment DP0 is judged to be valid and capture begins; if d a (0) Less than Q p , wait until the second data segment DP1, use the power average d a (1) and the expected power threshold Q p Compare, if d a (1) Greater than or equal to Q p , determine that the second data segment DP1 is the capture start segment; if d a (r-1) is still less than Q p , waiting for data segment r, using power average d a (r) and the expected power threshold Q p Compare, when d a (r) greater than or equal to Q p , data segment r is the first captured data segment DC0, otherwise wait for data segment r+1, repeat comparison and judgment; when the capture condition is met, start to capture the NL sample point set including the current data segment; Step S3, enter the capture period, the first captured data segment is DC0, the second segment is DC1, ..., the last captured data segment is DC NL-1 , capture NL data segments and record and track the capture status of each segment; for the kth captured data segment DC k , calculate the power average d a (k), compare the power average d a (k) and capture the expected power threshold Q c , 20% Rmax, if d a (k) greater than or equal to Q c , record the kth capture state T k Normally 0, if d a (k) is less than Q c , remember T k Exception 1, calculate and record each capture state; Among them, starting from the second capture state T1, tracking and judging two consecutive capture states T k and T k+1 , a total of NL-1 judgments are required.

2. The asynchronous signal capture method for improving hardware resource utilization efficiency as claimed in claim 1, characterized in that: In step S2, Q p The upper limit is 35% Rmax.

3. The asynchronous signal capture method for improving hardware resource utilization efficiency as claimed in claim 1, characterized in that: In step S3, if the capture status is abnormal for two consecutive times, the currently captured data segment will be abandoned, the capture will be stopped and the pre-judgment will be re-entered. In other cases, the capture will be maintained.

4. The asynchronous signal capture method for improving hardware resource utilization efficiency according to claim 1, characterized in that: In step S3, Q c The lower limit is 5% Rmax.

5. The asynchronous signal capture method for improving hardware resource utilization efficiency as claimed in claim 1, characterized in that: Before the captured data is stored in the memory, the ADC sampling data is first written into the depth 2N buffer. The capture trigger command makes the full write pointer valid. If one sample point is written per clock, the pointer always points to the cache address corresponding to the current write count modulo 2N counter value.

6. The asynchronous signal capture method for improving hardware resource utilization efficiency as claimed in claim 1, characterized in that: During the prediction period, at least N+M+3 buffers are required to contain the current N-length data segment DP. m And M+3 clock calculation delays are introduced, including 1 level of multiplication, 1 level of IQ square addition, M level of data segment accumulation, and 1 level of comparison delay.

7. The asynchronous signal capture method for improving hardware resource utilization efficiency as claimed in claim 1, characterized in that: During capture, if the capture rate is 1 sample point per clock, when N≥8, N+M+3 base 2 requires 2N caches B0 and B1 to cache 1 data segment and M+3 state calculation delay write samples respectively; the capture start command makes the capture read pointer valid, which always points to the cache address corresponding to the current read position modulo 2N counter value.

8. The asynchronous signal capture method for improving hardware resource utilization efficiency as claimed in claim 7, characterized in that: When the capture starts, the capture read pointer points to the first position of the first capture data segment DC0, which is cached in B1 at position n, denoted as CP n , the capture transfer is completed when the read pointer cycles to the capture read counter of NL-1.

9. The asynchronous signal capture method for improving hardware resource utilization efficiency as claimed in claim 1, characterized in that: During the capture process, the write pointer continuously loops to write to the 2N cache, while the read pointer continuously loops to read from the start to the completion of the capture.

Images