Asynchronous micro-pipeline structure based on'sending-relay-receiving 'structure

Abstract

The invention discloses an asynchronous micro-pipeline structure based on a'sending-relaying-receiving 'structure, which comprises an asynchronous control component, the asynchronous control component comprises one or more of a sender (Sender), a relay (Relay), a receiver (Receiver) or a relay permission (PmtRelay), and the Sender comprises a trigger, a phase inverter and a delay module; the Relay is composed of an exclusive-OR gate, an XNOR gate, an AND gate, a D trigger, an inverter and a delay module, and is realized based on a Click asynchronous controller; the Receiver comprises a trigger; according to the PmtRelay, a pmt control mechanism is added in a Click controller; the asynchronous control assembly is one of a Fifo, a PmtFifo, a Selector, a Splitter, a WaitMerge and a MutexMerge, and an asynchronous micro pipeline structure is constructed by one or more of the asynchronous control assemblies. According to the asynchronous micro-pipeline structure, fine-grained control is provided, event flow is used for driving control, a unified control chain template is adopted, the design is more direct and simple, the structure pays more attention to delay and generation conditions of event signals, and the design process is more flexible and efficient.

Description

Technical Field

[0001] The invention belongs to the technical field of asynchronous control circuits, and in particular relates to an asynchronous micro-pipeline structure based on a "send-relay-receive" structure. Background Art

[0002] The asynchronous micro-pipeline structure is the core of building asynchronous circuits. The traditional micro-pipeline is implemented with a coarse-grained static data flow structure. The design method based on the static data flow structure adopts a coarse-grained control structure. Designers only need to master a small number of event-driven details and design event-driven circuits completely from the perspective of control mode. This structure can better distinguish between control paths and data paths, ensure the consistency of data in the entire circuit, and avoid data conflicts or errors. However, the pipeline of the coarse-grained control structure needs to be refined many times according to the function and level, which makes it difficult to describe the event mechanism from the control aspect, and some structures need to be customized manually; and the pipeline of this structure uses a large number of C units as the basic structure. In large-scale digital design, the use of C units increases the difficulty of circuit verification and introduces additional obstacles to large-scale design; in addition, when using the coarse-grained static data flow structure for engineering practice, additional customized design tools are required, and the design process is not compatible with the existing mainstream design process.

[0003] Based on the static micro-pipeline, some studies have proposed a more fine-grained "chain-link" structural model, which combines various asynchronous controllers and necessary delays. The chain structure is responsible for event transmission and delay within the controlled module, while the link structure is responsible for event exchange and functional module management. Unlike the static data flow structure at the macro scale, the "chain-link" structure focuses on the dynamic driving mechanism of events rather than the abstract control method, which is more in line with the working principle of event-driven design. This method can adjust the implementation of the micro-pipeline structure from a micro perspective and is suitable for the development of high-speed asynchronous circuits. However, the development process of this structure requires mastering a large number of asynchronous controller principles and details, and involves the transformation and division of asynchronous control circuits. It is a difficult task to develop a micro-pipeline based on the "chain-link" structure. Summary of the invention

[0004] In view of the problems existing in the above-mentioned background technology, the object of the present invention is to provide an asynchronous micro-pipeline structure based on a "send-relay-receive" structure.

[0005] In order to achieve the above object, the present invention adopts the following technical solution: The present invention provides an asynchronous micro-pipeline structure based on a "send-relay-receive" structure, including an asynchronous control component, wherein the asynchronous control component includes one or more of a sender (Sender), a relay (Relay), a receiver (Receiver) or a permitted relay (PmtRelay), wherein: Sender: includes a trigger, an inverter and a delay module. When receiving the drive pulse signal i_drive, Sender flips the output level signal, and the input pulse signal i_free is delayed by the delay module and output as o_free. Relay: It is composed of XOR gate, XNOR gate, AND gate, D flip-flop, inverter and delay module, and is implemented based on Click asynchronous controller. Receiver: includes a trigger, which is activated when receiving the lower-level pulse signal i_freeNext; Permit relay (PmtRelay): Add a permission (pmt) control mechanism in the Click controller, connect the output end of the Click controller to the pmt control signal, and control the output level of the trigger to flip after the trigger pulse signal reaches the trigger end of the trigger; The asynchronous control component includes one of Fifo, PmtFifo, Selector, Splitter, WaitMerge, and MutexMerge. An asynchronous micro-pipeline structure is constructed by one or more of the asynchronous control components. The asynchronous control chain composed of the asynchronous control components is as follows: (1) Asynchronous control chain composed of Fifo: an input control chain and an output control chain. After the signals corresponding to the events and data pass through the input control chain, multiple pulse signals are generated during the transmission process to trigger the combinational logic circuit. The signals corresponding to the events and data are output by the output control chain. A delay module is added to the asynchronous control chain. (2) The asynchronous control chain composed of PmtFifo: an input control chain and an output control chain. After the signals corresponding to the events and data pass through the input control chain, the transmission is controlled by the permission mechanism. During the transmission process, a pulse signal is generated to trigger the combinational logic circuit. The signals corresponding to the events and data are output by the output control chain. A delay module is added to the asynchronous control chain. (3) Asynchronous control chain composed of Selectors: an input control chain and two branch chains. The signals corresponding to events and data are input by the input control chain, and after being transmitted by the branch chain, the signals corresponding to events and data of one branch chain are selected for output. A delay module is added to the asynchronous control chain. (4) Asynchronous control chain composed of Splitters: one input control chain and multiple branch output control chains. The signals corresponding to events and data are input by the input control chain, and the signals corresponding to multiple events and data are output by multiple branch output control chains respectively. (5) Asynchronous control chain composed of WaitMerge: multiple input control chains and one output control chain. Signals corresponding to multiple events and data are input by multiple input control chains respectively, and are output by one output control chain after merging. A delay module is added to the asynchronous control chain. (6) Asynchronous control chain composed of MutexMerge: multiple input control chains and one output control chain. The signals corresponding to multiple events and data are input by multiple input control chains respectively, and the signals corresponding to the events and data of one valid input are identified and output by the output control chain.

[0006] Furthermore, the Fifo includes: Sender, Relay, Receiver; the PmtFifo includes: Sender, PmtRelay, Receiver, and AND gate; the Selector includes: Sender, Relay, Receiver, AND gate, and NOT gate; the Splitter includes: Contap, AND gate, OR gate, and NOR gate; the WaitMerge includes: Contap, AND gate, OR gate; the MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; the Contap uses a Sender that does not generate a free signal, and Contap includes a trigger and an inverter for converting a pulse signal into a level signal.

[0007] Furthermore, in the Fifo, the Sender receives the driving pulse signal drive from the upper module and sends it to the Relay, which generates multiple pulse signals fire in sequence through multiple Relays to trigger the combinational logic circuit. When all the pulse signals fire are excited, they are sent to the Receiver to generate the lower-level driving pulse signal drive, which is transmitted to the lower-level module; at the same time, the Fifo returns a free signal to the upper-level module, indicating that the module at this level has completed the operation and can receive a new driving pulse signal.

[0008] Furthermore, in the PmtFifo, after the Sender receives the driving pulse signal drive from the upper module, it sends it to PmtRelay. After waiting for the permission control mechanism to change the state, PmtRelay generates a pulse signal fire to trigger the combinational logic circuit. When the pulse signal fire is excited, it is sent to the Receiver to generate the lower-level driving pulse signal drive, which is transmitted to the lower-level module. At the same time, PmtFifo returns a free signal to the upper-level module, indicating that the module at this level has completed the operation and can receive a new driving pulse signal.

[0009] Furthermore, in the Selector, after the Sender receives the driving pulse signal drive from the upper module, it is delayed by the delay module and output to the Relay. The Relay generates a pulse fire, which is transmitted to the two AND gates after being delayed by the delay module. One of the two AND gates is turned on and generates a lower-level driving pulse signal drive. The output data controls the trigger in the Receiver to collect data, thereby triggering the entire branch selection process.

[0010] Furthermore, in the Splitter, when events and data trigger the Splitter through the driving pulse signal drive, the Splitter copies and distributes the events and data to multiple branches, and the multiple branches process the events and data simultaneously. After all branches complete the processing and return a reply signal, the Splitter sends a free signal to the superior module through the free signal, waiting to receive the next event.

[0011] Furthermore, in the WaitMerge, after receiving the drive pulse signals drive and corresponding data data from multiple upper-level modules, WaitMerge merges the multiple drive pulse signals into a single drive pulse signal and transmits it to the lower-level module, and at the same time splices the multiple data into a single data stream and transmits it to the lower-level module.

[0012] Furthermore, in the MutexMerge, after receiving the drive pulse signals drive and corresponding data data of multiple upper-level modules, the result of the phase-OR of the drive pulse signals drive of the multiple upper-level modules is used as a valid input signal, and the events and data corresponding to the valid input signal are transmitted to the lower-level modules; at the same time, the drive pulse signals drive of the multiple upper-level modules respectively control Contap, and the Contap output signal is used as the selection signal of the selector, and one data output is selected by the selection signal. After all inputs are processed, MutexMerge sends a free signal to the upper-level module and waits to receive new data.

[0013] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects: (1) The asynchronous micro-pipeline structure based on the "send-relay-receive" structure proposed in the present invention provides fine-grained control, making the mechanism for describing events from the control level more intuitive, and using the flow of events to drive control. A unified control chain template is adopted, which is more straightforward and simple in design. (2) Compared with the coarse-grained static data flow structure that uses a large number of C units, the repeater of the present invention is implemented based on the Click asynchronous controller, and the Click unit is used to replace the C unit of the coarse-grained control structure. The Click unit will generate a trigger edge while transmitting the handshake signal. This asynchronous control method is closer to synchronous control, which is conducive to the verification of large-scale circuit designs; (3) The present invention uses basic logic units to build an asynchronous control chain composed of asynchronous control components, which is fully compatible with the synchronous design process in the design. This greatly alleviates the disadvantage of asynchronous design lacking a unique EDA, and makes the design process more standardized, reducing the dependence on customized design tools; (4) Compared with the "chain-link" structure that requires mastering a large number of asynchronous controller principles and details, the asynchronous micro-pipeline structure proposed in the present invention simplifies the design process. Designers only need to master a small number of event-driven details and design event-driven circuits entirely from the perspective of control methods, which reduces the learning difficulty for engineers and enables them to understand and apply these structures more quickly. In addition, the asynchronous micro-pipeline structure of the present invention pays more attention to the delay and generation conditions of event signals, making the design process more flexible and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of the structure of a Sender provided by an embodiment of the present invention; Figure 2 is a schematic diagram of the structure of the Relay provided in an embodiment of the present invention; Figure 3 is a schematic diagram of the structure of a Receiver provided in an embodiment of the present invention; Figure 4 is a schematic diagram of the structure of PmtRelay provided in an embodiment of the present invention; Figure 5 It is a schematic diagram of the structure of Fifo provided by an embodiment of the present invention; Figure 6 is a schematic diagram of the structure of PmtFifo provided by an embodiment of the present invention; Figure 7 is a schematic diagram of the structure of the Selector provided in an embodiment of the present invention; Figure 8 is a schematic diagram of the structure of a Splitter provided by an embodiment of the present invention; Fig. 9is a schematic diagram of the structure of WaitMerge provided by an embodiment of the present invention; Fig.10 It is a schematic diagram of the structure of MutexMerge provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0016] The present invention proposes a coarse-grained asynchronous micro-pipeline structure based on the "send-relay-receive" structure. The structure granularity is between the static data flow and the "chain-link" structure, focusing on the delay and generation conditions of event signals, making the design process more flexible and efficient. The structure includes one or more of four basic structures: sender (Sender), relay (Relay), receiver (Receiver) and allowed relay (PmtRelay). The core event-driven mechanism is expressed by these four basic structures, and the driving logic circuit of the event signal is expressed by Boolean logic.

[0017] Sender: The structure is as follows Figure 1 As shown, it includes a trigger, an inverter and a delay module, which are responsible for starting the asynchronous control path to ensure reliable data transmission. When the drive pulse signal i_drive is received, Sender flips the output level signal, and the input pulse signal i_free is output as o_free after being delayed by the delay module. The specific process is: at the initial moment, the output port outR is low level, and the D end of the trigger is high level. When the pulse signal i_free arrives, the data at the D end of the trigger is copied to the Q end, the output port outR changes to a high level, and the D end changes to a low level.

[0018] Relay: The structure is as follows Figure 2As shown, it is composed of an XOR gate, an XOR gate, an AND gate, a D flip-flop, an inverter, and a delay module, and is implemented based on a Click asynchronous controller. The Click controller interacts with the outside through two inputs and three outputs, where the input includes inR and outA signals, and the output includes inA, outR, and pulse fire. Pulse fire is responsible for controlling the trigger to collect data. The Click controller strictly manages data flow through pulse fire, and the remaining four signals are used to interact with adjacent Click controllers. In the initial state, all input and output level signals remain at a low level. The XOR operation of inR and inA results in inRA being a low level, and the XOR operation of outA and outR results in outRA being a high level. When inRA and outRA perform an AND operation, they continue to maintain a low level, so pulse fire also remains at a low level. When inR flips, the controller starts, inRA changes from a low level to a high level, and pulse fire also changes from a low level to a high level. At the same time, the trigger copies the data at the D end to the Q end. After a delay unit, the level signals of inA and outR will also be pulled high, and the next-level Click request signal and the previous-level Click response signal will be generated at the same time. Subsequently, the pulse fire is pulled down from the high level to generate a complete pulse signal, and the data is transmitted smoothly under this control. When the next level Click feedback outA, the controller is ready to receive the next round of event triggers. This is also the handshake mechanism between the two-level controllers, thereby ensuring the binding transmission of events and data.

[0019] Receiver: The structure is as follows Figure 3 As shown, it includes a trigger. When receiving the lower-level pulse signal i_freeNext, the trigger is activated, and the data at the D end of the trigger is copied to the Q end, that is, inR is passed to inA, to achieve data synchronization and ensure data consistency in the pipeline. This structure is usually located at the end of the micropipeline and is responsible for resetting the entire asynchronous control path.

[0020] PmtRelay: structure is as follows Figure 4 As shown in the figure, a permission (pmt) control mechanism is added to the Click controller to achieve more sophisticated data transmission control. The output of the Click controller is connected to the pmt control signal. When pmt is low level 0, the pulse fire cannot reach the trigger end of the trigger. When pmt is high level 1, the pulse fire reaches the trigger end of the trigger and controls the output level of the trigger to flip. In addition, the behavior of the two inputs inR and outA and the two outputs inA and outR is consistent with Click.

[0021] A variety of complex asynchronous control components are constructed with the help of four basic structures: Fifo, PmtFifo, Selector, Splitter, WaitMerge, and MutexMerge. An asynchronous micro-pipeline structure is built with one or more asynchronous control components, which will form an asynchronous control chain to complete various complex control tasks.

[0022] The asynchronous control chain composed of Fifo: an input control chain and an output control chain. After the signals corresponding to the events and data pass through the input control chain, multiple pulse signals are generated during the transmission process to trigger the combinational logic circuit, thereby controlling the flow of data in the pipeline; the signals corresponding to the events and data are output by the output control chain; a delay module is added to the asynchronous control chain.

[0023] The structure of Fifo is as follows Figure 5 As shown, it includes: Sender, multiple Relays, and Receiver. After receiving the driving pulse signal i_drive from the upper module, the Sender sends it to n Relays, which arrive at Relay 0, Relay 1...Relay n-1 in turn, and then the signals o_fire_0, o_fire_1...o_fire_n-1 are generated in turn to trigger the combinational logic circuit. After o_fire_n-1 is generated, a lower-level driving pulse signal o_driveNext is generated by a delay module, and then a pulse signal o_free is generated through another delay module, and the lower-level pulse signal i_freeNext is transmitted, indicating that the module at this level has completed the operation and can receive a new driving pulse signal. Rst is the reset signal of the module, which returns the module to the initial state. Fifo can realize the generation of any number of pulse fires to meet different data flow control requirements, and these driving pulses have a strict sequence in timing. The design of Fifo maps event transmission to the specific control level of the circuit, making the asynchronous circuit design based on it more logically clear and easy to understand and maintain.

[0024] The asynchronous control chain composed of PmtFifo: an input control chain and an output control chain. After the signals corresponding to the events and data pass through the input control chain, the transmission is controlled by the permission mechanism. A pulse signal is generated during the transmission process to trigger the combinational logic circuit. The signals corresponding to the events and data are output by the output control chain. A delay module is added to the asynchronous control chain.

[0025] The structure of PmtFifo is as follows Figure 6As shown, it includes: Sender, PmtRelay, and Receiver. After receiving the drive pulse signal i_drive from the upper module, Sender sends it to PmtRelay0, waiting for the input permission signal pmt to flip, and then generates the o_fire signal to trigger the combinational logic circuit. After o_fire is generated, a delay module generates a lower-level drive pulse signal o_driveNext, and then passes through a delay module. The pulse signal o_free is generated and transmits the lower-level pulse signal i_freeNext, indicating that the module at this level has completed the operation and can receive a new drive pulse signal. Rst is the reset signal of the module, which returns the module to the initial state. PmtFifo adds an permission control mechanism based on Fifo to achieve more sophisticated signal reception, processing and transmission.

[0026] The asynchronous control chain consists of Selector: an input control chain and two branch chains. The signals corresponding to the events and data are input by the input control chain, and after being transmitted by the branch chain, the signals corresponding to the events and data of one branch chain are selected for output. A delay module is added to the asynchronous control chain.

[0027] The structure of Selector is as follows Figure 7As shown, it includes: Sender, Relay, Receiver, AND gate, and NOT gate. After Sender receives the driving pulse signal i_drive from the upper module, it is delayed by the delay module and output to Relay0. The output data controls the trigger in the Receiver to collect data, thereby triggering the entire branch selection process. Relay0 generates a signal o_fire_0, which is delayed by the delay module and transmitted to two AND gates. The two AND gates generate the lower-level driving pulse signals o_dirveNext0 and o_dirveNext1 respectively. According to the selection bit in the input data i_data_x, only one of the two AND gates will be turned on, that is, o_dirveNext0 or o_dirveNext1 generates a pulse, and outputs data o_data0_y or o_data1_y. After the o_fire_0 signal is generated, the pulse signal o_free is generated through the delay module, and the lower-level pulse signals i_freeNext0 and i_freeNext1 are transmitted, indicating that the module at this level has completed the operation. rst is the reset signal of the module, which returns the module to the initial state. As a key control bit, the branch signal dynamically indicates which branch the data and signal should flow to. The Selector uses logical AND operations to ensure that the output drive pulse signal and output data of the correct branch are only valid when the branch signal is at a high level; conversely, the output drive pulse signal of the wrong branch is only valid when the branch signal is at a low level. The structure of the Selector allows designers to flexibly determine the data transmission path based on the input branch signal, while the data bound to the branch event is customized by the user, allowing the Selector to adapt to a variety of different data processing requirements, increasing the flexibility and adaptability of the design.

[0028] The asynchronous control chain composed of Splitters: one input control chain and multiple branch output control chains. The signals corresponding to events and data are input by the input control chain, and divided into multiple signals corresponding to events and data, which are output by multiple branch output control chains respectively.

[0029] The structure of Splitter is as follows Figure 8As shown, it includes: Contap, AND gate, OR gate, and NOR gate. Contap uses a Sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal. Splitter receives the drive pulse signal i_drive and the data i_data_x. i_drive is directly connected to two output signals o_driveNext0 and o_driveNext1. At the same time, the input data i_data_x is split into two output data o_data0_y and o_data1_z. i_drive pulls the signal high through Contap, and i_freeNext0 and i_freeNext1 pull the signal low through Contap to control the generation of the signal o_free, and then transmit the lower-level pulse signals i_freeNext0 and i_freeNext1. Rst is the reset signal of the module, which returns the module to the initial state. Splitter copies and distributes events and data to multiple branches. Multiple branches process events and data at the same time, allowing events to be processed in parallel in multiple branches, increasing the parallelism and throughput of the system. After all branches complete processing and return reply signals, the Splitter sends a free signal to the superior module through the free signal, waiting to receive the next event. This handshake mechanism ensures the orderly flow of events in the Splitter, avoiding data conflicts and processing errors, especially in scenarios where a single event needs to be distributed to multiple processing units for parallel processing. It not only improves the efficiency of event processing, but also allows the system to perform different operations on different branches, thereby increasing the flexibility and scalability of the system.

[0030] The asynchronous control chain composed of WaitMerge: multiple input control chains and one output control chain. The signals corresponding to multiple events and data are input by multiple input control chains respectively, and are output by one output control chain after being merged. A delay module is added to the asynchronous control chain.

[0031] The structure of WaitMerge is as follows Fig. 9As shown, it includes: Contap, AND gate, and OR gate. Contap uses a Sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal. After WaitMerge receives the driving pulse signals and corresponding data of multiple upper modules, WaitMerge merges the multiple driving pulse signals into a single driving pulse signal and transmits it to the lower module, indicating that it can safely process the spliced ​​data. At the same time, multiple data are spliced ​​into a single data stream and transmitted to the lower module. This spliced ​​data stream contains all the data provided by the upper modules. These data are merged together to form a complete data set so that the lower module can perform further processing or calculation. The two input signals i_drive0 and i_drive1 control the two Contaps to pull their output signals high respectively. Only when i_drive0 and i_drive1 arrive, the output signal o_driveNext is generated. o_driveNext pulls the signal low through Contap to control the generation of the signal o_free. The lower pulse signal i_freeNext restores the two Contap output signals to the initial state. The input data i_data0_x and i_data1_x are concatenated into new data as the output of o_data_y. rst is the reset signal of the module, which returns the module to its initial state. WaitMerge plays the role of data aggregation and control synchronization in the asynchronous micro-pipeline, allowing the lower-level modules to efficiently process the merged data stream, thereby improving the data processing capability and efficiency of the entire system.

[0032] MutexMerge is an asynchronous control chain: multiple input control chains and one output control chain. Signals corresponding to multiple events and data are input by multiple input control chains respectively, and the signals corresponding to the events and data of one valid input are identified and output by the output control chain. This design ensures that even if there are multiple input ports, only one input port carries events and data to the lower-level module each time it is processed, thus avoiding data conflicts.

[0033] The structure of MutexMerge is as follows Fig.10As shown, it includes: Contap, AND gate, OR gate, and multiplexer. Contap uses a sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal. After MutexMerge receives the driving pulse signals and corresponding data of multiple upper-level modules, the result of the OR of the driving pulse signals of multiple upper-level modules is used as a valid input signal, and the events and data corresponding to the valid input signal are passed to the lower-level module. The result of the OR of the two input signals i_drive0 and i_drive1 is used as the output result of o_driveNext; at the same time, i_drive0 and i_drive1 control the two Contaps respectively, so that their output signals are used as the selection signals of the selector, so as to select one of the two input data i_data0_x and i_data1_y as the output result of i_data0_z. After all inputs are processed, MutexMerge sends an o_free signal to the upper-level module, and the lower-level pulse signal i_freeNext restores the two Contap output signals to the initial state. rst is the reset signal of the module, which returns the module to the initial state. MutexMerge simplifies the management of multiple inputs by ensuring that only one path of data and events is output at a time, improving the stability and efficiency of the system. It is particularly suitable for scenarios that require ensuring data order and mutually exclusive access.

[0034] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An asynchronous micro-pipeline structure based on a "send-relay-receive" structure, characterized in that: The asynchronous control component includes one or more of Sender, Relay, Receiver, and PmtRelay, wherein: Sender: includes a trigger, an inverter and a delay module. When receiving the drive pulse signal i_drive, Sender flips the output level signal, and the input pulse signal i_free is delayed by the delay module and output as o_free. Relay: It consists of XOR gate, XNOR gate, AND gate, D flip-flop, inverter, and delay module, and is implemented based on Click asynchronous controller; Receiver: includes a trigger, which is activated when receiving the lower-level pulse signal i_freeNext; PmtRelay: Add a pmt control mechanism to the Click controller, connect the output of the Click controller to the pmt control signal, and control the output level of the trigger to flip after the trigger pulse signal reaches the trigger end of the trigger; The asynchronous control component is one of Fifo, PmtFifo, Selector, Splitter, WaitMerge, and MutexMerge. An asynchronous micro-pipeline structure is constructed by one or more of the asynchronous control components. The asynchronous control chain composed of the asynchronous control components is as follows: (1) Asynchronous control chain composed of Fifo: an input control chain and an output control chain. After the signals corresponding to the events and data pass through the input control chain, multiple pulse signals are generated during the transmission process to trigger the combinational logic circuit. The signals corresponding to the events and data are output by the output control chain. A delay module is added to the asynchronous control chain. (2) The asynchronous control chain composed of PmtFifo: an input control chain and an output control chain. After the signals corresponding to the events and data pass through the input control chain, the transmission is controlled by the permission mechanism. During the transmission process, a pulse signal is generated to trigger the combinational logic circuit. The signals corresponding to the events and data are output by the output control chain. A delay module is added to the asynchronous control chain. (3) Asynchronous control chain composed of Selectors: an input control chain and two branch chains. The signals corresponding to events and data are input by the input control chain, and after being transmitted by the branch chain, the signals corresponding to events and data of one branch chain are selected for output. A delay module is added to the asynchronous control chain. (4) Asynchronous control chain composed of Splitters: one input control chain and multiple branch output control chains. The signals corresponding to events and data are input by the input control chain, and the signals corresponding to multiple events and data are output by multiple branch output control chains respectively. (5) Asynchronous control chain composed of WaitMerge: multiple input control chains and one output control chain. Signals corresponding to multiple events and data are input by multiple input control chains respectively, and are output by one output control chain after merging. A delay module is added to the asynchronous control chain. (6) Asynchronous control chain composed of MutexMerge: multiple input control chains and one output control chain. The signals corresponding to multiple events and data are input by multiple input control chains respectively, and the signals corresponding to the events and data of one valid input are identified and output by the output control chain.

2. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 1, characterized in that: The Fifo includes: Sender, Relay, Receiver; the PmtFifo includes: Sender, PmtRelay, Receiver, and AND gate; the Selector includes: Sender, Relay, Receiver, AND gate, and NOT gate; the Splitter includes: Contap, AND gate, OR gate, and NOR gate; the WaitMerge includes: Contap, AND gate, OR gate; the MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; the Contap uses a Sender that does not generate a free signal, and the Contap includes a trigger and an inverter for converting a pulse signal into a level signal.

3. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 2, characterized in that: In the Fifo, the Sender receives the driving pulse signal drive from the upper module and sends it to the Relay, which generates multiple pulse signals fire in sequence through multiple Relays to trigger the combinational logic circuit. When all the pulse signals fire are excited, they are sent to the Receiver to generate the lower-level driving pulse signal drive, which is transmitted to the lower-level module; at the same time, the Fifo returns a free signal to the upper-level module, indicating that the module at this level has completed the operation and is waiting to receive a new driving pulse signal.

4. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 2, characterized in that: In the PmtFifo, after the Sender receives the driving pulse signal drive from the upper module, it sends it to PmtRelay. After waiting for the permission control mechanism to change the state, PmtRelay generates a pulse signal fire to trigger the combinational logic circuit. When the pulse signal fire is excited, it is sent to the Receiver to generate the lower-level driving pulse signal drive, which is transmitted to the lower-level module. At the same time, PmtFifo returns a free signal to the upper-level module, indicating that the module at this level has completed the operation and is waiting to receive a new driving pulse signal.

5. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 2, characterized in that: In the Selector, after the Sender receives the driving pulse signal drive from the upper module, it is output to the Relay after being delayed by the delay module. The Relay generates a pulse fire, which is transmitted to the two AND gates after being delayed by the delay module. One of the two AND gates is turned on and generates a lower-level driving pulse signal drive. The output data controls the trigger in the Receiver to collect data, thereby triggering the entire branch selection process.

6. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 2, characterized in that: In the Splitter, when events and data trigger the Splitter through the driving pulse signal drive, the Splitter copies and distributes the events and data to multiple branches. Multiple branches process events and data simultaneously. After all branches complete processing and return reply signals, the Splitter sends a free signal to the superior module through the free signal, waiting to receive the next event.

7. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 2, characterized in that: In the WaitMerge, after receiving the drive pulse signals drive and corresponding data data from multiple upper modules, WaitMerge merges the multiple drive pulse signals into a single drive pulse signal and transmits it to the lower module, and at the same time splices the multiple data into a single data stream and transmits it to the lower module.

8. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 2, characterized in that: In the MutexMerge, after receiving the drive pulse signals drive and corresponding data data of multiple upper-level modules, the result of the phase-OR of the drive pulse signals drive of the multiple upper-level modules is used as a valid input signal, and the events and data corresponding to the valid input signal are transmitted to the lower-level modules; at the same time, the drive pulse signals drive of the multiple upper-level modules respectively control Contap, and the Contap output signal is used as the selection signal of the selector. One data output is selected by the selection signal. After all inputs are processed, MutexMerge sends a free signal to the upper-level module and waits for receiving new data.

Images