Reset constraint determination method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a reset constraint determination method and system, a storage medium and electronic equipment, and the method comprises the steps: determining reset definition information according to an RTL code of a target chip, and the reset definition information comprises a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a level of the reset signal corresponding to the RCU; an effective level of the reset signal; obtaining a reset sequence of each level RCU in the target chip and a working mode of the target chip; and according to the reset definition information, the reset sequence and the working mode, determining a reset constraint for cross-reset-domain RDC check of the target chip. The technical problems of incomplete content and low efficiency of a reset constraint determination scheme in related technologies are solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular, to a method, device, storage medium and electronic device for determining a reset constraint. Background Art

[0002] The chip's system on chip (SoC) contains multiple reset control unit (RCU) modules, which are the main inputs of the chip's reset domain crossing (RDC) check based on the register-transfer level (RTL) code and reset constraints. However, in the prior art, the entire RDC check process is manually completed by designers, which is inefficient, and the reset structure, RTL code, and reset constraints are more likely to be inconsistent or missing, which is prone to errors.

[0003] Regarding the scheme for determining the reset constraint in the related art, there are technical problems such as incomplete content and low efficiency, and no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present application provide a method, device, storage medium and electronic device for determining a reset constraint, so as to at least solve the technical problems of incomplete content and low efficiency in the reset constraint determination scheme in the related art.

[0005] According to one embodiment of the present application, reset definition information is determined according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a valid level of the reset signal; and obtaining a reset sequence of RCUs of each level in the target chip, and an operating mode of the target chip; and determining a reset constraint for a cross-reset domain RDC check of the target chip according to the reset definition information, the reset sequence and the operating mode.

[0006] In an exemplary embodiment, the reset definition information is determined according to the RTL code of the target chip, including: obtaining the instantiation name of each level of RCU and the level information of each level of RCU; matching the reset signal name, the level of the reset signal corresponding to the RCU, and the effective level of the reset signal in the RTL code according to the instantiation name and the level information.

[0007] In an exemplary embodiment, in the process of obtaining the reset order of RCUs of each level in the target chip, the method includes: for a first RCU having only one input reset, obtaining a reset signal of the input reset of the first RCU and a reset signal of the output reset of the first RCU; and determining the reset order of the first RCU according to the reset signal of the input reset of the first RCU and the reset signal of the output reset.

[0008] In an exemplary embodiment, in the process of obtaining the reset sequence of each level RCU in the target chip, the method includes: for a second RCU with multiple input resets, determining the reset structure of the second RCU, wherein the reset structure includes one of the following: software reset, hardware reset; wherein the software reset is used to indicate that the reset signal is controlled by software, and the hardware reset (hardware control) is used to indicate that the reset signal is controlled by a hardware circuit; when it is determined that the reset structure of the second RCU is the software reset, obtaining the reset signal of the input reset corresponding to the second RCU and the reset signal of the output reset of the second RCU in the RTL code, and determining that the reset structure is the second RCU of the software reset according to the reset signal of the input reset corresponding to the second RCU and the reset signal of the output reset of the second RCU CU reset sequence; when it is determined that the reset structure of the second RCU is the hardware reset, determine the hardware logic circuit corresponding to the hardware reset, and obtain the reset logic path corresponding to the hardware logic circuit; determine multiple components in the reset logic path, and respectively determine the component characteristics of the multiple components; when the component characteristics indicate that the target component among the multiple components is an AND gate, the reset sequence of the second RCU is obtained according to the input reset of the AND gate and the output reset of the AND gate; the method also includes: after obtaining the reset sequence of the RCUs of each level, obtaining the connection relationship of the RCUs of each level; according to the connection relationship of the RCUs of each level, the reset sequence of the first RCU and the reset sequence of the second RCU determine the reset sequence of the RCUs of each level.

[0009] In an exemplary embodiment, after respectively determining the component characteristics of the multiple components, the method further includes: in a case where the component characteristics indicate that a target component among the multiple components is an OR gate, determining a target input reset and a target output reset from an input reset of the OR gate and an output reset of the OR gate; and obtaining a reset order of the second RCU according to the target input reset and the target output reset.

[0010] In an exemplary embodiment, obtaining the working mode of the target chip includes: obtaining the working mode of the target chip, wherein the working mode includes at least one of the following: functional mode, low power mode, debug mode and test mode; wherein different working modes correspond to different reset conditions, reset signals in the same working mode will be reset at the same time, and reset signals in different reset modes will not be reset at the same time.

[0011] In an exemplary embodiment, after determining the reset constraints for cross-reset domain RDC check of the target chip according to the reset definition information, the reset sequence and the working mode, the method further includes: performing an RDC check on the target chip according to the reset constraints to obtain a check result; parsing the check result to determine a modification strategy for the reset constraints; and modifying the reset constraints according to the modification strategy to obtain a modified reset constraint.

[0012] According to another embodiment of the present application, a reset constraint determination device is also provided, including: a first determination module, used to determine reset definition information according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to the reset control unit RCU in the target chip, the level of the reset signal corresponding to the RCU, and the effective level of the reset signal; and an acquisition module, used to obtain the reset sequence of each level RCU in the target chip, and the working mode of the target chip; a second determination module, used to determine the reset constraint for cross-reset domain RDC check of the target chip according to the reset definition information, the reset sequence and the working mode.

[0013] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0014] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0015] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiment are implemented.

[0016] Through this application, reset definition information is determined according to the RTL code of the target chip, and the reset sequence of each level RCU in the target chip and the working mode of the target chip are obtained, and the reset constraint for the cross-reset domain RDC check of the target chip is determined according to the reset definition information, the reset sequence and the working mode. Therefore, the technical problem of incomplete content and low efficiency in the determination scheme of reset constraints in the related art can be solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a hardware structure block diagram of a method for determining a reset constraint in an embodiment of the present application;

[0018] Figure 2 is a flowchart of a method for determining a reset constraint according to an embodiment of the present application;

[0019] Figure 3 is a schematic diagram of a SoC chip according to a method for determining a reset constraint according to an embodiment of the present application;

[0020] Figure 4 is a flowchart of RDC checking in a method for determining a reset constraint according to an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of an RDC check violation in a reset constraint determination method according to an embodiment of the present application;

[0022] Figure 6 is a metastable signal waveform diagram of a method for determining a reset constraint according to an embodiment of the present application;

[0023] Figure 7 is a reset constraint schematic diagram of a reset constraint determination method according to an embodiment of the present application;

[0024] Figure 8 It is a logic diagram of software reset and hardware reset according to the reset constraint determination method of an embodiment of the present application;

[0025] Fig. 9 is a schematic diagram of the reset sequence of the RCU with multiple input resets in the reset constraint determination method according to an embodiment of the present application;

[0026] Fig.10 is a schematic diagram of an RDC inspection device according to a method for determining a reset constraint in an embodiment of the present application;

[0027] Fig.11 is a schematic diagram of resetting definition information parsing according to a method for determining resetting constraints according to an embodiment of the present application;

[0028] Fig.12is a schematic diagram of reset definition constraints according to a method for determining reset constraints in an embodiment of the present application;

[0029] Fig.13 is a schematic diagram of reset sequence constraints according to a method for determining reset constraints in an embodiment of the present application;

[0030] Fig.14 It is a structural block diagram of a reset constraint determination device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0033] The method embodiments provided in the embodiments of the present application can be executed in an integrated development tool or a similar computing device. Taking running on an integrated development tool as an example, Figure 1 is a hardware structure block diagram of a method for determining a reset constraint in an embodiment of the present application. Figure 1 As shown, the integrated development tool may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned integrated development tool may also include a transmission device 106 for communication functions and an input and output device 108. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above integrated development tool. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0034] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the reset constraint in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the method for determining the reset constraint is realized. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the integrated development tool via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0035] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by the communication provider of the integrated development tool. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0036] In this embodiment, a method for determining a reset constraint is provided, which is applied to the above-mentioned integrated development tool. Figure 2 is a flow chart of a method for determining a reset constraint according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0037] Step S202, determining reset definition information according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a valid level of the reset signal;

[0038] Step S204, and obtaining the reset sequence of each level RCU in the target chip and the working mode of the target chip;

[0039] Step S206: Determine a reset constraint for a cross-reset domain RDC check on the target chip according to the reset definition information, the reset sequence and the working mode.

[0040] Through the above steps, the reset definition information is determined according to the RTL code of the target chip, and the reset sequence of each level RCU in the target chip and the working mode of the target chip are obtained, and the reset constraint for the cross-reset domain RDC check of the target chip is determined according to the reset definition information, the reset sequence and the working mode. Therefore, the technical problem of incomplete content and low efficiency in the determination scheme of reset constraints in the related art can be solved.

[0041] In an exemplary embodiment, the reset definition information is determined according to the RTL code of the target chip, including: obtaining the instantiation name of each level of RCU and the level information of each level of RCU; matching the reset signal name, the level of the reset signal corresponding to the RCU, and the effective level of the reset signal in the RTL code according to the instantiation name and the level information.

[0042] Get the instantiation name and level information of each level RCU from the RTL code, and determine the reset information of each level RCU according to the instantiation name and level information of each level RCU. The reset information includes: reset signal for input reset, reset signal for output reset, reset signal name, and level of reset signal. The reset signal name follows certain rules, such as reset_n_i represents a low-valid input reset signal, and reset_o represents an output reset signal. The effective level can be determined from the reset signal name. For example, the _n suffix in reset_n_i usually represents low-validity.

[0043] In this embodiment, according to the instantiation name of each level of RCU and the level information of each level of RCU, the reset information of each level of RCU is determined from the RTL code, and the effective level of the reset signal is determined according to the reset signal name. The reset definition information is determined according to the reset signal name, the level of the reset signal, and the effective level of the reset signal.

[0044] In an exemplary embodiment, in the process of obtaining the reset order of RCUs of each level in the target chip, the method includes: for a first RCU having only one input reset, obtaining a reset signal of the input reset of the first RCU and a reset signal of the output reset of the first RCU; and determining the reset order of the first RCU according to the reset signal of the input reset of the first RCU and the reset signal of the output reset.

[0045] In the case of a first RCU with only one input reset, obtain the reset signal of the input reset of the first RCU and the reset signal of the output reset of the first RCU. Optionally, pwron_reset is the reset signal of the only input reset of the first RCU, reset1-reset6 are the reset signals of the output reset of the first RCU, and when pwron_reset is reset, reset1-reset6 are simultaneously set to the reset state. Therefore, it can be concluded that the reset order inside the first RCU is to reset reset1-reset6 first and then reset pwron_reset. This means that for the first RCU with only one input reset, the reset signal of the output reset of the first RCU is earlier than or simultaneous with the reset signal of the input reset of the first RCU to determine the reset order of the first RCU.

[0046] In this embodiment, it is clarified that when the first RCU has only one input reset, the reset order of the first RCU is determined according to the reset signal of the input reset of the first RCU and the reset signal of the output reset of the first RCU, wherein the reset order of the first RCU is that the reset signal of the output reset of the first RCU is earlier than or simultaneous with the reset signal of the input reset of the first RCU.

[0047] In an exemplary embodiment, in the process of obtaining the reset sequence of each level RCU in the target chip, the method includes: for a second RCU with multiple input resets, determining the reset structure of the second RCU, wherein the reset structure includes one of the following: software reset, hardware reset; wherein the software reset is used to indicate that the reset signal is controlled by software, and the hardware reset is used to indicate that the reset signal is controlled by a hardware circuit; when it is determined that the reset structure of the second RCU is the software reset, obtaining the reset signal of the input reset corresponding to the second RCU and the reset signal of the output reset of the second RCU in the RTL code, and determining the reset structure of the second RCU whose reset structure is the software reset according to the reset signal of the input reset corresponding to the second RCU and the reset signal of the output reset of the second RCU Reset sequence; when it is determined that the reset structure of the second RCU is the hardware reset, determine the hardware logic circuit corresponding to the hardware reset, and obtain the reset logic path corresponding to the hardware logic circuit; determine multiple components in the reset logic path, and respectively determine the component characteristics of the multiple components; when the component characteristics indicate that the target component among the multiple components is an AND gate, the reset sequence of the second RCU is obtained according to the input reset of the AND gate and the output reset of the AND gate; the method also includes: after obtaining the reset sequence of the RCUs of each level, obtain the connection relationship of the RCUs of each level; according to the connection relationship of the RCUs of each level, the reset sequence of the first RCU and the reset sequence of the second RCU determine the reset sequence of the RCUs of each level.

[0048] In the case of a second RCU with multiple input resets, it is necessary to determine whether there are both software reset and hardware reset in the reset structure of the second RCU. In the case where it is determined that the reset structure of the second RCU is a software reset, obtain the reset signal of the input reset of the second RCU and the reset signal of the output reset of the second RCU. Optionally, assuming that reset1_i is the reset signal of the input reset of the second RCU, reset1-reset3 are the reset signals of the output reset of the second RCU, and when reset1_i is reset, reset1-reset3 are simultaneously set to the reset state. Therefore, it can be concluded that the reset order inside the second RCU is to reset reset1-reset3 first, and then reset1_i. This means that in the case where the reset structure of the second RCU is a software reset, the reset signal of the output reset of the second RCU is earlier than or simultaneous with the reset signal of the input reset of the second RCU to determine the reset order of the second RCU.

[0049] When it is determined that the reset structure of the second RCU is a hardware reset, the reset signal propagates through a series of logic gates, such as AND gates, OR gates, NOT gates, etc., and other components such as flip-flops, latches, etc. To analyze the reset behavior, it is necessary to obtain all component information on these reset logic paths. Therefore, it is necessary to obtain the reset logic path of the hardware reset input signal from the RTL code, and obtain multiple components on the reset logic path. If the target component among the multiple components is an AND gate, when the reset signal of the input reset of any AND gate is reset, the reset signal of the output reset is simultaneously set to the reset state. Therefore, when the reset structure of the second RCU is a hardware reset and the target component on the reset logic path is an AND gate, the reset signal of the output reset of the second RCU is earlier than or at the same time as the reset signal of the input reset of the second RCU. This is because the AND gate requires that the output is true only when all inputs are true. Therefore, in the reset logic, if the reset signal of the input reset of any AND gate is reset, due to the logical characteristics of the AND gate, the reset signal of its output reset will also be reset immediately. If the target component is an OR gate, the reset signal of the input reset does not necessarily cause the reset signal of the output reset to be reset. Therefore, when the reset structure of the second RCU is a hardware reset and the target component on the reset logic path is an OR gate, the reset order cannot be determined.

[0050] It should be clear that the reset logic path refers to the logical connection path from the reset signal source to the circuit elements that need to be reset. The components on this path may include various logic gates, such as AND gates, OR gates, NOT gates, etc., triggers and registers, etc. These components jointly participate in the transmission and processing of reset signals.

[0051] In the reset sequence extraction between multiple RCUs, it is necessary to clarify the connection relationship between RCUs at all levels in the SoC, including the hierarchical structure and mutual connection between the first-level RCU, the second-level RCU, the third-level RCU, etc. Optionally, assuming that RCU is a first-level RCU, RCU1 is a second-level RCU, RCU1_1 is a third-level RCU, pwron_reset is the reset signal for input reset of RCU, reset1-reset6 is the reset signal for output reset of RCU, reset1 is the reset signal for input reset of RCU1, reset1_1-reset1_3 is the reset signal for output reset of RCU1, reset1_1-reset1_3 is the reset signal for input reset of RCU1_1, reset1_1_1-reset1_1_2 is the reset signal for output reset of RCU1_1, the reset structure of RCU1 is a software structure, the reset structure of RCU1_1 is a hardware structure and the target component is an AND gate. It can be determined that when pwron_reset is reset, reset1-reset6 will also be reset, reset1 is the reset signal of RCU1 input reset, and when reset1 is reset, reset1_1-reset1_3 are also reset, thus causing reset1_1_1-reset1_1_2 to be reset. Therefore, the reset order of RCU, RCU1, and RCU1_1 is determined as follows: the reset signal of RCU1_1 output reset is earlier than or simultaneously with the reset signal of RCU1_1 input reset, i.e., the reset signal of RCU1 output reset, the reset signal of RCU1 output reset is earlier than or simultaneously with the reset signal of RCU1 input reset, i.e., the reset signal of RCU output reset, and the reset signal of RCU output reset is earlier than or simultaneously with the reset signal of RCU input reset.

[0052] In this embodiment, it is clarified that when there are multiple second RCUs with input resets and the reset structure of the second RCU is software reset, the reset order of the second RCU is that the reset signal of the output reset of the second RCU is earlier than or simultaneously with the reset signal of the input reset of the second RCU. When there are multiple second RCUs with input resets and the reset structure of the second RCU is hardware reset, only when the target component is an AND gate, the reset order of the second RCU is that the reset signal of the output reset of the second RCU is earlier than or simultaneously with the reset signal of the input reset of the second RCU. At the same time, the reset order between RCUs connected at each level is clarified.

[0053] In an exemplary embodiment, after respectively determining the component characteristics of the multiple components, the method further includes: in a case where the component characteristics indicate that a target component among the multiple components is an OR gate, determining a target input reset and a target output reset from an input reset of the OR gate and an output reset of the OR gate; and obtaining a reset order of the second RCU according to the target input reset and the target output reset.

[0054] In a specific scenario, when the reset signals of the input reset of the OR gate are all 0, the corresponding reset signals of the output reset are also 0, which means that only when the reset structure of the second RCU is a hardware reset, and the target component on the reset logic path is the OR gate, and the reset signals of the input reset of the OR gate are all reset, the reset signal of the output reset of the second RCU is earlier than or simultaneous with the reset signal of the input reset of the second RCU.

[0055] In this embodiment, it is clarified that the reset order of the second RCU can be determined only when the reset structure of the second RCU is a hardware reset, the target component on the reset logic path is an OR gate, and the reset signals of the input reset of the OR gate are all reset.

[0056] In an exemplary embodiment, obtaining the working mode of the target chip includes: obtaining the working mode of the target chip, wherein the working mode includes at least one of the following: functional mode, low power mode, debug mode and test mode; wherein different working modes correspond to different reset conditions, reset signals in the same working mode will be reset at the same time, and reset signals in different reset modes will not be reset at the same time.

[0057] The working modes of the target chip are defined based on the reset requirements of the SoC chip in different working states. These working modes include but are not limited to: functional mode, the mode in which the target chip runs under normal operation. Low power mode, a state in which the target chip enters to reduce power consumption in order to save energy. In low power mode, the reset is different because the needs of power optimization and fast wake-up need to be taken into account. Debug mode, a mode that allows developers to debug and test the target chip. In debug mode, reset can be used to reset the debug environment or restore to a specific debug state. Test mode, a mode specifically used for manufacturing testing or functional verification. Reset can be used to initialize the test environment or reset test results in test mode. In the RTL code, the name of the reset signal usually reflects the working mode in which the reset signal acts, and different working modes correspond to different reset situations. For example, suppose there are signals such as rst_n_functional, rst_n_low_power, rst_n_debug, and rst_n_test, which correspond to the resets of functional mode, low power mode, debug mode, and test mode respectively. These reset signals are extracted from the RTL code and classified according to the working modes corresponding to these reset signals. Reset signals in the same working mode will be reset at the same time, while reset signals in different working modes will not be reset at the same time.

[0058] In this embodiment, the working mode of the target chip is clarified, and the working mode includes but is not limited to: functional mode, low power mode, debug mode and test mode. Among them, different working modes correspond to different reset conditions, and reset signals in the same working mode will be reset at the same time, and reset signals in different reset modes will not be reset at the same time.

[0059] In an exemplary embodiment, after determining the reset constraints for cross-reset domain RDC check of the target chip according to the reset definition information, the reset sequence and the working mode, the method further includes: performing an RDC check on the target chip according to the reset constraints to obtain a check result; parsing the check result to determine a modification strategy for the reset constraints; and modifying the reset constraints according to the modification strategy to obtain a modified reset constraint.

[0060] According to the reset definition information, reset sequence and working mode of the target chip, the reset constraints used for RDC check of the target chip are determined. The target chip is checked for RDC through the reset constraints. After the RDC check is completed, an inspection result will be obtained. This result will show whether there are still violations in the target chip with the reset constraints added. The inspection results are analyzed to determine whether the reset constraints need to be modified. If there are still violations in the target chip, the modification strategy of the reset constraints is determined based on the analysis of the inspection results. This modification strategy will indicate how to adjust the reset constraints, and the reset constraints are adjusted accordingly according to the modification strategy. After the modification is completed, a new set of reset constraints is obtained. The new reset constraints can better meet the RDC check of the target chip to reduce violations.

[0061] In this embodiment, it is clarified that after the reset constraint is determined, an RDC check is performed on the target chip according to the reset constraint to obtain a check result, and the reset constraint is improved according to the check result to ensure that the probability of a violation in the target chip is minimized.

[0062] The above embodiment describes a method for determining reset constraints for cross-reset domain RDC checking of a target chip. However, before clarifying the above reset constraint determination method, the system-on-chip SoC of the target chip of the embodiment of the present application and the internal structure of the SoC are introduced as follows.

[0063] Figure 3 is a schematic diagram of a SoC chip according to a method for determining a reset constraint according to an embodiment of the present application, such as Figure 3 As shown, it specifically includes the following contents:

[0064] As the complexity of integrated circuits increases, a chip's system on chip (SoC) contains multiple subsystems, and each subsystem requires an independent reset signal. This has led to a significant increase in the number of resets for the entire SoC chip. If the asynchronous reset signal is not handled correctly, it may cause a reset domain conflict (RDC). This may cause problems when the reset signal propagates between different clock domains, such as the reset signal being lost in some clock domains, resulting in system instability. Therefore, RDC checking is an essential check in the SoC chip design process, and it is also an important means to ensure the correct and reliable function of the chip.

[0065] During the SoC chip design process, the reset structure will be defined first, including the source, generation, distribution and related control of the reset. Register transfer level (RTL) designers manually write corresponding codes based on the reset structure and scheme to form a module specifically used to generate resets. This module is called a reset control unit (RCU). In this embodiment, since the SoC contains multiple subsystems, an RCU is designed in the top layer of the SoC to generate module reset signals for each subsystem. Each subsystem also has an RCU inside to generate specific module reset signals for the IP blocks in the subsystem.

[0066] In the above embodiment, it is mentioned that the RDC check is an essential check in the SoC chip design process. Therefore, the specific process of the RDC check needs to be clarified.

[0067] Figure 4 is a flow chart of RDC checking in the method for determining reset constraints according to an embodiment of the present application, such as Figure 4 As shown, the specific steps include:

[0068] Step S402: defining the reset structure includes: including information such as the level of the reset signal, whether the reset is a synchronous reset or an asynchronous reset, whether the reset is high level effective or low level effective, etc.

[0069] Step S404: Write RTL code according to the reset structure.

[0070] Step S406: forming a reset constraint according to the reset structure and the RTL code.

[0071] Step S408: Use the RTL code and reset constraints as inputs for RDC checking, and output a check report after the RDC checking is completed.

[0072] Step S410: Analyze and add the definition of reset sequence according to the inspection result to improve the reset constraint.

[0073] In the above embodiment, the inspection result is obtained through RDC inspection to determine whether there is a violation in the target chip. There are the following three situations for the violation.

[0074] Figure 5 is a schematic diagram of an RDC check violation in a method for determining a reset constraint according to an embodiment of the present application, such as Figure 5 As shown, it specifically includes the following contents:

[0075] rst1 is called "source reset", F1 is called "source register", rst2 is called "destination reset", F2 is called "destination register", and there are three situations in the reset order of rst1 and rst2:

[0076] (1) "Source reset" and "destination reset" are reset at the same time. At this time, the F1 register and the F2 register are reset at the same time. The data changes caused by the reset operation of F1 will not be sampled at the D end of F2.

[0077] (2) The "source reset" is reset earlier than the "destination reset". At this time, the F1 register is reset but the F2 register is not reset. The data changes caused by the reset operation of F1 will be sampled at the D end of F2, causing the Q end of F2 to produce a metastable state, resulting in a logical error in the target chip and affecting the circuit function.

[0078] (3) The "source reset" is reset later than the "destination reset". This order usually does not cause F2 to be metastable because the F2 register is already in a stable state before the F1 register is reset.

[0079] The above embodiment introduces three situations of violations. When the "source reset" is reset earlier than the "destination reset", a metastable state will occur. The metastable state will cause a logic error in the target chip and affect the circuit function. Figure 6 The signal waveform diagram is shown when the "source reset" is reset earlier than the "destination reset".

[0080] Figure 6 is a metastable signal waveform diagram of a method for determining a reset constraint according to an embodiment of the present application, such as Figure 6 As shown, it specifically includes the following contents:

[0081] When the source reset rst1 is reset earlier than the destination reset rst2, Q1 of the F1 register is set to 0 and the reset signal is transmitted to D2 of the F2 register, causing Q2 of the F2 register to be in a metastable state.

[0082] In order to avoid metastable state in the target chip, it is necessary to determine the reset constraints of the target chip.

[0083] Figure 7 is a reset constraint diagram of a reset constraint determination method according to an embodiment of the present application, such as Figure 7 As shown, it specifically includes the following contents:

[0084] The reset constraints used for RDC checking include three parts: reset definition information, reset order of RCUs at each level in the target chip, and working mode of the target chip (equivalent to the reset mode in the figure). This example mainly describes how to determine these three parts.

[0085] The reset definition information is obtained from the RTL code of the target chip. The instantiation names of RCUs at each level are obtained from the RTL code. The number of RCUs and the reset signal name in the entire SoC chip can be determined through the instantiation names of RCUs. The reset information of each RCU is extracted one by one. The reset information includes: the reset signal of the input reset, the reset signal of the output reset, the reset signal name, and the level of the reset signal, i.e., the reset definition point. The naming of the reset signal usually follows certain rules, such as reset_n_i represents a low-valid input reset signal, and reset_o represents an output reset signal. The valid level can be inferred from the reset signal name. For example, the _n suffix in reset_n_i usually indicates low validity. The reset signal name, the level of the reset signal, and the effective level of the reset signal are the three elements of the reset definition information in the reset constraint. Fill the three elements of the reset signal name, the level of the reset signal, and the effective level of the reset signal into the reset constraint format pattern_A to obtain the extracted reset definition information.

[0086] The extraction of the reset order of each level RCU in the target chip needs to be divided into two parts: the extraction of the reset order within a single RCU and the extraction of the reset order between multiple RCUs. At the same time, the extraction of the reset order within a single RCU is divided into two cases:

[0087] In the case of a first RCU with only one input reset, obtain the reset signal of the input reset of the first RCU and the reset signal of the output reset of the first RCU. Optionally, pwron_reset is the reset signal of the only input reset of the first RCU, reset1-reset6 are the reset signals of the output reset of the first RCU, and when pwron_reset is reset, reset1-reset6 are simultaneously set to the reset state. Therefore, it can be concluded that the reset order inside the first RCU is to reset reset1-reset6 first and then reset pwron_reset. This means that for the first RCU with only one input reset, the reset signal of the output reset of the first RCU is earlier than or simultaneous with the reset signal of the input reset of the first RCU to determine the reset order of the first RCU. Similarly, RCU1 to RCU4 are the secondary RCUs of the first RCU, and the input reset of the secondary RCU is the output reset reset1-reset4 of the first RCU. The output reset is as shown in this embodiment. According to the reset signal of the input reset and the reset signal of the output reset of each RCU in RCU1-RCU4, the reset order inside the secondary RCU can be determined. Similarly, RCU1_1 and RCU4_1 are the third-level RCUs, and the reset order inside the three-level RCU can also be obtained.

[0088] In the case of a second RCU with multiple input resets, it is necessary to determine whether there are both software reset and hardware reset in the reset structure of the second RCU. In the case where it is determined that the reset structure of the second RCU is a software reset, obtain the reset signal of the input reset of the second RCU and the reset signal of the output reset of the second RCU. Optionally, assuming that reset1_i is the reset signal of the input reset of the second RCU, reset1-reset3 are the reset signals of the output reset of the second RCU, and when reset1_i is reset, reset1-reset3 are simultaneously set to the reset state. Therefore, it can be concluded that the reset order inside the second RCU is to reset reset1-reset3 first, and then reset1_i. This means that in the case where the reset structure of the second RCU is a software reset, the reset signal of the output reset of the second RCU is earlier than or simultaneous with the reset signal of the input reset of the second RCU to determine the reset order of the second RCU.

[0089] When it is determined that the reset structure of the second RCU is a hardware reset, the reset signal propagates through a series of logic gates, such as AND gates, OR gates, NOT gates, etc., and other components such as flip-flops, latches, etc. To analyze the reset behavior, it is necessary to obtain all component information on these reset logic paths. Therefore, it is necessary to obtain the reset logic path of the hardware reset input signal from the RTL code, and obtain multiple components on the reset logic path. If the target component among the multiple components is an AND gate, when the reset signal of the input reset of any AND gate is reset, the reset signal of the output reset is simultaneously set to the reset state. Therefore, when the reset structure of the second RCU is a hardware reset and the target component on the reset logic path is an AND gate, the reset signal of the output reset of the second RCU is earlier than or at the same time as the reset signal of the input reset of the second RCU. This is because the AND gate requires that the output is true only when all inputs are true. Therefore, in the reset logic, if the reset signal of the input reset of any AND gate is reset, due to the logical characteristics of the AND gate, the reset signal of its output reset will also be reset immediately. If the target component is an OR gate, the reset signal of the input reset does not necessarily cause the reset signal of the output reset to be reset. Therefore, when the reset structure of the second RCU is a hardware reset and the target component on the reset logic path is an OR gate, the reset order cannot be determined.

[0090] In the reset sequence extraction between multiple RCUs, it is necessary to clarify the connection relationship between the RCUs at all levels in the SoC, including the hierarchical structure and mutual connection between the first-level RCU, the second-level RCU, the third-level RCU, etc., and analyze the connection relationship between the internal input reset and output reset of each RCU to derive the reset sequence of each module or subsystem in the reset process of the entire SoC. Optionally, assuming that RCU is a first-level RCU, RCU1 is a second-level RCU, RCU1_1 is a third-level RCU, pwron_reset is a reset signal for input reset of RCU, reset1-reset6 are reset signals for output reset of RCU, reset1 is a reset signal for input reset of RCU1, reset1_1-reset1_3 are reset signals for output reset of RCU1, reset1_1-reset1_3 are reset signals for input reset of RCU1_1, reset1_1_1-reset1_1_2 are reset signals for output reset of RCU1_1, the reset structure of RCU1 is a software structure, the reset structure of RCU1_1 is a hardware structure and the target component is an AND gate. It can be determined that when pwron_reset is reset, reset1-reset6 will also be reset, reset1 is the reset signal of the input reset of RCU1, and when reset1 is reset, reset1_1-reset1_3 are also reset, thus causing reset1_1_1-reset1_1_2 to be reset. Therefore, the reset order of RCU, RCU1, and RCU1_1 is determined as follows: the reset signal of the output reset of RCU1_1 is earlier than or simultaneously with the reset signal of the input reset of RCU1_1, i.e., the reset signal of the output reset of RCU1, the reset signal of the output reset of RCU1 is earlier than or simultaneously with the reset signal of the input reset of RCU1, i.e., the reset signal of the output reset of RCU1, and the reset signal of the output reset of RCU is earlier than or simultaneously with the reset signal of the input reset of RCU1. The connection relationship of each level in the second RCU, the reset signal of the input reset, and the reset signal of the output reset are filled in the reset constraint format pattern_C.

[0091] The working modes of the target chip are defined based on the reset requirements of the SoC chip in different working states. These working modes include but are not limited to: functional mode, the mode in which the target chip runs under normal operation. Low power mode, a state in which the target chip enters to reduce power consumption in order to save energy. In low power mode, the reset may be different because the needs of power optimization and fast wake-up need to be taken into account. Debug mode, a mode that allows developers to debug and test the target chip. In debug mode, reset can be used to reset the debug environment or restore to a specific debug state. Test mode, a mode specifically used for manufacturing testing or functional verification. Reset can be used to initialize the test environment or reset test results in test mode. In the RTL code, the name of the reset signal usually reflects the working mode in which the reset signal acts, and different working modes correspond to different reset situations. For example, suppose there are signals such as rst_n_functional, rst_n_low_power, rst_n_debug, and rst_n_test, which correspond to the resets of functional mode, low power mode, debug mode, and test mode respectively. These reset signals are extracted from the RTL code and classified according to the working modes corresponding to these reset signals. The reset signals in the same working mode will be reset at the same time, while the reset signals in different working modes will not be reset at the same time. Fill in the working mode of the target chip in the reset constraint format pattern_B.

[0092] By combining the reset definition information constraints, reset sequence constraints, and working mode constraints, a complete SoC reset constraint for RDC checking can be obtained.

[0093] The above embodiment clarifies the method for determining the reset constraint, which mainly includes: obtaining reset definition information, reset sequence and working mode of the target chip. In the process of determining the reset sequence of the RCU, it is necessary to discuss the situation according to the reset structure of the RCU.

[0094] Figure 8 is a logic diagram of software reset and hardware reset according to the reset constraint determination method of an embodiment of the present application, such as Figure 8 As shown, it specifically includes the following contents:

[0095] This embodiment introduces the situation where software reset and hardware reset exist simultaneously in the RCU, wherein the software reset is generally generated by software configuration, and the hardware reset is generated by hardware circuit control. In the case where the reset structure of the RCU is a software reset, the register control unit is controlled by the CPU, and the input is reset1_i. When reset1_i is reset, it indicates that the register control unit is reset, and its three output reset reset signals will be reset at the same time, and the resulting reset sequence is reset1_n_o, reset2_n_o, and reset3_n_o are all reset earlier than or at the same time as reset1_i. The hardware reset is not controlled by the CPU, but by the hardware circuit. The reset logic path of the hardware reset input signal is obtained from the RTL code, and multiple components on the reset logic path are obtained. If the target component among the multiple components is an AND gate, when the reset signal of the input reset of any AND gate is reset, the reset signal of the output reset is simultaneously set to the reset state.

[0096] The above embodiment introduces the situation where software reset and hardware reset exist simultaneously in the RCU. Combining the above method for determining the reset sequence of the RCU, Fig. 9 The overall implementation steps for determining the reset sequence of the RCU are introduced.

[0097] Fig. 9 is a schematic diagram of the reset sequence of the RCU with multiple input resets in the reset constraint determination method according to an embodiment of the present application, such as Fig. 9 As shown, the specific steps include:

[0098] Step S902: Determine the number of input resets of the RCU.

[0099] Step S904: When the RCU has only one input reset, the reset relationship between the output reset and the input reset can be directly determined, where the reset signal of the output reset of the RCU is earlier than or simultaneous with the reset signal of the input reset of the RCU.

[0100] Step S906: When the RCU has multiple input resets, determine whether the RCU has a software reset.

[0101] Step S908: When the RCU has multiple input resets and the reset structure of the RCU is a software reset, a reset signal of the input reset of the RCU and a reset signal of the output reset of the RCU are obtained.

[0102] Step S910: Determine a reset order according to the reset signal of the RCU input reset and the reset signal of the RCU output reset, wherein the reset order is that the reset signal of the RCU output reset is earlier than or simultaneous with the reset signal of the RCU input reset.

[0103] Step S912: when the RCU has multiple input resets and the reset structure of the RCU is a hardware reset, a reset logic path of the hardware reset input signal is obtained from the RTL code, and multiple components on the reset logic path are obtained.

[0104] Step S914: Determine component characteristics of the plurality of components to determine a reset sequence.

[0105] Step S916: When the component characteristic indicates an AND gate, the reset signal of the input reset of any AND gate being reset will cause the reset signal of the output reset to be reset as well.

[0106] Step S918: Determine the reset sequence, where the reset signal of the RCU output reset must be earlier than or simultaneous with the reset signal of the RCU input reset.

[0107] Step S920: When the component characteristic indicates an OR gate, when the reset signal of the input reset is reset, it does not necessarily cause the reset signal of the output reset to be reset as well.

[0108] Step S922: The reset sequence cannot be determined.

[0109] The above embodiment clarifies the overall implementation steps of the reset sequence of the RCU. However, it is also necessary to clarify the overall device for determining the reset definition information, the reset sequence of the RCU, the working mode of the target chip and the reset constraint.

[0110] Fig.10 is a schematic diagram of an RDC inspection device according to a method for determining a reset constraint in an embodiment of the present application, such as Fig.10 As shown, it specifically includes the following contents:

[0111] This embodiment introduces a reset constraint automatic generation device for RDC checking, which includes: an RCUhierachy generation module, a reset definition generation module, a reset relationship generation module (equivalent to a reset sequence generation module), a reset mode generation module (equivalent to a working mode generation module), and a reset constraint output module.

[0112] The RCU hierachy generation module is used to read input files, where the format of the input files includes but is not limited to EXCEL format. The input file is parsed according to the instantiation name of the RCU, the hierarchy information of the RCU, and the connection relationship between the RCUs at each level. The instantiation name and hierarchy information of the RCU are used to generate the constraints of the reset definition part, and the connection relationship between the RCUs at each level is used to generate some constraints of the reset order. Optionally, create an input file excel table as shown in Table 1, corresponding to Figure 7The RCU structure includes: the instance name of the RCU, such as RCU1, RCU1_1, etc.; the hierarchical information of the RCU, such as hierachay: xx / xx / xx / xx; the connection relationship between the RCUs of each level, such as level1 is the RCU, which is the superior of level2 RCU1, and RCU1 is the superior of RCU1_1.

[0113] Table 1 RCU hierachy input file content

[0114]

[0115] The reset definition generation module is used to extract information about the reset signal from the RTL code, and generate a reset definition constraint based on the reset signal information. Optionally, the reset definition generation module searches for the corresponding RCU module in the RTL code according to the RCU instance name and hierarchical information output by the RCU hierachy generation module, and obtains the reset signal of the input reset and the reset signal of the output reset in the RCU module, wherein the reset signal of the input reset and the reset signal of the output reset need to be standardized names. Extract keywords from the reset signal name, such as sync, async, reset_n_i, reset_i. These keywords are used to indicate the type and polarity of the reset signal, for example, synchronous or asynchronous, low level valid or high level valid. By combining these keywords with the reset signal name and the hierarchical information of the RCU, a complete reset definition constraint can be obtained.

[0116] The reset sequence module generates the complete sequence and dependency of the reset signal according to the output of the reset definition generation module and the output of the RCU hierachy generation module. Among them, the output of the reset definition generation module includes the reset definition information obtained from the RTL code, and the reset definition information includes the name of the reset signal, whether the structure of the RCU is a software reset or a hardware reset, and the reset sequence corresponding to the software reset and the hardware reset, whether the effective level is a high level or a low level, and whether it is a synchronous or asynchronous reset. The RCU hierachy generation module outputs the connection relationship between the RCUs at each level, that is, which RCUs are the upper RCUs and which are the lower RCUs. The upper RCU can control or trigger the reset operation of the lower RCU, thus forming a reset signal propagation and dependency chain.

[0117] The reset mode generation module (equivalent to the working mode generation module) generates corresponding reset signals according to different operating modes of the system, such as functional mode, debug mode, low power mode, etc. These reset signals have different characteristics, such as synchronous or asynchronous, high level active or low level active. In RTL design, the use of standardized naming methods is crucial to improve the readability and maintainability of the code. For reset signals, the naming should contain enough information to indicate its type, action mode, effective level, and whether it is output or input. For example: reset_func_async_n_o is a low-level active asynchronous output reset in functional mode, and reset_dbg_async_n_o is a low-level active asynchronous output reset in debug mode. In addition, in low power mode, assuming that there are two ARM clusters, one of which contains 4 cores and the other contains 8 cores, the cluster containing 8 cores will not work in low power mode. In this case, all reset signals related to the 8-core cluster will not issue reset signals or cancel reset signals. The definition of reset mode is conducive to excluding invalid violations in RDC check results, thereby improving the analysis efficiency of RDC check results.

[0118] The reset constraint output module combines the constraints output by the "reset definition generation module", "reset sequence generation module" and "reset mode generation module" to output a complete set of reset constraints for the SoC chip, which can be directly used for RDC checking.

[0119] The above embodiment introduces the specific implementation steps of the RCU hierachy generation module, the reset definition generation module, and the reset sequence generation module. Fig.11 — Fig.13 The result diagram of the corresponding module is shown.

[0120] Fig.11 FIG. 1 is a schematic diagram of resetting definition information parsing according to a method for determining resetting constraints according to an embodiment of the present application. Fig.11 As shown, it specifically includes the following contents:

[0121] Parse the Excel table input in the RCU hierachy generation module to form the RCU_hierachy.tcl file. The file shows the instance name, hierarchical information and connection relationship of each RCU, for example, the instance name of RCU, such as RUC, RCU1, RCU1_1, etc.; the hierarchical information of RCU, such as hierachay: xx / xx / xx / xx; the connection relationship of RCU, such as level1 RCU is the superior of level2 RCU1, and RCU1 is the superior of level3 RCU1_1.

[0122] Fig.12 is a schematic diagram of a reset definition constraint according to a method for determining a reset constraint in an embodiment of the present application, such as Fig.12 As shown, it specifically includes the following contents:

[0123] Three reset definition constraints are shown in this embodiment. In the reset definition constraint whose reset signal name is poron_reset_async_n_i, the level information of RCU is get_port xx, and the keyword is -sense, low, which means that the sensing mode of the reset signal is valid at a low level, and -async means that this is an asynchronous reset signal. In the reset definition constraint whose reset signal name is reset1_async_n_o, the level information of RCU is get_pinsxx / xx / xx, and the keyword is -sense, low, which means that the sensing mode of the reset signal is valid at a low level, and -async means that this is an asynchronous reset signal. In the reset definition constraint whose reset signal name is reset2_async_n_o, the level information of RCU is get_pinsxx / xx / xx, and the keyword is -sense, low, which means that the sensing mode of the reset signal is valid at a low level, and -async means that this is an asynchronous reset signal.

[0124] Fig.13 is a schematic diagram of reset sequence constraints according to a method for determining reset constraints in an embodiment of the present application, such as Fig.13 As shown, it specifically includes the following contents:

[0125] This embodiment shows the output result of the reset sequence module. Optionally, in the first row of reset constraints, pwron_resert is the input reset of RCU. Once pwron_resert is reset, the output resets reset1, reset2-reset6 of RCU will also be reset; in the second row of constraints, reset1 is the input reset of RCU1. When reset1 is reset, the output resets reset1_1-reset1_4 of RCU1 will also be reset. At the same time, since RCU is the superior RCU of RCU1, there is also pwron_resert in the -from_reset list, that is, pwron_reset is also included in the reset dependency chain of RCU1; by analogy, the third row of constraints is the reset sequence of RCU1_1. The -from_reset list includes pwron_resert, reset1, reset1_1, and the -to_reset list is all the output resets of RCU1_1.

[0126] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0127] In this embodiment, a reset constraint determination device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and will not be repeated hereafter. As used below, the term "module" may be a combination of software and / or hardware that implements a predetermined function. Although the system described in the following embodiments is preferably implemented in software, the implementation in hardware, or a combination of software and hardware, is also possible and conceivable.

[0128] Fig.14 is a structural block diagram of a reset constraint determination device according to an embodiment of the present application, such as Fig.14 As shown, the system includes:

[0129] A first determining module 10 is used to determine reset definition information according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a valid level of the reset signal; and

[0130] An acquisition module 12 is used to acquire the reset sequence of each level RCU in the target chip and the working mode of the target chip;

[0131] The second determination module 14 is used to determine the reset constraint for the cross-reset domain RDC check of the target chip according to the reset definition information, the reset sequence and the working mode.

[0132] In an embodiment of the present application, reset definition information is determined according to the RTL code of the target chip, wherein the reset definition information includes: the reset signal name corresponding to the reset control unit RCU in the target chip, the level of the reset signal corresponding to the RCU, and the effective level of the reset signal; and the reset sequence of each level RCU in the target chip and the working mode of the target chip are obtained; the reset constraint for the cross-reset domain RDC check of the target chip is determined according to the reset definition information, the reset sequence and the working mode. The above technical solution is adopted to solve the technical problems of incomplete content and low efficiency in the determination scheme of reset constraints in the related art.

[0133] In an exemplary embodiment, the first determination module 10 is also used to obtain the instantiation name of each level of RCU and the level information of each level of RCU; according to the instantiation name and the level information, the reset signal name, the level of the reset signal corresponding to the RCU, and the effective level of the reset signal are matched in the RTL code.

[0134] In an exemplary embodiment, the acquisition module 12 is further used to acquire, for a first RCU having only one input reset, a reset signal of the input reset of the first RCU and a reset signal of the output reset of the first RCU; and determine the reset order of the first RCU according to the reset signal of the input reset of the first RCU and the reset signal of the output reset.

[0135] In an exemplary embodiment, the acquisition module 12 is further used to determine, for a second RCU having multiple input resets, a reset structure of the second RCU, wherein the reset structure includes one of the following: software reset, hardware reset; wherein the software reset is used to indicate that a reset signal is controlled by software, and the hardware reset is used to indicate that a reset signal is controlled by a hardware circuit; when it is determined that the reset structure of the second RCU is the software reset, the reset signal of the input reset corresponding to the second RCU and the reset signal of the output reset of the second RCU are obtained in the RTL code, and the reset order of the second RCU whose reset structure is the software reset is determined according to the reset signal of the input reset corresponding to the second RCU and the reset signal of the output reset of the second RCU; when it is determined that the reset structure of the second RCU is the software reset When the reset structure of the RCU is the hardware reset, determine the hardware logic circuit corresponding to the hardware reset, and obtain the reset logic path corresponding to the hardware logic circuit; determine multiple components in the reset logic path, and respectively determine the component characteristics of the multiple components; when the component characteristics indicate that the target component among the multiple components is an AND gate, obtain the reset order of the second RCU according to the input reset of the AND gate and the output reset of the AND gate; the method also includes: after obtaining the reset order of the RCUs of each level, obtain the connection relationship of the RCUs of each level; according to the connection relationship of the RCUs of each level, the reset order of the first RCU and the reset order of the second RCU determine the reset order of the RCUs of each level.

[0136] In an exemplary embodiment, the acquisition module 12 is also used to determine the target input reset and the target output reset from the input reset of the OR gate and the output reset of the OR gate when the component characteristics indicate that the target component among the multiple components is an OR gate; and obtain the reset order of the second RCU according to the target input reset and the target output reset.

[0137] In an exemplary embodiment, the acquisition module 12 is also used to obtain the working mode of the target chip, wherein the working mode includes at least one of the following: functional mode, low power mode, debug mode and test mode; wherein different working modes correspond to different reset conditions, the reset signals in the same working mode will be reset at the same time, and the reset signals in different reset modes will not be reset at the same time.

[0138] In an exemplary embodiment, the second determination module 14 is further used to perform an RDC check on the target chip according to the reset constraint to obtain a check result; analyze the check result to determine a modification strategy for the reset constraint; modify the reset constraint according to the modification strategy to obtain a modified reset constraint. It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to this: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0139] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0140] Optionally, in this embodiment, the storage medium may be configured to store program codes for executing the following steps:

[0141] S1, determining reset definition information according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a valid level of the reset signal; and

[0142] S2, obtaining the reset sequence of each level RCU in the target chip and the working mode of the target chip;

[0143] S3: Determine a reset constraint for a cross-reset domain RDC check on the target chip according to the reset definition information, the reset sequence and the working mode.

[0144] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0145] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0146] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0147] S1, determining reset definition information according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a valid level of the reset signal; and

[0148] S2, obtaining the reset sequence of each level RCU in the target chip and the working mode of the target chip;

[0149] S3: Determine a reset constraint for a cross-reset domain RDC check on the target chip according to the reset definition information, the reset sequence and the working mode.

[0150] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0151] Optionally, in this embodiment, the computer program may be configured to perform the following steps by means of the computer program:

[0152] S1, determining reset definition information according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a valid level of the reset signal; and

[0153] S2, obtaining the reset sequence of each level RCU in the target chip and the working mode of the target chip;

[0154] S3: Determine a reset constraint for a cross-reset domain RDC check on the target chip according to the reset definition information, the reset sequence and the working mode.

[0155] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0156] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0157] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for determining a reset constraint, characterized in that: include: Determine reset definition information according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a valid level of the reset signal; and Obtaining the reset sequence of each level of RCU in the target chip and the working mode of the target chip; A reset constraint for a cross-reset domain RDC check on the target chip is determined according to the reset definition information, the reset sequence and the working mode.

2. The method according to claim 1, characterized in that Determine the reset definition information based on the RTL code of the target chip, including: Obtaining the instantiation name of each level RCU and the level information of each level RCU; The reset signal name, the level of the reset signal corresponding to the RCU, and the effective level of the reset signal are obtained by matching the instantiation name and the level information in the RTL code.

3. The method according to claim 1, characterized in that In the process of obtaining the reset sequence of each level RCU in the target chip, the method includes: For a first RCU having only one input reset, obtaining a reset signal of an input reset of the first RCU and a reset signal of an output reset of the first RCU; A reset order of the first RCU is determined according to a reset signal of an input reset of the first RCU and a reset signal of an output reset.

4. The method according to claim 3, characterized in that In the process of obtaining the reset sequence of each level RCU in the target chip, the method includes: For a second RCU having multiple input resets, determining a reset structure of the second RCU, wherein the reset structure includes one of: software reset, hardware reset; Wherein, the software reset is used to indicate that the reset signal is controlled by software, and the hardware reset is used to indicate that the reset signal is controlled by a hardware circuit; When it is determined that the reset structure of the second RCU is the software reset, obtaining a reset signal of an input reset corresponding to the second RCU and a reset signal of an output reset of the second RCU in the RTL code, and determining a reset order of the second RCU whose reset structure is the software reset according to the reset signal of the input reset corresponding to the second RCU and the reset signal of the output reset of the second RCU; In the case where it is determined that the reset structure of the second RCU is the hardware reset, a hardware logic circuit corresponding to the hardware reset is determined, and a reset logic path corresponding to the hardware logic circuit is obtained; multiple components in the reset logic path are determined, and component characteristics of the multiple components are respectively determined; if the component characteristics indicate that a target component among the multiple components is an AND gate, a reset sequence of the second RCU is obtained according to an input reset of the AND gate and an output reset of the AND gate; The method further comprises: After obtaining the reset order of the RCUs at each level, obtaining the connection relationship of the RCUs at each level; The reset order of the RCUs at the various levels is determined according to the connection relationship between the RCUs at the various levels, the reset order of the first RCU and the reset order of the second RCU.

5. The method according to claim 4, characterized in that After respectively determining the component features of the plurality of components, the method further includes: In a case where the component characteristic indicates that a target component among the plurality of components is an OR gate, determining a target input reset and a target output reset from an input reset of the OR gate and an output reset of the OR gate; A reset sequence of the second RCU is obtained according to the target input reset and the target output reset.

6. The method according to claim 1, characterized in that Obtaining the working mode of the target chip includes: Obtain the working mode of the target chip, wherein the working mode includes at least one of the following: functional mode, low power mode, debug mode and test mode; wherein different working modes correspond to different reset conditions, reset signals in the same working mode will be reset at the same time, and reset signals in different reset modes will not be reset at the same time.

7. The method according to claim 1, characterized in that After determining the reset constraints for the cross-reset domain RDC check of the target chip according to the reset definition information, the reset sequence and the working mode, the method further includes: Performing an RDC check on the target chip according to the reset constraint to obtain a check result; Analyzing the inspection result to determine a modification strategy for the reset constraint; The reset constraint is modified according to the modification strategy to obtain a modified reset constraint.

8. A reset constraint determination device, characterized in that: include: A first determination module is used to determine reset definition information according to the RTL code of the target chip, wherein the reset definition information includes: a reset signal name corresponding to a reset control unit RCU in the target chip, a level of the reset signal corresponding to the RCU, and a valid level of the reset signal; and An acquisition module, used to acquire the reset sequence of each level RCU in the target chip and the working mode of the target chip; The second determination module is used to determine the reset constraint for the cross-reset domain RDC check of the target chip according to the reset definition information, the reset sequence and the working mode.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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