Simulation implementation method and system capable of controlling ideal voltage source

Abstract

The invention discloses a simulation implementation method and system capable of controlling an ideal voltage source, and aims to solve the problem that the voltage source cannot be dynamically adjusted to adapt to the state change of a circuit in the simulation of an existing analog circuit. The method comprises the steps of initializing a voltage reference value, selecting the number of power supply voltage sources, configuring power-on parameters, detecting power-on completion and stabilizing voltage, selectively adding noise, detecting circuit stability, setting power-down parameters, executing a power-down process and detecting a circuit state after power-down. According to the invention, the flexibility and efficiency of simulation can be improved, so that the circuit design and verification process is more efficient and accurate.

Description

Technical Field

[0001] The invention relates to a simulation implementation method capable of controlling an ideal voltage source, and also relates to a simulation implementation system capable of controlling an ideal voltage source, belonging to the technical field of analog circuit design. Background Art

[0002] In modern electronic devices, voltage sources are core components for power management and signal processing. Ideal voltage sources, i.e., power sources that can provide a constant output voltage, keep the output voltage constant regardless of load changes, are essential for fields such as test equipment, analog circuit system simulation and design. They are not only used to provide a stable reference voltage, but also to ensure the required voltage level in signal processing and transmission. However, the existing technology has limitations in analog circuit simulation: the voltage level can only be predicted before simulation and cannot be flexibly adjusted according to different situations, resulting in multiple simulations and manual selections when testing complex application scenarios, which seriously reduces the efficiency of verification work. In addition, analog circuit simulation is slow and involves continuous-time signal processing, especially in complex circuits or large-scale systems, the simulation time is long. At the same time, analog circuits in large-scale simulations may occupy a lot of computing resources, especially when a large number of parameter scans and optimizations are required, and resource consumption increases significantly.

[0003] In response to these challenges, analog simulation and controllable ideal voltage sources play a vital role in the electronics field. First, it can provide precise voltage output, which is essential for testing and verifying electronic devices and circuits. Engineers can simulate voltage changes under different working conditions by adjusting the output of the voltage source, thereby evaluating the performance and stability of electronic equipment. Secondly, during the design and verification of electronic systems, controllable ideal voltage sources allow engineers to test and adjust the voltage of each component to ensure the normal operation of the entire system. By simulating voltage conditions under various working conditions, engineers can build complex application scenarios, optimize system design, and discover and solve potential problems in the design.

[0004] However, the existing technology still has a common shortcoming: the voltage source output excitation is based on the voltage value at a preset time point, lacks the ability to respond to state changes in the simulation, and cannot judge and adjust according to the scene changes during the simulation, which limits the flexibility and accuracy of the simulation. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a simulation implementation method capable of controlling an ideal voltage source.

[0006] Another technical problem to be solved by the present invention is to provide a simulation implementation system capable of controlling an ideal voltage source.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, there is provided a simulation implementation method for a controllable ideal voltage source, comprising the following steps:

[0009] Step 1: Initialize voltage reference value;

[0010] Step 2: Select the number of power supply voltage sources;

[0011] Step 3: Configure the power-on parameters of multiple power supplies, including setting the starting voltage value, power-on completion voltage value, power-on time of each power supply, and turning on the corresponding power-on enable;

[0012] Step 4: Check that the power-on is complete and the voltage is stable, turn on the stable state enable, and ensure that the voltage source remains stable at the set voltage value;

[0013] Step 5: Selectively add noise;

[0014] Step 6: Check the circuit stability. If the signal indicating abnormal circuit status is pulled high, the simulation will stop and an unstable message will be displayed.

[0015] Step 7: Set the power-off parameters, including the starting power-off voltage value, the power-off completion voltage value, the power-off time, and turn on the corresponding power-off enable;

[0016] Step 8: Execute the power-off process, select and turn on the power-off enable, and start the power-off process of the simulated circuit;

[0017] Step 9: Check the circuit status after power failure. If the flag signal is not pulled high, it indicates that there is no error in the circuit during the power failure process. The simulation stops after the power failure is completed.

[0018] According to a second aspect of an embodiment of the present invention, there is provided a simulation implementation system for a controllable ideal voltage source, comprising a processor and a memory, wherein the processor and the memory are coupled; wherein the memory is used to store a computer program; and the processor is used to run the computer program stored in the memory to execute the above-mentioned simulation implementation method for a controllable ideal voltage source.

[0019] Unlike traditional voltage sources that can only preset voltage values ​​before simulation, the present invention can make selections according to the current circuit state during simulation to change the power-on state, which makes it unnecessary to manually calculate the time for some circuit states and then simulate again, greatly reducing the complexity and time required for verification work. During the simulation process, the present invention can adjust the preset time voltage value in real time according to the signal state, realizing the re-presetting of the signal time voltage during the simulation process. This capability greatly improves the flexibility and efficiency of simulation, making the circuit design and verification process more efficient and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A diagram of a simulation environment structure for implementing an embodiment of the present invention;

[0021] Figure 2 A flow chart of a simulation implementation method for a controllable ideal voltage source provided by an embodiment of the present invention;

[0022] Figure 3 A waveform logic diagram of an interactive process for finding an attack voltage value in an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of an interactive process for dynamically adjusting a voltage source in an embodiment of the present invention;

[0024] Figure 5 This is a waveform logic diagram of the interactive process of powering on and off multiple times in succession in an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of a simulation implementation system for a controllable ideal voltage source provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] The technical concept of the embodiment of the present invention is: to dynamically adjust the function of the voltage source output according to the real-time signal state of the circuit during the simulation process. The above improvement solves the problem that the traditional voltage source can only pre-set a fixed voltage value and cannot adapt to the changing state in the simulation, thereby improving the efficiency and flexibility of the simulation. Through this real-time adjustment, engineers can select and adjust the ideal voltage source in the simulation according to the different working scenarios of the circuit, avoiding the inefficiency caused by multiple manual selections and repeated simulations. In addition, the preset time voltage is changed according to the signal state during the simulation process, realizing the ability to reset the signal time voltage during the simulation process, thereby more accurately simulating the circuit behavior under real working conditions.

[0028] First embodiment

[0029] Figure 1 The simulation environment for implementing the embodiment of the present invention is shown. The simulation environment is composed of multiple functional modules working together to ensure accurate simulation and verification of the circuit under test under various conditions.

[0030] First, the simulation vector driver module (St_driver.vams) is the starting point of the simulation process and is responsible for activating the circuit under test in netlist.vams. It ensures that the circuit can work properly when the simulation starts by sending control signals, such as work enable. Next, the digital-to-analog conversion rule control module (Connrules.vams) intervenes, which defines the conversion rules between digital signals and analog voltages. Given that digital circuits only recognize 0 and 1, while analog circuits require specific voltage values, Connrules.vams ensures that digital high levels can be correctly converted to corresponding analog voltage values ​​to drive the analog circuit.

[0031] During the simulation process, the waveform loading module (Probe.vams) allows engineers to observe and analyze the response of the circuit through a graphical interface. This module loads the waveform data of the signal, providing engineers with a tool to deeply understand the behavior of the circuit and verify the accuracy of the design. In addition, the circuit status monitoring module (Monitor_check.vams) plays a monitoring role in the entire simulation process. It not only detects the flag signal of the circuit under test, but also monitors the power control command sent by St_driver.vams. Once the flag signal is detected, Monitor_check.vams passes the control signal to the controllable ideal voltage source, triggering it to work according to the predetermined time and voltage value. If the circuit state is abnormal, Monitor_check.vams will detect it in time and take corresponding measures, such as triggering the power-off process or stopping the simulation to prevent the error from spreading.

[0032] The circuit status monitoring module (Monitor_check.vams) can be implemented by using the "analogbeginend" code blocks in the Verilog-Ams language. These code blocks are specifically used to describe the behavior of analog circuits. They operate on a continuous time basis and can respond to dynamic changes in the circuit.

[0033] It should be noted that in different embodiments of the present invention, the flag signals for different functional modules are diverse. For example, in the attack module, the signal may be the attack signal output by the attack module; and in the voltage stabilization module, it may be the output voltage value. These signals need to be connected to the "monitor_check.vams" monitoring module in the simulation environment according to the different functions being tested. The monitoring module will evaluate the input signal according to the preset judgment criteria.

[0034] Taking the power on and off test of the power supply as an example, when "monitor_check.vams" makes a judgment based on the established conditions and the conditions are met, it will send a flag = 1 signal to "st_driver.vams", indicating that the module under test has an error state. This will cause the driver module to interrupt the current preset operating state and execute a new state process, such as switching from the power-on state to the power-off process. At this time, "st_driver.vams" will activate the power-off drive of the "controllable ideal voltage source", input the preset power-off time and voltage value, and start the power-off process. On the contrary, if the judgment condition is not met, "monitor_check.vams" will keep outputting a flag = 0 signal to "st_driver.vams", indicating that the circuit under test is operating normally. In this case, the simulation will continue according to the normal preset drive mode, that is, it will remain stable after completing the power-on, and then power off.

[0035] The controllable ideal voltage source module is the core of the simulation environment. It can dynamically adjust the output voltage according to the instructions of Monitor_check.vams. This dynamic adjustment capability makes the simulation process more flexible and can adapt to different circuit states and working conditions. After receiving the power-on signal, the controllable ideal voltage source module will work according to the predetermined time and voltage value, transmit the voltage to the circuit under test, and drive the circuit under test to work. If the circuit has an error state, Monitor_check.vams will detect the change of the flag signal and take corresponding measures, such as triggering the power-off process or stopping the simulation.

[0036] Before the simulation begins, the Connrules.vams module first defines the digital-to-analog conversion rules to ensure that the digital signal can be correctly converted into analog voltage values. At the same time, the Probe.vams module is ready to load waveform data for subsequent signal monitoring and analysis.

[0037] Next, the St_driver.vams module acts as a simulation vector driver and starts sending control signals to activate the circuit under test in etlist.vams. This includes turning on the circuit's work enable to provide initial conditions for the circuit. The Monitor_check.vams module continuously monitors the state of the circuit under test during the simulation process, including flag signals and power control commands sent by St_driver.vams. Once the flag signal is detected, Monitor_check.vams passes the control signal to the controllable ideal voltage source module.

[0038] The ideal voltage source module can be controlled to dynamically adjust its output voltage according to the instructions of the Monitor_check.vams module. After receiving the power-on signal, the ideal voltage source module can be controlled to work according to the predetermined time and voltage value, transmit the voltage to the circuit under test, and drive the circuit to work normally. The Probe.vams module loads the signal waveform during the simulation process, allowing engineers to observe and analyze the response of the circuit in a graphical interface. This helps to verify whether the circuit design meets expectations.

[0039] After the simulation is completed, all functional modules work together to generate a simulation report, including circuit performance data and waveform analysis results. The entire simulation process is structured, starting from defining the conversion rules and loading signals, to the St_driver.vams module driving the circuit under test, and then to the Monitor_check.vams module monitoring the circuit status and controlling the voltage source. This structured process ensures the accuracy and efficiency of the simulation, enabling engineers to accurately control and monitor the circuit simulation process, thereby improving the reliability and performance of the circuit design.

[0040] Based on the above simulation environment, the first embodiment of the present invention first provides a simulation implementation method that can control an ideal voltage source. Figure 2 As shown, the method comprises at least the following steps:

[0041] Step 1: Initialize voltage reference value

[0042] Before the circuit under test (RTL) starts to operate normally, a reference voltage V must be input for the ideal voltage source model. REF In one embodiment of the present invention, V REF Set to 1 V. This reference voltage is the basis for the ideal voltage source model to calculate the output voltage stability, providing a stable starting point for the entire simulation process.

[0043] Step 2: Select the number of supply voltage sources

[0044] Next, the user needs to select the number of voltage sources that will be powered simultaneously. This step is determined by the complexity of the circuit design and the test requirements, and can be a single or multiple voltage sources.

[0045] Step 3: Configure the power-on parameters of multiple power supplies

[0046] If the user selects multiple power supplies, detailed settings will be made for each power supply (such as power supply A, power supply B, etc., up to five). Specifically, it includes setting the starting voltage value, power-on completion voltage value, power-on time of each power supply, and turning on the corresponding power-on enable. This process involves processing the data as a continuous time signal to simulate the power-on process of a real ideal power supply, ensuring that the power supply can gradually increase the voltage in the expected manner until it reaches a stable state.

[0047] In one embodiment of the present invention, the simulation environment is configured to control two power supplies, namely power supply A and power supply B, at the same time. For power supply A, the simulation parameters are set to a starting voltage of 0V, and the goal is to gradually increase to a power-on completion voltage value of 3V. This process is set to be completed within 10 microseconds (us), and the power-on enable of power supply A is started. Similarly, the simulation parameters of power supply B are also set, and its starting voltage is also 0V, but the power-on completion voltage value is slightly different, which is 3.3V, and the power-on time is longer, set to 20 microseconds. Like power supply A, the power-on enable of power supply B is also activated. Such a setting allows the simulation environment to simulate the process of two power supplies being powered on almost simultaneously but at different rates and different final voltage values, so that the performance and stability of the circuit in this specific power management scenario can be tested and verified.

[0048] Step 4: Check that power is on and the voltage is stable

[0049] After the power supply is set, the circuit is tested to see if it has completed power-on at the preset time. Once power-on is completed, the stable state enable is turned on to ensure that the voltage source remains stable at the set voltage value, providing continuous power for the normal operation of the circuit.

[0050] In one embodiment of the present invention, real-time monitoring is performed during the power-on process of power supply A and power supply B to ensure that they reach their respective power-on completion voltage values, i.e., 3V and 3.3V, within the set 10 microseconds and 20 microseconds, respectively. Once both power supply A and power supply B have completed the power-on process, the system will activate their stable state enable. This means that power supply A and power supply B will be maintained at their respective final voltage values, i.e., 3V and 3.3V, to ensure that the circuit continues to operate under these stable voltage conditions. Such a design allows the circuit to enter a stable working state immediately after power-on, providing a stable power supply environment for subsequent performance testing and verification.

[0051] Step 5: Add noise selectively

[0052] The user can choose whether to turn on the noise enable. If it is turned on, the user can further select the type of noise, including sine wave, square wave, triangle wave, etc., and set the amplitude of the noise to ±10% of the current voltage source. This step simulates the noise interference that the circuit may encounter in the actual working environment. If you choose not to turn on the noise enable, the voltage source will maintain the voltage of the current state and maintain a stable voltage input.

[0053] In one embodiment of the present invention, for power supply A, the system provides a noise enable option, allowing the user to selectively add noise to power supply A. In this particular case, the user selected a sine wave as the noise type and set the amplitude of the noise to ±10% of the current voltage value of power supply A. This means that once power supply A reaches its power-on completion voltage value of 3V, the system will superimpose a sine wave noise with an amplitude of ±10% of 3V, that is, ±0.3V, on its voltage. Such a setting can simulate the voltage fluctuations that power supply A may encounter in an actual working environment. In contrast, for power supply B, the user chooses not to add any noise, so power supply B will maintain its stable state of 3.3V power-on completion voltage value, ensuring that voltage source B provides a constant voltage input to facilitate testing the performance of the circuit without noise interference. This differentiated noise processing method allows engineers to evaluate the impact of noise on different power supplies and circuit parts separately.

[0054] Step 6: Check circuit stability

[0055] When the circuit is in a stable state, the stability of the circuit is tested. If the circuit is unstable, such as the abnormal state of the circuit flag signal is pulled high, the simulation will stop and prompt the instability information. This step ensures that potential stability problems can be discovered and solved in time during circuit design.

[0056] In one embodiment of the present invention, the key to stability detection is to monitor a specific flag signal, which should remain in a low level state when the circuit is working normally. If the flag signal is detected to be abnormally high, it indicates that the circuit may have encountered a problem, such as voltage fluctuations, overload or other error conditions that cause the circuit to not work properly. Once the system recognizes this high-level state, it will automatically trigger the simulation stop mechanism and immediately issue a prompt to the user, clearly indicating the unstable state of the circuit. This automated detection and response mechanism is an important part of ensuring the reliability and safety of circuit design, allowing engineers to promptly discover and resolve potential design defects.

[0057] Step 7: Set power-off parameters

[0058] After the circuit runs stably for a period of time, the power-off setting is performed, including setting the starting power-off voltage value, the power-off completion voltage value, the power-off time, and turning on the corresponding power-off enable.

[0059] Step 8: Execute the power-off process

[0060] Select and turn on the power-down enable to start simulating the power-down process of the circuit. This step simulates the sudden power-off situation that the circuit may encounter in actual application.

[0061] In one embodiment of the present invention, a series of operations are performed to simulate the power-off process of power supply A and power supply B. First, for power supply A, the starting power-off voltage value is set to 3V, which is the voltage value of power supply A in a stable state. Then, the power-off completion voltage value is set to 0V, which means that power supply A will be completely shut down. The power-off time is set to 10 microseconds (us), which is the time required for power supply A to drop from 3V to 0V. At the same time, the power-off enable of power supply A will be activated to start this process.

[0062] Similar steps are taken for Power Supply B. The start power-down voltage value is set to 3.3V, which is the voltage value of Power Supply B in the steady state. The power-down completion voltage value is also set to 0V, indicating that Power Supply B will also be completely shut down. The power-down time of Power Supply B is also set to 10 microseconds, the same as Power Supply A, to ensure that the two supplies can be powered down synchronously. Finally, the power-down enable of Power Supply B is turned on to start the power-down process.

[0063] In this way, the power-off process of Power A and Power B linearly decreasing from their respective stable voltage values ​​(3V and 3.3V) to 0V within 10 microseconds can be simulated, which helps to test and verify the behavior and stability of the circuit under power-off conditions.

[0064] Step 9: Check the circuit status after power failure

[0065] During the power-off process, the circuit status is checked again, especially whether the flag signal is pulled high. If the flag signal is not pulled high, it indicates that there is no error in the circuit during the power-off process. The simulation stops after the power-off is completed, and prompts that the simulation passed. If the flag signal is pulled high, the simulation will also stop and prompt an unstable message, indicating that there is a problem with the circuit during the power-off process.

[0066] In one embodiment of the present invention, a strict monitoring task is performed during the power-off process of power supply A and power supply B. The core of this monitoring process is to detect a key flag signal, which should remain at a low level under normal circumstances. After power supply A and power supply B drop from their respective starting voltage values ​​(3V and 3.3V) to 0V according to the predetermined power-off time (10 microseconds), the system will check the status of the flag signal. If the flag signal remains at a low level after the power-off is completed, it indicates that the circuit did not encounter any problems during the power-off process. The system will stop the simulation and display the message "Simulation Failed", which actually means that the simulation is successful because the circuit shows the expected stability.

[0067] On the contrary, if the flag signal is pulled high during the power-off process, it indicates that the circuit may have encountered an unstable condition, such as a voltage drop or current anomaly. In this case, the system will not stop the simulation, but will display "unstable information", indicating that a problem occurred during the power-off process and further inspection and adjustment are required. This automated detection and feedback mechanism is critical to ensuring the reliability of circuit design, allowing engineers to identify and resolve potential stability issues during the design phase.

[0068] Through the above steps, the power-on and power-off processes of the ideal voltage source can be fully simulated to ensure the reliability and stability of the circuit design under various working conditions.

[0069] In one embodiment of the present invention, it is assumed that the goal is to determine the exact voltage value generated by the attack. Due to the attack delay in the internal attack circuit, if the power-on process is too fast, the output voltage value may be inaccurate. In order to solve this problem, the advantage of the controllable ideal voltage source can be used to adopt a binary strategy. First, quickly power on to the "drive voltage" VDD to determine the approximate voltage range generated by the attack. Then, control the voltage source to power down to VDD / 2, and then power on again at a slower speed. When the attack occurs, power down to 3 / 4VDD again. In this way, the binary strategy can be used to accurately find the attack voltage value in a shorter time while saving simulation resources.

[0070] The specific steps of the binary strategy are as follows: First, the initial voltage value is set to VDD 1, that is, the full supply voltage VDD. After the first power-off, the voltage value VDD2 of the second power-on is set to half of VDD, that is, VDD / 2. Subsequently, the voltage value VDD3 of the third power-on is obtained by taking the average value of VDD 1 and VDD2 and slightly adjusting it. The calculation formula is (VDD-VDD / 2) / 2+VDD / 2, and the result is 3 / 4VDD. Then, the voltage value VDD4 of the fourth power-on is again obtained by taking the average value of VDD3 and VDD2 and slightly adjusting it. The calculation formula is (3 / 4VDD-VDD / 2) / 2+VDD / 2, and the result is 5 / 8VDD. This process is repeated continuously, and the voltage value VDD5 of the fifth power-on is calculated as (3 / 4VDD-5 / 8VDD) / 2+5 / 8VDD, and the result is 11 / 16VDD. It can be expressed as follows:

[0071] VDD 1: VDD

[0072] VDD2: VDD / 2;

[0073] VDD3: (VDD-VDD / 2) / 2+VDD / 2=3 / 4VDD;

[0074] VDD4: (3 / 4VDD-VDD / 2) / 2+VDD / 2=5 / 8VDD

[0075] VDD5: (3 / 4VDD-5 / 8VDD) / 2+5 / 8VDD=11 / 16VDD

[0076] …

[0077] And so on.

[0078] With this method, the voltage value after each power-on is the middle value of the previous voltage range, thereby gradually approaching the attack voltage, improving the search efficiency and saving simulation resources.

[0079] In one embodiment of the present invention, the voltage range is gradually narrowed down through continuous power-on and power-off processes to determine the attack voltage. The interaction process between the driving voltage and the enable signal and the flag signal is the key to ensuring the circuit stability and accuracy.

[0080] Figure 3 The following describes the interactive process of finding the attack voltage value in the simulation implementation. It details how to determine the attack voltage by gradually adjusting the voltage value, using a binary strategy. Figure 2 Steps 3 and 4 are closely related, namely, configuring power-on parameters and detecting power-on completion and voltage stabilization. Figure 3 The voltage changes and decision points in this process are shown, and how the voltage is dynamically adjusted based on the flag signal. The following are the detailed steps of this interactive process:

[0081] Step 1: First, set the first power-on parameters of the circuit, including the power-on time (time 1) and the target voltage value (VDD 1). Then, activate the power-on enable signal to start the power-on process.

[0082] Step 2: After power-on is completed, wait for the flag signal to be pulled high to indicate that the circuit has reached a stable state. Once the flag signal is pulled high, the stable enable signal is activated and will remain stable at the current voltage value for time2 to ensure the stability of the flag signal.

[0083] Step 3: After the time t ime2 is maintained stably, the power-off enable signal is activated and the power-off parameters are set, including the power-off time and the target voltage value (VDD2). At this point, the power-off process begins, and the above-mentioned binary strategy is used to determine the power-off threshold to save time and accurately find the attack voltage value.

[0084] Step 4: During the power-off process, the flag signal is continuously monitored. When the flag signal is pulled low, it indicates that the circuit state has changed. At this time, the VDD2 voltage value is maintained for time 2 to determine the new stable state of the circuit.

[0085] Step 5: Set the parameters for the second power-on, including the power-on time (time 1) and the new voltage value (VDD3), and start powering on.

[0086] Step 6: After power-on is completed, wait for the flag signal to be pulled high again, then activate the stable enable signal and keep the current voltage value unchanged to ensure the stability of the flag signal.

[0087] Step 7: After the time t ime2 is kept stable, the power-off enable signal is activated again, and new power-off parameters are set, including the power-off time and the target voltage value (VDD4), and the power-off process begins.

[0088] Step 8: During the power-off process, monitor the flag signal. When the flag signal is pulled low, it indicates that the circuit state changes again, and at this time, the voltage value of VDD4 is maintained for time t ime2.

[0089] Step 9: Set the parameters for the third power-on, including the power-on time (time 1) and the new voltage value (VDD5), and start powering on.

[0090] Step 10: After power-on is completed, wait for the flag signal to be pulled high, activate the stable enable signal, and collect the voltage value at this time, which is considered to be a relatively accurate voltage value.

[0091] Step 11: After the accurate voltage value is collected, the final power-off process is performed to reduce the voltage to ground (GND), and the voltage value collected when the third attack is generated is output as the final result.

[0092] The advantage of the above method is that it allows the voltage source to be dynamically adjusted during the simulation process to adapt to changes in the circuit state. Compared with the traditional simulation method, which requires stopping the simulation and modifying the control logic after an attack occurs, the method provided by the embodiment of the present invention can significantly improve the efficiency and accuracy of the simulation.

[0093] Next, how to dynamically adjust the voltage source is further described. Figure 4 shows a schematic diagram of the interactive process of dynamically adjusting the voltage source. It shows how to adjust the voltage parameters according to the signal status during the simulation. Figure 2 Steps five and six are related, namely, selectively adding noise and testing circuit stability.

[0094] Figure 4It shows how to adjust the voltage when instability is detected to ensure the accuracy and stability of the simulation. When a flag signal is encountered during the power-on process, the power-off operation is performed and then the power-on operation is performed again, including the following sub-steps:

[0095] (1) Set the expected power-on time x1, and the goal is to increase the voltage to the voltage value y1;

[0096] (2) Start the power-on process, so that the voltage gradually rises to the voltage value y1 within the time x1; during the power-on process, continuously check whether the flag signal changes;

[0097] (3) When the voltage reaches voltage value y2, if the flag signal is detected to be pulled high, the time point x2 at this time is recorded;

[0098] (4) At time x2, once the flag signal is detected to be pulled high, the power-down enable is activated immediately;

[0099] (5) At time x2, record the current voltage value y2 to prepare for the power-off process;

[0100] (6) Starting the power-off process according to the preset power-off time x3 and the target power-off voltage value y3;

[0101] (7) At time x3, the power-off process is completed to ensure that the voltage drops to the target power-off voltage value y3;

[0102] (8) At time x3, after the power-off is completed, the power-on enable is reactivated to prepare for the next round of power-on;

[0103] (9) Using the voltage value y1 as the new target voltage value, the power-on process is started again;

[0104] (10) Record the time point x4 when power-on is completed, and ensure that the voltage reaches the voltage value y1 at time x4.

[0105] Among them, the power-on and power-off processes can be described by a linear function curve.

[0106] Power-on process function y = (y1 / x1)x2;

[0107] Power-off process function y=y2-((y2-y3) / (x3-x2))x3;

[0108] Power on again Function y = (y1-y3) / (x4-x3)x4+y3

[0109] In this way, simulation testing can accurately simulate the dynamic response of the circuit when it encounters a specific signal, which is crucial for evaluating the stability and reliability of the circuit.

[0110] In another embodiment of the present invention, a scenario is simulated in which a flag signal is generated in a random manner to test the controllability of a voltage source. The specific simulation process is as follows: when the flag signal is detected, a power-down operation is immediately performed to reduce the voltage to ground (GND), and then the power-on process is restarted. After powering on again, the rising edge of the flag signal is detected again to ensure that the circuit can work normally at the new voltage level. This continuous power-on and power-off process demonstrates the flexibility and responsiveness of the voltage source control.

[0111] Figure 5 The waveform logic diagram shows the interaction process during steady state and after the flag signal is detected during the power-up process. It details how to control the voltage source during multiple power-up and power-down cycles to test the stability and performance of the circuit under different power management scenarios. Figure 2 Steps 7 and 8 are closely related, i.e. setting the power-off parameters and executing the power-off process. The following are the detailed steps of the test process:

[0112] Step 1: First, set up the circuit for the first power-up, which includes specifying the power-up time (time 1) and the target voltage value (VDD). The power-up enable signal is activated and the circuit starts to power up to VDD.

[0113] Step 2: After power-on, if no flag signal is detected at this stage, the stabilization enable is turned on to allow the circuit to stabilize at the VDD voltage for the expected time (time2).

[0114] Step 3: If the flag signal is detected to be pulled high at time 3 (in this example, the flag signal is a pulse signal that will be automatically cleared after being pulled high), this indicates that the circuit may have encountered a specific event or condition.

[0115] Step 4: Once the flag signal is detected, the power-down process starts immediately. This includes setting the power-down time (time4) and reducing the voltage to ground (GND).

[0116] Step 5: After the power is off, the stability enable will be turned on and the GND voltage will be maintained for a period of time (time5) to ensure that the circuit is stable after the power is off.

[0117] Step 6: After the stable state is maintained for time5, set the power-on enable again to start a new power-on cycle, power up to VDD, and the power-on time is time6.

[0118] Step 7: In the new power-on process, if the flag signal is detected to be pulled high again at time 7, the power-off operation is performed again to reduce the voltage to GND. After the power-off is completed, turn on the stability enable and maintain the GND voltage to ensure that the circuit is stable after power-off.

[0119] Through this series of steps, the stability and responsiveness of the controllable ideal voltage source provided by the embodiment of the present invention when facing a burst marker signal, as well as its adaptability to random events in practical applications can be verified.

[0120] In one embodiment of the present invention, in order to ensure the stability and accuracy of Verilog-Ams in simulation, the following steps may be followed to construct and implement a controllable ideal voltage source:

[0121] First, define a Verilog-Ams module named voltage_control, which will encapsulate all the voltage source control logic. In this module, you can declare all necessary parameters and variables, including the reference voltage VREF, the number of power supplies, the starting voltage of each power supply, the power-on completion voltage, the power-on time, and the power-off time.

[0122] During the initialization phase, the VREF voltage value is set to 1 V through the initial block of Verilog-Ams. This step ensures that the controllable ideal voltage source has a definite reference point when starting the simulation.

[0123] Next, use conditional statements (such as if, case) to implement the power selection logic, allowing the user to select one or more power supplies for simulation as needed. In the analog block of Verilog-Ams, use analog operators (such as <+) to process continuous time signals and simulate the power-on and power-off process of the voltage source.

[0124] In Verilog-Ams, the analog block is the core of analog circuit design, which provides designers with a behavioral-level method to simulate continuous-time circuit characteristics. This block is the basis for implementing analog circuit simulation, which allows the use of specialized analog operators such as <+ for analog voltage sources, <- for analog voltage sources, and analog functions such as V() and I() to obtain voltages and currents between nodes. The capabilities of the analog block are not limited to linear relationships, it also supports nonlinear equations, allowing the complex behavior of analog circuit elements to be accurately simulated. In addition, the analog block is able to handle time-dependent expressions, which allows the behavior of analog signals that change over time to be realistically reproduced. Statements in the analog block can also be set to event-driven, which means that they can respond in real time to any changes in the analog signal, ensuring the continuity and dynamics of the simulation process.

[0125] Within the analog block, designers can use the simulation functions provided by Verilog-Ams to precisely control the power-on process of the power supply. For example, through the V() function, the starting voltage of the power supply can be set and gradually adjusted to the predetermined power-on completion voltage during the power-on time, thereby simulating the actual power-on behavior of the power supply. Such simulation is not limited to a single power supply, but can be applied to multiple power supplies at the same time. Each power supply can be independently controlled according to its specific parameters to test and verify the performance and stability of the circuit under different power management strategies. In this way, the analog block provides designers with a powerful tool for implementing and evaluating complex analog circuit designs in the Verilog-Ams environment.

[0126] Verilog-Ams has the ability to process continuous-time signals, so in the simulation environment, the simulation accuracy can be controlled at any time by flexibly setting parameters. Specifically, the maximum time step of the simulation can be set to 200 picoseconds (ps). This setting helps to reduce the voltage step effect during the power-on process, making the power-on curve smoother, thereby improving the authenticity and accuracy of the simulation results.

[0127] During the simulation, the value of the flag signal is continuously monitored to evaluate the stability of the circuit. If the flag signal is pulled high, it indicates that the circuit may be abnormal. At this time, the $stop system task of Verilog-Ams is used to stop the simulation. In addition, noise can be added to the analog block, and a sine wave, square wave, or triangle wave can be generated through the analog function and superimposed on the voltage source to simulate the noise interference in the actual working environment.

[0128] After the circuit runs stably for a period of time, you can simulate the power-off process through the analog block, and gradually reduce the voltage value of the voltage source to 0V. At the end of the power-off process, check the flag signal again. If the flag signal is not pulled high, it means that the circuit remains stable during the power-off process. Use the $finish system task of Verilog-Ams to end the simulation and output the information that the simulation passed; if the flag signal is pulled high, use $stop to stop the simulation and report the unstable information.

[0129] Finally, the constructed Verilog-Ams is compiled into the simulation environment and simulated together with other circuit modules to verify the performance and stability of the circuit design under different power management scenarios. In this way, the reliability and effectiveness of the circuit design in practical applications can be ensured.

[0130] Second embodiment

[0131] Based on the above method, the second embodiment of the present invention provides a simulation implementation system capable of controlling an ideal voltage source. Figure 6As shown, the simulation implementation system includes a processor and a memory; wherein the memory is coupled to the processor and is used to store a computer program. When the computer program is executed by the processor, the processor implements the above-mentioned simulation implementation method of the controllable ideal voltage source.

[0132] Wherein, the processor is used to control the overall operation of the simulation implementation system to complete all or part of the steps of the above method. The processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. The memory is used to store various types of data to support the operation of the simulation implementation system, and these data can, for example, include instructions for any application or method for operating on the simulation implementation system, and application-related data. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc.

[0133] In an exemplary embodiment, the simulation implementation system can be implemented by a computer or a microprocessor, or by a product with a certain function, for executing the above method and achieving the same technical effect as the above method. Specifically, the computer can be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0134] In another exemplary embodiment, the present invention further provides a computer-readable storage medium including program instructions, which, when executed by a processor, implements the steps of the method in any of the above embodiments. For example, the computer-readable storage medium may be the above-mentioned memory including program instructions, which may be executed by a processor to complete the above-mentioned method and achieve the same technical effect as the above-mentioned method.

[0135] Compared with the prior art, the embodiment of the present invention uses the Verilog-Ams language for modeling, which allows continuous time signal processing of input data, thereby reducing the voltage steps in the power-on process with maximum accuracy, making the power-on process smoother and more realistic. This continuous time processing method not only improves the accuracy of the simulation, but also because the embodiment of the present invention is an ideal voltage source constructed at the code level, it can provide high-precision voltage output, which can theoretically reach the accuracy range covered by floating-point numbers.

[0136] On the other hand, during the simulation process, the embodiments of the present invention can adjust the preset time voltage value in real time according to the signal state, realizing the re-presetting of the signal time voltage during the simulation process. This capability greatly improves the flexibility and efficiency of the simulation, making the circuit design and verification process more efficient and accurate.

[0137] It should be noted that the above embodiments are only examples, and the technical solutions of the various embodiments can be combined, all within the protection scope of the present invention.

[0138] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0139] The above is a detailed description of the simulation implementation method and system of the controllable ideal voltage source provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A simulation implementation method for controlling an ideal voltage source, characterized in that The steps include: Step 1: Initialize voltage reference value; Step 2: Select the number of power supply voltage sources; Step 3: Configure the power-on parameters of multiple power supplies, including setting the starting voltage value, power-on completion voltage value, power-on time of each power supply, and turning on the corresponding power-on enable; Step 4: Check that the power-on is complete and the voltage is stable, turn on the stable state enable, and ensure that the voltage source remains stable at the set voltage value; Step 5: Selectively add noise; Step 6: Check the circuit stability. If the signal indicating abnormal circuit status is pulled high, the simulation will stop and an unstable message will be displayed. Step 7: Set the power-off parameters, including the starting power-off voltage value, the power-off completion voltage value, the power-off time, and turn on the corresponding power-off enable; Step 8: Execute the power-off process, select and turn on the power-off enable, and start the power-off process of the simulated circuit; Step 9: Check the circuit status after power failure. If the flag signal is not pulled high, it indicates that there is no error in the circuit during the power failure process. The simulation stops after the power failure is completed.

2. The simulation implementation method of the controllable ideal voltage source as claimed in claim 1, characterized in that Through the continuous power-on and power-off process, the voltage range is gradually narrowed to determine the attack voltage.

3. The simulation implementation method of the controllable ideal voltage source as claimed in claim 2, characterized in that The following sub-steps are included: Step 1: First, set the first power-on parameters of the circuit, including the power-on time and the first voltage value; then, activate the power-on enable signal to start the power-on process; Step 2: After power-on is completed, wait for the flag signal to be pulled high to indicate that the circuit has reached a stable state; Once the flag signal is pulled high, the stability enable signal is activated and will remain stable at the current voltage value for a preset time to ensure the stability of the flag signal; Step 3: After the preset time is maintained stably, the power-off enable signal is activated, and the power-off parameters are set, including the power-off time and the second voltage value; Start the power-off process and use the binary strategy to determine the power-off threshold to save time and accurately find the attack voltage value; Step 4: During the power-off process, the flag signal is continuously monitored; when the flag signal is pulled low, it indicates that the circuit state has changed, and at this time, the second voltage value is maintained for a preset time to determine the new stable state of the circuit; Step 5: Set the parameters for the second power-on, including the power-on time and the third voltage value, and start powering on; Step 6: After power-on is completed, wait for the flag signal to be pulled high again, then activate the stable enable signal, and keep the current voltage value unchanged to ensure the stability of the flag signal; Step 7: After the preset time is maintained stably, the power-off enable signal is activated again, new power-off parameters are set, including the power-off time and the fourth voltage value, and the power-off process is started; Step 8: During the power-off process, monitor the flag signal; when the flag signal is pulled low, it indicates that the circuit state changes again, and at this time, the fourth voltage value is maintained for a preset time; Step 9: Set the third power-on parameters, including the power-on time and the fifth voltage value, and start powering on; Step 10: After power-on is completed, wait for the flag signal to be pulled high, activate the stable enable signal, collect the voltage value at this time, and consider it to be the accurate voltage value; Step 11: After the accurate voltage value is collected, the final power-off process is performed to reduce the voltage to ground, and the voltage value collected in step 10 is output as the final result.

4. The simulation implementation method of the controllable ideal voltage source as claimed in claim 3, characterized in that The dichotomy strategy includes the following sub-steps: First, the power is quickly turned on to the driving voltage VDD to determine the approximate voltage range of the attack; then, the voltage source is controlled to power down to VDD / 2, and then powered up again at a slower speed; when the attack occurs, the power is turned off again to 3 / 4VDD, and so on.

5. The simulation implementation method of the controllable ideal voltage source as claimed in claim 1, characterized in that When a flag signal is encountered during the power-on process, powering on again after power-off operation includes the following sub-steps: (1) Set the expected power-on time x1, and the goal is to increase the voltage to the voltage value y1; (2) Start the power-on process, so that the voltage gradually rises to the voltage value y1 within the time x1; During the power-on process, continuously check whether the flag signal changes; (3) When the voltage reaches voltage value y2, if the flag signal is detected to be pulled high, the time point x2 at this time is recorded; (4) At time x2, once the flag signal is detected to be pulled high, the power-down enable is activated immediately; (5) At time x2, record the current voltage value y2 to prepare for the power-off process; (6) Starting the power-off process according to the preset power-off time x3 and the target power-off voltage value y3; (7) At time x3, the power-off process is completed to ensure that the voltage drops to the target power-off voltage value y3; (8) At time x3, after the power-off is completed, the power-on enable is reactivated to prepare for the next round of power-on; (9) Using the voltage value y1 as the new target voltage value, the power-on process is started again; (10) Record the time point x4 when power-on is completed, and ensure that the voltage reaches the voltage value y1 at time x4.

6. The simulation implementation method of the controllable ideal voltage source as claimed in claim 5, characterized in that A linear function curve is used to describe the power-on and power-off processes; among them, Power-on process function y = (y1 / x1)x2; Power-off process function y=y2-((y2-y3) / (x3-x2))x3; The power-on process function y=(y1-y3) / (x4-x3)x4+y3.

7. The method for simulating a controllable ideal voltage source according to any one of claims 1 to 6, characterized in that: Verilog-Ams language is used for modeling in order to perform continuous-time signal processing on the input data.

8. A simulation implementation system capable of controlling an ideal voltage source, characterized in that It comprises a processor and a memory, wherein the processor and the memory are coupled; wherein the memory is used to store a computer program; and the processor is used to run the computer program stored in the memory to execute the simulation implementation method of the controllable ideal voltage source as claimed in any one of claims 1 to 7.

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