Method for accelerating system-level simulation verification, electronic equipment and storage medium

Abstract

The invention discloses a method for accelerating system-level simulation verification, electronic equipment and a storage medium, and the method comprises the steps: building a register model in a simulation verification environment, and the register model comprises a built-in reading function used for accessing a target register through a backdoor path; reading and storing an initial value of a target register through a backdoor path of the register model after use case link establishment is completed; reading a current value of a target register in real time through a backdoor path of the register model in a case execution process, and comparing the current value with a predefined condition to verify a simulation state; when simulation is finished, the final value of the target register is read again through the backdoor path of the register model; and comparing the initial value with the final value, and if the initial value is not consistent with the final value, triggering an error report.

Description

Technical Field

[0001] The invention relates to the field of switching chips, and in particular to a method for accelerating system-level simulation verification, electronic equipment and storage medium. Background Art

[0002] With the rapid development of network communications, the scale of switching chips is getting larger and larger. Faced with the growing functional requirements, verification engineers are also facing great challenges. How to save simulation time in the large-scale verification process has become an urgent problem to be solved.

[0003] First, each use case needs to check the values ​​of a large number of status registers before the end of the simulation, such as the interrupt status register, error status register, back pressure register, fifo status, etc., to prevent unexpected phenomena. As the chip scale increases, the number of registers that need to be read will also increase, and this part will take longer and longer simulation time. Secondly, traditional register checking relies on the verifier's understanding of the final state, that is, the check requires the verifier to give an expected value. If the verifier has a misunderstanding, it may cause the check to fail, thereby missing the real bug. Summary of the invention

[0004] To achieve the above-mentioned purpose and other related purposes, the present invention discloses a method for accelerating system-level simulation verification, comprising the following steps: Step S1: establishing a register model in a simulation verification environment, wherein the register model includes a built-in read function for accessing a target register through a backdoor path; Step S2: after the use case chain is built, the initial value of the target register is read and stored through the backdoor path of the register model; Step S3: during the execution of the use case, the current value of the target register is read in real time through the backdoor path of the register model, and compared with the predefined conditions to verify the simulation state; Step S4: at the end of the simulation, the final value of the target register is read again through the backdoor path of the register model; Step S5: Compare the initial value with the final value, and trigger an error report if they are inconsistent.

[0005] Furthermore, the execution timing of step S2 is in the configure_phase stage of the UVM verification platform.

[0006] Further, the execution timing of step S4 is located in the shutdown_phase stage of the UVM verification platform.

[0007] Furthermore, the predefined condition in step S3 is an expected state value of the state machine, and if the current value does not match the expected state value, a real-time error alarm is triggered.

[0008] Furthermore, the target register includes at least one of an interrupt status register, an error status register, a back pressure register and a FIFO status register.

[0009] Furthermore, the backdoor path access is implemented through the UVM_BACKDOOR mode and does not occupy simulation time resources.

[0010] Furthermore, the establishment of the register model includes a status register mapping relationship defined in the protocol specification, and non-blocking reading is achieved through a built-in function.

[0011] Furthermore, when an error report is triggered in step S5, identification information of a specific register is associated to assist in locating the problem.

[0012] On the other hand, the present invention provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and the processor implements the above-mentioned method of accelerating system-level simulation verification when executing the computer program.

[0013] On the other hand, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program implements the above-mentioned method for accelerating system-level simulation verification when executed by a processor.

[0014] By adopting the above technical solution, the status check before the end of the simulation is performed by the traditional way of reading registers, and the reading time accounts for about 20%-30% of the entire simulation process. The use of the present invention to perform the status register check before the end of the simulation does not consume simulation time, and can reduce the time of the entire simulation process by 20%-30%, thereby improving the verification efficiency. The traditional register status check before the end of the simulation depends on the judgment of the verification personnel. The verification personnel are required to give the expected value. The present invention uses the value of the register after the link is established to compare with the register value before the end of the simulation, which can improve the simulation correctness and avoid the additional overhead caused by the verification personnel's incorrect judgment of the register status before the end of the simulation. When developing a use case, the current state will be obtained by reading the register during the execution of the use case. This part of the time takes up about 5%-10% of the entire simulation time on average. Using the present invention instead of the register check strategy in the use case can significantly speed up the simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which: Figure 1 The present invention is a flow chart of the method. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0017] Reference Figure 1 The embodiment of the present invention provides a method for accelerating system-level simulation verification, comprising the following steps: Step S1: establishing a register model in a simulation verification environment, wherein the register model includes a built-in read function for accessing a target register through a backdoor path; Step S2: after the use case chain is built, the initial value of the target register is read and stored through the backdoor path of the register model; The execution timing of step S2 is in the configure_phase stage of the UVM verification platform.

[0018] Step S3: during the execution of the use case, the current value of the target register is read in real time through the backdoor path of the register model, and compared with the predefined conditions to verify the simulation state; The predefined condition in step S3 is the expected state value of the state machine. If the current value does not match the expected state value, a real-time error alarm is triggered.

[0019] Step S4: at the end of the simulation, the final value of the target register is read again through the backdoor path of the register model; The execution timing of step S4 is located in the shutdown_phase stage step of the UVM verification platform.

[0020] S5: Compare the initial value with the final value, and trigger an error report if they are inconsistent.

[0021] The present invention realizes accelerated simulation and improves verification efficiency by optimizing the register reading method and improves verification accuracy by optimizing the register value comparison method.

[0022] First, establish a register model for the status register that needs final_check.

[0023] There is a built-in function in the register model: read, which is used to read the value in the register backdoor path. The read function can be placed in the configure_phase in the UVM platform, and configure_phase is located in base_test.sv.

[0024] After the use case chain is built, the register value is read using the register model backdoor access method and recorded. This step does not consume any simulation time.

[0025] Example: reg_model.INTERRUPT_REQ.read(status,rdata,UVM_BACKDOOR); During the use case simulation, if there is a need to check registers, the register model backdoor access method can be used to read the register value and compare it with the expected value. This step is placed in the run_phase of each use case. Different use cases may need to check different registers.

[0026] Specifically, taking the PCIE protocol as an example, the use case often needs to check the value of the LTSSM status register. The backdoor path reading process is: reg_model.LTSSM_REQ.read(status,rdata_ltssm,UVM_BACKDOOR); During the use case execution, it is necessary to determine whether the ltssm state machine is in the L0 state. If not, an error is reported.

[0027] Specifically, they include: if(rdata_ltssm !='h10)begin `uvm_error(get_type_name(),$sformatf("check fail for L0 state") end Before each use case simulation ends, read the register value again using the register model backdoor access method and record it. This step does not consume simulation time at all. This step is placed in UVM shutdown_phase, and shutdown_phase is located in base_test.sv. Compare the value obtained in this step with the value in the read register backdoor path. If they are not equal (for example, rdata!=rdata1), an error is reported. The verification personnel analyze which register check has a problem based on the error report. Example: reg_model.INTERRUPT_REQ.read(status,rdata1,UVM_BACKDOOR).

[0028] The method of the present invention uses the traditional way of reading registers to perform a status check before the end of the simulation, and the reading time accounts for about 20%-30% of the entire simulation process. Using the present invention to perform a status register check before the end of the simulation does not consume simulation time, and can reduce the time of the entire simulation process by 20%-30%, thereby improving verification efficiency. The traditional register status check before the end of the simulation depends on the judgment of the verification personnel. The verification personnel are required to give an expected value. The present invention uses the value of the register after the link is established to compare with the register value before the end of the simulation, which can improve the simulation correctness and avoid the additional overhead caused by the verification personnel's incorrect judgment of the register state before the end of the simulation. When developing a use case, the current state will be obtained by reading the register during the execution of the use case. This part of the time takes up about 5%-10% of the entire simulation time on average. Using the present invention instead of the register check strategy in the use case can significantly speed up the simulation.

[0029] On the other hand, the present invention provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and the processor implements the above-mentioned method of accelerating system-level simulation verification when executing the computer program.

[0030] On the other hand, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program implements the above-mentioned method for accelerating system-level simulation verification when executed by a processor.

[0031] Those skilled in the art will appreciate that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined.

[0032] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0033] It can be known from the description of the above implementation modes that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute the methods described in the various implementation modes of the present application or certain parts of the implementation modes.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for accelerating system-level simulation verification, characterized in that: The following steps are involved: Step S1: establishing a register model in a simulation verification environment, wherein the register model includes a built-in read function for accessing a target register through a backdoor path; Step S2: after the use case chain is built, the initial value of the target register is read and stored through the backdoor path of the register model; Step S3: during the execution of the use case, the current value of the target register is read in real time through the backdoor path of the register model, and compared with the predefined conditions to verify the simulation state; Step S4: at the end of the simulation, the final value of the target register is read again through the backdoor path of the register model; Step S5: Compare the initial value with the final value, and trigger an error report if they are inconsistent.

2. The method for accelerating system-level simulation verification according to claim 1, characterized in that: The execution timing of step S2 is in the configure_phase stage of the UVM verification platform.

3. The method for accelerating system-level simulation verification according to claim 1, characterized in that: The execution timing of step S4 is located in the shutdown_phase stage of the UVM verification platform.

4. The method for accelerating system-level simulation verification according to claim 1, characterized in that: The predefined condition in step S3 is the expected state value of the state machine. If the current value does not match the expected state value, a real-time error alarm is triggered.

5. The method for accelerating system-level simulation verification according to claim 1, characterized in that: The target register includes at least one of an interrupt status register, an error status register, a back pressure register and a FIFO status register.

6. The method for accelerating system-level simulation verification according to claim 1, characterized in that: The backdoor path access is implemented through the UVM_BACKDOOR mode and does not occupy simulation time resources.

7. The method for accelerating system-level simulation verification according to claim 1, characterized in that: The establishment of the register model includes a status register mapping relationship defined in the protocol specification, and non-blocking reading is achieved through a built-in function.

8. The method for accelerating system-level simulation verification according to claim 1, characterized in that: When an error report is triggered in step S5, the identification information of the specific register is associated to assist in locating the problem.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the method for accelerating system-level simulation verification as claimed in any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: A computer program is stored, and when the computer program is executed by a processor, the method for accelerating system-level simulation verification according to any one of claims 1 to 8 is implemented.

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