Method and device for constructing circuit model of electro-thermal migration effect of interconnects

Abstract

The disclosed embodiments relate to the technical field of package interconnect reliability analysis. A method and apparatus for constructing a circuit model for the electro-thermal migration effect of interconnects is provided. Based on the Korhonen governing equations and boundary conditions, the electro-thermal migration effect is converted into circuit parameter changes, capturing the significant influence of temperature and temperature gradients on atomic migration. An equivalent circuit model of the interconnect under the electro-thermal migration effect is derived. An improved node analysis method is used to determine the circuit matrix equation corresponding to the equivalent circuit model. The circuit matrix equation is then subjected to dimensionality reduction to obtain the electro-thermal migration effect circuit model of the interconnect. This method effectively compresses the system dimensions, thereby reducing computational complexity and significantly improving solution efficiency. This method enables rapid analysis of stress evolution in complex multi-branch interconnects and dynamic simulation of void length evolution, balancing both accuracy and efficiency requirements.

Description

Technical Field

[0001] The present disclosure relates to the technical field of package interconnect reliability analysis, and in particular to a method and device for constructing an electro-thermal migration effect circuit model of an interconnect line. Background Art

[0002] Aging and failure issues caused by electromigration (EM) have become a major issue that needs to be addressed in the reliability of integrated packaging in advanced nanotechnology. Electromigration refers to the process by which, under high current density, electron momentum in interconnects is transferred to metal atoms, causing them to gradually migrate from their lattice positions. Furthermore, the thermal migration (TM) effect significantly contributes to atomic migration. Thermal migration refers to the migration of atoms caused by temperature gradients, where atoms tend to move from high temperatures to low temperatures. As technology advances toward miniaturization and three-dimensional stacked integration, the impact of TM will become more prominent, but most existing technologies do not fully consider the impact of TM on the atomic migration process.

[0003] Currently, physics-based EM analysis methods primarily perform analysis by solving partial differential equations (PDEs) induced by stress diffusion governed by the Korhonen governing equation. The Korhonen governing equation describes the time evolution of stress within a conductor and is an important theoretical basis for studying electromigration failure. This approach typically relies on introducing boundary conditions and initial conditions at the nodes of the interconnect structure to accurately track stress changes in a multi-branch interconnect tree. However, due to the complexity of the multi-branch interconnect structure and the diversity of boundary conditions, the boundary conditions and initial conditions that need to be handled during the solution process are relatively complex, which not only increases the computational difficulty but can also lead to decreased solution efficiency and accuracy, posing significant challenges to practical applications.

[0004] Furthermore, computational acceleration methods such as model reduction and macromodeling, such as the Krylov subspace method and singular value decomposition, are relatively mature. These methods can significantly improve computational efficiency, especially in large-scale, complex systems. However, their application to electro-thermal migration issues remains limited, and their potential has yet to be fully explored. Summary of the Invention

[0005] The present disclosure aims to solve at least one of the problems existing in the prior art and provides a method and device for constructing an electro-thermal migration effect circuit model of an interconnect line.

[0006] One aspect of the present disclosure provides a method for constructing an electro-thermal migration effect circuit model of an interconnect, the method comprising:

[0007] Based on the Korhonen governing equations and boundary conditions, the equivalent circuit model of the interconnect under the electro-thermal migration effect is derived;

[0008] Determine the circuit matrix equation corresponding to the equivalent circuit model using an improved node analysis method;

[0009] Dimensionality reduction processing is performed on the circuit matrix equation to obtain an electro-thermal migration effect circuit model of the interconnection line.

[0010] Optionally, the derivation of an equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen governing equation and boundary conditions includes:

[0011] Dividing the interconnect into a plurality of line segment units, and assuming that each of the line segment units is consistent in terms of current density, temperature, and temperature gradient;

[0012] The physical meanings of voltage, current, resistance, and capacitance are mapped to the relationship between voltage and diffusion flux of the electro-thermal migration effect, and the resistance, capacitance, and current in the equivalent circuit model corresponding to the line segment unit are expressed as:

[0013] ;

[0014] ;

[0015] ;

[0016] Where i represents the number of the line segment unit; represents the resistance in the equivalent circuit model corresponding to the i-th line segment unit; represents the capacitance in the equivalent circuit model corresponding to the i-th line segment unit; represents the current in the equivalent circuit model corresponding to the i-th line segment unit; represents the Boltzmann constant; represents the temperature in the equivalent circuit model corresponding to the i-th line segment unit; represents the length of the equivalent circuit model corresponding to the i-th line segment unit; represents the diffusion coefficient in the equivalent circuit model corresponding to the i-th line segment unit; represents the cross-sectional area in the equivalent circuit model corresponding to the i-th line segment unit; represents the first scale factor; represents the bulk modulus; represents the atomic volume; represents the second scale factor; Indicates the amount of electron charge; represents the effective valence charge; represents resistivity; represents the current density in the equivalent circuit model corresponding to the i-th line segment unit; represents atomic transport heat; Represents displacement in space.

[0017] Optionally, the determining the circuit matrix equation corresponding to the equivalent circuit model by using an improved node analysis method includes:

[0018] Using the improved node analysis method, the circuit matrix equation of the void nucleation stage is expressed as:

[0019] ;

[0020] in, They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage, respectively. represents a vector consisting of voltages of n nodes obtained by dividing the interconnect into a number of line segment units, express rate of change;

[0021] Based on the improved node analysis method, it is assumed that the interconnection line A void is formed at the hole, and the circuit matrix equation in the void growth stage is expressed as;

[0022] ;

[0023] ;

[0024] in, Indicates the location of the generated cavity; represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage respectively; represents the capacitance indicating the predicted void length and , represents the third scale factor; represents the conductance used to indicate the void boundary condition and ; Indicates the initial length of the cavity when it is generated; They represent the node voltage and current source of the line segment unit where the void is located.

[0025] Optionally, performing dimensionality reduction processing on the circuit matrix equation to obtain the electro-thermal migration effect circuit model of the interconnect line includes:

[0026] According to the circuit matrix equation, a transient voltage node equation and a stress conversion equation are constructed; wherein the transient voltage node equation is expressed as: ;

[0027] The stress conversion equation is expressed as: ;

[0028] in, Initial voltage value ; Represent the initial voltage values ​​corresponding to the 1st, 2nd,…,nth nodes respectively; Respectively represent the capacitance matrix, conductance matrix, and current source matrix of the circuit matrix equation; in the void nucleation stage, The values ​​of ; During the cavity growth stage, The values ​​of ; express Stress at time; transpose matrix of matrix L for A matrix of order , which means that r samples are selected from n nodes for the measurement of stress Σ; T represents the transpose of the matrix;

[0029] Based on the Arnoldi method, when When the initial voltage value is not 0, the macro modeling of the system is performed, and the Laplace transform of the transient voltage node equation is performed to obtain the stress vector in the complex frequency domain. :

[0030] ;

[0031] in, represents a complex variable; represents the current in the equivalent circuit model corresponding to the nth line segment unit; A represents the first intermediate variable and ; R represents the second intermediate variable and ;

[0032] Corresponding stress vector Perform Taylor expansion, calculate the coefficient matrix of the expansion, and use QR decomposition to determine the basis vectors, and construct the space transformation matrix X based on the basis vectors:

[0033] ;

[0034] Among them, q represents the order after dimensionality reduction;

[0035] Use the spatial transformation matrix X to Performing order reduction, we get:

[0036] ;

[0037] ;

[0038] ;

[0039] ;

[0040] in, Respectively represent the reduced ;

[0041] use The transient voltage node equation is reduced in dimension to obtain the electro-thermal migration effect circuit model of the interconnect:

[0042] ;

[0043] in, express The rate of change.

[0044] Optionally, the construction method further includes: verifying the electro-thermal migration effect circuit model.

[0045] Optionally, verifying the electro-thermomigration effect circuit model includes:

[0046] The electro-thermal migration effect circuit model is solved using a SPICE solver or an Euler iteration method to reconstruct the distribution of the high-dimensional stress field. The distribution of the high-dimensional stress field is expressed as: , and obtain the corresponding model simulation results; among them, express The corresponding high-dimensional stress field and ;

[0047] Using a finite element method to simulate the electro-thermal migration effect of the interconnection line to obtain corresponding finite element simulation results;

[0048] The model simulation results are compared with the finite element simulation results to obtain verification results of the electro-thermal migration effect circuit model.

[0049] Another aspect of the present disclosure provides a device for constructing an electro-thermal migration effect circuit model of an interconnect line, the device comprising:

[0050] A derivation module is used to derive the equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen governing equations and boundary conditions;

[0051] A determination module, configured to determine a circuit matrix equation corresponding to the equivalent circuit model using an improved node analysis method;

[0052] A dimensionality reduction module is used to perform dimensionality reduction processing on the circuit matrix equation to obtain an electro-thermal migration effect circuit model of the interconnection line.

[0053] Optionally, the construction device further comprises:

[0054] A verification module is used to verify the electro-thermal migration effect circuit model.

[0055] Another aspect of the present disclosure provides an electronic device, including:

[0056] at least one processor; and,

[0057] a memory communicatively connected to at least one processor; wherein,

[0058] The memory stores instructions that can be executed by at least one processor. The instructions are executed by the at least one processor so that the at least one processor can execute the method for constructing the electro-thermal migration effect circuit model of the interconnection line described above.

[0059] Another aspect of the present disclosure provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method for constructing the electro-thermal migration effect circuit model of the interconnect described above.

[0060] Another aspect of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the method for constructing the electro-thermal migration effect circuit model of the interconnection line described above.

[0061] Compared with the prior art, the present invention converts the electro-thermal migration effect into circuit parameter changes based on the Korhonen control equation and boundary conditions, captures the significant influence of temperature and temperature gradient on atomic migration, and derives the equivalent circuit model of the interconnect under the electro-thermal migration effect. The improved node analysis method is used to determine the circuit matrix equation corresponding to the equivalent circuit model, and the circuit matrix equation is subjected to dimensionality reduction processing to obtain the electro-thermal migration effect circuit model of the interconnect, which effectively compresses the system dimension, thereby effectively reducing the computational complexity and significantly improving the solution efficiency, so that it can quickly analyze the stress evolution in complex multi-branch interconnects, and dynamically simulate the evolution of void length, taking into account both accuracy and efficiency requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0063] Figure 1 A flow chart of a method for constructing an electro-thermal migration effect circuit model of an interconnect provided in one embodiment of the present disclosure;

[0064] Figure 2 A schematic diagram of an equivalent circuit model of an i-th line segment unit provided in another embodiment of the present disclosure;

[0065] Figure 3 A schematic diagram of an equivalent circuit model of a three-segment interconnect structure in the void nucleation stage according to another embodiment of the present disclosure;

[0066] Figure 4 A schematic diagram of an equivalent circuit model of a two-segment interconnect structure during a void growth phase according to another embodiment of the present disclosure;

[0067] Figure 5 The matrix obtained by solving another embodiment of the present disclosure is Schematic diagram of the first 24 largest eigenvalues;

[0068] Figure 6 A schematic diagram comparing model simulation results and finite element simulation results of a section of interconnect line at the void nucleation stage provided by another embodiment of the present disclosure;

[0069] Figure 7 A schematic diagram comparing model simulation results and finite element simulation results of a section of interconnect line during the void growth stage provided by another embodiment of the present disclosure;

[0070] Figure 8 A schematic structural diagram of a device for constructing an electro-thermal migration effect circuit model of an interconnect provided by another embodiment of the present disclosure;

[0071] Figure 9 A schematic structural diagram of an electronic device provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in each embodiment of the present disclosure, many technical details are provided to enable readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined and referenced with each other under the premise that there is no contradiction.

[0073] One embodiment of the present disclosure relates to a method for constructing an electro-thermal migration effect circuit model of an interconnect line, the process of which is as follows: Figure 1 As shown, including:

[0074] Step S110 : deriving an equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen governing equation and boundary conditions.

[0075] Specifically, the temperature of the thermal migration effect is determined by the Joule heating generated by the interconnect at a certain current density. Step S110 can determine the current density, temperature, and temperature gradient of the interconnect elements as inputs to the equivalent circuit model to calculate the circuit element values ​​of the equivalent circuit model. Furthermore, to ensure consistency in model units, multiple scaling factors can be introduced for variable conversion.

[0076] Exemplarily, step S110 includes: dividing the interconnect into a number of line segment units, and assuming that each line segment unit is consistent in terms of current density, temperature, and temperature gradient. In this case, the governing equation of electro-thermal migration is The governing equations of the non-inductive and non-leakage transmission line Therefore, the physical meanings of voltage, current, resistance, and capacitance can be mapped to the relationship between voltage and diffusion flux of the electro-thermal migration effect, and the resistance and capacitance in the equivalent circuit model corresponding to the line segment unit can be expressed as:

[0077] ; .

[0078] A current source is introduced to describe the flux flow between the starting and ending points of the line segment unit. According to the boundary conditions, the current of the i-th line segment unit can be expressed as: .

[0079] Where i represents the number of the line segment unit; represents the resistance in the equivalent circuit model corresponding to the i-th line segment unit; represents the capacitance in the equivalent circuit model corresponding to the i-th line segment unit; represents the current in the equivalent circuit model corresponding to the i-th line segment unit; represents the Boltzmann constant; represents the temperature in the equivalent circuit model corresponding to the i-th line segment unit; represents the length of the equivalent circuit model corresponding to the i-th line segment unit; represents the diffusion coefficient in the equivalent circuit model corresponding to the i-th line segment unit; represents the cross-sectional area in the equivalent circuit model corresponding to the i-th line segment unit; represents the first scale factor; represents the bulk modulus; represents the atomic volume; represents the second scale factor; Indicates the amount of electron charge; represents the effective valence charge; represents resistivity; represents the current density in the equivalent circuit model corresponding to the i-th line segment unit; represents atomic transport heat; Represents displacement in space.

[0080] Based on the above content, the equivalent circuit model of the i-th line segment unit is as follows Figure 2 As shown, and Respectively represent the end and starting end of the i-th line segment unit.

[0081] During the void growth phase, assuming the interconnect is at position A cavity is generated at the location of the cavity. Based on the boundary conditions of the cavity and the prediction method of the cavity length, the conductivity can be defined. and capacitors , which are used to describe the boundary conditions of the cavity and predict its length change. Indicates the location of the generated hole. Indicates the initial length of the cavity when it is generated. Represents the third scale factor.

[0082] Step S120: Determine the circuit matrix equation corresponding to the equivalent circuit model using an improved node analysis method.

[0083] Specifically, based on the equivalent circuit model of each line segment unit obtained in step S110 , the equivalent circuit models of the interconnects at different stages under the action of electro-thermal migration are written into a matrix form using an improved node analysis method.

[0084] For example, Figure 3 Taking a three-segment interconnect structure as an example, the equivalent circuit model of its void nucleation stage is shown. Figure 3 (a) shows a three-segment interconnection structure and four segment units at the connection. Figure 3 (b) in the formula indicates Figure 3 (a) shows the equivalent circuit model of four line segment units in the void nucleation stage. Figure 4 Taking a two-segment interconnect structure as an example, the equivalent circuit model of the void growth stage is shown. Figure 4 (a) shows a two-segment interconnection line structure and two line segment units on its right. Figure 4 (b) in the formula indicates Figure 4 (a) shows the equivalent circuit model of two line segment units in the void growth stage. Figure 3 and Figure 4 On this basis, the circuit matrix equations corresponding to the equivalent circuit models of the void nucleation stage and the void growth stage can be determined respectively.

[0085] Exemplarily, step S120 includes: using an improved node analysis method, expressing the circuit matrix equation in the void nucleation stage as: .in, They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage, respectively. A vector representing the voltages of n nodes obtained by dividing the interconnect into several line segment units. express The rate of change.

[0086] Based on the improved node analysis method, it is assumed that the interconnection line A void is formed at the hole, and the circuit matrix equation in the void growth stage is expressed as; ; .in, Indicates the location of the generated hole. They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage, respectively. represents the capacitance indicating the predicted void length and , Represents the third scale factor. represents the conductance used to indicate the void boundary condition and . Indicates the initial length of the cavity when it is generated. They represent the node voltage and current source of the line segment unit where the void is located.

[0087] Step S130 , performing dimensionality reduction processing on the circuit matrix equation to obtain an electro-thermal migration effect circuit model of the interconnection line.

[0088] Specifically, step S130 can be based on the circuit matrix equation obtained in step S120, and by applying the Arnoldi process, an improved PRIMA method can be further derived to perform dimensionality reduction processing on the circuit system. This can effectively reduce the dimension of the system while retaining the main dynamic characteristics of the system. On this basis, the improved PRIMA method uses orthogonal decomposition technology to extract the most representative low-dimensional subspace from the original high-dimensional circuit matrix, thereby generating a low-dimensional macro model as the electro-thermal migration effect circuit model of the interconnect line. This low-dimensional macro model can significantly reduce the computational complexity while maintaining sufficient accuracy, facilitating the rapid solution and analysis of complex electro-thermal migration problems. This order reduction method can greatly improve simulation efficiency, especially when dealing with large-scale multi-branch interconnect structures, it has significant advantages.

[0089] Exemplarily, step S130 includes: constructing a transient voltage node equation and a stress conversion equation according to the circuit matrix equation.

[0090] Among them, the transient voltage node equation is expressed as: The stress conversion equation is expressed as: .

[0091] in, Initial voltage value . They represent the initial voltage values ​​corresponding to the 1st, 2nd,…,nth nodes respectively. Represent the capacitance matrix, conductance matrix, and current source matrix of the circuit matrix equation respectively. In the void nucleation stage, The values ​​of During the cavity growth stage, The values ​​of . express The stress at the moment. The transpose matrix of matrix L for A matrix of order , which indicates that r samples are selected from n nodes for measuring stress Σ. T represents the transpose of the matrix.

[0092] Based on the Arnoldi method, when When the initial voltage value is not 0, the macro modeling of the system is performed, and the transient voltage node equation is Laplace transformed to obtain the stress vector in the complex frequency domain. :

[0093] .

[0094] in, Represents a complex variable. represents the current in the equivalent circuit model corresponding to the nth line segment unit. A represents the first intermediate variable and . R represents the second intermediate variable and .

[0095] Corresponding stress vector Perform Taylor expansion, calculate the coefficient matrix of the expansion, and use QR decomposition to determine the basis vectors, and construct the space transformation matrix X based on the basis vectors:

[0096] ;

[0097] Among them, q represents the order after dimensionality reduction. The value of q can be obtained by calculating the matrix For example, the number of eigenvalues ​​whose cumulative energy exceeds a preset value, such as 97%, can be selected as the order q after dimensionality reduction. This setting can significantly reduce the computational complexity while maintaining sufficient accuracy. For example, Figure 5 The matrix obtained by solving The first 24 largest eigenvalues ​​of , and the order after dimensionality reduction can be determined by the proportion of eigenvalues.

[0098] The solution process of the space transformation matrix X is:

[0099] .

[0100] Use the spatial transformation matrix X to Perform rank reduction to obtain a low-dimensional matrix:

[0101] ; ; ; .

[0102] in, Respectively represent the reduced .

[0103] use By reducing the dimension of the transient voltage node equation, we can obtain the circuit model of the electro-thermal migration effect of the interconnect: .in, express The rate of change.

[0104] Exemplarily, the method for constructing an electro-thermal migration effect circuit model of an interconnect further includes: verifying the electro-thermal migration effect circuit model.

[0105] Specifically, after obtaining the electro-thermal migration effect circuit model of the interconnect line, the electro-thermal migration effect circuit model can be solved by SPICE solver or Euler iteration, and the high-dimensional stress field distribution can be reconstructed to verify the accuracy and effectiveness of the electro-thermal migration effect circuit model.

[0106] Exemplarily, verifying the electro-thermomigration effect circuit model includes: solving the electro-thermomigration effect circuit model using a SPICE solver or an Euler iteration method, reconstructing the distribution of the high-dimensional stress field, and expressing the distribution of the high-dimensional stress field as: , and get the corresponding model simulation results. Among them, express The corresponding high-dimensional stress field and The finite element method (FEM) was used to simulate the electro-thermal migration effect of the interconnects, and the corresponding finite element simulation results were obtained. The model simulation results were compared with the finite element simulation results to obtain the verification results of the electro-thermal migration effect circuit model.

[0107] For example, Figure 6The figure shows the comparison between the model simulation results and the finite element simulation results of a section of interconnect line during the void nucleation stage. Figure 6 (a) is the stress distribution diagram at different time points. Figure 6 (b) is a comparison chart of the relative errors between the model simulation results and the finite element simulation results at different time points. Figure 7 The figure shows the comparison between the model simulation results and the finite element simulation results of a section of interconnect line during the void growth stage. Figure 7 (a) shows the change in void length when there is a void at the beginning (without going through the void nucleation stage). Figure 7 (b) shows the change in void length in the initial void-free state (after the void nucleation stage and into the void growth stage). Figure 6 and Figure 7 In the table, COMSOL refers to the finite element simulation results obtained using COMSOL software, and SPICE refers to the model simulation results obtained using the SPICE solver. The following Table 1 shows the simulation performance comparison between the model simulation results of multi-segment interconnects and the finite element simulation results. Among them, the number of segments and the number of nodes respectively represent the number of segments of the multi-segment interconnect and the number of nodes obtained by dividing the interconnect into a number of line segment units. q represents the order after dimensionality reduction, that is, the order of the electro-thermal migration effect circuit model of the interconnect. FEM represents the time used for solving using the finite element method. The order reduction, solution, and sum in the time of this method respectively represent the order reduction time, solution time, and the sum of the order reduction time and solution time used to solve the electro-thermal migration effect circuit model of the interconnect constructed using the embodiment of the present disclosure. The acceleration multiple represents the multiple of the task completion speed of solving the electro-thermal migration effect circuit model of the interconnect constructed using the embodiment of the present disclosure relative to the task completion speed of solving using the finite element method. The error represents the relative error between the model simulation result and the finite element simulation result.

[0108] Table 1 Comparison of simulation performance of multi-segment interconnects

[0109]

[0110] Combine Figure 6 、 Figure 7 As can be seen from Table 1, the electro-thermal migration effect circuit model of the interconnect constructed in the embodiment of the present disclosure can effectively reduce the computational complexity, improve the solution efficiency, and has high accuracy, providing a simplified but accurate analysis tool for complex multi-physics field coupling problems, thereby providing support for reliability evaluation and optimization in engineering design.

[0111] Compared with the prior art, the method for constructing a circuit model of the electro-thermal migration effect of interconnects provided in the embodiments of the present disclosure converts the electro-thermal migration effect into circuit parameter changes based on the Korhonen control equation and boundary conditions, captures the significant influence of temperature and temperature gradient on atomic migration, and derives an equivalent circuit model of the interconnects under the electro-thermal migration effect. The improved node analysis method is used to determine the circuit matrix equation corresponding to the equivalent circuit model, and the circuit matrix equation is subjected to dimensionality reduction processing to obtain the electro-thermal migration effect circuit model of the interconnects. This effectively compresses the system dimension, thereby effectively reducing the computational complexity and significantly improving the solution efficiency, enabling rapid analysis of stress evolution in complex multi-branch interconnects and dynamic simulation of void length evolution, while taking into account both accuracy and efficiency requirements.

[0112] Another embodiment of the present disclosure relates to a device for constructing an electro-thermal migration effect circuit model of an interconnect line, such as Figure 8 As shown, it includes a derivation module 810, a determination module 820, and a dimensionality reduction module 830.

[0113] The derivation module 810 is used to derive an equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen control equation and boundary conditions.

[0114] The determination module 820 is used to determine the circuit matrix equation corresponding to the equivalent circuit model by using an improved node analysis method.

[0115] The dimension reduction module 830 is used to perform dimension reduction processing on the circuit matrix equation to obtain an electro-thermal migration effect circuit model of the interconnection line.

[0116] Exemplarily, the apparatus for constructing the electro-thermo-migration effect circuit model of the interconnect further includes a verification module, which is used to verify the electro-thermo-migration effect circuit model.

[0117] The specific implementation method of the device for constructing the electro-thermal migration effect circuit model of the interconnect provided in the embodiment of the present disclosure can be found in the method for constructing the electro-thermal migration effect circuit model of the interconnect provided in the embodiment of the present disclosure, and will not be repeated here.

[0118] Compared with the prior art, the device for constructing a circuit model of the electro-thermal migration effect of interconnects provided in the embodiments of the present disclosure converts the electro-thermal migration effect into circuit parameter changes based on the Korhonen control equation and boundary conditions, captures the significant influence of temperature and temperature gradient on atomic migration, and derives an equivalent circuit model of the interconnects under the electro-thermal migration effect. Using an improved node analysis method, the circuit matrix equation corresponding to the equivalent circuit model is determined, and the circuit matrix equation is subjected to dimensionality reduction processing to obtain the electro-thermal migration effect circuit model of the interconnects. This effectively compresses the system dimension, thereby effectively reducing the computational complexity and significantly improving the solution efficiency, enabling rapid analysis of stress evolution in complex multi-branch interconnects and dynamic simulation of void length evolution, while taking into account both accuracy and efficiency requirements.

[0119] Another embodiment of the present disclosure relates to an electronic device, such as Figure 9 As shown, including:

[0120] at least one processor 901; and,

[0121] A memory 902 in communication with at least one processor 901; wherein,

[0122] The memory 902 stores instructions that can be executed by at least one processor 901. The instructions are executed by at least one processor 901 so that the at least one processor 901 can execute the method for constructing the electro-thermal migration effect circuit model of the interconnection line described in the above embodiment.

[0123] The memory and processor are connected using a bus, which can include any number of interconnected buses and bridges. The bus connects various circuits of one or more processors and memories. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits. These are all well known in the art and are therefore not described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over a wireless medium via an antenna. Furthermore, the antenna receives data and transmits it to the processor.

[0124] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0125] Another embodiment of the present disclosure relates to a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the method for constructing an electro-thermal migration effect circuit model of an interconnect as described in the above embodiment is implemented.

[0126] That is, those skilled in the art will understand that all or part of the steps in the methods described in the above embodiments can be implemented by instructing related hardware through a program. The program is stored in a storage medium and includes a number of instructions for causing a device (such as a microcontroller or chip) or a processor to execute all or part of the steps in the methods described in the various embodiments of the present disclosure. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0127] Another embodiment of the present disclosure relates to a computer program product, including a computer program. When the computer program is executed by a processor, the method for constructing an electro-thermal migration effect circuit model of an interconnection line described in the above embodiment is implemented.

[0128] Those skilled in the art will appreciate that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for constructing an electro-thermal migration effect circuit model of an interconnect, characterized in that: The construction method comprises: Based on the Korhonen governing equations and boundary conditions, the equivalent circuit model of the interconnect under the electro-thermal migration effect is derived; Determine the circuit matrix equation corresponding to the equivalent circuit model using an improved node analysis method; Performing dimensionality reduction processing on the circuit matrix equation to obtain an electro-thermal migration effect circuit model of the interconnection line; Based on the Korhonen governing equations and boundary conditions, an equivalent circuit model of the interconnect under the electro-thermal migration effect is derived, including: Dividing the interconnect into a plurality of line segment units, and assuming that each of the line segment units is consistent in terms of current density, temperature, and temperature gradient; The physical meanings of voltage, current, resistance, and capacitance are mapped to the relationship between voltage and diffusion flux of the electro-thermal migration effect, and the resistance, capacitance, and current in the equivalent circuit model corresponding to the line segment unit are expressed as: ； ； ； Where i represents the number of the line segment unit; represents the resistance in the equivalent circuit model corresponding to the i-th line segment unit; represents the capacitance in the equivalent circuit model corresponding to the i-th line segment unit; represents the current in the equivalent circuit model corresponding to the i-th line segment unit; represents the Boltzmann constant; represents the temperature in the equivalent circuit model corresponding to the i-th line segment unit; represents the length of the equivalent circuit model corresponding to the i-th line segment unit; represents the diffusion coefficient in the equivalent circuit model corresponding to the i-th line segment unit; represents the cross-sectional area in the equivalent circuit model corresponding to the i-th line segment unit; represents the first scale factor; represents the bulk modulus; represents the atomic volume; represents the second scale factor; Indicates the amount of electron charge; represents the effective valence charge; represents resistivity; represents the current density in the equivalent circuit model corresponding to the i-th line segment unit; represents atomic transport heat; Represents displacement in space.

2. The construction method according to claim 1, wherein The method of determining the circuit matrix equation corresponding to the equivalent circuit model by using the improved node analysis method includes: Using the improved node analysis method, the circuit matrix equation in the void nucleation stage is expressed as: ； in, They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage, respectively. represents a vector consisting of voltages of n nodes obtained by dividing the interconnection line into a number of line segment units, express rate of change; Based on the improved node analysis method, it is assumed that the interconnection line A void is formed at the hole, and the circuit matrix equation in the void growth stage is expressed as; ； ； in, Indicates the location of the generated cavity; represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage respectively; represents the capacitance indicating the predicted void length and , represents the third scale factor; represents the conductance used to indicate the void boundary condition and ; Indicates the initial length of the cavity when it is generated; They represent the node voltage and current source of the line segment unit where the void is located.

3. The construction method according to claim 2, characterized in that The dimensionality reduction processing of the circuit matrix equation to obtain the electro-thermal migration effect circuit model of the interconnection line includes: According to the circuit matrix equation, a transient voltage node equation and a stress conversion equation are constructed; wherein the transient voltage node equation is expressed as: ; The stress conversion equation is expressed as: ; in, Initial voltage value ; Represent the initial voltage values ​​corresponding to the 1st, 2nd,…,nth nodes respectively; Respectively represent the capacitance matrix, conductance matrix, and current source matrix of the circuit matrix equation; in the void nucleation stage, The values ​​of ; During the cavity growth stage, The values ​​of ; express Stress at time; transpose matrix of matrix L for A matrix of order , which means that r samples are selected from n nodes for the measurement of stress Σ; T represents the transpose of the matrix; Based on the Arnoldi method, when When the initial voltage value is not 0, the macro modeling of the system is performed, and the Laplace transform of the transient voltage node equation is performed to obtain the stress vector in the complex frequency domain. : ； in, represents a complex variable; represents the current in the equivalent circuit model corresponding to the nth line segment unit; A represents the first intermediate variable and ; R represents the second intermediate variable and ; Corresponding stress vector Perform Taylor expansion, calculate the coefficient matrix of the expansion, and use QR decomposition to determine the basis vectors, and construct the space transformation matrix X based on the basis vectors: ； Among them, q represents the order after dimensionality reduction; Use the spatial transformation matrix X to Performing order reduction, we get: ； ； ； ； in, Respectively represent the reduced ; use The transient voltage node equation is reduced in dimension to obtain the electro-thermal migration effect circuit model of the interconnect: ； in, express The rate of change.

4. The construction method according to claim 3, characterized in that The construction method further includes: verifying the electro-thermal migration effect circuit model.

5. The construction method according to claim 4, characterized in that The verifying of the electro-thermal migration effect circuit model includes: The electro-thermal migration effect circuit model is solved using a SPICE solver or an Euler iteration method to reconstruct the distribution of the high-dimensional stress field. The distribution of the high-dimensional stress field is expressed as: , and obtain the corresponding model simulation results; among them, express The corresponding high-dimensional stress field and ; Using a finite element method to simulate the electro-thermal migration effect of the interconnection line to obtain corresponding finite element simulation results; The model simulation results are compared with the finite element simulation results to obtain verification results of the electro-thermal migration effect circuit model.

6. A device for constructing a circuit model of an electro-thermal migration effect of an interconnect, characterized in that: The construction device comprises: A derivation module is used to derive the equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen governing equations and boundary conditions; A determination module, configured to determine a circuit matrix equation corresponding to the equivalent circuit model using an improved node analysis method; A dimensionality reduction module, configured to perform dimensionality reduction processing on the circuit matrix equation to obtain an electro-thermal migration effect circuit model of the interconnection line; Based on the Korhonen governing equations and boundary conditions, an equivalent circuit model of the interconnect under the electro-thermal migration effect is derived, including: Dividing the interconnect into a plurality of line segment units, and assuming that each of the line segment units is consistent in terms of current density, temperature, and temperature gradient; The physical meanings of voltage, current, resistance, and capacitance are mapped to the relationship between voltage and diffusion flux of the electro-thermal migration effect, and the resistance, capacitance, and current in the equivalent circuit model corresponding to the line segment unit are expressed as: ； ； ； Where i represents the number of the line segment unit; represents the resistance in the equivalent circuit model corresponding to the i-th line segment unit; represents the capacitance in the equivalent circuit model corresponding to the i-th line segment unit; represents the current in the equivalent circuit model corresponding to the i-th line segment unit; represents the Boltzmann constant; represents the temperature in the equivalent circuit model corresponding to the i-th line segment unit; represents the length of the equivalent circuit model corresponding to the i-th line segment unit; represents the diffusion coefficient in the equivalent circuit model corresponding to the i-th line segment unit; represents the cross-sectional area in the equivalent circuit model corresponding to the i-th line segment unit; represents the first scale factor; represents the bulk modulus; represents the atomic volume; represents the second scale factor; Indicates the amount of electron charge; represents the effective valence charge; represents resistivity; represents the current density in the equivalent circuit model corresponding to the i-th line segment unit; represents atomic transport heat; Represents displacement in space.

7. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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