Sub-pixel curve rendering in content generation systems and applications

Abstract

The invention discloses sub-pixel curve rendering in content generation systems and applications. The methods presented herein are used to generate image content that includes a fine object (e.g., a fine object that may be less than one pixel in width). Fine objects (e.g., hair) may be represented with curvilinear equations, and curves defined by these equations may be endowed with a width of expansion in order to perform a conservative hit test to efficiently identify pixels where the hair may intersect. For example, once a candidate pixel is identified by ray tracing or sampling, a false positive or almost no hair representation pixel may be removed from consideration. For the remaining pixels, a linear representation of the expansion curve may be used to determine intersections and vertices of blocks of pixels corresponding to the hair, which may be used to generate a convex geometry representative of the object. A percentage of pixel area occupied by the geometry may be used to determine an alpha or mix value for mixing pixel values of the hair or object with background pixel colors.

Description

Background Art

[0001] In various applications (such as, for example, animation or online video game creation), it may be necessary to generate fine details, such as may correspond to individual strands of hair or other such objects or features. In some cases, the width (or other dimensions) of an object such as an individual strand of hair may be less than one pixel, such as when the person or character to which the hair belongs is at least a minimum distance from a virtual camera used to determine the view of the scene for a determined resolution or number of pixels. In many image generation processes, rasterization is performed, in which small or fine objects (such as individual strands of hair or blades of grass) are represented as curves that are subdivided into a series of triangles. The rasterization pipeline will iterate through each triangle representation of the curve to "conservatively" rasterize these triangles so that they are each at least one pixel wide, which helps avoid problems such as aliasing or other fine features of sub-pixel wide curves. Processes such as ray tracing can sample screen space at a sub-pixel level by performing intersection tests with scene geometry; however, tracing a single primary ray is insufficient to correctly rasterize the curve, resulting in an image whose perceived quality may be unacceptable. Increasing the number of samples can improve quality, but may not be performed at a sufficient speed to meet a minimum frame rate or other such goals. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0003] Figure 1A , Figure 1B and Figure 1C shows an image including a curve for representing human hair according to at least one embodiment;

[0004] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F illustrates the stages of a sampling and rendering process for a fine curve according to at least one embodiment;

[0005] Figure 3A and Figure 3B illustrates the stages of an alpha blending process according to at least one embodiment;

[0006] Figure 4 illustrates components of an example content generation system in accordance with at least one embodiment;

[0007] Figure 5 An example process for generating image content including fine details according to at least one embodiment is shown;

[0008] Figure 6Components of a distributed system that may be used to perform content composition according to at least one embodiment are shown;

[0009] Fig. 7A Inference and / or training logic according to at least one embodiment is shown;

[0010] Figure 7B Inference and / or training logic according to at least one embodiment is shown;

[0011] Figure 8 An example data center system is shown in accordance with at least one embodiment;

[0012] Fig. 9 A computer system according to at least one embodiment is shown;

[0013] Fig.10 A computer system according to at least one embodiment is shown;

[0014] Fig.11 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0015] Fig.12 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0016] Fig.13 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0017] Fig.14 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline according to at least one embodiment; and

[0018] Fig.15A and Fig. 15B A data flow diagram of a process for training a machine learning model, and a client-server architecture for augmenting an annotation tool with a pre-trained annotation model, according to at least one embodiment are shown. DETAILED DESCRIPTION

[0019] In the following description, various embodiments will be described. For the purpose of explanation, specific configurations and details are set forth to provide a thorough understanding of the embodiments. However, it will also be appreciated by those skilled in the art that the embodiments may be practiced without the specific details. In addition, well-known features may be omitted or simplified to avoid obscuring the described embodiments.

[0020] The systems and methods described herein may be used, without limitation, in non-content generation and gaming systems, autonomous vehicles, semi-autonomous vehicles (e.g., in one or more advanced driver assistance systems (“ADAS”)), manned and unmanned robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles coupled to one or more trailers, spacecraft, boats, space shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, airplanes, construction vehicles, trains, underwater vehicles, remotely controlled vehicles (e.g., drones), and / or other vehicle types. In addition, the systems and methods described herein may be used for a variety of purposes, such as, but not limited to, machine control, machine motion, machine driving, synthetic data generation, model training or updating, perception, augmented reality, virtual reality, mixed reality, robotics, safety and surveillance, simulation and digital twins, autonomous or semi-autonomous machine applications, deep learning, environmental simulation, object or participant simulation and / or digital twins, data center processing, conversational AI, generative artificial intelligence with large language models (LLMs), light transport simulation (e.g., ray tracing, path tracing, etc.), collaborative content creation of three-dimensional (“3D”) assets, cloud computing, and / or any other suitable application.

[0021] The disclosed embodiments may be included in a variety of different systems, such as content generation or gaming systems, automotive systems (e.g., control systems for autonomous or semi-autonomous machines, perception systems for autonomous or semi-autonomous machines), systems implemented using robots, aviation systems, medical systems, boating systems, smart area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems for performing digital twin operations, systems implemented using edge devices, systems including one or more virtual machines (VMs), systems for performing synthetic data generation operations, systems implemented at least in part in a data center, systems for performing conversational AI operations, systems for performing generative AI operations using LLMs, systems for performing light transport simulations, systems for performing collaborative content creation of 3D assets, systems implemented at least in part using cloud computing resources, and / or other types of systems.

[0022] In at least one embodiment, the content generation system can render "thin" or "thin" objects, where at least one dimension of these objects (e.g., width) may be smaller than the width of a pixel of the image to be rendered. These objects (e.g., hair, threads, or fibers) can be represented by curves or curve equations, with each individual object represented by a separate curve or equation in world or screen space. In at least one embodiment, images of objects may need to be rendered in near real time, such as may need to meet a minimum frame rate target for an online video game. Due at least in part to the need to quickly generate individual images or video frames of content, traditional methods of rendering small or thin objects (e.g., whose width in screen space may be smaller than a pixel) may be flawed because they typically either require too much sampling to be performed at the target frame rate or compromises are made for efficiency, thereby reducing the quality of the final rendered output. When identifying fine objects (e.g., hair, grass, rope, wire, or other fine objects or materials) that will be used to determine the final pixel color of each pixel, the representative curve may have an initial width appropriate for (e.g.) hair, but may also have a determined "expansion" width that is at least one pixel wide, and in some cases one pixel wide on each side of the representative curve for a total width of two pixels to ensure that pixels that the expansion curve may pass through are not missed. Ray tracing (or another such light transport simulation method) may be performed on pixels that include at least a portion of the expansion curve to provide a conservative sampling or set of pixels that are covered or intersected by these curves. Pixels that are not "hit" by the traced rays relative to the object, or pixels that are determined to contain less than a threshold amount of objects, may be removed from consideration. For pixels that are hit by the traced rays, the convex geometry of the curve may be determined within the pixel. The normal of the curve within the pixel (which may be derived from the hit curve tangent and may be more stable) and the curve thickness may be used to represent the portion of the curve within a given pixel with a straight line. A pair of line segments and their corresponding linear equations can be determined that approximate the edge of the line representation of the curve within the pixel, and an intersection test can be performed for the boundary of the pixel to determine the intersection corresponding to these linear equations. The identified intersections can be used to determine which vertices of the pixel boundary or pixel block (quad) are contained within the width of the curve and form part of the geometry of the curve within the pixel block. The intersections and vertices can be used to determine the convex geometry corresponding to the curve within the pixel. The percentage of the space occupied by the geometry in the pixel block can be calculated, and the percentage (or fraction, etc.) can be used as an alpha value to perform alpha blending on the pixel. In alpha blending, the color of the foreground curve can be blended with the background color at the pixel position according to, for example, the alpha value or blending weight in the anti-aliasing process. It can be determined which curves should be considered for a given pixel.In at least one embodiment, for a pixel, only the curve that is "on top" or closest to the virtual camera is considered to avoid having to perform these operations on multiple curves that may intersect a given pixel but do not significantly affect the final value of the pixel or the overall appearance of the final rendered image. Other methods may also be used, such as random selection, artist specifications, etc. This method can be used to analytically rasterize fine curves for use in a ray tracing pipeline, thereby preserving fine details and producing high-quality images. This method can also efficiently calculate alpha or blending values ​​for determining pixel values ​​corresponding to these fine curves or objects.

[0023] Figure 1A An example image 100 that can be produced using an image generation process according to at least one embodiment is shown. In this example, a person or character to be rendered in the image has hair represented by a large number of individual hairs. Figure 1B As shown in image 110 of , a single hair 112 of a person or character can be represented or modeled individually and can be approximated using a curve having a determined width. A single hair will have a determined width in object space, and the width of the hair in screen space can depend in part on the "distance" between the hair and the virtual camera used to determine the view of the person or character, as well as any other objects of the scene or environment to be represented in the generated image. In at least some cases, the width of the hair in screen space will be less than the width (or other dimension) of a pixel. For example, in Figure 1C In the image 120 of FIG. 1 , a portion 122 of a hair is shown, and the width of the hair in the image is significantly smaller than the width of each pixel 124 at the current viewing distance and the resolution of the image to be generated. In some cases, the image may be generated at a lower resolution for transmission and then enlarged or upsampled for display, so that the width of the pixels in the generated image may be relatively larger relative to a single hair than the relative width of the pixels in the final generated image.

[0024] Methods according to various embodiments can analytically and efficiently rasterize thin curves for use in ray tracing pipelines, thereby preserving fine details and producing high-quality images. This method can involve using an increased curve width (or other representation) for ray tracing or sampling purposes, and the widened curve can be used to determine conservative sampling positions. Other methods can also be used, such as emitting a primary ray to a pixel, and then also considering rays traced to neighboring pixels, such as in a 3x3 pixel matrix centered on the pixel of interest, to determine whether there are any hits for a given object in at least one of these neighboring pixels. Although conservative, this method of determining hair sampling positions is much more efficient than sampling each individual pixel position that hits for a given hair. Conservative sample positions can correspond to those pixels that may include a portion of a thin curve, and an intersection algorithm can be used to determine whether the curve at least partially intersects with a given pixel. The portion of the pixel area occupied by the curve (e.g., hair) can then be used to determine a blending value (e.g., an alpha value) for determining the final pixel value of a given pixel in the image to be generated.

[0025] As an example, Figure 2A A portion of hair to be rendered in a subset of pixels 200 of an image to be generated is shown. In this example, a portion of a curve may be represented by a line segment 202 passing through these pixels 200. In other embodiments, non-linear representations or approximations of curves or objects may also be used. It may be assumed that for typical hair or thin objects, the curvature between adjacent pixels and individual pixels does not vary greatly, so relatively small segments of the curve may be approximated using straight lines or segments within the boundaries of a given pixel in pixel space. In at least one embodiment, the straight line segment may be determined or defined by the normal of the curve within the boundaries of that pixel. Once the segment is determined using the curve normal, the width of the curve may be applied, which will provide a small, straight band that can be used for purposes such as intersection detection and ray hit determination.

[0026] The width of line segment 202 can correspond to the approximate width of the corresponding hair or curve at a determined distance from a virtual camera used to generate an image of the object or scene. In this example, the width of line segment 202 is shown to be less than the width of individual pixels at the target resolution of the image to be generated. Because the segment occupies only a small portion of the area of ​​a given pixel, the ray tracing process may select sample positions that do not correspond to hair, and therefore may not represent the presence of hair in the pixel when rendered. Therefore, a method according to at least one embodiment may consider a wider or "inflated" line segment 202, at least for sampling, hit determination, or ray tracing purposes. Figure 2A In the example of , the dilated line segment has a width selected to be at least one pixel on each side of the line segment so that a majority of the area of ​​any pixel through which the line segment passes will be occupied by the dilated line segment.

[0027] Figure 2B An example view of a pixel set 200 is shown, including a set of sample locations 210 at which a ray tracing process may perform sampling or ray tracing for each pixel. In this example, the ray tracing process selects the same sample location within each individual pixel, or the same coordinate location within each pixel. However, the sample location may not be at the center of each pixel, as processes such as sampling jittering may be used, where the sample location varies slightly between consecutive frames in an attempt to capture sub-pixel detail even though the sampling is performed at the pixel level. As shown, only a small fraction of the sample points for pixels that a line portion passes through will "hit" the line segment 202. However, for a dilated line segment, every sample location in a pixel that a line portion passes through appears to hit the dilated line segment. Therefore, this sampling method can be used to quickly determine a set of pixels that may represent hair, curves, or other thin objects or fine features. While still conservative, this method is more efficient than other previous sampling methods in determining pixels to sample for a given hair. Figure 2C Such a candidate pixel set 220 is shown in , where the sample points are determined to hit the dilated line segment 204 .

[0028] like Figure 2C As shown, there may be some pixels where the sample point hits the dilated line segment, but the original curve does not actually intersect. These pixels can be identified as false positives, and knowing the equation and position of the curve or line segment can allow the algorithm to identify these pixels as false positives, and then remove them from further consideration. There may also be cases where the original curve, line segment, or hair only occupies a small portion of the pixel area, so considering different hairs or at least not considering the impact of the hair on the final pixel value of that pixel may produce better results because it may not affect the final color much, and if objects or features that do not affect the final pixel value much are removed from consideration, the resources required to render the image can be reduced. Therefore, the algorithm can also be used to determine the "coverage" of the curve in a given pixel, which can correspond to the portion or fraction of the pixel area of ​​the given pixel in screen space that is occupied by the line segment. As shown Figure 2D As shown, the shading 230 of the pixels can indicate the portion or coverage of hair in a single pixel and can also be used to indicate which pixels that were initially considered under the conservative approach were determined to be false positives. In this example, darker colors can represent higher pixel coverage values, although other approaches can also be used. In addition, Figure 2DThe shading 230 in is primarily for explanatory purposes, and in many embodiments, the coverage can be calculated mathematically without generating any graphical representation. Once the coverage values ​​are determined for the considered pixels for a given curve, a threshold (or at least one other selection criterion) can be applied to these values ​​to determine which pixels to exclude from consideration. For example, a threshold can be set so that if a curve occupies less than 5% of the pixel area, the curve is not used to determine the final color of the pixel. In some embodiments, a minimum threshold can be set so that any pixel with a coverage value greater than 0% or 1% will be considered, and its value can therefore be stored in the g-buffer of the shading pipeline.

[0029] After applying such a threshold and determining which pixels have at least a minimum coverage of the dilation curve, a set of candidate pixels 240 may be selected, such as Figure 2E As shown. In the forward shading pass of the ray tracing process, the same primary rays can be traced (or "shot", etc.) at the same sample positions to determine which rays (or sample points 242) actually hit or intersect the non-expanded original curve or line segment. The values ​​determined from this process can then be provided as input to an alpha blending process, for example, where the alpha values ​​(or other blending values) of individual pixels are determined based in part on the coverage values ​​of those pixels. In at least some embodiments, the alpha values ​​can be adjusted to resolve false positive hits in the ray tracing process for the image or frame. Figure 2F An example final set of pixel values ​​250 is shown for the set of pixels 200 of an image to be rendered, where the values ​​represent hairs in place in those pixels.

[0030] This approach can rasterize curves or other fine features in an analytical manner, and can use features that are wider than the curve to conservatively and efficiently determine the appropriate pixels for sampling. Once the pixel is identified, the geometric information of the curve can be used to determine whether the curve intersects a given pixel, and the percentage coverage within the pixel. For example, the location of a line segment representing the curve can be determined within a set of pixels. Using the line width, the edge location of the line segment can be determined. The edge location can be used to determine whether at least one edge of the line segment intersects the boundary (or "block") of a given pixel, and the portion of the pixel occupied by the line segment. Any of a variety of intersection algorithms can be used to determine whether at least one of these edges intersects the boundary of a given pixel, as well as the location and number of these intersections 302, 304. For any given pixel, there can be 0 (no intersection) to 4 intersections, with a maximum of two intersections for each edge of the curve (or representative line segment).

[0031] Once the intersection points are determined, the corner coordinates of the pixel boundaries can be tested to determine whether these coordinates are inside or outside the line segment. For example, using only the intersection points 302, 304 is not sufficient to determine whether the line is to the left or right of the line between these points 302, 304. Figure 3A As shown. A testing algorithm can be used to determine that three of the pixel corners 306, 308, 310 are within the line segment, and the coordinates of these corners can be identified. Once the intersection points 302, 304 and the included pixel corners 306, 308, 310 are identified, these points can be used to determine the convex geometric shape 312 that corresponds to the portion of the line segment represented in that given pixel. The percentage (or fraction or portion, etc.) of the pixel area occupied by the geometric shape can be calculated, which in this example may indicate that 85% of the pixel area is occupied by the line segment and 15% of the pixel area is not occupied. In this case, an alpha (or blending) value of 0.85 can be set, which determines a single final pixel value for the pixel in the rendered image, such as Figure 3B , where the final pixel value is a blended combination of the hair color and the background color, weighted by an alpha value, which may be given, for example, by a value = 0.15*(background color) + 0.85*(foreground / hair color) - or a value = α*foreground + (1-α)*background. In at least one embodiment, the hair may be considered to have a single color within a given pixel, since only a single color may be rendered for a given pixel in such a process, and any expected variation may be captured in the determined pixel value of the hair (or other foreground object) at that location. As used herein, a "pixel value" may refer to any value that may be used to generate an image or image data to represent the final color or appearance of the pixel, and may include, for example, other such options such as a color value or a brightness value. In at least one embodiment, the foreground pixel value and alpha value may be determined in a forward shading pass, and then blended with the background pixel value in a backward shading pass to derive the final pixel value (without regard to any additional or potential post-processing to be applied). Any such geometry is convex, and the positions or coordinates of all vertices can be averaged (or otherwise processed, such as by using a centroid function) to determine a point in the middle of the geometry, which can be used to decompose the geometry into triangles or other shapes for use in the shading and / or rendering process.

[0032] As used herein, alpha blending may refer to weighted blending or pixel value combination for determining the final pixel value (e.g., color value) of a pixel in pixel space. If there is only one visible object within the boundary of a pixel (from the perspective of a virtual camera used to generate an image), the color of that object may have a blending or "alpha" value of 1.0, so that the pixel value of the object at that position will correspond to the pixel value for that pixel (ignoring the possibility of transparency, reflection, glare, or other aspects that may affect the final pixel value, in at least one embodiment, it may be considered as another object at that pixel position). If there are two objects occupying equal portions of the pixel boundary, or if one object covers another object over the entire pixel area but has 50% transparency (or opacity), an alpha value of 0.5 may be used for each object so that the final pixel value is the average of the two pixel values. In many cases, when there are two or more visible objects (or at least considered visible) in a pixel area, the contributions to the final pixel color will be unequal, and determining an alpha value (or blending weight) may help determine the final pixel value based on these weighted contributions. Thus, the alpha value may be determined based on a variety of factors, including spatial, reflective, specular, and / or transmissive factors, and other such options. Thus, a hair that occupies 50% of the area of ​​a pixel and has an opacity value of 50% may have a calculated alpha value of 0.25.

[0033] In at least one embodiment, a pixel corresponding to a hair region may be represented by a single selected hair (or foreground object) and the background. Although there may be multiple hairs of different sub-pixel widths and at least partially visible at the current pixel location, the colors of these hairs are similar, and considering more than one hair per pixel may not significantly change the final pixel color, but may significantly increase the resources required to process all potential hairs on all potential pixels. In at least one embodiment, the hair rendering system may select (at most) one hair per pixel, such as the hair closest to the virtual camera or the "topmost" hair in the hair group, or the hair that occupies most of the space within the pixel. It makes sense to select the topmost hair because it is most likely to be perceived by the user if it is not rendered accurately. The human eye is less sensitive to outer hair or overlapping hair under an object. In many cases, the ends of the hair or the topmost hair are the most obvious and perceptible to the user, so they can be considered more important for realistic rendering.

[0034] In addition to reducing the resources required for rendering, selecting a single hair (or curve, etc.) per pixel location can also help increase rendering speed. For operations such as online games, it is very important that rendering occurs over the longest period of time. For example, if the game runs at a frame rate of 60 frames per second (fps), the rendering of each frame must be done within that frame rate. Being able to reduce the number of objects to be considered or sampled during rendering can help increase rendering speed, which is important as factors such as resolution, perceived quality, and fine detail levels continue to increase. By only having to consider at most one hair per pixel location instead of all possible hairs at that location, the amount of sampling and value processing to be performed can be significantly reduced, resulting in significant savings in resources, cost, and time. In at least one embodiment, this method can allow thin anti-aliased curves to be rendered in near real time using a ray tracing process. Intelligent sampling can be performed so that a large number of rays do not have to be fired to largely avoid intersections with a given hair or object. The methods described herein also allow high-quality rendering to be achieved using a minimum number of samples or rays per frame (e.g., one ray or one sample location per pixel location), and use sample jittering to try to further preserve fine sub-pixel details.

[0035] As described above, such methods of determining pixel values ​​in ray tracing or other such processes may be performed as part of an image generation process or system. Figure 4 Components of an example rendering (or content generation) pipeline that can be used with such a system or process are shown. Such a pipeline can be used to generate or synthesize one or more images, such as video frames in a sequence. In this example, pixel data 402 (which may include G-buffer data for a primary surface) for a current frame to be rendered can be received, which may include pixel data for various objects to be rendered in a scene from a viewpoint defined by a virtual camera. The pixel data can be provided as input to a reflection and refraction component 404 of the rendering pipeline. The reflection and refraction component 404 can attempt to determine the reflection and / or refraction of the pixel data and provide the data to a backprojection and G-buffer patching component 406, which can perform backpropagation to locate corresponding points of these reflections and refractions, and use the data to patch a G-buffer 418, which can provide updated input for subsequent frames to be rendered. The pixel data may then be provided to a light sample generation component 408 to perform light sampling, to a ray tracing lighting component 410 to perform ray tracing lighting, and to one or more shaders 412 (which may be implemented in hardware and / or software), which may set the pixel color of each pixel of the frame based at least in part on the determined lighting information (as well as other information such as color, texture, etc.). The results may be accumulated by an accumulation module 414 or component to generate an output frame 416 of a desired size, resolution, or format.

[0036] In at least one embodiment, the operations of pipeline 400 may be performed under the direction of a rendering manager 420 or other such system or process. The rendering manager may perform tasks such as directing ray tracing lighting component 410 to perform ray tracing to obtain samples at determined locations and perform hit tests. The rendering manager may use a curve manager component 422 or process to determine which object (e.g., hair) will be used as a foreground object for a given pixel, as well as to determine intersections and coverage that can be used to calculate alpha blending values. The curve manager 422 may then collaborate with the shader 412 during a shader pass to perform shading and blending tasks to determine final pixel values, including for those pixels where at least a portion of a fine object or curve (e.g., hair or bristles) is located.

[0037] In at least one embodiment, the light sample generation component 408 may perform a backprojection step. Once the backprojection pass is complete and the gradient surface parameters have been patched into the current G-buffer, the renderer can perform a lighting pass. Using information from the lighting pass and the lighting results from the previous frame, gradients can be calculated and then filtered and used for history rejection. This approach can be used to calculate robust temporal gradients between the current frame and the previous frame in a temporal denoiser of a ray tracing renderer. This backprojection-based approach can also work through reflections and refractions and can work with rasterized G-buffers. Some backprojection methods may omit G-buffer patching and may rely on the original current G-buffer samples. Patching the surface parameters can help reduce or eliminate false positives in the vast majority of cases, making the denoised image very stable but still able to respond quickly to lighting changes. Once the backprojection pass is complete and the gradient surface parameters have been patched into the current G-buffer, the renderer can perform a lighting pass. Using information from the lighting pass and the lighting results from the previous frame, gradients can be calculated.

[0038] In at least one embodiment, such a pipeline can generate images or video frames in a sequence, wherein at least a certain amount of temporal information is retained between frames. Thus, various types of information can be at least temporarily stored in one or more buffers between frames, for example, at least one graphics buffer can be involved, which can include or work with a color buffer, a motion vector buffer, and / or a depth buffer, as well as other such options. In at least one embodiment, a preprocessor (e.g., can be involved in one or more processes running on one or more processors on one or more computing devices) can receive as input the color information of the current frame generated by a rendering engine or application and the output of a warper such as a warp function or application executing one or more processors of one or more devices. In at least one embodiment, the warper receives as input the motion vector information of the current frame stored in the motion vector buffer, and as input the depth information of the current frame stored in the depth buffer. In at least one embodiment, the warper can receive this data directly from the application or renderer, and a dedicated buffer can be used. The temporal process can also take the high-resolution color data of the previous image in the sequence (stored in a history buffer) as input to the warper. Information for each final output image can also be stored in a history buffer for generating subsequent images or frames in the sequence. The warper may utilize the motion vectors and depth data to warp pixel data or color data of a particular feature of a previous image to a corresponding pixel location in a current image frame, effectively using the motion vectors to map corresponding pixel locations of features in the two images so that color values ​​of similar features may be compared and blended. The preprocessor may perform any relevant processing on the current color data from the color buffer or the warped previous color data from the warper. After any preprocessing, the data may be provided as input to a neural network, such as a deep learning (DL) based generator, which may analyze the data to determine pixel specific weights for each pixel location in the image to be generated. The generated data may be processed by a postprocessor, which may include one or more processes executed on one or more processors of one or more computing devices, which may output a final high resolution color image. In at least one embodiment, the postprocessor may also output information for storage in a high resolution color and history buffer for use in generating subsequent images in the current sequence.

[0039] In at least one embodiment, generating a frame using this approach may involve an application providing a low-resolution jittered input image and associated jitter values, a low-resolution backward motion vector for each individual input image pixel, and other quantities, such as exposure values ​​and a depth buffer, to a reconstruction algorithm. These low-resolution input (backward) motion vectors may be used to warp the previous frame output image to align with the geometry in the current time step. An upsampling algorithm may be used to upsample the low-resolution current frame image (after any denoising and detail enhancement discussed herein) to the resolution of the output image. A neural network may be used to infer a weighted value w for each output pixel (at the output resolution). In at least one embodiment, a high-resolution output image of the current frame may be created as follows:

[0040] Output = w*(upsampled current frame input image) +

[0041] (1-w)*(previous output image after deformation)

[0042] In this type of temporal image reconstruction algorithm, an important factor in the quality (IQ) of the resulting image may be the weighting factor w described above. In at least one embodiment, w should accommodate various criteria, including at least that when an area in the output image is occluded due to motion of objects in the rendered scene, the weighting factor should favor the current input image, or give greater weight to the color values ​​of the current image, such as when w=1.0. When an area in the output image is visible in a previous frame (and the shading is similar), the optimal weighting factor may result in an appropriate blend between these previous output images and the current input image. In at least one embodiment, this blending may be more favorable to historical data, such as when the value of w is close to zero because more frames have made the area visible.

[0043] The network can establish the prediction weighting based at least in part on the current frame input image and the deformed previous frame output image. In at least one embodiment, when the upsampled current image has values ​​that are significantly different from the deformed previous frame output image, and therefore will appear very different when displayed, the neural network can predict a high-valued weighting factor w, thereby giving more importance to the upsampled current frame input image. When the current image has values ​​similar to the deformed previous frame output image, and therefore will appear very similar when displayed, the neural network can predict a low-valued weighting factor w, thereby giving more importance to the deformed previous frame output image.

[0044] Figure 5An example process 500 for generating an image according to at least one embodiment is shown. It should be understood that for this process and other processes described herein, more, fewer or alternative steps may be performed, or performed in a similar or alternative order, or at least partially in parallel, within the scope of various embodiments, unless otherwise explicitly stated. In addition, although this example will be discussed for elongated objects (e.g., hair, grass, fiber, or rope), other types of objects or features may also be synthesized using this process within the scope of various embodiments. In this example, scene data for an image to be rendered is received 502) or otherwise obtained, which scene data may correspond to a single image or one of a sequence of images, such as a video frame of a scene. "Fine" objects can be identified 504 in the scene, which can be modeled using curve equations and coarseness or other such mechanisms or values. In some embodiments, a collection of such objects can be defined or identified, where such a modeling approach can be advantageously used, such as a character's "hair" comprising multiple individual hairs, rather than identifying each individual hair as such an object. In some embodiments, certain types of objects may specify such modeling in a classification or label, or may be defined using equations, which may then be used to identify or determine where such modeling may be beneficially applied.

[0045] In this example process, the curve can be modeled as a collection of line segments because the curvature does not usually vary significantly between adjacent pixels. Therefore, for one or more subsets of the image to be rendered, a linear approximation 506 of a fine object can be generated, wherein the linear approximation can be associated with a first thickness corresponding to the thickness of the object (e.g., hair) and an expansion thickness that can be based at least in part on the relative size of the pixels in the image to be rendered. In at least one embodiment, the width of the pixel is projected into screen space to determine a target width of the expansion curve, which can be at least two pixels wide to capture all potential pixels that the curve may intersect. The slope or orientation of the line segment can correspond to the normal vector of the curve within the pixel boundary. The expansion of the thickness can be performed in two directions relative to the elongated line segment or curve and is used to increase the area for ray tracing or sample selection, as described herein. The expansion width can also be at least partially dependent on the depth, because objects farther away from the virtual camera may require a larger expansion width to increase the sampling probability. Then, the elongated edge of the expansion segment can be described using a corresponding linear equation. Ray tracing (or another sampling process) may be performed 508 to determine a set of pixels where the sampled locations (or ray intersections) correspond to a dilated linear approximation of the object. These are referred to herein as "conservative" hits because the intersections are relative to the dilation coarseness. Such a process may help efficiently determine pixels for sampling objects that are smaller than a pixel width (e.g., a strand of hair), and may not be sampled frequently if a random sampling approach were to be used. The pixels in the set are selected using the dilation approximation and analyzed 510 by an algorithm (or other means) to eliminate false positives or pixels where the dilated object does not actually appear or intersect, as well as to remove from consideration pixels where the presence of an object in a pixel area is determined to be insignificant, such as where the area of ​​a single pixel occupied by the object is less than a threshold percentage.

[0046] For each remaining pixel, the geometry of the area or region of the pixel (in pixel space) occupied by the object can be determined 512. This can be determined in at least one embodiment by running an intersection test between the elongated edges of the object (or the linear equations of these edges) and the pixel boundary. For line segments of a specific width, where the normal of the representative curve in the pixel can be used to determine the line segment, the intersection test can look at each elongated edge to determine whether there are 0, 1 or 2 intersections with the pixel boundary. If the pixel boundary has at least one intersection with at least one edge, a coordinate test can be performed to determine which corners of the pixel boundary are included in the area of ​​the object (or thick line segment). In at least one embodiment, this can involve performing a dot product of the normal and determining the difference in sign. The included corners and intersections can be sorted, such as in a clockwise or counterclockwise manner, and used to determine the geometry of the object area representing a given pixel position. The percentage of the pixel area occupied by the geometry can be determined 514 for each corresponding pixel, where the percentage can be used to determine the blending weight of the object relative to the pixel value of the pixel position. Other factors can also be used, such as opacity or reflectivity in at least one embodiment. Once the blend or alpha value is determined for a given pixel, at least the foreground pixel value and the background pixel value may be blended according to the alpha value to determine a final pixel value for that pixel value 516. This final pixel value may then be used in generating the final output image, subject to any additional processing or modifications performed.

[0047] As an example, Figure 6An example networked system configuration 600 is shown that can be used to provide, generate, modify, encode, process and / or transmit image data or other such content. In at least one embodiment, a client device 602 can generate or receive session data using components of a content application 604 on the client device 602 and data stored locally on the client device. In at least one embodiment, a content application 624 executed on a server 620 (e.g., a cloud server or an edge server) can initiate a session associated with at least the client device 602, can use a session manager and user data stored in a user database 636, and can cause a content manager 626 to select content (e.g., one or more object representations, such as one or more geometric meshes with density information) from an object repository 634 for processing. The content manager 626 can collaborate with a rendering engine 628 or pipeline to generate such content. In at least one embodiment, the rendering engine 628 can work in conjunction with an image processing component 630 and / or a blending component 632 to attempt to determine the pixel values ​​to be used for each pixel of the image to be rendered, which may be part of a shading process. As described herein, this may include performing conservative hit testing and alpha value calculations for small or sub-pixel objects. At least a portion of the generated content (which may correspond to a composite image or data useful in generating such an image) may be transmitted to the client device 602 using an appropriate transmission manager 622 for transmission via download, streaming, or another such transmission channel. An encoder may be used to encode and / or compress at least a portion of such data before transmitting it to the client device 602. In at least one embodiment, a client device 602 receiving such content may provide the content to a corresponding control application 604, which may also or alternatively include a rendering engine 610, an image processor 612, and a mixing component 614 for selecting, providing, synthesizing, rendering, modifying, or using content for presentation on or by the client device 602 (or other purposes). The decoder may also be used to decode data received over the network 640 for presentation by the client device 602, such as images or video content presented by a display 606 and audio (e.g., sounds and music) presented by at least one audio playback device 608 (e.g., speakers or headphones). In at least one embodiment, at least part of the content may already be stored on the client device 602, rendered on the client device 602, or accessible to the client device 602, so at least the part of the content does not need to be transmitted over the network 640, for example, the content may have been previously downloaded or stored locally on a hard disk or optical disk. In at least one embodiment, the content can be transmitted from the server 620 or the user database 636 to the client device 602 using a transmission mechanism (e.g., data streaming).In at least one embodiment, at least a portion of the content may be obtained, enhanced, and / or streamed from another source (e.g., third-party service 660 or other client device 650), which may also include a content application 662 for generating, enhancing, or providing the content. In at least one embodiment, multiple computing devices or multiple processors within one or more computing devices (e.g., which may include a combination of CPUs and GPUs) may be used to perform portions of this functionality.

[0048] In this example, these client devices may include any appropriate computing devices, such as desktop computers, laptops, set-top boxes, streaming devices, game consoles, smartphones, tablet computers, VR headsets, AR goggles, wearable computers, or smart TVs. Each client device may submit a request across at least one wired or wireless network, which may include the Internet, Ethernet, a local area network (LAN), or a cellular network, as well as other such options. In this example, these requests may be submitted to an address associated with a cloud provider, which may operate or control one or more electronic resources in a cloud provider environment, such as a data center or a server farm. In at least one embodiment, the request may be received or processed by at least one edge server located at the edge of the network and outside of at least one security layer associated with the cloud provider environment. In this way, latency can be reduced by enabling client devices to interact with servers that are closer, while also improving the security of resources in the cloud provider environment.

[0049] In at least one embodiment, such a system may be used to perform graphics rendering operations. In other embodiments, such a system may be used for other purposes, such as for providing image or video content to test or verify autonomous machine applications, or for performing deep learning operations. In at least one embodiment, such a system may be implemented using an edge device, or may be combined with one or more VMs. In at least one embodiment, such a system may be implemented at least in part in a data center or at least in part using cloud computing resources.

[0050] Reasoning and training logic

[0051] Fig. 7A Inference and / or training logic 715 is shown for performing reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Details regarding the inference and / or training logic 715 are provided.

[0052] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software to control timing and / or sequence, where weights and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 701 stores input / output data during training and / or inference using aspects of one or more embodiments and / or weight parameters during forward propagation of each layer of a neural network trained or used in conjunction with one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0053] In at least one embodiment, any portion of the code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the data storage 701 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the data storage 701 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage space on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0054] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, code and / or data storage 705 for storing reverse and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 705 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during back propagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as ALUs). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 705 is internal or external to the processor, for example, consisting of DRAM, SRAM, flash memory, or some other storage type, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0055] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be the same storage structure. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0056] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 710 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 720, which is a function of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, activations are performed in response to executing instructions or other code, linear algebra and / or matrix-based mathematics performed by ALU 710 to generate activations stored in activation storage 720, where weight values ​​stored in code and / or data storage 701 and / or code and / or data storage 705 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 701 or code and / or data storage 705 or other on-chip or off-chip storage.

[0057] In at least one embodiment, one or more ALUs 710 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 710 may be outside a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 710 may be included in an execution unit of a processor, or otherwise included in a group of ALUs accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., CPU, GPU, fixed function unit, etc.). In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation storage 720 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 720 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0058] In at least one embodiment, activation storage 720 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 720 may be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, activation storage 720 may be selected to be internal or external to a processor, for example, or include DRAM, SRAM, flash memory, or other storage types, depending on the storage available on-chip or off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors. In at least one embodiment, Fig. 7A The inference and / or training logic 715 shown in FIG. 7 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp (e.g., "LakeCrest") processor. In at least one embodiment, Fig. 7A The illustrated inference and / or training logic 715 may be used in conjunction with CPU hardware, GPU hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0059] Figure 7B Inference and / or training logic 715 is shown in accordance with at least one or more embodiments. In at least one embodiment, the reasoning and / or training logic 715 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 7B The inference and / or training logic 715 shown in FIG. 7 can be used in conjunction with an ASIC, such as the one from Google. Processing unit from Graphcore TM IPU from Intel Corp (e.g., "Lake Crest") processor. In at least one embodiment, Figure 7B The reasoning and / or training logic 715 shown in can be used in conjunction with CPU hardware, GPU hardware, or other hardware (e.g., FPGA). In at least one embodiment, the reasoning and / or training logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 7BIn at least one embodiment shown in , each of code and / or data storage 701 and code and / or data storage 705 is associated with a dedicated computing resource (e.g., computing hardware 702 and computing hardware 706), respectively. In at least one embodiment, each of computing hardware 702 and computing hardware 706 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 701 and code and / or data storage 705, respectively, and the results of performing the functions are stored in activation storage 720.

[0060] In at least one embodiment, each of the code and / or data stores 701 and 705 and the corresponding computing hardware 702 and 706 corresponds to a different layer of the neural network, such that activations from one "storage / compute pair 701 / 702" of the code and / or data store 701 and computing hardware 702 are provided as inputs to the next "storage / compute pair 705 / 706" of the code and / or data store 705 and computing hardware 706, so as to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 701 / 702 and 705 / 706 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 715 after or in parallel with the storage / compute pairs 701 / 702 and 705 / 706.

[0061] Data Center

[0062] Figure 8 An example data center 800 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0063] In at least one embodiment, Figure 8 As shown, the data center infrastructure layer 810 may include a resource coordinator 812, grouped computing resources 814, and node computing resources ("node CRs") 816(1)-816(N), where "N" represents any positive integer. In at least one embodiment, the node CRs 816(1)-816(N) may include, but are not limited to, any number of CPUs or other processors (including accelerators, FPGAs, graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NWI / O") devices, network switches, VMs, power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 816(1)-816(N) may be a server having one or more of the above computing resources.

[0064] In at least one embodiment, the grouped computing resources 814 may include a separate grouping (not shown) of node CRs housed in one or more racks, or many racks (also not shown) housed in data centers at various geographic locations. The separate grouping of node CRs within the grouped computing resources 814 may include computing, networks, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0065] In at least one embodiment, resource coordinator 812 may configure or otherwise control one or more node CRs 816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource coordinator 812 may include a software design infrastructure ("SDI") management entity for data center 800. In at least one embodiment, resource coordinator 812 may include hardware, software, or some combination thereof.

[0066] In at least one embodiment, Figure 8As shown, the framework layer 820 includes a job scheduler 822, a configuration manager 824, a resource manager 826, and a distributed file system 828. In at least one embodiment, the framework layer 820 may include a framework that supports software 832 of the software layer 830 and / or one or more applications 842 of the application layer 840. In at least one embodiment, the software 832 or the application 842 may include a web-based service software or application, such as a service or application provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 820 may be, but is not limited to, a free and open source software network application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can use the distributed file system 828 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 832 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 800. In at least one embodiment, the configuration manager 824 may be able to configure different layers, such as the software layer 830 and the framework layer 820 including Spark and a distributed file system 828 for supporting large-scale data processing. In at least one embodiment, the resource manager 826 can manage cluster or group computing resources mapped to or allocated to support the distributed file system 828 and the job scheduler 822. In at least one embodiment, the cluster or group computing resources can include group computing resources 814 on the data center infrastructure layer 810. In at least one embodiment, the resource manager 826 can coordinate with the resource coordinator 812 to manage these mapped or allocated computing resources.

[0067] In at least one embodiment, the software 832 included in the software layer 830 may include software used by at least a portion of the node CRs 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 828 of the framework layer 820. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0068] In at least one embodiment, one or more applications 842 included in the application layer 840 may include one or more types of applications used by at least a portion of the node CRs 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 828 of the framework layer 820. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0069] In at least one embodiment, any of the configuration manager 824, resource manager 826, and resource coordinator 812 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 800 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0070] In at least one embodiment, the data center 800 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 800. In at least one embodiment, by using weight parameters calculated by one or more training techniques described herein, information may be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to the data center 800.

[0071] In at least one embodiment, the data center can use CPU, ASIC, GPU, FPGA or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition or other artificial intelligence ("AI") services.

[0072] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7BProvides details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Figure 8 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0073] Such a component may be used to efficiently determine alpha blending values ​​for objects that may have at least one sub-pixel dimension but that are to be accurately represented in generated image content.

[0074] Computer Systems

[0075] Fig. 9 900 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, the computer system 900 may include, but is not limited to, components, such as a processor 902, whose execution unit includes logic to execute algorithms for processing data. In at least one embodiment, the computer system 900 may include a processor, such as a processor available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 900 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0076] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a SOC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0077] In at least one embodiment, the computer system 900 may include, but is not limited to, a processor 902, which may include, but is not limited to, one or more execution units 908 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 900 is a single-processor desktop or server system, but in another embodiment, the computer system 900 may be a multi-processor system. In at least one embodiment, the processor 902 may include, but is not limited to, a complex instruction set computing ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word computing ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a DSP. In at least one embodiment, the processor 902 may be coupled to a processor bus 910, which may transmit data signals between the processor 902 and other components in the computer system 900.

[0078] In at least one embodiment, processor 902 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 904. In at least one embodiment, processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache 904 may reside external to processor 902. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, register file 906 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.

[0079] In at least one embodiment, logic execution unit 908 that performs integer and floating point operations is also located in processor 902, including, but not limited to. In at least one embodiment, processor 902 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 908 may include logic for processing a packed instruction set 909. In at least one embodiment, by including a packed instruction set 909 in the instruction set of a general purpose processor, and associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in processor 902. In one or more embodiments, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus 910 to perform operations on packed data, which may not require the transfer of smaller units of data on the processor's data bus 910 to perform one or more operations one data element at a time.

[0080] In at least one embodiment, execution unit 908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 900 may include, but is not limited to, memory 920. In at least one embodiment, memory 920 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. In at least one embodiment, memory 920 may store instructions 919 and / or data 921 represented by data signals that may be executed by processor 902.

[0081] In at least one embodiment, the system logic chip can be coupled to the processor bus 910 and the memory 920. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 916, and the processor 902 can communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 can provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 916 can initiate data signals between the processor 902, the memory 920, and other components in the computer system 900, and bridge data signals between the processor bus 910, the memory 920, and the system I / O 922. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 can be coupled to the memory 920 via a high-bandwidth memory path 918, and the graphics / video card 912 can be coupled to the MCH 916 via an Accelerated Graphics Port ("AGP") interconnect 914.

[0082] In at least one embodiment, the computer system 900 may use a system I / O 922, which is a proprietary hub interface bus to couple the MCH 916 to an I / O controller hub ("ICH") 930. In at least one embodiment, the ICH 930 may provide direct connections to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 920, chipset, and processor 902. Examples may include, but are not limited to, an audio controller 929, a firmware hub ("Flash BIOS") 928, a wireless transceiver 926, a data store 924, a traditional I / O controller 923 including a user input and keyboard interface, a serial expansion port 927 (e.g., a universal serial bus (USB) port), and a network controller 934. The data store 924 may include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0083] In at least one embodiment, Fig. 9 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Fig. 9 SOC may be shown). In at least one embodiment, the devices may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 900 are interconnected using a Compute Express Link (CXL) interconnect.

[0084] The reasoning and / or training logic 715 is used to perform reasoning and / or training operations related to one or more embodiments. Fig. 7A and / or Figure 7B Provide details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be Fig. 9 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0085] Such a component may be used to efficiently determine alpha blending values ​​for objects that may have at least one sub-pixel dimension but that are to be accurately represented in generated image content.

[0086] Fig.10 1 is a block diagram illustrating an electronic device 1000 for using a processor 1010 according to at least one embodiment. In at least one embodiment, the electronic device 1000 may be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0087] In at least one embodiment, the electronic device 1000 may include, but is not limited to, a processor 1010 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 1010 is coupled using a bus or interface, such as an Ic bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a USB (version 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig.10 An electronic device 1000 is shown that includes interconnected hardware devices or "chips", while in other embodiments, Fig.10 An exemplary SOC may be shown. In at least one embodiment, Fig.10 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig.10 One or more components of the system are interconnected using CXL interconnect lines.

[0088] In at least one embodiment, Fig.10It may include a display 1024, a touch screen 1025, a touch pad 1030, a near field communication (“NFC”) unit 1045, a sensor hub 1040, a thermal sensor 1046, a fast chipset (“EC”) 1035, a trusted platform module (“TPM”) 1038, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1022, a DSP 1060, a drive 1020 (e.g., a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network (“WLAN”) unit 1050, a Bluetooth unit 1052, a wireless wide area network (“WWAN”) unit 1056, a global positioning system (GPS) 1055, a camera (“USB 3.0 camera”) 1054 (e.g., a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1015 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0089] In at least one embodiment, other components may be communicatively coupled to the processor 1010 through the components described above. In at least one embodiment, the accelerometer 1041, ambient light sensor (“ALS”) 1042, compass 1043, and gyroscope 1044 may be communicatively coupled to the sensor hub 1040. In at least one embodiment, the thermal sensor 1039, fan 1037, keyboard 1036, and touchpad 1030 may be communicatively coupled to the EC 1035. In at least one embodiment, the speaker 1063, earphone 1064, and microphone (“mic”) 1065 may be communicatively coupled to the audio unit (“audio codec and class D amplifier”) 1062, which in turn may be communicatively coupled to the DSP 1060. In at least one embodiment, the audio unit 1062 may include, for example, but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, the SIM card (“SIM”) 1057 may be communicatively coupled to the WWAN unit 1056. In at least one embodiment, components such as the WLAN unit 1050 and the Bluetooth unit 1052 and the WWAN unit 1056 may be implemented as a next generation form factor (NGFF).

[0090] The reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Provide details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be Fig.10Systems for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0091] Such a component may be used to efficiently determine alpha blending values ​​for objects that may have at least one sub-pixel dimension but that are to be accurately represented in generated image content.

[0092] Fig.11 1100 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 1100 includes one or more processors 1102 and one or more graphics processors 1108, and can be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1102 or processor cores 1107. In at least one embodiment, system 1100 is a processing platform incorporated within a SoC integrated circuit for use in a mobile, handheld, or embedded device.

[0093] In at least one embodiment, the system 1100 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console for gaming and media consoles. In at least one embodiment, the system 1100 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the system 1100 may also include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an AR device, or a VR device. In at least one embodiment, the system 1100 is a television or set-top box device having one or more processors 1102 and a graphical interface generated by one or more graphics processors 1108.

[0094] In at least one embodiment, one or more processors 1102 each include one or more processor cores 1107 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1107 is configured to process a specific instruction group 1109. In at least one embodiment, the instruction group 1109 can facilitate CISC, RISC, or calculate through VLIW. In at least one embodiment, the processor cores 1107 can each process a different instruction group 1109, which can include instructions that help emulate other instruction groups. In at least one embodiment, the processor cores 1107 can also include other processing devices, such as DSPs.

[0095] In at least one embodiment, the processor 1102 includes a cache memory (cache) 1104. In at least one embodiment, the processor 1102 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between various components of the processor 1102. In at least one embodiment, the processor 1102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared between the processor cores 1107 using known cache coherence techniques. In at least one embodiment, the processor 1102 additionally includes a register file 1106, and the processor can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 1106 can include general registers or other registers.

[0096] In at least one embodiment, one or more processors 1102 are coupled to one or more interface buses 1110 to transmit communication signals, such as address, data, or control signals, between the processor 1102 and other components in the system 1100. In at least one embodiment, the interface bus 1110 may be a processor bus, such as a version of a direct media interface (DMI) bus, in one embodiment. In at least one embodiment, the interface bus 1110 is not limited to a DMI bus, and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1102 includes an integrated memory controller 1116 and a platform controller hub ("PCH") 1130. In at least one embodiment, the memory controller 1116 facilitates communication between the memory device 1120 and other components of the processing system 1100, while the PCH 1130 provides connections to I / O devices through a local I / O bus.

[0097] In at least one embodiment, the memory device 1120 may be a DRAM device, an SRAM device, a flash memory device, a phase change memory device, or have appropriate performance to be used as a processor memory. In at least one embodiment, the memory device 1120 may be used as a system memory of the processing system 1100 to store data 1122 and instructions 1121 for use when one or more processors 1102 execute an application or process. In at least one embodiment, the memory controller 1116 is also coupled to an optional external graphics processor 1112, which may communicate with one or more graphics processors 1108 in the processor 1102 to perform graphics and media operations. In at least one embodiment, a display device 1111 may be connected to the processor 1102. In at least one embodiment, the display device 1111 may include one or more of the internal display devices, such as in a mobile electronic device or laptop device or an external display device connected via a display interface (e.g., a display port (DisplayPort) or the like). In at least one embodiment, the display device 1111 may include a head mounted display (HMD), such as a stereoscopic display device for VR applications or AR applications.

[0098] In at least one embodiment, the PCH 1130 enables peripheral devices to be connected to the memory device 1120 and the processor 1102 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1146, a network controller 1134, a firmware interface 1128, a wireless transceiver 1126, a touch sensor 1125, a data storage device 1124 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long-term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1128 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 1134 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1110. In at least one embodiment, the audio controller 1146 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1100 includes an optional legacy I / O controller 1140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 1100. In at least one embodiment, the PCH 1130 can also be connected to one or more USB controllers 1142, which connect input devices such as a keyboard and mouse 1143 combination, a camera 1144, or other USB input devices.

[0099] In at least one embodiment, instances of memory controller 1116 and PCH 1130 may be integrated into a discrete external graphics processor, such as external graphics processor 1112. In at least one embodiment, PCH 1130 and / or memory controller 1116 may be external to one or more processors 1102. For example, in at least one embodiment, system 1100 may include external memory controller 1116 and PCH 1130, which may be configured as a memory controller hub (MCH) and a peripheral controller hub in a system chipset that communicates with processor 1102.

[0100] The reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7BDetail is provided regarding the inference and / or training logic 715. In at least one embodiment, some or all of the inference and / or training logic 715 may be incorporated into the graphics processor 1100. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs that are embodied in the graphics processor. In addition, in at least one embodiment, the inference and / or training operations described herein may use the ALUs other than the ALUs. Fig. 7A and / or Figure 7B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0101] Such a component may be used to efficiently determine alpha blending values ​​for objects that may have at least one sub-pixel dimension but that are to be accurately represented in generated image content.

[0102] Fig.12 is a block diagram of a processor 1200 having one or more processor cores 1202A-1202N, an integrated memory controller 1214, and an integrated graphics processor 1208, according to at least one embodiment. In at least one embodiment, the processor 1200 may include additional cores, up to and including the additional core 1202N represented by the dashed box. In at least one embodiment, each processor core 1202A-1202N includes one or more internal cache units 1204A-1204N. In at least one embodiment, each processor core may also have access to one or more shared cache units 1206.

[0103] In at least one embodiment, the internal cache units 1204A-1204N and the shared cache unit 1206 represent a cache memory hierarchy within the processor 1200. In at least one embodiment, the cache memory units 1204A-1204N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is categorized as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 1206 and 1204A-1204N.

[0104] In at least one embodiment, the processor 1200 may also include a set of one or more bus controller units 1216 and a system agent core 1210. In at least one embodiment, the one or more bus controller units 1216 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 1210 provides management functions for various processor components. In at least one embodiment, the system agent core 1210 includes one or more integrated memory controllers 1214 to manage access to various external memory devices (not shown).

[0105] In at least one embodiment, one or more processor cores 1202A-1202N include support for multiple threads simultaneously. In at least one embodiment, system agent core 1210 includes components for coordinating and processing processor cores 1202A-1202N during multithreaded processing. In at least one embodiment, system agent core 1210 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 1202A-1202N and graphics processor 1208.

[0106] In at least one embodiment, the processor 1200 also includes a graphics processor 1208 for performing graphics processing operations. In at least one embodiment, the graphics processor 1208 is coupled to a shared cache unit 1206 and a system agent core 1210 including one or more integrated memory controllers 1214. In at least one embodiment, the system agent core 1210 also includes a display controller 1211 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 1211 may also be a separate module coupled to the graphics processor 1208 via at least one interconnect, or may be integrated within the graphics processor 1208.

[0107] In at least one embodiment, a ring-based interconnect unit 1212 is used to couple the internal components of the processor 1200. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 1208 is coupled to the ring-based interconnect unit 1212 via an I / O link 1213.

[0108] In at least one embodiment, I / O link 1213 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 1218 (e.g., eDRAM modules). In at least one embodiment, each of processor cores 1202A-1202N and graphics processor 1208 uses embedded memory modules 1218 as a shared last level cache.

[0109] In at least one embodiment, the processor cores 1202A-1202N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 1202A-1202N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 1202A-1202N execute a common instruction set, while one or more other processor cores 1202A-1202N execute a subset or a different instruction set of the common instruction set. In at least one embodiment, the processor cores 1202A-1202N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 1200 can be implemented on one or more chips or implemented as a SOC integrated circuit.

[0110] The reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 7A and / or Figure 7B Detail is provided regarding the inference and / or training logic 715. In at least one embodiment, some or all of the inference and / or training logic 715 may be incorporated into the processor 1200. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in Fig.12 In addition, in at least one embodiment, the inference and / or training operations described herein may use the inference and / or training operations described herein. Fig. 7A and / or Figure 7B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 1200 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0111] Such a component may be used to efficiently determine alpha blending values ​​for objects that may have at least one sub-pixel dimension but that are to be accurately represented in generated image content.

[0112] Virtualized computing platform

[0113] Fig.13 is an example data flow diagram of a process 1300 for generating and deploying an image processing and inference pipeline according to at least one embodiment. In at least one embodiment, the process 1300 can be deployed for use with imaging devices, processing devices, and / or other device types at one or more facilities 1302. The process 1300 can be executed within a training system 1304 and / or a deployment system 1306. In at least one embodiment, the training system 1304 can be used to perform training, deployment, and implementation of machine learning models (e.g., neural networks, object detection algorithms, computer vision algorithms, etc.) for use with the deployment system 1306. In at least one embodiment, the deployment system 1306 can be configured to offload processing and computing resources in a distributed computing environment to reduce infrastructure requirements of the facility 1302. In at least one embodiment, one or more applications in the pipeline can use or call services (e.g., reasoning, visualization, computation, AI, etc.) of the deployment system 1306 during application execution.

[0114] In at least one embodiment, some applications used in the high-level processing and reasoning pipeline may use machine learning models or other AI to perform one or more processing steps. In at least one embodiment, the machine learning model may be trained at the facility 1302 using data 1308 (e.g., imaging data) generated at the facility 1302 (and stored on one or more picture archiving and communication system (PACS) servers at the facility 1302), the machine learning model may be trained using imaging or sequencing data 1308 from another one or more facilities 1302, or a combination thereof. In at least one embodiment, the training system 1304 may be used to provide applications, services, and / or other resources to generate a working, deployable machine learning model for the deployment system 1306.

[0115] In at least one embodiment, the model registry 1324 can be backed by an object store, which can support versioning and object metadata. In at least one embodiment, the object store can be accessed from within the cloud platform through, for example, a cloud storage compatible application programming interface (API). In at least one embodiment, the machine learning models within the model registry 1324 can be uploaded, listed, modified, or deleted by developers or partners of the system interacting with the API. In at least one embodiment, the API can provide access to methods that allow users with appropriate credentials to associate a model with an application so that the model can be executed as part of the execution of a containerized instantiation of the application.

[0116] In at least one embodiment, training pipeline 1304 ( Fig.13 ) may include situations where the facility 1302 is training their own machine learning model, or has an existing machine learning model that needs to be optimized or updated. In at least one embodiment, imaging data 1308 generated by an imaging device, a sequencing device, and / or other type of device may be received. In at least one embodiment, once the imaging data 1308 is received, the AI-assisted annotation 1310 may be used to help generate annotations corresponding to the imaging data 1308 to be used as ground truth data for the machine learning model. In at least one embodiment, the AI-assisted annotation 1310 may include one or more machine learning models (e.g., a convolutional neural network (CNN)) that may be trained to generate annotations corresponding to certain types of imaging data 1308 (e.g., from certain devices). In at least one embodiment, the AI-assisted annotation 1310 may then be used directly, or may be adjusted or fine-tuned using an annotation tool to generate ground truth data. In at least one embodiment, the AI-assisted annotation 1310, the labeled data 1312, or a combination thereof may be used as ground truth data for training a machine learning model. In at least one embodiment, the trained machine learning model can be referred to as an output model 1316 and can be used by the deployment system 1306 as described herein.

[0117] In at least one embodiment, the training pipeline may include a scenario where the facility 1302 requires a machine learning model for performing one or more processing tasks for one or more applications in the deployment system 1306, but the facility 1302 may not currently have such a machine learning model (or may not have a model that is optimized, efficient, or effective for this purpose). In at least one embodiment, an existing machine learning model may be selected from the model registry 1324. In at least one embodiment, the model registry 1324 may include machine learning models that are trained to perform a variety of different reasoning tasks on imaging data. In at least one embodiment, the machine learning models in the model registry 1324 may be trained on imaging data from a different facility (e.g., a facility located far away) rather than the facility 1302. In at least one embodiment, the machine learning model may have been trained on imaging data from one location, two locations, or any number of locations. In at least one embodiment, when training is performed on imaging data from a specific location, the training may be performed at that location, or at least in a manner that protects the confidentiality of the imaging data or restricts the transfer of the imaging data from off-site. In at least one embodiment, once a model is trained or partially trained at one location, the machine learning model can be added to the model registry 1324. In at least one embodiment, the machine learning model can then be retrained or updated at any number of other facilities, and the retrained or updated model can be used in the model registry 1324. In at least one embodiment, the machine learning model can then be selected from the model registry 1324 (and referred to as the output model 1316) and can be deployed in the deployment system 1306 to perform one or more processing tasks for one or more applications of the deployment system.

[0118] In at least one embodiment, the scenario may include a facility 1302 that requires a machine learning model for performing one or more processing tasks for one or more applications in the deployment system 1306, but the facility 1302 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model). In at least one embodiment, the machine learning model selected from the model registry 1324 may not be fine-tuned or optimized for the imaging data 1308 generated at the facility 1302 due to population differences, robustness of the training data used to train the machine learning model, diversity of training data anomalies, and / or other issues with the training data. In at least one embodiment, AI-assisted annotations 1310 can be used to help generate annotations corresponding to the imaging data 1308 for use as ground truth data for training or updating the machine learning model. In at least one embodiment, labeled clinical data 1312 can be used as ground truth data for training the machine learning model. In at least one embodiment, retraining or updating the machine learning model can be referred to as model training 1314. In at least one embodiment, model training 1314 (e.g., AI-assisted annotation 1310, labeled clinical data 1312, or a combination thereof) can be used as ground truth data to retrain or update the machine learning model. In at least one embodiment, the trained machine learning model can be referred to as an output model 1316 and can be used by the deployment system 1306, as described herein.

[0119] In at least one embodiment, the deployment system 1306 may include software 1318, services 1320, hardware 1322, and / or other components, features, and functions. In at least one embodiment, the deployment system 1306 may include a software "stack" such that the software 1318 may be built on top of the services 1320 and may use the services 1320 to perform some or all of the processing tasks, and the services 1320 and software 1318 may be built on top of the hardware 1322 and use the hardware 1322 to perform the processing, storage, and / or other computing tasks of the deployment system. In at least one embodiment, the software 1318 may include any number of different containers, each of which may perform an instantiation of an application. In at least one embodiment, each application may perform one or more processing tasks (e.g., reasoning, object detection, feature detection, segmentation, image enhancement, calibration, etc.) in a high-level processing and reasoning pipeline. In at least one embodiment, in addition to receiving and configuring imaging data for use by each container and / or containers used by facility 1302 after processing through the pipeline, a high-level processing and reasoning pipeline can also be defined based on the selection of different containers desired or required to process imaging data 1308 (e.g., to convert the output back into a usable data type. In at least one embodiment, the combination of containers within software 1318 (e.g., which constitute a pipeline) can be referred to as a virtual instrument (as described in more detail herein), and the virtual instrument can utilize services 1320 and hardware 1322 to perform some or all of the processing tasks of an application instantiated in a container.

[0120] In at least one embodiment, the data processing pipeline can receive input data (e.g., imaging data 1308) in a specific format in response to an inference request (e.g., a request from a user of the deployment system 1306). In at least one embodiment, the input data can represent one or more images, videos, and / or other data representations generated by one or more imaging devices. In at least one embodiment, the data can be pre-processed as part of the data processing pipeline to prepare the data for processing by one or more applications. In at least one embodiment, post-processing can be performed on the output of one or more inference tasks or other processing tasks of the pipeline to prepare output data for the next application and / or prepare the output data for transmission and / or use by the user (e.g., as a response to the inference request). In at least one embodiment, the inference task can be performed by one or more machine learning models, such as a trained or deployed neural network, which can include the output model 1316 of the training system 1304.

[0121] In at least one embodiment, tasks of a data processing pipeline may be encapsulated in containers, each container representing a discrete, fully functional instantiation of an application and a virtualized computing environment capable of referencing a machine learning model. In at least one embodiment, containers or applications may be published to a private (e.g., limited access) area of ​​a container registry (described in more detail herein), and trained or deployed models may be stored in the model registry 1324 and associated with one or more applications. In at least one embodiment, an image of an application (e.g., a container image) may be available in a container registry, and once a user selects an image from a container registry for deployment in a pipeline, the image may be used to generate an instantiated container for the application for use by the user's system.

[0122] In at least one embodiment, a developer (e.g., a software developer, a clinician, a physician, etc.) can develop, publish, and store applications (e.g., as containers) for performing image processing and / or reasoning on provided data. In at least one embodiment, the development, publishing, and / or storage can be performed using a software development kit (SDK) associated with the system (e.g., to ensure that the developed applications and / or containers conform to or are compatible with the system). In at least one embodiment, the developed applications can be tested locally (e.g., at a first facility, on data from the first facility) using the SDK, which is installed as part of the system (e.g., Fig.12 Processor 1200 in the process 1300) may support at least some services 1320. In at least one embodiment, because a DICOM object may contain from one to hundreds of images or other data types, and because the data varies, the developer may be responsible for managing (e.g., setting up constructs for building pre-processing into the application, etc.) the extraction and preparation of the incoming data. In at least one embodiment, once validated by process 1300 (e.g., for accuracy), the application is made available in the container registry for selection and / or implementation by the user to perform one or more processing tasks on the data at the user's facility (e.g., a second facility).

[0123] In at least one embodiment, the developer can then share the application or container over a network for use by a system (e.g., Fig.131300). In at least one embodiment, the completed and validated application or container can be stored in the container registry, and the associated machine learning model can be stored in the model registry 1324. In at least one embodiment, the requesting entity (which provides the reasoning or image processing request) can browse the container registry and / or the model registry 1324 to obtain applications, containers, data sets, machine learning models, etc., select the desired combination of elements to be included in the data processing pipeline, and submit the image processing request. In at least one embodiment, the request may include the input data necessary to execute the request (and in some examples, patient-related data), and / or may include a selection of applications and / or machine learning models to be executed when processing the request. In at least one embodiment, the request can then be passed to one or more components (e.g., a cloud) of the deployment system 1306 to perform processing of the data processing pipeline. In at least one embodiment, the processing performed by the deployment system 1306 may include referencing elements (e.g., applications, containers, models, etc.) selected from the container registry and / or the model registry 1324. In at least one embodiment, once the results are generated by the pipeline, the results may be returned to the user for reference (eg, for viewing in a viewing application suite executing locally, on a local workstation or terminal).

[0124] In at least one embodiment, in order to help process or execute applications or containers in the pipeline, services 1320 can be utilized. In at least one embodiment, services 1320 may include computing services, AI services, visualization services, and / or other service types. In at least one embodiment, services 1320 may provide functions common to one or more applications in software 1318, so the functions may be abstracted into services that can be called or utilized by applications. In at least one embodiment, the functions provided by services 1320 may run dynamically and more efficiently, while also being well scaled by allowing applications to process data in parallel (e.g., using parallel computing platforms). In at least one embodiment, rather than requiring each application that shares the same functions provided by services 1320 to have a corresponding instance of services 1320, services 1320 may be shared between and among various applications. In at least one embodiment, as a non-limiting example, services 1320 may include an inference server or engine that can be used to perform detection or segmentation tasks. In at least one embodiment, a model training service may be included that may provide machine learning model training and / or retraining capabilities. In at least one embodiment, data enhancement services may further be included that may provide GPU accelerated data (e.g., DICOM, RIS, CIS, REST, RPC, raw, etc.) extraction, resizing, scaling, and / or other enhancements. In at least one embodiment, visualization services may be used that may add image rendering effects (e.g., ray tracing, rasterization, denoising, sharpening, etc.) to add realism to two-dimensional (2D) and / or 3D models. In at least one embodiment, virtual instrument services may be included that provide beamforming, segmentation, reasoning, imaging, and / or support for other applications within the pipeline of the virtual instrument.

[0125] In at least one embodiment, where the service 1320 includes an AI service (e.g., an inference service), as part of the execution of an application, one or more machine learning models can be executed by calling (e.g., as an API call) an inference service (e.g., an inference server) to execute one or more machine learning models or processing thereof. In at least one embodiment, where another application includes one or more machine learning models for a segmentation task, the application can call the inference service to execute the machine learning model for performing one or more processing operations associated with the segmentation task. In at least one embodiment, the software 1318 implementing the high-level processing and inference pipeline, which includes a segmentation application and anomaly detection application, can be pipelined because each application can call the same inference service to perform one or more inference tasks.

[0126] In at least one embodiment, the hardware 1322 may include a GPU, a CPU, a graphics card, an AI / deep learning system (e.g., an AI supercomputer, such as NVIDIA's DGX system), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 1322 may be used to provide efficient, purpose-built support for the software 1318 and services 1320 in the deployment system 1306. In at least one embodiment, the use of GPU processing may be implemented for local processing (e.g., at the facility 1302) within the AI / deep learning system, in the cloud system, and / or other processing components of the deployment system 1306 to improve the efficiency, accuracy, and effectiveness of image processing and generation. In at least one embodiment, as a non-limiting example, with respect to deep learning, machine learning, and / or high-performance computing, the software 1318 and / or services 1320 may be optimized for GPU processing. In at least one embodiment, at least some of the computing environments of the deployment system 1306 and / or training system 1304 may be executed in a data center, one or more supercomputers, or high-performance computer systems with GPU-optimized software (e.g., a combination of hardware and software of the NVIDIA DGX system). In at least one embodiment, as described herein, hardware 1322 may include any number of GPUs that may be called to perform data processing in parallel. In at least one embodiment, the cloud platform may also include GPU optimized execution for deep learning tasks, GPU processing for machine learning tasks or other computing tasks. In at least one embodiment, an AI / deep learning supercomputer and / or GPU optimized software (e.g., as provided on NVIDIA's DGX system) may be used as a hardware abstraction and scaling platform to execute a cloud platform (e.g., NVIDIA's NGC). In at least one embodiment, the cloud platform may integrate an application container cluster system or coordination system (e.g., KUBERNETES) on multiple GPUs to achieve seamless scaling and load balancing.

[0127] Fig.14 is a system diagram of an example system 1400 for generating and deploying an imaging deployment pipeline according to at least one embodiment. In at least one embodiment, the system 1400 can be used to implement Fig.13 The process 1300 and / or other processes of the system 1400 may include a high-level processing and reasoning pipeline. In at least one embodiment, the system 1400 may include a training system 1304 and a deployment system 1306. In at least one embodiment, the training system 1304 and the deployment system 1306 may be implemented using software 1318, services 1320, and / or hardware 1322, as described herein.

[0128] In at least one embodiment, system 1400 (e.g., training system 1304 and / or deployment system 1306) can be implemented in a cloud computing environment (e.g., using cloud 1426). In at least one embodiment, system 1400 can be implemented locally (with respect to a healthcare service facility) or as a combination of cloud computing resources and local computing resources. In at least one embodiment, access to APIs in cloud 1426 can be restricted to authorized users by establishing security measures or protocols. In at least one embodiment, the security protocol can include a network token, which can be signed by an authentication (e.g., AuthN, AuthZ, Gluecon, etc.) service and can carry appropriate authorization. In at least one embodiment, the API of the virtual instrument (described herein) or other instances of system 1400 can be restricted to a set of public IPs that have been audited or authorized for interaction.

[0129] In at least one embodiment, the various components of system 1400 can communicate with each other using any of a variety of different network types, including but not limited to LAN and / or WAN via wired and / or wireless communication protocols. In at least one embodiment, communications between facilities and components of system 1400 (e.g., for sending inference requests, for receiving results of inference requests, etc.) can be transmitted via one or more data buses, wireless data protocols (Wi-Fi), wired data protocols (e.g., Ethernet), etc.

[0130] In at least one embodiment, similar to the present disclosure regarding Fig.13 As described, the training system 1304 can execute the training pipeline 1404. In at least one embodiment, where the deployment system 1306 will use one or more machine learning models in the deployment pipeline 1410, the training pipeline 1404 can be used to train or retrain one or more (e.g., pre-trained) models, and / or implement one or more pre-trained models 1406 (e.g., without retraining or updating). In at least one embodiment, as a result of the training pipeline 1404, an output model 1316 can be generated. In at least one embodiment, the training pipeline 1404 can include any number of processing steps, such as, but not limited to, conversion or adaptation of imaging data (or other input data). In at least one embodiment, different training pipelines 1404 can be used for different machine learning models used by the deployment system 1306. In at least one embodiment, similar to the description regarding Fig.13 The first example training pipeline 1404 described may be used for a first machine learning model, similar to the training pipeline 1404 described with respect to FIG. Fig.13 The second example training pipeline 1404 described may be used for a second machine learning model, similar to the one described with respect to Fig.13The training pipeline 1404 of the third example described may be used for a third machine learning model. In at least one embodiment, any combination of tasks within the training system 1304 may be used according to the requirements of each corresponding machine learning model. In at least one embodiment, one or more machine learning models may have been trained and ready for deployment, so the training system 1304 may not perform any processing on the machine learning model, and one or more machine learning models may be implemented by the deployment system 1306.

[0131] In at least one embodiment, the output model 1316 and / or the pre-trained model 1406 may include any type of machine learning model, depending on the implementation or embodiment. In at least one embodiment and without limitation, the machine learning model used by the system 1400 may include using linear regression, logistic regression, decision tree, support vector machine (SVM), naive Bayes, k-nearest neighbor (Knn), k-means clustering, random forest, dimensionality reduction algorithm, gradient boosting algorithm, neural network (e.g., autoencoder, convolution, recursion, perceptron, long / short term memory (LSTM), Hopfield, Boltzmann, deep belief, deconvolution, generative adversarial, liquid state machine, etc.), and / or other types of machine learning models.

[0132] In at least one embodiment, the training pipeline 1404 may include AI-assisted annotation, as described herein with respect to at least Fig.14In more detail. In at least one embodiment, the labeled clinical data 1312 (e.g., traditional annotations) can be generated by any number of techniques. In at least one embodiment, in some examples, labels or other annotations can be generated in a drawing program (e.g., an annotation program), a computer-aided design (CAD) program, a labeling program, another type of application suitable for generating ground-truth annotations or labels, and / or can be hand-drawn. In at least one embodiment, the ground-truth data can be synthetically generated (e.g., generated from a computer model or rendering), truly generated (e.g., designed and generated from real-world data), machine-generated (e.g., using feature analysis and learning to extract features from the data and then generate labels), manually annotated (e.g., a labeler or annotation expert, defining the location of the label), and / or a combination thereof. In at least one embodiment, for each instance of imaging data 1308 (or other data types used by machine learning models), there can be corresponding ground-truth data generated by the training system 1304. In at least one embodiment, AI-assisted annotation 1310 can be performed as part of a deployment pipeline 1410; supplementing or replacing the AI-assisted annotation 1310 included in the training pipeline 1404. In at least one embodiment, the system 1400 may include a multi-layer platform that may include a software layer (e.g., software 1318) of a diagnostic application (or other application type) that may perform one or more medical imaging and diagnostic functions. In at least one embodiment, the system 1400 may be communicatively coupled (e.g., via an encrypted link) to a PACS server network of one or more facilities. In at least one embodiment, the system 1400 may be configured to access and reference data from a PACS server to perform operations such as training a machine learning model, deploying a machine learning model, image processing, reasoning, and / or other operations.

[0133] In at least one embodiment, the software layer may be implemented as a secure, encrypted, and / or authenticated API through which an application or container may be invoked (e.g., called) from an external environment (e.g., facility 1302). In at least one embodiment, the application may then call or execute one or more services 1320 to perform computational, AI, or visualization tasks associated with the respective application, and the software 1318 and / or services 1320 may utilize hardware 1322 to perform processing tasks in an effective and efficient manner. In at least one embodiment, a pair of DICOM adapters 1402A, 1402B may be used to send or receive communications to and from the training system 1304 and the deployment system 1306.

[0134] In at least one embodiment, the deployment system 1306 can execute a deployment pipeline 1410. In at least one embodiment, the deployment pipeline 1410 can include any number of applications, which can be sequential, non-sequential, or otherwise applied to imaging data (and / or other data types) - including AI-assisted annotations, generated by imaging devices, sequencing devices, genomics devices, etc., as described above. In at least one embodiment, as described herein, the deployment pipeline 1410 for an individual device can be referred to as a virtual instrument for the device (e.g., a virtual ultrasound instrument, a virtual CT scanning instrument, a virtual sequencing instrument, etc.). In at least one embodiment, there can be more than one deployment pipeline 1410 for a single device, depending on the information desired from the data generated by the device. In at least one embodiment, there can be a first deployment pipeline 1410 in the case where an abnormality is desired to be detected from an MRI machine, and there can be a second deployment pipeline 1410 in the case where image enhancement is desired from the output of the MRI machine.

[0135] In at least one embodiment, the image generation application may include a processing task that includes the use of a machine learning model. In at least one embodiment, a user may wish to use their own machine learning model, or select a machine learning model from the model registry 1324. In at least one embodiment, a user may implement their own machine learning model or select a machine learning model to be included in an application that performs a processing task. In at least one embodiment, the application may be selectable and customizable, and by defining the construction of the application, the deployment and implementation of the application for a particular user is presented as a more seamless user experience. In at least one embodiment, by leveraging other features of the system 1400 (e.g., services 1320 and hardware 1322), the deployment pipeline 1410 may be more user-friendly, provide easier integration, and produce more accurate, efficient, and timely results.

[0136] In at least one embodiment, deployment system 1306 may include a user interface 1414 (e.g., a graphical user interface ("UI"), a web interface, etc.) that may be used to select applications to be included in deployment pipeline 1410, to arrange applications, to modify or change applications or their parameters or configuration, to use and interact with deployment pipeline 1410 during setup and / or deployment, and / or to otherwise interact with deployment system 1306. In at least one embodiment, although not shown with respect to training system 1304, UI 1414 (or a different user interface) may be used to select models to use in deployment system 1306, to select models to train or retrain in training system 1304, and / or to otherwise interact with training system 1304.

[0137] In at least one embodiment, in addition to the application coordination system 1428, a pipeline manager 1412 may be used to manage the interaction between the application or container of the deployment pipeline 1410 and the service 1320 and / or the hardware 1322. In at least one embodiment, the pipeline manager 1412 may be configured to facilitate the interaction from application to application, from application to service 1320, and / or from application or service to hardware 1322. In at least one embodiment, although shown as included in the software 1318, this is not intended to be limiting, and in some examples, the pipeline manager 1412 may be included in the service 1320. In at least one embodiment, the application coordination system 1428 (e.g., Kubernetes, DOCKER, etc.) may include a container coordination system that can group applications into containers as a logical unit for coordination, management, scaling, and deployment. In at least one embodiment, by associating applications from the deployment pipeline 1410 (e.g., rebuilding applications, splitting applications, etc.) with individual containers, each application can be executed in a self-contained environment (e.g., at the kernel level) to improve speed and efficiency.

[0138] In at least one embodiment, each application and / or container (or its image) can be developed, modified, and deployed separately (e.g., a first user or developer can develop, modify, and deploy a first application, and a second user or developer can develop, modify, and deploy a second application separate from the first user or developer), which can allow for focus and attention on the tasks of a single application and / or container without being hindered by the tasks of another application or container. In at least one embodiment, the pipeline manager 1412 and the application coordination system 1428 can assist in communication and collaboration between different containers or applications. In at least one embodiment, as long as the expected inputs and / or outputs of each container or application are known to the system (e.g., based on the construction of the application or container), the application coordination system 1428 and / or the pipeline manager 1412 can facilitate communication and sharing of resources between and among each application or container. In at least one embodiment, since one or more applications or containers in the deployment pipeline 1410 can share the same services and resources, the application coordination system 1428 can coordinate, load balance, and determine the sharing of services or resources between and among the various applications or containers. In at least one embodiment, the scheduler can be used to track resource requirements of applications or containers, current or planned use of those resources, and resource availability. Thus, in at least one embodiment, the scheduler can allocate resources to different applications and allocate resources between and among applications, taking into account the needs and availability of the system. In some examples, the scheduler (and / or other components of the application coordination system 1428) can determine resource availability and distribution based on constraints imposed on the system (e.g., user constraints), such as quality of service (QoS), the urgency of data output (e.g., to determine whether to perform real-time processing or delayed processing), etc.

[0139] In at least one embodiment, the services 1320 utilized and shared by the applications or containers in the deployment system 1306 may include computing services 1416, AI services 1418, visualization services 1420, and / or other service types. In at least one embodiment, an application may call (e.g., execute) one or more services 1320 to perform processing operations for the application. In at least one embodiment, an application may utilize computing services 1416 to perform supercomputing or other high performance computing (HPC) tasks. In at least one embodiment, one or more computing services 1416 may be utilized to perform parallel processing (e.g., using a parallel computing platform 1430) to process data substantially simultaneously by one or more applications and / or one or more tasks of a single application. In at least one embodiment, a parallel computing platform 1430 (e.g., NVIDIA's CUDA) may implement general computing on a GPU (GPGPU) (e.g., GPU / graphics 1422). In at least one embodiment, the software layer of the parallel computing platform 1430 may provide access to a virtual instruction set and parallel computing elements of a GPU to execute computing kernels. In at least one embodiment, the parallel computing platform 1430 may include memory, and in some embodiments, memory may be shared between and among multiple containers, and / or between and among different processing tasks within a single container. In at least one embodiment, inter-process communication (IPC) calls may be generated for multiple containers and / or multiple processes within a container to enable the same data (e.g., where multiple different stages of an application or multiple applications are processing the same information) to be used for a shared memory segment from the parallel computing platform 1430. In at least one embodiment, instead of copying data and moving the data to different locations in memory (e.g., read / write operations), the same data in the same location of the memory may be used for any number of processing tasks (e.g., at the same time, at different times, etc.). In at least one embodiment, since the data as a result of processing is used to generate new data, this information of the new location of the data may be stored and shared between various applications. In at least one embodiment, the location of the data and the location of the updated or modified data may be part of the definition of how to understand the payload in the container.

[0140] In at least one embodiment, the AI ​​service 1418 may be utilized to perform a reasoning service for executing a machine learning model associated with an application (e.g., a task is to execute one or more processing tasks of an application). In at least one embodiment, the AI ​​service 1418 may utilize the AI ​​system 1424 to execute a machine learning model (e.g., a neural network such as a CNN) for segmentation, reconstruction, object detection, feature detection, classification, and / or other reasoning tasks. In at least one embodiment, the application of the deployment pipeline 1410 may use one or more output models 1316 of the self-training system 1304 and / or other models of the application to perform reasoning on the imaging data. In at least one embodiment, two or more examples of reasoning using the application coordination system 1428 (e.g., a scheduler) may be available. In at least one embodiment, the first category may include a high priority / low latency path that can achieve a higher service level agreement, such as for performing reasoning on an urgent request in an emergency, or for a radiologist during a diagnostic process. In at least one embodiment, the second category may include a standard priority path that may be used for requests that may not be urgent or where analysis can be performed at a later time. In at least one embodiment, application coordination system 1428 can allocate resources (e.g., services 1320 and / or hardware 1322) for different reasoning tasks of AI service 1418 based on priority paths.

[0141] In at least one embodiment, the shared memory may be installed to the AI ​​service 1418 in the system 1400. In at least one embodiment, the shared memory may operate as a cache (or other storage device type) and may be used to process inference requests from applications. In at least one embodiment, when an inference request is submitted, a set of API instances of the deployment system 1306 may receive the request and may select one or more instances (e.g., for best fit, for load balancing, etc.) to process the request. In at least one embodiment, in order to process the request, the request may be entered into a database, and if it is not already in the cache, the machine learning model may be located from the model registry 1324, a verification step may ensure that the appropriate machine learning model is loaded into the cache (e.g., shared storage), and / or a copy of the model may be saved to the cache. In at least one embodiment, if the application is not yet running or there are not enough instances of the application, a scheduler (e.g., a scheduler of the pipeline manager 1412) may be used to start the application referenced in the request. In at least one embodiment, if the inference server has not yet been started to execute the model, the inference server may be started. Any number of inference servers may be started for each model. In at least one embodiment, in a pull model that clusters inference servers, the model can be cached whenever load balancing is beneficial. In at least one embodiment, the inference servers can be statically loaded into the corresponding distributed servers.

[0142] In at least one embodiment, inference can be performed using an inference server running in a container. In at least one embodiment, an instance of an inference server can be associated with a model (and optionally with multiple versions of a model). In at least one embodiment, if an instance of an inference server does not exist when a request is received to perform inference on a model, a new instance can be loaded. In at least one embodiment, when the inference server is started, the model can be passed to the inference server so that the same container can be used to serve different models as long as the inference server is running as a different instance.

[0143] In at least one embodiment, during application execution, a request for reasoning for a given application may be received, and a container (e.g., an instance of a hosting reasoning server) may be loaded (if not already loaded), and a launcher may be called. In at least one embodiment, preprocessing logic in the container may load, decode, and / or perform any additional preprocessing on the incoming data (e.g., using a CPU and / or GPU). In at least one embodiment, once the data is ready for reasoning, the container may perform reasoning on the data as needed. In at least one embodiment, this may include a single reasoning call for one image (e.g., a hand X-ray), or may require reasoning for hundreds of images (e.g., a chest CT). In at least one embodiment, the application may summarize the results before completion, which may include, but is not limited to, a single confidence score, pixel-level segmentation, voxel-level segmentation, generating visualizations, or generating text to summarize the results. In at least one embodiment, different priorities may be assigned to different models or applications. For example, some models may have a real-time (TAT less than 1 minute) priority, while other models may have a lower priority (e.g., TAT less than 10 minutes). In at least one embodiment, model execution time may be measured from a requesting mechanism or entity and may include collaborative network traversal time as well as execution time of an inference service.

[0144] In at least one embodiment, the transmission of requests between the service 1320 and the reasoning application can be hidden behind the SDK, and a robust transmission can be provided through a queue. In at least one embodiment, requests will be placed in a queue through an API for individual application / tenant ID combinations, and the SDK will pull the request from the queue and provide the request to the application. In at least one embodiment, the name of the queue can be provided in the environment where the SDK will pick up the queue. In at least one embodiment, asynchronous communication through queues may be useful because it can allow any instance of the application to pick up work when it is available. The results can be transmitted back through the queue to ensure that no data is lost. In at least one embodiment, the queue can also provide the ability to split the work, because the highest priority work can enter the queue connected to most instances of the application, and the lowest priority work can enter the queue connected to a single instance, which processes the tasks in the order received. In at least one embodiment, the application can run on a GPU-accelerated instance generated in the cloud 1426, and the reasoning service can perform reasoning on the GPU.

[0145] In at least one embodiment, visualization services 1420 may be utilized to generate visualizations for viewing application and / or deployment pipeline 1410 outputs. In at least one embodiment, visualization services 1420 may utilize GPU / graphics 1422 to generate visualizations. In at least one embodiment, visualization services 1420 may implement rendering effects such as ray tracing to generate higher quality visualizations. In at least one embodiment, visualizations may include, but are not limited to, 2D image rendering, 3D volume rendering, 3D volume reconstruction, 2D tomographic slices, VR displays, AR displays, and the like. In at least one embodiment, a virtualized environment may be used to generate a virtual interactive display or environment (e.g., a virtual environment) for system users (e.g., doctors, nurses, radiologists, etc.) to interact with. In at least one embodiment, visualization services 1420 may include internal visualizers, movies, and / or other rendering or image processing capabilities or functions (e.g., ray tracing, rasterization, internal optics, etc.).

[0146] In at least one embodiment, hardware 1322 may include GPU / graphics 1422, AI system 1424, cloud 1426, and / or any other hardware for executing training system 1304 and / or deployment system 1306. In at least one embodiment, GPU / graphics 1422 (e.g., NVIDIA's TESLA and / or QUADRO GPUs) may include any number of GPUs that may be used to perform processing tasks for any feature or functionality of compute services 1416, AI services 1418, visualization services 1420, other services, and / or software 1318. For example, for AI services 1418, GPU / graphics 1422 may be used to perform pre-processing on imaging data (or other data types used by machine learning models), post-processing on the output of machine learning models, and / or perform inference (e.g., to execute machine learning models). In at least one embodiment, cloud 1426, AI system 1424, and / or other components of system 1400 may use GPU / graphics 1422. In at least one embodiment, cloud 1426 may include a GPU-optimized platform for deep learning tasks. In at least one embodiment, AI system 1424 may use a GPU, and cloud 1426 (or at least part of a task being deep learning or reasoning) may be executed using one or more AI systems 1424. Likewise, while hardware 1322 is shown as discrete components, this is not intended to be limiting, and any component of hardware 1322 may be combined with or utilized by any other component of hardware 1322.

[0147] In at least one embodiment, AI system 1424 may include a purpose-built computing system (e.g., a supercomputer or HPC) configured for reasoning, deep learning, machine learning, and / or other AI tasks. In at least one embodiment, in addition to CPU, RAM, storage, and / or other components, features, or functions, AI system 1424 (e.g., NVIDIA's DGX system) may also include software (e.g., a software stack) that can use multiple GPUs / graphics 1422 to perform GPU-optimized tasks. In at least one embodiment, one or more AI systems 1424 may be implemented in a cloud 1426 (e.g., in a data center) to perform some or all of the AI-based processing tasks of system 1400.

[0148] In at least one embodiment, cloud 1426 may include a GPU-accelerated infrastructure (e.g., NVIDIA's NGC) that may provide a GPU-optimized platform for executing processing tasks of system 1400. In at least one embodiment, cloud 1426 may include an AI system 1424 for executing one or more AI-based tasks of system 1400 (e.g., as a hardware abstraction and scaling platform). In at least one embodiment, cloud 1426 may be integrated with an application coordination system 1428 that utilizes multiple GPUs to enable seamless scaling and load balancing between and among applications and services 1320. In at least one embodiment, cloud 1426 may be responsible for executing at least some services 1320 of system 1400, including compute services 1416, AI services 1418, and / or visualization services 1420, as described herein. In at least one embodiment, cloud 1426 can perform large and small batch inference (e.g., executing NVIDIA's TENSORRT), provide accelerated parallel computing APIs and platforms 1430 (e.g., NVIDIA's CUDA), execute application coordination system 1428 (e.g., Kubernetes), provide graphics rendering APIs and platforms (e.g., for ray tracing, 2D graphics, 3D graphics, and / or other rendering techniques to produce higher quality movie effects), and / or can provide other functionality for system 1400.

[0149] Fig.15A A data flow diagram of a process 1500 for training, retraining, or updating a machine learning model according to at least one embodiment is shown. In at least one embodiment, a non-limiting example may be used. Fig.15A The process 1500 may be performed by a system 1500 of the system 1500. In at least one embodiment, the process 1500 may utilize services and / or hardware as described herein. In at least one embodiment, the refined model 1512 generated by the process 1500 may be executed by the deployment system for one or more containerized applications in the deployment pipeline.

[0150] In at least one embodiment, model training 1514 may include retraining or updating an initial model 1504 (e.g., a pre-trained model) using new training data (e.g., new input data (such as customer data set 1506), and / or new ground truth data associated with the input data). In at least one embodiment, to retrain or update the initial model 1504, the output or loss layer of the initial model 1504 may be reset or deleted, and / or replaced with an updated or new output or loss layer. In at least one embodiment, the initial model 1504 may have previously fine-tuned parameters (e.g., weights and / or biases) retained from previous training, so training or retraining may not take as long or require as much processing as training the model from scratch. In at least one embodiment, during model training 1514, by resetting or replacing the output or loss layer of the initial model 1504, when generating predictions on the new customer data set 1506, the parameters for the new data set may be updated and re-adjusted based on the loss calculation associated with the accuracy of the output or loss layer.

[0151] In at least one embodiment, the pre-trained model 1406 may be stored in a data store or registry. In at least one embodiment, the pre-trained model 1406 may have been trained at least in part at one or more facilities other than the facility performing process 1500. In at least one embodiment, in order to protect the privacy and rights of patients, subjects, or customers of different facilities, the pre-trained model 1406 may have been trained locally using locally generated customer or patient data. In at least one embodiment, the cloud and / or other hardware may be used to train the pre-trained model 1406, but confidential, privacy-protected patient data may not be transmitted to, used by, or accessed by any component of the cloud (or other non-local hardware). In at least one embodiment, if the pre-trained model 1406 is trained using patient data from more than one facility, the pre-trained model 1406 may have been trained separately for each facility before training on patient or customer data from another facility. In at least one embodiment, for example where customer or patient data has been issued privacy issues (e.g., by being relinquished, used for experimental purposes, etc.), or where the customer or patient data is included in a public dataset, customer or patient data from any number of facilities can be used to train pre-trained models 1406 locally and / or externally, such as in a data center or other cloud computing infrastructure.

[0152] In at least one embodiment, when selecting an application to use in a deployment pipeline, a user may also select a machine learning model to use for a particular application. In at least one embodiment, a user may not have a model to use, so the user may select a pre-trained model to use with the application. In at least one embodiment, the pre-trained model may not be optimized to generate accurate results on the customer data set 1506 of the user facility (e.g., based on patient diversity, demographics, type of medical imaging equipment used, etc.). In at least one embodiment, before the pre-trained model 1406 is deployed into a deployment pipeline for use with one or more applications, the pre-trained model may be updated, retrained, and / or fine-tuned for use at various facilities.

[0153] In at least one embodiment, a user may select a pre-trained model 1406 to be updated, retrained, and / or fine-tuned, and the pre-trained model may be referred to as the initial model 1504 for training the system in process 1500. In at least one embodiment, a customer data set 1506 (e.g., imaging data, genomic data, sequencing data, or other data types generated by equipment at a facility) may be used to perform model training (which may include, but is not limited to, transfer learning) on ​​the initial model 1504 to generate a refined model 1512. In at least one embodiment, ground truth data corresponding to the customer data set 1506 may be generated by the model training system 1304. In at least one embodiment, the ground truth data may be generated, at least in part, at the facility by a clinician, scientist, physician, practitioner.

[0154] In at least one embodiment, AI-assisted annotation 1310 may be used in some examples to generate ground truth data. In at least one embodiment, AI-assisted annotation 1310 (e.g., implemented using an AI-assisted annotation SDK) may utilize a machine learning model (e.g., a neural network) to generate ground truth data for recommendations or predictions for a customer data set. In at least one embodiment, a user may use the annotation tool within a user interface (GUI) on a computing device.

[0155] In at least one embodiment, user 1510 can interact with the GUI via computing device 1508 to edit or fine-tune annotations or automatic annotations. In at least one embodiment, a polygon editing feature can be used to move vertices of a polygon to a more precise or fine-tuned position.

[0156] In at least one embodiment, once the customer dataset 1506 has associated ground truth data, the ground truth data (e.g., from AI-assisted annotations 1310, manual labeling, etc.) can be used during model training to generate a refined model 1512. In at least one embodiment, the customer dataset 1506 can be applied to the initial model 1504 any number of times, and the ground truth data can be used to update the parameters of the initial model 1504 until an acceptable level of accuracy is achieved for the refined model 1512. In at least one embodiment, once the refined model 1512 is generated, the refined model 1512 can be deployed within one or more deployment pipelines at a facility for use in performing one or more processing tasks with respect to medical imaging data.

[0157] In at least one embodiment, the refined model 1512 can be uploaded to the pre-trained models 1542 in the model registry for selection by another facility. In at least one embodiment, this process can be completed at any number of facilities, so that the refined model 1512 can be further refined any number of times on new data sets to generate a more general model.

[0158] Fig. 15B is an example illustration of a client-server architecture 1532 for enhancing an annotation tool with a pre-trained model 1542 according to at least one embodiment. In at least one embodiment, an AI-assisted annotation tool 1536 can be instantiated based on the client-server architecture 1532. In at least one embodiment, the AI-assisted annotation tool 1536 in an imaging application can assist a radiologist, for example, in identifying organs and abnormalities. In at least one embodiment, the imaging application can include a software tool that, as a non-limiting example, helps a user 1510 identify several extreme points on a specific organ of interest in an original image 1534 (e.g., in a 3D MRI or CT scan) and receive automatic annotation results for all 2D slices of the specific organ. In at least one embodiment, the results can be stored in a data store as training data 1538 and used as, for example, but not limited to, ground truth data for training. In at least one embodiment, when a computing device 1508 sends extreme points for AI-assisted annotation, for example, a deep learning model can receive the data as input and return an inference result for segmenting an organ or anomaly. In at least one embodiment, a pre-instantiated annotation tool (e.g., Fig. 15BThe AI-assisted annotation tools 1536 in the example may be enhanced by making an API call (e.g., API call 1544) to a server (such as an annotation assistant server 1540), which may include a set of pre-trained models 1542 stored in, for example, an annotation model registry. In at least one embodiment, the annotation model registry may store pre-trained models 1542 (e.g., machine learning models, such as deep learning models) that are pre-trained to perform AI-assisted annotation 1310 on specific organs or abnormalities. In at least one embodiment, these models may be further updated using a training pipeline. In at least one embodiment, the pre-installed annotation tools may be improved over time as new annotation data is added.

[0159] Various embodiments may be described by the following terms:

[0160] 1. A computer-implemented method comprising:

[0161] For a to-be-rendered image of a scene, determining a curve equation that approximates an object in the scene;

[0162] determining one or more pixel positions of the image to be rendered, the pixel positions including a portion of a curve determined according to the curve equation and having a width greater than a specified width corresponding to the object;

[0163] performing ray tracing on the determined pixel locations to identify one or more pixels where the traced ray intersects the object;

[0164] For individual pixels where the traced ray intersects the object, determining a geometry of a portion of the object represented within a pixel boundary approximating the pixel at the respective pixel location; and

[0165] The pixel values ​​of the object are blended with the background values ​​of the individual pixels according to one or more blending weights determined for the respective pixel positions, wherein the individual blending weights correspond to the fraction or percentage of the area of ​​the respective pixel occupied by the portion of the object.

[0166] 2. A computer-implemented method according to clause 1, wherein the curve equation is approximated using line segments within pixel boundaries of pixels where the traced ray intersects the object.

[0167] 3. A computer-implemented method according to clause 2, wherein the line segment is represented within a pixel boundary using two linear edges, the two linear edges being derived using the specified width and a hit normal of the curve within the pixel boundary.

[0168] 4. A computer-implemented method according to clause 3, wherein the geometric shape is determined in part by identifying one or more intersections of the two linear edges of the line segment having the specified width with the pixel boundary and identifying one or more vertices of the pixel boundary contained within the line segment.

[0169] 5. The computer-implemented method of clause 1, wherein the object having a specified width is at least one of: hair, fiber, string, blade of grass, string, antenna, or bristle.

[0170] 6. A computer-implemented method according to clause 1, wherein the specified width of the object is less than the width of one pixel of the image to be rendered, and wherein the width greater than the specified width is at least equal to the width of one pixel of the image to be rendered.

[0171] 7. A computer-implemented method according to clause 1, wherein the determined curve equation corresponds to the object that is closest to the virtual camera for the view of at least one pixel position of the image to be rendered.

[0172] 8. A processor, comprising:

[0173] One or more circuits for:

[0174] One or more circuits for:

[0175] For a to-be-rendered image of a scene, determining a curve equation that approximates an object in the scene;

[0176] determining one or more pixel positions of the image to be rendered, the pixel positions including a portion of a curve determined according to the curve equation and having a width greater than a specified width corresponding to the object;

[0177] performing ray tracing on the determined pixel locations to identify one or more pixels where the traced ray intersects the object;

[0178] For individual pixels where the traced ray intersects the object, determining a geometry of a portion of the object represented within a pixel boundary approximating the pixel at the respective pixel location; and

[0179] The pixel values ​​of the object are blended with the background values ​​of the individual pixels according to one or more blending weights determined for the respective pixel positions, wherein the individual blending weights correspond to the fraction or percentage of the area of ​​the respective pixel occupied by the portion of the object.

[0180] 9. A processor according to clause 8, wherein the curve equation is approximated using line segments within pixel boundaries of pixels where the traced ray intersects the object.

[0181] 10. A processor according to clause 9, wherein the line segment is represented within a pixel boundary using two linear edges, the two linear edges being derived using the specified width and a hit normal of the curve within the pixel boundary.

[0182] 11. A processor according to clause 8, wherein the geometric shape is determined in part by identifying one or more intersections of the two linear edges of the line segment having the specified width with the pixel boundary and identifying one or more vertices of the pixel boundary contained within the line segment.

[0183] 12. A processor according to clause 8, wherein the specified width of the object is less than the width of one pixel of the image to be rendered, and wherein the width greater than the specified width is at least equal to the width of one pixel of the image to be rendered.

[0184] 13. A processor according to clause 8, wherein the determined curve equation corresponds, for at least one pixel position of the image to be rendered, to the object that is closest to the virtual camera for the view of the at least one pixel position.

[0185] 14. A processor according to clause 8, wherein the processor is comprised of at least one of:

[0186] A system for performing simulation operations;

[0187] Systems for performing simulated operations to test or validate autonomous machine applications;

[0188] Systems for performing digital twin operations;

[0189] A system for performing light transport simulations;

[0190] Systems for rendering graphics output;

[0191] Systems for performing deep learning operations;

[0192] Systems implemented using edge devices;

[0193] Systems for generating or presenting virtual reality (VR) content;

[0194] Systems for generating or presenting augmented reality (AR) content;

[0195] Systems for generating or presenting mixed reality (MR) content;

[0196] A system comprising one or more virtual machines VM;

[0197] A system implemented at least in part in a data center;

[0198] A system for performing hardware testing using simulation;

[0199] Systems for synthetic data generation;

[0200] A system for performing generative AI operations using large language models (LLMs),

[0201] A collaborative content creation platform for 3D assets; or

[0202] A system implemented at least in part using cloud computing resources.

[0203] 15. A system comprising:

[0204] One or more processors for determining one or more blending weights for individual pixels of an image, the individual pixels of the image comprising a representation of a portion of an object approximated by a curve equation, the one or more processors for performing ray tracing on a first group of pixels identified using a curve determined according to the curve equation and having increasing width, the one or more blending weights being determined for a second group of pixels where traced rays are determined to intersect the elongated object, the one or more blending weights corresponding to the portion of the individual pixels occupied by the geometric representation of the portion of the object contained within the boundaries of the respective pixels.

[0205] 16. The system of clause 15, wherein the curve equation is approximated using line segments within pixel boundaries of pixels where the traced ray intersects the object.

[0206] 17. The system of clause 16, wherein the line segment is represented within a pixel boundary using two linear edges derived using the increased width and a hit normal of the curve within the pixel boundary.

[0207] 18. A system according to clause 15, wherein the geometric representation is determined in part by identifying one or more intersections of the two linear edges of the line segment with the pixel boundary and identifying one or more vertices of the pixel boundary contained within the line segment.

[0208] 19. A system according to clause 15, wherein at least one dimension of the object is smaller than the width of one pixel of the image to be rendered, and wherein the increased width is at least equal to the width of one pixel of the image to be rendered.

[0209] 20. The system of clause 15, wherein the system comprises at least one of the following:

[0210] A system for performing simulation operations;

[0211] Systems for performing simulated operations to test or validate autonomous machine applications;

[0212] Systems for performing digital twin operations;

[0213] A system for performing light transport simulations;

[0214] Systems for rendering graphics output;

[0215] Systems for performing deep learning operations;

[0216] A system for performing generative AI operations using large language models (LLMs),

[0217] Systems implemented using edge devices;

[0218] Systems for generating or presenting virtual reality (VR) content;

[0219] Systems for generating or presenting augmented reality (AR) content;

[0220] Systems for generating or presenting mixed reality (MR) content;

[0221] A system comprising one or more virtual machines VM;

[0222] A system implemented at least in part in a data center;

[0223] Systems that perform hardware testing using simulation;

[0224] Systems for synthetic data generation;

[0225] A collaborative content creation platform for 3D assets; or

[0226] A system implemented at least in part using cloud computing resources.

[0227] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described in detail above. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0228] Unless otherwise noted or clearly contradictory to the context, in the context of describing the disclosed embodiments (particularly in the context of the appended claims), the use of the terms "one" and "an" and "the" and similar references should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include", "have", "include" and "contain" should be interpreted as open terms (meaning "including but not limited to") unless otherwise noted. The term "connected" (which refers to a physical connection when unmodified) should be interpreted as partially or completely included, attached to or connected together, even if there are some interventions. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, respectively, and each individual value is incorporated into the specification as if it were individually described herein. Unless otherwise noted or contradictory to the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set including one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0229] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B and C" are understood in context to be generally used to refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A and B and C. For example, in the illustrative example of a set having three members, the conjunction phrases "at least one of A, B, and C" and "at least one of A, B and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunction language is not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. In addition, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to a plural state (e.g., "plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, the phrase "based on" means "based at least in part on" rather than "based solely on" unless otherwise specified or clear from context.

[0230] Unless otherwise indicated herein or clearly contradictory to the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are jointly executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions), but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) on which executable instructions are stored, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all the code, but the plurality of non-transitory computer-readable storage media stores all the code together. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and the main CPU executes some instructions, while the GPU executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0231] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. In addition, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system that includes multiple devices that operate in different ways, so that the distributed computer system performs the operations described herein, and so that a single device does not perform all operations.

[0232] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating that any non-claimed element is essential to practicing the disclosure.

[0233] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0234] In the specification and claims, the terms "coupled" and "connected," as well as their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. On the contrary, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0235] Unless explicitly stated otherwise, it is to be understood that throughout the specification, terms such as “processing”, “computing”, “calculating”, “determining” and the like refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers or other such information storage, transmission or display devices of the computing system.

[0236] In a similar manner, the term "processor" may refer to any device or part of a memory that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Similarly, each process may refer to multiple processes to execute instructions sequentially or in parallel, continuously or intermittently. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0237] In this document, reference may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, a computer system or a computer-implemented machine. It is possible to obtain, acquire, receive or input analog and digital data in a variety of ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving or inputting analog or digital data can be accomplished by transmitting data from providing an entity to acquiring an entity via a computer network. It is also possible to reference to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending or presenting analog or digital data can be accomplished by transmitting data as an input or output parameter of a function call, an API or an interprocess communication mechanism.

[0238] Although the above discussion sets forth example implementations of the described techniques, other architectures may be used to implement the described functionality and are intended to fall within the scope of the present disclosure. In addition, although specific responsibilities are defined above for discussion purposes, various functions and responsibilities may be allocated and divided in different ways, depending on the circumstances.

[0239] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A computer-implemented method comprising: For a to-be-rendered image of a scene, determining a curve equation that approximates an object in the scene; determining one or more pixel positions of the image to be rendered, the pixel positions including a portion of a curve determined according to the curve equation and having a width greater than a specified width corresponding to the object; performing ray tracing on the determined pixel locations to identify one or more pixels where the traced ray intersects the object; For individual pixels where the traced ray intersects the object, determining a geometry of a portion of the object represented within a pixel boundary approximating the pixel at the respective pixel location; as well as The pixel values ​​of the object are blended with the background values ​​of the individual pixels according to one or more blending weights determined for the respective pixel positions, wherein the individual blending weights correspond to the fraction or percentage of the area of ​​the respective pixel occupied by the portion of the object.

2. The computer-implemented method of claim 1 , wherein: The curve equation is approximated using line segments within pixel boundaries of pixels where the traced ray intersects the object.

3. The computer-implemented method of claim 2, wherein: The line segment is represented within a pixel boundary using two linear edges derived using the specified width and a hit normal of the curve within the pixel boundary.

4. The computer-implemented method of claim 3, wherein: The geometric shape is determined in part by identifying one or more intersections of the two linear edges of the line segment having the specified width with the pixel boundary and identifying one or more vertices of the pixel boundary contained within the line segment.

5. The computer-implemented method of claim 1 , wherein: The object having the specified width is at least one of: hair, fiber, string, blade of grass, string, antennae, or bristles.

6. The computer-implemented method of claim 1 , wherein: The specified width of the object is smaller than a width of one pixel of the image to be rendered, and a width greater than the specified width is at least equal to a width of one pixel of the image to be rendered.

7. The computer-implemented method of claim 1 , wherein: The determined curve equation corresponds to the object that is closest to the virtual camera for the view of the at least one pixel position for the image to be rendered.

8. A processor, comprising: One or more circuits for: For a to-be-rendered image of a scene, determining a curve equation that approximates an object in the scene; determining one or more pixel positions of the image to be rendered, the pixel positions including a portion of a curve determined according to the curve equation and having a width greater than a specified width corresponding to the object; performing ray tracing on the determined pixel locations to identify one or more pixels where the traced ray intersects the object; For individual pixels where the traced ray intersects the object, determining a geometry of a portion of the object represented within a pixel boundary approximating the pixel at the respective pixel location; as well as The pixel values ​​of the object are blended with the background values ​​of the individual pixels according to one or more blending weights determined for the respective pixel positions, wherein the individual blending weights correspond to the fraction or percentage of the area of ​​the respective pixel occupied by the portion of the object.

9. The processor of claim 8, wherein: The curve equation is approximated using line segments within pixel boundaries of pixels where the traced ray intersects the object.

10. The processor of claim 9, wherein: The line segment is represented within a pixel boundary using two linear edges derived using the specified width and a hit normal of the curve within the pixel boundary.

11. The processor of claim 8, wherein: The geometric shape is determined in part by identifying one or more intersections of the two linear edges of the line segment having the specified width with the pixel boundary and identifying one or more vertices of the pixel boundary contained within the line segment.

12. The processor of claim 8, wherein: The specified width of the object is smaller than a width of one pixel of the image to be rendered, and the width greater than the specified width is at least equal to a width of one pixel of the image to be rendered.

13. The processor of claim 8, wherein: The determined curve equation corresponds to the object that is closest to the virtual camera for the view of the at least one pixel position for the image to be rendered.

14. The processor of claim 8, wherein: The processor is included in at least one of the following: A system for performing simulation operations; Systems for performing simulated operations to test or validate autonomous machine applications; Systems for performing digital twin operations; A system for performing light transport simulations; Systems for rendering graphical output; Systems for performing deep learning operations; Systems implemented using edge devices; Systems for generating or presenting virtual reality (VR) content; Systems for generating or presenting augmented reality (AR) content; Systems for generating or presenting mixed reality (MR) content; A system comprising one or more virtual machines VM; A system implemented at least in part in a data center; A system for performing hardware testing using simulation; Systems for synthetic data generation; A system for performing generative AI operations using large language models (LLMs), A collaborative content creation platform for 3D assets; or A system implemented at least in part using cloud computing resources.

15. A system comprising: One or more processors for determining one or more blending weights for individual pixels of an image, the individual pixels of the image comprising a representation of a portion of an object approximated by a curve equation, the one or more processors for performing ray tracing on a first group of pixels identified using a curve determined according to the curve equation and having increasing width, the one or more blending weights being determined for a second group of pixels where traced rays are determined to intersect the elongated object, the one or more blending weights corresponding to the portion of the individual pixels occupied by the geometric representation of the portion of the object contained within the boundaries of the respective pixels.

16. The system of claim 15, wherein: The curve equation is approximated using line segments within the pixel boundaries of pixels where the traced ray intersects the object.

17. The system of claim 16, wherein: The line segment is represented within a pixel boundary using two linear edges derived using the increased width and a hit normal of the curve within the pixel boundary.

18. The system of claim 15, wherein: The geometric representation is determined in part by identifying one or more intersections of the two linear edges of the line segment with the pixel boundary and identifying one or more vertices of the pixel boundary contained within the line segment.

19. The system of claim 15, wherein: At least one dimension of the object is smaller than a width of one pixel of the image to be rendered, and wherein the increased width is at least equal to a width of one pixel of the image to be rendered.

20. The system of claim 15, wherein: The system includes at least one of the following: A system for performing simulation operations; Systems for performing simulated operations to test or validate autonomous machine applications; Systems for performing digital twin operations; A system for performing light transport simulations; Systems for rendering graphical output; Systems for performing deep learning operations; A system for performing generative AI operations using large language models (LLMs), Systems implemented using edge devices; Systems for generating or presenting virtual reality (VR) content; Systems for generating or presenting augmented reality (AR) content; Systems for generating or presenting mixed reality (MR) content; A system comprising one or more virtual machines VM; A system implemented at least in part in a data center; Systems that perform hardware testing using simulation; Systems for synthetic data generation; A collaborative content creation platform for 3D assets; or A system implemented at least in part using cloud computing resources.

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