Power supply and display device including the same

Abstract

A display device includes a display panel configured to display an image, a timing controller configured to control the display panel, and a power supply including: an output circuit configured to generate output power for supplying power to the display panel based on input power; and an output controller configured to sense a voltage output through an output terminal of the output circuit to obtain a sensing value, in which the output controller provides a reference voltage value and a compensation voltage value of a level different from that of the reference voltage value based on an external signal, at least one of a reference voltage value and a compensation voltage value is selectively output based on an external signal to provide a voltage value, and a control signal for controlling the output circuit is generated based on the sensing value and the voltage value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0154579, filed on November 9, 2023, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a power supply and a display device including the power supply. Background Art

[0004] As information technology advances, the market for display devices, which are connecting media between users and information, continues to grow. Therefore, the use of display devices such as light-emitting display devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices continues to grow.

[0005] The display device described above includes: a display panel including a plurality of sub-pixels; a driver outputting a driving signal for driving the display panel; and a power supply generating power to be supplied to the display panel or the driver.

[0006] In such a display device, when a driving signal (eg, a scan signal and a data signal) is supplied to each of subpixels provided in a display panel, a selected subpixel may transmit light or may self-emit light, and thus an image may be displayed. Summary of the invention

[0007] In order to overcome the above-mentioned problems of the related art, the present disclosure can provide a power supply and a display device including a power supply, which can remove or reduce (improve) the output voltage ripple caused by the occurrence of load transient conditions when driving a display panel to prevent (minimize) the possibility of motion afterimages, thereby improving the display quality of motion images.

[0008] To achieve these objectives and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device includes a display panel configured to display an image, a timing controller configured to control the display panel, and a power supply, the power supply including: an output circuit configured to generate output power for supplying power to the display panel based on input power; and an output controller configured to sense a voltage output through an output terminal of the output circuit to obtain a sensing value, wherein the output controller provides a reference voltage value and a compensation voltage value having a level different from the reference voltage value based on an external signal, selectively outputs at least one of the reference voltage value and the compensation voltage value based on the external signal to provide a voltage value, and generates a control signal for controlling the output circuit based on the sensing value and the voltage value.

[0009] The output controller may cancel an output voltage ripple appearing in an output terminal of the output circuit when an output current is generated from the output circuit based on the compensation voltage value.

[0010] The output controller may include: a reference voltage setting circuit, which is configured to output a reference voltage value based on voltage setting data included in an external signal; and a first compensation voltage setting circuit and a second compensation voltage setting circuit, which are configured to output a first compensation voltage value and a second compensation voltage value, respectively, based on current setting data included in the external signal.

[0011] The reference voltage value, the first compensation voltage value, and the second compensation voltage value may have the following relationship: second compensation voltage value<reference voltage value<first compensation voltage value.

[0012] The reference voltage setting circuit can output a reference voltage value, the level of which increases as the voltage setting data value included in the voltage setting data increases, the first compensation voltage setting circuit can output a first compensation voltage value, the level of which increases as the current setting data value included in the current setting data increases, and the second compensation voltage setting circuit can output a second compensation voltage value, the level of which decreases as the current setting data value included in the current setting data increases.

[0013] The output controller may include a selection circuit configured to selectively output one of the reference voltage value, the first compensation voltage value, and the second compensation voltage value based on a logic state of each of a global shutter-on signal and a global shutter-off signal included in the external signal.

[0014] The first compensation voltage value and the second compensation voltage value may have an inverse relationship.

[0015] The selection circuit may output a reference voltage value during a first time period in which a load transient caused by the driving of the display panel does not occur, output a first compensation voltage value during a second time period in which the load transient caused by the driving of the display panel starts, output the reference voltage value during a third time period in which the driving of the display panel is maintained, and output a second compensation voltage value during a fourth time period in which the load transient caused by the driving of the display panel ends.

[0016] In another aspect of the present disclosure, a power supply includes: an output circuit configured to generate output power based on input power; and an output controller configured to sense a voltage output through an output terminal of the output circuit to obtain a sensing value, wherein the output controller provides a reference voltage value and a compensation voltage value having a level different from the reference voltage value based on an external signal, selectively outputs at least one of the reference voltage value and the compensation voltage value based on the external signal to provide a voltage value, and generates a control signal for controlling the output circuit based on the sensing value and the voltage value.

[0017] The output controller may include: a reference voltage setting circuit, which is configured to output a reference voltage value based on voltage setting data included in an external signal; and a first compensation voltage setting circuit and a second compensation voltage setting circuit, the first compensation voltage setting circuit and the second compensation voltage setting circuit are configured to output a first compensation voltage value and a second compensation voltage value, respectively, based on current setting data included in the external signal, and the reference voltage value, the first compensation voltage value and the second compensation voltage value may have the following relationship: second compensation voltage value < reference voltage value < first compensation voltage value.

[0018] The reference voltage setting circuit can output a reference voltage value, the level of which increases as the voltage setting data value included in the voltage setting data increases, the first compensation voltage setting circuit can output a first compensation voltage value, the level of which increases as the current setting data value included in the current setting data increases, and the second compensation voltage setting circuit can output a second compensation voltage value, the level of which decreases as the current setting data value included in the current setting data increases.

[0019] The output controller may include a selection circuit configured to selectively output one of the reference voltage value, the first compensation voltage value, and the second compensation voltage value based on a logic state of each of an on signal and an off signal included in the external signal.

[0020] The selection circuit can output a reference voltage value during a first time period when an output current is not generated from the output circuit, output a first compensation voltage value during a second time period when the output current starts to be generated, output the reference voltage value during a third time period when the output current is maintained, and output a second compensation voltage value during a fourth time period when the generation of the output current ends. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0022] Figure 1 is a block diagram schematically showing a light emitting display device, Figure 2 and Figure 3 is a diagram for describing the configuration of a gate-in-panel (GIP) type scan driver, and Figure 4 is an exemplary diagram of a sub-pixel;

[0023] Figures 5 to 7 is a graph for describing changes in current with respect to a driving mode when expressing a high-grayscale still image, a medium-grayscale still image, and a low-grayscale still image, and Figure 8 and Fig. 9 is a graph used to describe the change in current with respect to drive mode when changing gray levels in a moving image;

[0024] Fig.10 is a block diagram schematically showing some elements of a light emitting display device according to a first embodiment, Fig.11 is an output waveform diagram for describing the output control concept of the power supply according to the first embodiment, and Fig.12 is an output waveform diagram showing the difference before and after applying the first embodiment;

[0025] Fig.13 is a block diagram showing in more detail the configuration of the power supply according to the second embodiment, Fig.14 is an output waveform diagram for describing the output control concept of the power supply according to the second embodiment, Fig.15 and Fig.16 is a diagram for describing the operation of a partial period when the operation of the power supply according to the second embodiment is performed, and Fig.17 It is shown Fig.14 A block diagram of an implementation example of the circuit shown in ; and

[0026] Fig.18 is a block diagram schematically showing some elements of a light emitting display device according to a third embodiment, Fig.19 is a block diagram showing in more detail the configuration of the power supply according to the third embodiment, Fig. 20 is an output waveform diagram for describing the output control concept of the power supply according to the third embodiment, Fig.21 and Fig. 22 is a diagram for describing the operation of a partial period when the operation of the power supply according to the third embodiment is performed, and Fig.23 and Fig.24 is a diagram for describing a ratio setting circuit unit. DETAILED DESCRIPTION

[0027] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings showing exemplary embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art.

[0028] The display device according to the present disclosure can be applied to a television (TV), a video player, a personal computer (PC), a home theater, a vehicle electronic device, and a smart phone, but is not limited thereto. The display device according to the present disclosure can be implemented as a light-emitting display device, a quantum dot display (QDD) device, or a liquid crystal display (LCD) device. Hereinafter, for ease of description, for example, a light-emitting display device that emits light by using an inorganic light-emitting diode or an organic light-emitting diode will be described.

[0029] Figure 1 is a block diagram schematically showing a light emitting display device, Figure 2 and Figure 3 is a diagram for describing the configuration of a gate-in-panel (GIP) type scan driver, and Figure 4 is an exemplary diagram of a sub-pixel.

[0030] like Figures 1 to 4 As shown, the light emitting display device according to an embodiment of the present disclosure may include a video supply unit 110 , a timing controller 120 , a scan driver 130 , a data driver 140 , a display panel 150 , and a power supply 180 .

[0031] The video supply unit 110 (group or host system) may output a video data signal supplied from the outside or various driving signals and image data signals stored in its internal memory. The video supply unit 110 may supply the data signal and various driving signals to the timing controller 120.

[0032] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the scan driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals (a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync). The timing controller 120 may provide the data driver 140 with the data signal DATA and the data timing control signal DDC supplied by the video supply unit 110. The timing controller 120 may be implemented as an integrated circuit (IC) type and may be mounted on a printed circuit board (PCB), but is not limited thereto.

[0033] The scan driver 130 may output a scan signal (or a scan voltage) in response to a gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 may supply the scan signal to a plurality of sub-pixels included in the display panel 150 through a plurality of gate lines GL1 to GLm. The scan driver 130 may be implemented as an IC type, or may be directly disposed on the display panel 150 in a GIP type, but is not limited thereto. However, hereinafter, for ease of description, the gate driver 130 will be described in terms of gate timing control signals GDC and gate lines GL1 to GLm. Figure 2 and Figure 3 A GIP type scan driver in is described as an example.

[0034] like Figure 2 and Figure 3 As shown, the GIP type scan driver 130 may include shift registers 130a and 130b, which are formed as a GIP type at one side and the other side of the non-display area NA of the display panel 150. The shift registers 130a and 130b may be formed as a thin film type in the non-display area NA of the display panel 150 based on the GIP type. The GIP type scan driver 130 may output scan signals Scan[1] to Scan[m] for turning on or off transistors provided in the display area AA of the display panel 150.

[0035] The GIP type scan driver 130 may operate based on voltages and signals output from the timing controller 120, the power supply 180, and the level shifter 160. The level shifter 160 may generate signals required to drive the GIP type scan driver 130 (130a and 130b) based on voltages and signals output from the timing controller 120 and the power supply 180.

[0036] In response to the data timing control signal DDC supplied from the timing controller 120, the data driver 140 may sample and latch the data signal DATA, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driver 140 may supply data voltages to the sub-pixels of the display panel 150 through a plurality of data lines DL1 to DLn, respectively. The data driver 140 may be implemented as an IC type, or may be mounted on the display panel 150 or a PCB, but is not limited thereto.

[0037] The power supply 180 may generate an output voltage including a high level voltage and a low level voltage based on an input voltage supplied from the outside, and may output the high level voltage and the low level voltage through a high level voltage line EVDD and a low level voltage line EVSS each connected to the display panel 150. In addition to the high level voltage and the low level voltage, the power supply 180 may also generate and output a voltage (e.g., a gate high voltage and a gate low voltage) required to drive the scan driver 130 or a voltage (e.g., a drain voltage and a half-drain voltage) required to drive the data driver 140.

[0038] The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. The display panel 150 may include a plurality of sub-pixels SP for displaying an image based on a driving signal including a scan signal and a data voltage, a high level voltage, and a low level voltage. Figure 4 As shown, the sub-pixel SP may be connected to the first data line DL1, the first gate line GL1, the high-level voltage line EVDD, and the low-level voltage line EVSS. The sub-pixel SP may emit light by itself. The sub-pixel SP may emit light having one color among red, green, blue, and white.

[0039] Hereinbefore, each of the timing controller 120, the scan driver 130 and the data driver 140 is described as a separate element. However, one or more of the timing controller 120, the scan driver 130 and the data driver 140 may be integrated into one IC based on the implementation type of the light emitting display device.

[0040] The above-mentioned light-emitting display device can be operated based on a normal driving mode and a global shutter driving mode, the normal driving mode maintains the output of the current fully applied to the display panel 150 and expresses an image, and the global shutter driving mode controls the on / off of the output of the current fully applied to the display panel 150 and expresses an image. In addition, the output of the power supply 180 can be changed based on the characteristics of the image and the driving mode. This will be briefly described below.

[0041] Figures 5 to 7 is a graph for describing changes in current with respect to a driving mode when expressing a high-grayscale still image, a medium-grayscale still image, and a low-grayscale still image, and Figure 8 and Fig. 9 A diagram for describing changes in current with respect to a driving mode when grayscale levels are changed in a moving image.

[0042] like Figures 5 to 7As shown, the display panel can express a still image, which is divided into high grayscale, medium grayscale and low grayscale with respect to the intensity of the current applied to the device. In the case of driving the display panel based on the normal drive mode NMD, it can be seen that the output of the current is maintained without disconnection during the frame time period (Nth frame to (n+2) frame). On the other hand, in the case of driving the display panel based on the global shutter drive mode GSD, it can be seen that the output of the current is applied in the form of on / off and then disconnected, as in a part of the frame time period (Nth frame to (n+2) frame).

[0043] like Figure 8 and Fig. 9 As shown, in the normal drive mode NMD, in the case of expressing a moving image that changes from a high grayscale to a low grayscale or a moving image that changes from a low grayscale to a high grayscale, there may be a possibility of motion afterimages occurring due to the output of the maintained current, wherein an unexpected image is recognized by the change in current as in the Nth frame + 1st frame (the (n+1)th frame). On the other hand, in the global shutter drive mode GSD, in the case of expressing a moving image that changes from a high grayscale to a low grayscale or a moving image that changes from a low grayscale to a high grayscale, after the output of the current is disconnected during the grayscale conversion period, the output of the current may occur immediately during the image expression period, thereby preventing (minimizing) the possibility of motion afterimages occurring.

[0044] In the embodiments described below, based on the global shutter drive mode GSD, the output voltage ripple caused by the occurrence of load transient conditions when driving the display panel can be removed or reduced (improved). However, the embodiments described below are not limited to the case where the display panel is driven based on the global shutter drive mode GSD, and can be applied to various drive modes.

[0045] Fig.10 is a block diagram schematically showing some elements of a light emitting display device according to a first embodiment, Fig.11 is an output waveform diagram for describing the output control concept of the power supply according to the first embodiment, and Fig.12 1 is an output waveform diagram showing the difference before and after the first embodiment is applied.

[0046] like Fig.10 As shown, the light emitting display device according to the first embodiment may include a display panel 150 , a power supply 180 , and a timing controller 120 .

[0047] The timing controller 120 may output a global shutter on signal GSO, a global shutter off signal GSF, voltage setting data OVD, and current setting data OCD to control the power supply 180. Hereinafter, an example will be described in which a global shutter signal including a global shutter on signal GSO and a global shutter off signal GSF is output from the timing controller 120 and is divided into an on signal and an off signal. However, the global shutter on signal GSO and the global shutter off signal GSF may be integrated into one global shutter signal and may be output as one signal.

[0048] The timing controller 120 may transmit a global shutter on signal GSO, a global shutter off signal GSF, voltage setting data OVD, and current setting data OCD based on a communication interface connected to the power supply 180. For example, the communication interface connected between the timing controller 120 and the power supply 180 may be I2C, SPI, or S-Wire, but is not limited thereto.

[0049] The global shutter on signal GSO may be defined as a signal activating the operation of the global shutter, and the global shutter off signal GSF may be defined as a signal deactivating the operation of the global shutter. The global shutter on signal GSO and the global shutter off signal GSF may be configured as signals such as logic high or logic low, but are not limited thereto.

[0050] The voltage setting data OVD may be defined as a data signal for setting an output voltage of a circuit included in the power supply 180, and the current setting data OCD may be defined as a data signal for setting an output current of a circuit included in the power supply 180. The voltage setting data OVD and the current setting data OCD may be configured with N (where N may be an integer of 1 or more) bits of data, but are not limited thereto.

[0051] The power supply 180 may generate a high level voltage required to drive the display panel 150 based on an input power VIN applied from the outside. The high level voltage output from the power supply 180 may be applied through a high level voltage line EVDD connected to an output terminal of the power supply 180. The power supply 180 may include an output circuit unit 183 that generates a high level voltage based on the input power VIN, and an output controller 185 that controls the operation of the output circuit unit 183.

[0052] The output circuit unit 183 may include an input capacitor CI, an inductor LI, a first transistor M1, a second transistor M2, and an output capacitor CO. The input capacitor CI may be connected to the input terminal at one end thereof, and the other end thereof may be connected to the ground terminal. The inductor LI may be connected to the input terminal at one end thereof, and the other end thereof may be connected to the first electrode of the first transistor M1. The first transistor M1 may include a first electrode connected to the other end of the inductor LI, a second electrode connected to the output terminal, and a gate electrode connected to the first control line MC1. The second transistor M2 may include a first electrode connected to the first transistor M1 and the other end of the inductor LI, a second electrode connected to the ground terminal, and a gate electrode connected to the second control line MC2. The output capacitor CO may be connected to the output terminal at one end thereof, and the other end thereof may be connected to the ground terminal.

[0053] The output controller 185 may sense a high level voltage output through the output terminal of the output circuit unit 183 to obtain a sense value VSEN, and may generate a first control signal and a second control signal output through the first control line MC1 and the second control line MC2, thereby controlling the output circuit unit 183. The output controller 185 may change generation conditions of the first control signal and the second control signal based on an external signal such as a global shutter-on signal GSO, a global shutter-off signal GSF, voltage setting data OVD, and current setting data OCD supplied from the timing controller 120, and the sense value VSEN.

[0054] like Fig.10 and Fig.11 As shown, the power supply 180 according to the first embodiment can provide compensation values ​​VC1 and VC2 appearing in the “output voltage-controlled value” when generating the output current to remove the ripple values ​​RP1 and RP2 appearing in the “output voltage-predicted value”. The power supply 180 according to the first embodiment can compensate the output voltage based on the compensation values ​​VC1 and VC2 to provide the “output voltage-actual value”, and the compensation values ​​VC1 and VC2 are provided corresponding to the on-time period when the output current starts to be generated and the off-time period when the generation of the output current ends.

[0055] like Fig.12 As shown, before applying the power supply 180 according to the first embodiment, it can be seen that a large output voltage ripple is displayed. On the other hand, after applying the power supply 180 according to the first embodiment, it can be seen that the situation is improved and almost no output voltage ripple is displayed.

[0056] Therefore, the power supply 180 according to the first embodiment can remove or reduce (improve) the output voltage ripple by compensating the output voltage based on the load transient condition (eg, the occurrence of the output current based on the signal and data output from the timing controller).

[0057] Fig.13 is a block diagram showing the configuration of the power supply 180 according to the second embodiment in more detail, Fig.14 is an output waveform diagram for describing the output control concept of the power supply 180 according to the second embodiment, Fig.15 and Fig.16 is a diagram for describing the operation of a partial period when the operation of the power supply 180 according to the second embodiment is performed, and Fig.17 It is shown Fig.14 A block diagram of an implementation example of the circuit shown in .

[0058] like Fig.13 As shown, the power supply 180 according to the second embodiment may include an output circuit unit 183 that generates a high-level voltage based on the input power VIN, and an output controller 185 that controls the operation of the output circuit unit 183 as described in the first embodiment. The power supply 180 according to the second embodiment may be different from the first embodiment in the configuration of the output controller 185, and therefore, the difference will be described in more detail.

[0059] The output controller 185 may include a reference voltage setting circuit unit OVC1, a first compensation voltage setting circuit unit OVC2, a second compensation voltage setting circuit unit OVC3, a first selection circuit unit SEL1, a second selection circuit unit SEL2, a voltage sensing circuit unit ERA, R1 and R2, and a control signal generator PWMC.

[0060] The reference voltage setting circuit unit OVC1 may output a reference voltage value Vref0 based on the voltage setting data OVD. The level of the reference voltage value Vref0 may vary based on the voltage setting data OVD. For example, the reference voltage setting circuit unit OVC1 may output a reference voltage value Vref0 whose level increases as the voltage setting data value included in the voltage setting data OVD increases.

[0061] The first compensation voltage setting circuit unit OVC2 may output a first compensation voltage value Vref1 based on the current setting data OCD. The level of the first compensation voltage value Vref1 may vary based on the current setting data OCD. For example, the first compensation voltage setting circuit unit OVC2 may output a first compensation voltage value Vref1 whose level increases as the current setting data value included in the current setting data OCD increases.

[0062] The second compensation voltage setting circuit unit OVC3 may output a second compensation voltage value Vref2 having an inverse relationship with the first compensation voltage value Vref1 based on the current setting data OCD. The level of the second compensation voltage value Vref2 may vary based on the current setting data OCD. For example, the second compensation voltage setting circuit unit OVC3 may output a second compensation voltage value Vref2 whose level decreases as the current setting data value included in the current setting data OCD increases.

[0063] Furthermore, in the second embodiment, for example, the first compensation voltage setting circuit unit OVC2 and the second compensation voltage setting circuit unit OVC3 may output the first compensation voltage value Vref1 and the second compensation voltage value Vref2 having an inverse relationship based on the current setting data OCD.

[0064] However, according to a modified embodiment of the second embodiment, the first compensation voltage setting circuit unit OVC2 may be implemented to output the first compensation voltage value Vref1 based on the first current setting data, and the second compensation voltage setting circuit unit OVC3 may be implemented to output the second compensation voltage value Vref2 based on the second current setting data. In this case, the first compensation voltage value Vref1 and the second compensation voltage value Vref2 may be set to a type that is not completely matched therebetween, so that the first compensation voltage value Vref1 and the second compensation voltage value Vref2 have an inverse relationship, but one of the voltage values ​​has a different level.

[0065] The first selection circuit unit SEL1 may output a reference voltage value Vref0 or may output a first compensation voltage value Vref1 in response to a global shutter-on signal GSO. The first selection circuit unit SEL1 may supply one of the reference voltage value Vref0 and the first compensation voltage value Vref1 to the second selection circuit unit SEL2.

[0066] The second selection circuit unit SEL2 may output one of the reference voltage value Vref0 and the first compensation voltage value Vref1 supplied from the first selection circuit unit SEL1 in response to the global shutter off signal GSF, or may output the second compensation voltage value Vref2. The second selection circuit unit SEL2 may supply one of the reference voltage value Vref0, the first compensation voltage value Vref1, and the second compensation voltage value Vref2 to the voltage sensing circuit units ERA, R1, and R2.

[0067] The voltage sensing circuit units ERA, R1, and R2 can sense the high level voltage output from the output terminal of the output circuit unit 183 to obtain the sensing value VSEN. The voltage sensing circuit units ERA, R1, and R2 can output a signal for controlling the control signal generator PWMC based on the sensing value VSEN and the voltage value Vref output from the second selection circuit unit SEL2.

[0068] The voltage sensing circuit unit ERA, R1 and R2 may include an error amplifier ERA, a first resistor R1 and a second resistor R2. The first resistor R1 may be connected to the output terminal of the output circuit unit 183 at one end thereof, and the other end thereof may be connected to the inverting terminal (-) of the error amplifier ERA and one end of the second resistor R2. The second resistor R2 may be connected to the inverting terminal (-) of the error amplifier ERA and the other end of the first resistor R1 at one end thereof, and the other end thereof may be connected to the ground terminal. The inverting terminal (-) of the error amplifier ERA may be connected to a node connected to the first resistor R1 and the second resistor R2, and its non-inverting terminal (+) may be connected to the output terminal of the second selection circuit unit SEL2.

[0069] The control signal generator PWMC may generate a first control signal and a second control signal for controlling the first transistor M1 and the second transistor M2 included in the output circuit unit 183 based on a signal output from the error amplifier ERA. The first control signal and the second control signal may be generated as a pulse width modulation (PWM) signal. The control signal generator PWMC may change a generation condition of the first control signal, and may output a second control signal generated by the control signal generator PWMC through a first control line MC1 and a second control line MC2.

[0070] In addition, the power supply 180 according to the second embodiment can generate a high output that increases with the increase in the level of the voltage value Vref, as in the relationship of the second compensation voltage value Vref2 <reference voltage value Vref0 <first compensation voltage value Vref1. Here, the level ratio of the second compensation voltage value Vref2 <reference voltage value Vref0 <first compensation voltage value Vref1 can be adjusted based on the driving condition (condition).

[0071] like Fig.13 and Fig.14 As shown, in the power supply 180 according to the second embodiment, the voltage value Vref applied to the non-inverting terminal (+) of the error amplifier ERA can be changed based on the time period when the output current is not generated, the on time period when the output current starts to be generated, and the off time period when the generation of the output current ends. This will be described below.

[0072] When the global shutter on signal GSO and the global shutter off signal GSF are in a logic low L state, a reference voltage value Vref0 may be applied to the non-inverting terminal (+) of the error amplifier ERA. When the global shutter on signal GSO is in a logic high H state and the global shutter off signal GSF is in a logic low L state, a first compensation voltage value Vref1 may be applied to the non-inverting terminal (+) of the error amplifier ERA. When the global shutter on signal GSO is in a logic low L state and the global shutter off signal GSF is in a logic high H state, a second compensation voltage value Vref2 may be applied to the non-inverting terminal (+) of the error amplifier ERA. Therefore, the voltage value Vref applied to the non-inverting terminal (+) of the error amplifier ERA may change based on the logic state of each of the global shutter on signal GSO and the global shutter off signal GSF.

[0073] like Fig.15 and Fig.16 As shown, when the global shutter turn-on signal GSO is applied in a logic low L state, the first selection circuit unit SEL1 may output a reference voltage value Vref0, and when the global shutter turn-on signal GSO is applied in a logic high H state, the first selection circuit unit SEL1 may output a first compensation voltage value Vref1. When the global shutter turn-off signal GSF is applied in a logic low L state, the second selection circuit unit SEL2 may output a reference voltage value Vref0 or a first compensation voltage value Vref1, and when the global shutter turn-off signal GSF is applied in a logic high H state, the first selection circuit unit SEL1 may output a second compensation voltage value Vref2.

[0074] exist Fig.16 In the first time period P1, the first time period P1 may be defined as a time period in which the output current is not generated (or a load transient non-occurrence time period). In the first time period P1, the output voltage of the power supply may be set to an initial value.

[0075] exist Fig.16 In the second period P2, the second period P2 may be defined as a turn-on period when the output current starts to be generated (or an output current rising period starting based on the occurrence of a load transient). In the second period P2, the output voltage of the power supply may be set higher than the initial value.

[0076] exist Fig.16 In the third period P3, the third period P3 may be defined as a holding period of the output current (or a load transient occurrence / holding period). In the third period P3, the output voltage of the power supply may be set to an initial value.

[0077] exist Fig.16In the fourth period P4, the fourth period P4 may be defined as a shutdown period in which the generation of the output current ends (or an output current drop period in which the generation of the load transient ends). In the fourth period P4, the output voltage of the power supply may be set lower than the initial value.

[0078] Furthermore, the time ratios of the first period P1 , the second period P2 , the third period P3 , and the fourth period P4 may be adjusted based on driving conditions (status).

[0079] like Figures 13 to 16 As shown, the power supply 180 according to the second embodiment can output a first compensation voltage value Vref1 and a second compensation voltage value Vref2 for canceling the output voltage ripple when generating an output current, as in "output voltage-control value". Therefore, the power supply 180 according to the second embodiment can generate an output voltage that is improved so that the output voltage ripple is almost invisible, as in "output voltage-actual value".

[0080] like Fig.17 As shown, according to the second embodiment, the reference voltage setting circuit unit OVC1, the first compensation voltage setting circuit unit OVC2 and the second compensation voltage setting circuit unit OVC3 may include a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2 and a third digital-to-analog converter DAC3, respectively. In addition, the first selection circuit unit SEL1 and the second selection circuit unit SEL2 may include a first multiplexer MUX1 and a second multiplexer MUX2, respectively, each multiplexer having a 2:1 form. However, Fig.17 This may be just one implementation mode, but the present disclosure is not limited thereto.

[0081] Fig.18 is a block diagram schematically showing some elements of a light emitting display device according to a third embodiment, Fig.19 is a block diagram showing in more detail the configuration of the power supply according to the third embodiment, Fig. 20 is an output waveform diagram for describing the output control concept of the power supply according to the third embodiment, Fig.21 and Fig. 22 is a diagram for describing the operation of a partial period when the operation of the power supply according to the third embodiment is performed, and Fig.23 and Fig.24 is a diagram for describing a ratio setting circuit unit.

[0082] like Fig.18 As shown, the light emitting display device according to the third embodiment may include a display panel 150 , a power supply 180 , and a timing controller 120 .

[0083] The timing controller 120 may output a global shutter signal GSS, global shutter on / off time setting data GST, voltage setting data OVD, current setting data OCD, and voltage ratio setting data VRD to control the power supply 180. The timing controller 120 may transmit the global shutter signal GSS, the global shutter on / off time setting data GST, the voltage setting data OVD, the current setting data OCD, and the voltage ratio setting data VRD based on a communication interface connected to the power supply 180. For example, the communication interface connected between the timing controller 120 and the power supply 180 may be I2C, SPI, or S-Wire, but is not limited thereto.

[0084] According to a third embodiment, the output controller 185 included in the power supply 180 can change the generation conditions of the first control signal and the second control signal based on the sensing value VSEN and the global shutter signal GSS, the global shutter on / off time setting data GST, the voltage setting data OVD, the current setting data OCD and the voltage ratio setting data VRD supplied from the timing controller 120.

[0085] like Fig.19 As shown, the power supply 180 according to the third embodiment may include an output circuit unit 183 that generates a high-level voltage based on the input power VIN, and an output controller 185 that controls the operation of the output circuit unit 183, as described in the first and second embodiments. The power supply 180 according to the third embodiment may differ from the second embodiment in the configuration of the output controller 185, and therefore, the difference will be described in more detail.

[0086] The output controller 185 may include a reference voltage setting circuit unit OVC1, a first compensation voltage setting circuit unit OVC2, a second compensation voltage setting circuit unit OVC3, a ratio setting circuit unit VRC, a first selection circuit unit SEL1, a second selection circuit unit SEL2, an edge detection circuit unit EDC, a voltage sensing circuit unit ERA, R1 and R2, and a control signal generator PWMC.

[0087] The reference voltage setting circuit unit OVC1 may output a reference voltage value Vref0 based on the voltage setting data OVD. A level of the reference voltage value Vref0 may vary based on the voltage setting data OVD.

[0088] The first compensation voltage setting circuit unit OVC2 may output a first compensation voltage value Vref1 based on the first data output from the ratio setting circuit unit VRC. A level of the first compensation voltage value Vref1 may vary based on the first data output from the ratio setting circuit unit VRC.

[0089] The second compensation voltage setting circuit unit OVC3 may output a second compensation voltage value Vref2 based on the second data output from the ratio setting circuit unit VRC. A level of the second compensation voltage value Vref2 may vary based on the second data output from the ratio setting circuit unit VRC.

[0090] The ratio setting circuit unit VRC can output first data and second data to be supplied to the first compensation voltage setting circuit unit OVC2 and the second compensation voltage setting circuit unit OVC3 based on the current setting data OCD and the voltage ratio setting data VRD. The first data may be different from the second data. A description associated with the ratio setting circuit unit VRC will be given below.

[0091] The edge detection circuit unit EDC may generate a global shutter-on signal GSO and a global shutter-off signal GSF based on the global shutter signal GSS and the global shutter on / off time setting data GST. A description associated with the edge detection circuit unit EDC will be given below.

[0092] The first selection circuit unit SEL1 may output a reference voltage value Vref0 or may output a first compensation voltage value Vref1 in response to a global shutter on signal GSO output from the edge detection circuit unit EDC. The first selection circuit unit SEL1 may supply one of the reference voltage value Vref0 and the first compensation voltage value Vref1 to the second selection circuit unit SEL2.

[0093] The second selection circuit unit SEL2 may output one of the reference voltage value Vref0 and the first compensation voltage value Vref1 supplied from the first selection circuit unit SEL1 in response to the global shutter off signal GSF output from the edge detection circuit unit EDC, or may output the second compensation voltage value Vref2. The second selection circuit unit SEL2 may supply one of the reference voltage value Vref0, the first compensation voltage value Vref1, and the second compensation voltage value Vref2 to the voltage sensing circuit units ERA, R1, and R2.

[0094] The voltage sensing circuit units ERA, R1, and R2 can sense the high level voltage output from the output terminal of the output circuit unit 183 to obtain the sensing value VSEN. The voltage sensing circuit units ERA, R1, and R2 can output a signal for controlling the control signal generator PWMC based on the sensing value VSEN and the voltage value Vref output from the second selection circuit unit SEL2.

[0095] The voltage sensing circuit unit ERA, R1 and R2 may include an error amplifier ERA, a first resistor R1 and a second resistor R2. The first resistor R1 may be connected to the output terminal of the output circuit unit 183 at one end thereof, and the other end thereof may be connected to the inverting terminal (-) of the error amplifier ERA and one end of the second resistor R2. The second resistor R2 may be connected to the inverting terminal (-) of the error amplifier ERA and the other end of the first resistor R1 at one end thereof, and the other end thereof may be connected to the ground terminal. The inverting terminal (-) of the error amplifier ERA may be connected to a node connected to the first resistor R1 and the second resistor R2, and its non-inverting terminal (+) may be connected to the output terminal of the second selection circuit unit SEL2.

[0096] The control signal generator PWMC may generate a first control signal and a second control signal for controlling the first transistor M1 and the second transistor M2 included in the output circuit unit 183 based on the signal output from the error amplifier ERA. The control signal generator PWMC may change the generation conditions of the first control signal and the second control signal based on the signal output from the error amplifier ERA. The first control signal and the second control signal generated by the control signal generator PWMC may be output through the first control line MC1 and the second control line MC2.

[0097] like Fig.19 and Fig. 20 As shown, in the power supply 180 according to the third embodiment, the voltage value Vref applied to the non-inverting terminal (+) of the error amplifier ERA can be changed based on the time period when the output current is not generated, the on time period when the output current starts to be generated, and the off time period when the generation of the output current ends. This will be described below.

[0098] The edge detection circuit unit EDC can extract the logic low L time and the logic high H time in the global shutter signal GSS based on the time information included in the global shutter on / off time setting data GST. In addition, based on this, the edge detection circuit unit EDC can generate the global shutter on signal GSO and the global shutter off signal GSF, and can generate the logic low L time and the logic high H time of the global shutter on signal GSO and the logic low L time and the logic high H time of the global shutter off signal GSF. In addition, based on this, the edge detection circuit unit EDC can output the global shutter on signal GSO and the global shutter off signal GSF.

[0099] When the global shutter on signal GSO and the global shutter off signal GSF are in a logic low L state, the reference voltage value Vref0 may be applied to the non-inverting terminal (+) of the error amplifier ERA. When the global shutter on signal GSO is in a logic high H state and the global shutter off signal GSF is in a logic low L state, the first compensation voltage value Vref1 may be applied to the non-inverting terminal (+) of the error amplifier ERA. When the global shutter on signal GSO is in a logic low L state and the global shutter off signal GSF is in a logic high H state, the second compensation voltage value Vref2 may be applied to the non-inverting terminal (+) of the error amplifier ERA.

[0100] like Fig.21 and Fig. 22 As shown, the reference voltage setting circuit unit OVC1, the first compensation voltage setting circuit unit OVC2, and the second compensation voltage setting circuit unit OVC3 may include a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, and a third digital-to-analog converter DAC3, respectively. In addition, the first selection circuit unit SEL1 and the second selection circuit unit SEL2 may include a first multiplexer MUX1 and a second multiplexer MUX2, respectively, each multiplexer having a 2:1 form. In addition, the ratio setting circuit unit VRC may include a multiplier MULT. However, Fig.21 This may be just one implementation mode, but the present disclosure is not limited thereto.

[0101] When the global shutter-on signal GSO is applied in a logic low L state, the first selection circuit unit SEL1 may output a reference voltage value Vref0, and when the global shutter-on signal GSO is applied in a logic high H state, the first selection circuit unit SEL1 may output a first compensation voltage value Vref1. When the global shutter-off signal GSF is applied in a logic low L state, the second selection circuit unit SEL2 may output a reference voltage value Vref0 or a first compensation voltage value Vref1, and when the global shutter-off signal GSF is applied in a logic high H state, the first selection circuit unit SEL1 may output a second compensation voltage value Vref2.

[0102] exist Fig. 22 In the embodiment, the first time period P1 may be defined as a time period during which no output current is generated. Fig. 22 In the embodiment, the second time period P2 may be defined as a turn-on time period during which the output current starts to be generated. Fig. 22 In the embodiment, the third time period P3 can be defined as a holding time period of the third time period P3. Fig. 22 In the embodiment, the fourth period P4 may be defined as an off period during which the generation of the output current ends.

[0103] like Figures 18 to 22As shown, the power supply 180 according to the third embodiment can output the first compensation voltage value Vref1 and the second compensation voltage value Vref2 for canceling the output voltage ripple when generating the output current, as shown in "output voltage-control value". Therefore, the power supply 180 according to the third embodiment can generate an output voltage that is improved so that the output voltage ripple is almost invisible, as shown in "output voltage-actual value".

[0104] like Fig.21 As shown, the ratio setting circuit unit VRC can provide first data and second data supplied to the first compensation voltage setting circuit unit OVC2 and the second compensation voltage setting circuit unit OVC3 respectively based on the current setting data OCD and the voltage ratio setting data VRD. The first data and the second data can be associated with a compensation value for compensating for the output voltage ripple.

[0105] The ratio setting circuit unit VRC may include: a first ratio setting circuit block which provides first data (OVC2 input data) to be input to the first compensation voltage setting circuit unit OVC2, such as Fig.23 and a second ratio setting circuit block, which provides a second data (OVC3 input data) to be input to the second compensation voltage setting circuit unit OVC3, such as Fig.24 shown.

[0106] Reference Fig.23 The first ratio setting circuit block and Fig.24 The first ratio setting circuit block and the second ratio setting circuit block may include voltage ratio setting data VRD provided in a different manner. Therefore, even when the current setting data OCD and the voltage ratio setting data VRD are input as the same value, the first ratio setting circuit block and the second ratio setting circuit block may provide data having different values, such as the difference between the 0 value and the N value.

[0107] In addition, Fig.23 and Fig.24 In the example of providing the voltage ratio setting data VRD as a straight line graph type, it can be described, but it can also be provided as a curve graph type. In addition, the interval between the voltage ratio setting data VRD may be constant or may not be constant. Therefore, Fig.23 The first ratio setting circuit block and Fig.24 The second ratio setting circuit block may be described only to aid understanding, and should be understood to be set (adjusted) based on the output of the power supply and the load transient condition of the display panel.

[0108] In the above, the present disclosure can remove or reduce (improve) the output voltage ripple caused by the occurrence of load transient conditions when driving the display panel. In addition, in the present disclosure, when expressing a moving image, after the output of the current is disconnected during the grayscale conversion period, the output of the current can occur immediately during the image expression period, thereby preventing (minimizing) the possibility of motion afterimages. In addition, the present disclosure can remove or improve the output voltage ripple caused by the occurrence of load transient conditions when driving the display panel based on the global shutter drive mode, and thus the display quality of the moving image can be enhanced.

[0109] The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.

[0110] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display device, comprising: a display panel configured to display an image; a timing controller configured to control the display panel; as well as a power supply including: an output circuit configured to generate output power for supplying power to the display panel based on input power; and an output controller configured to sense a voltage output through an output terminal of the output circuit to obtain a sensed value, In which, the output controller provides a reference voltage value and a compensation voltage value having a level different from the reference voltage value based on an external signal, selectively outputs at least one of the reference voltage value and the compensation voltage value based on the external signal to provide a voltage value, and generates a control signal for controlling the output circuit based on the sensing value and the voltage value.

2. The display device according to claim 1, wherein: The output controller cancels an output voltage ripple that appears in an output terminal of the output circuit when an output current is generated from the output circuit based on the compensation voltage value.

3. The display device according to claim 1, wherein: The output controller comprises: a reference voltage setting circuit configured to output the reference voltage value based on voltage setting data included in the external signal; and A first compensation voltage setting circuit and a second compensation voltage setting circuit are configured to output a first compensation voltage value and a second compensation voltage value, respectively, based on current setting data included in the external signal.

4. The display device according to claim 3, wherein: The reference voltage value, the first compensation voltage value, and the second compensation voltage value have the following relationship: the second compensation voltage value<the reference voltage value<the first compensation voltage value.

5. The display device according to claim 4, wherein: the reference voltage setting circuit outputting the reference voltage value, the level of which increases as the voltage setting data value included in the voltage setting data increases, the first compensation voltage setting circuit outputs the first compensation voltage value, the level of the first compensation voltage value increasing as the current setting data value included in the current setting data increases, and The second compensation voltage setting circuit outputs the second compensation voltage value whose level decreases as a current setting data value included in the current setting data increases.

6. The display device according to claim 5, wherein: The output controller includes a selection circuit configured to selectively output one of the reference voltage value, the first compensation voltage value, and the second compensation voltage value based on a logic state of each of a global shutter-on signal and a global shutter-off signal.

7. The display device according to claim 6, wherein: The global shutter-on signal and the global shutter-off signal are included in the external signal.

8. The display device according to claim 6, wherein: The output controller further includes an edge detection circuit configured to generate the global shutter-on signal and the global shutter-off signal based on a global shutter signal and global shutter-on / off time setting data included in the external signal.

9. The display device according to claim 4, wherein: The first compensation voltage value and the second compensation voltage value have an inverse relationship.

10. The display device according to claim 6, wherein: The selection circuit outputs the reference voltage value during a first time period in which a load transient caused by the driving of the display panel does not occur, outputs the first compensation voltage value during a second time period in which the load transient caused by the driving of the display panel starts, outputs the reference voltage value during a third time period in which the driving of the display panel is maintained, and outputs the second compensation voltage value during a fourth time period in which the load transient caused by the driving of the display panel ends.

11. The display device according to claim 3, wherein: The output controller also includes a ratio setting circuit, which is configured to provide first data and second data supplied to the first compensation voltage setting circuit and the second compensation voltage setting circuit respectively based on current setting data and voltage ratio setting data included in the external signal, wherein the first compensation voltage setting circuit and the second compensation voltage setting circuit output the first compensation voltage value and the second compensation voltage value based on the first data and the second data respectively.

12. A power supply comprising: an output circuit configured to generate output power based on input power; as well as an output controller configured to sense a voltage output through an output terminal of the output circuit to obtain a sensed value, Wherein, the output controller provides a reference voltage value and a compensation voltage value having a level different from the reference voltage value based on an external signal, selectively outputs at least one of the reference voltage value and the compensation voltage value based on the external signal to provide a voltage value, and generates a control signal for controlling the output circuit based on the sensing value and the voltage value.

13. The power supply of claim 12, wherein: The output controller comprises: a reference voltage setting circuit configured to output the reference voltage value based on voltage setting data included in the external signal; and a first compensation voltage setting circuit and a second compensation voltage setting circuit, the first compensation voltage setting circuit and the second compensation voltage setting circuit being configured to output a first compensation voltage value and a second compensation voltage value, respectively, based on current setting data included in the external signal, and The reference voltage value, the first compensation voltage value, and the second compensation voltage value have the following relationship: the second compensation voltage value<the reference voltage value<the first compensation voltage value.

14. The power supply of claim 13, wherein: the reference voltage setting circuit outputting the reference voltage value, the level of which increases as the voltage setting data value included in the voltage setting data increases, the first compensation voltage setting circuit outputs the first compensation voltage value, the level of the first compensation voltage value increasing as the current setting data value included in the current setting data increases, and The second compensation voltage setting circuit outputs the second compensation voltage value whose level decreases as a current setting data value included in the current setting data increases.

15. The power supply of claim 14, wherein: The output controller includes a selection circuit configured to selectively output one of the reference voltage value, the first compensation voltage value, and the second compensation voltage value based on a logic state of each of an on signal and an off signal.

16. The power supply of claim 15, wherein: The on signal and the off signal are included in the external signal.

17. The power supply of claim 15, wherein: The output controller further includes an edge detection circuit configured to generate the on signal and the off signal based on a global shutter signal and global shutter on / off time setting data included in the external signal.

18. The power supply of claim 15, wherein: The selection circuit outputs the reference voltage value during a first time period in which an output current is not generated from the output circuit, outputs the first compensation voltage value during a second time period in which the output current starts to be generated, outputs the reference voltage value during a third time period in which the output current is maintained, and outputs the second compensation voltage value during a fourth time period in which the generation of the output current ends.

19. The power supply of claim 13, wherein: The output controller also includes a ratio setting circuit, which is configured to provide first data and second data supplied to the first compensation voltage setting circuit and the second compensation voltage setting circuit respectively based on current setting data and voltage ratio setting data included in the external signal, wherein the first compensation voltage setting circuit and the second compensation voltage setting circuit output the first compensation voltage value and the second compensation voltage value based on the first data and the second data respectively.

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