Display device

Abstract

A display device includes a display panel driven in units of frames, and the display panel includes pixels including a pixel driving circuit and a light emitting element. The pixel driving circuit may include a first driving sub-transistor, a second driving sub-transistor, and a brightness transistor. The first driving sub-transistor includes a first electrode connected to a first node and a gate electrode connected to a second node. The second driving sub-transistor includes a gate electrode connected to the second node. The luminance transistor includes a first electrode connected to a first node, a second electrode connected to a third node, and a gate electrode receiving a luminance signal. The frames may include a first frame and a second frame, and the luminance signal may be activated in the first frame to have a first pulse width and may be activated in the second frame to have a second pulse width.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Korean Patent Application No. 10-2023-0155150 filed on November 10, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments described herein relate to a display device. Background Art

[0004] The display device may include various electronic components such as a display panel for displaying an image, an input sensor for sensing an external input, and an electronic module. These electronic components may be electrically connected to each other via signal lines arranged in various ways. The display panel includes a plurality of pixels. Each of the plurality of pixels includes a light emitting element for generating light and a pixel driving circuit for controlling the amount of current flowing to the light emitting element. Summary of the invention

[0005] The present disclosure provides a display device with improved display quality.

[0006] An embodiment of the present invention provides a display device, the display device includes a display panel, the display panel is driven in units of frames, and the display panel includes pixels, the pixels include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit, wherein the pixel driving circuit may include: a first capacitor connected between a second node and a first voltage line provided with a first driving voltage; a (1-1)th transistor including a first electrode electrically connected to the first voltage line and connected to the first node, a second electrode electrically connected to a third node, and a gate electrode electrically connected to the second node; a (1-2)th transistor including a first electrode electrically connected to the third node, a second electrode electrically connected to the light-emitting element, and a gate electrode electrically connected to the second node; and a brightness transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the third node, and a gate electrode configured to receive a brightness signal. The frame may include a first frame and a second frame connected in series. The brightness signal may be activated to have a first pulse width in the first frame, and may be activated to have a second pulse width different from the first pulse width in the second frame.

[0007] In an embodiment, the display panel may have a first brightness value in a first frame and a second brightness value greater than the first brightness value in a second frame, and the second pulse width may be greater than the first pulse width.

[0008] In an embodiment, the frame may further include a third frame continuous with the second frame and a fourth frame continuous with the third frame, and the brightness signal may be activated to have a third pulse width in the third frame and may be activated to have a fourth pulse width different from the third pulse width in the fourth frame.

[0009] In an embodiment, the display panel may have a third brightness value greater than the second brightness value in a third frame and a fourth brightness value greater than the third brightness value in a fourth frame.

[0010] In an embodiment, the first to fourth pulse widths may increase gradually or progressively in this order.

[0011] In an embodiment, the frame may also include a fifth frame, a sixth frame, a seventh frame, and an eighth frame that are driven continuously, the brightness signal may be activated to have a fifth pulse width in the fifth frame, may be activated to have a sixth pulse width in the sixth frame, may be activated to have a seventh pulse width in the seventh frame, and may be activated to have an eighth pulse width in the eighth frame, and the fifth to eighth pulse widths may be different from each other.

[0012] In an embodiment, the display panel may have a fifth brightness value in a fifth frame, a sixth brightness value in a sixth frame, a seventh brightness value in a seventh frame, and an eighth brightness value in an eighth frame, and the fifth to eighth brightness values ​​may gradually or progressively decrease in this order.

[0013] In an embodiment, the fifth to eighth pulse widths may be gradually or progressively decreased in this order.

[0014] In an embodiment, the pixel driving circuit may further include a second transistor including a first electrode electrically connected to a data line provided with a data signal, a second electrode electrically connected to the first node, and a gate electrode configured to receive a first scan signal.

[0015] In an embodiment, the pixel driving circuit may further include a third transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to the second electrode of the (1-2)th transistor, and a gate electrode configured to receive a first scan signal.

[0016] In an embodiment, the pixel driving circuit may further include a fourth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a first initialization voltage line provided with a first initialization voltage, and a gate electrode configured to receive a second scan signal.

[0017] In an embodiment of the present invention, a display device includes a display panel, the display panel is driven in units of frames, and the display panel includes pixels, the pixels include a pixel driving circuit and a light emitting element electrically connected to the pixel driving circuit, wherein the pixel driving circuit may include: a (1-1)th transistor electrically connected to a first voltage line provided with a first driving voltage, the (1-1)th transistor electrically connected between a first node and a second node and including a gate electrode; a (1-2)th transistor electrically connected between the second node and the light emitting element and including a gate electrode electrically connected to the gate electrode of the (1-1)th transistor; and a brightness transistor electrically connected between the first node and the second node and receiving a brightness signal. The display panel may be driven in a first mode, a second mode, and a third mode, in which the (1-1)th transistor and the (1-2)th transistor may be activated, and the display panel may have a first brightness value, in which the (1-2)th transistor and the brightness transistor may be activated, and the display panel may gradually or progressively change in brightness value from the first brightness value to a second brightness value different from the first brightness value. In the third mode, the (1-1)th transistor and the brightness transistor may be activated, and the display panel may have a second brightness value.

[0018] In an embodiment, the second brightness value may be greater than the first brightness value.

[0019] In an embodiment, the brightness signal may be disabled in the first mode, and the brightness signal may be activated in the second mode and the third mode.

[0020] In an embodiment, the second mode may be disposed between the first mode and the third mode.

[0021] In an embodiment, the display panel may be driven in the second mode for the plurality of second frames, and a pulse width of a brightness signal activated in each of the plurality of second frames may be gradually or progressively increased.

[0022] In an embodiment, the display panel may be driven in the third mode for the third frame, and a pulse width of a brightness signal activated in the third frame may be greater than a pulse width of a brightness signal activated in each of the plurality of second frames.

[0023] In an embodiment, the pixel driving circuit may further include a second transistor electrically connected between the data line supplied with the data signal and the first node and receiving the first scan signal.

[0024] In an embodiment, the pixel driving circuit may further include a third transistor electrically connected between the gate electrode of the (1-2)th transistor and one end of the (1-2)th transistor and receiving the first scan signal.

[0025] In an embodiment, the pixel driving circuit may further include a fourth transistor electrically connected between the gate electrode of the (1-2)th transistor and the first initialization voltage line supplied with the first initialization voltage and receiving the second scan signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0027] Figure 1 is a perspective view of a display device according to an embodiment of the inventive concept;

[0028] Figure 2 is a block diagram of a display device according to an embodiment of the inventive concept;

[0029] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept;

[0030] Figure 4 and Figure 5 is a diagram illustrating a brightness driver of a display device according to an embodiment of the inventive concept;

[0031] Figure 6 is a timing diagram illustrating the operation of a pixel according to an embodiment of the inventive concept; and

[0032] Figure 7 is a timing diagram illustrating the operation of a pixel according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0033] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, the element can be directly set on, connected to or coupled to the other element, or an intervening element may be set between the element and the other element.

[0034] The same reference numerals or symbols always refer to the same elements. In addition, in the drawings, the thickness, proportion and size of the elements are exaggerated for the effective description of the technical content. The term "and / or" includes all one or more combinations that the related elements can define.

[0035] Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can also be referred to as the first element. Unless the context clearly indicates otherwise, the singular form also includes the plural form.

[0036] In addition, terms such as "below", "lower", "above", and "upper" are used to describe the relationship of elements shown in the drawings. These terms have relative concepts and are described based on the directions indicated in the drawings.

[0037] It will be understood that when used herein, terms such as “include” or “have” are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. In addition, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an overly idealized or overly formalized meaning.

[0039] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0040] Figure 1 is a perspective view of a display device 1000 according to an embodiment of the inventive concept.

[0041] Reference Figure 1 , the display device 1000 can be activated in response to the electrical signal. The display device 1000 can be implemented in various forms. For example, the display device 1000 can be used in a large display device (e.g., a television, a monitor, or an outdoor billboard) or a small or medium-sized display device such as a personal computer (e.g., a laptop computer), a personal digital assistant, a car navigation unit, a game console, a portable electronic device, or a camera. These are presented as examples only. In other embodiments, without departing from the scope of the present inventive concept, the display device 1000 can be adopted in other electronic devices. In the present embodiment, a smart phone is shown as an example of the display device 1000.

[0042] The display device 1000 may include a display surface 1000-F parallel to a plane extending in a first direction DR1 and a second direction DR2 crossing the first direction DR1. The display surface 1000-F may include a transmissive region 1000-T and a bezel region 1000-B.

[0043] The image 1000-I may be displayed toward the third direction DR3 in the transmissive region 1000-T. The third direction DR3 may be referred to as a thickness direction. The image 1000-I may include a static image and a dynamic (or moving) image. Figure 1 A clock image and an icon are shown as examples of the image 1000 -I. A display surface 1000 -F displaying the image 1000 -I may correspond to a front surface of the display device 1000 .

[0044] In the present embodiment, for example, the front surface (or upper surface) and the rear surface (or lower surface) of the display device 1000 may be determined based on the direction in which the image 1000-I is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. As used herein, the expression "when viewed on a plane" may mean viewed in the third direction DR3. The image 1000-I may not be displayed in the frame area 1000-B.

[0045] The display device 1000 according to an embodiment of the present invention can sense input from a user. For example, the display device 1000 can sense input made from a part of the user's body 2000 (e.g., a finger). The user input may include external input in various forms such as a part of the user's body or from a stylus, light, heat, or pressure. In addition, the display device 1000 can sense input applied to the side surface or rear surface of the display device 1000 depending on the structure of the display device 1000, and is not limited to any one embodiment.

[0046] Figure 2 is a block diagram of a display device 1000 according to an embodiment of the inventive concept.

[0047] Reference Figure 2 , also refer to Figure 1 , the display device 1000 includes a display panel DP, a driving controller 100 , a data driving circuit 200 , and a voltage generator 300 .

[0048] The driving controller 100 receives the image information RGB and the control signal CTRL. The driving controller 100 generates the image data DATA by converting the data format of the image information RGB to comply with the specification of the interface with the data driving circuit 200. The driving controller 100 outputs the scanning control signal SCS, the data control signal DCS and the emission control signal ECS.

[0049] The data driving circuit 200 receives the data control signal DCS and the image data DATA from the driving controller 100. The data driving circuit 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1, DL2, ... and DLm described later. The data signal is an analog voltage corresponding to the grayscale value of the image data DATA.

[0050] The voltage generator 300 generates voltages for operation of the display panel DP In the present embodiment, the voltage generator 300 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0051] The display panel DP includes scan lines GIL1 to GILn and GWL1 to GWLn, emission control lines EML1 to EMLn, brightness control lines CBL1 to CBLn, data lines DL1 to DLm, and a plurality of pixels PX. The scan lines GIL1 to GILn and GWL1 to GWLn may include first scan lines GIL1 to GILn and second scan lines GWL1 to GWLn. The display panel DP may further include a scan drive circuit SD and an emission drive circuit EDC. In an embodiment, the scan drive circuit SD is arranged on a first side of the display panel DP. The scan lines GIL1 to GILn and GWL1 to GWLn and the brightness control lines CBL1 to CBLn extend from the scan drive circuit SD in a first direction DR1.

[0052] The display panel DP includes a display area DA corresponding to the transmissive area 1000-T and a frame area 1000-B (eg, see Figure 1 ) corresponds to a non-display area NDA. A plurality of pixels PX may be disposed in the display area DA, and a scan driving circuit SD and an emission driving circuit EDC may be disposed in the non-display area NDA.

[0053] The emission driving circuit EDC is disposed on the second side of the display panel DP. The second side of the display panel DP may be an opposite side with respect to the first side of the display panel DP. The emission control lines EML1 to EMLn may extend from the emission driving circuit EDC in a direction opposite to the first direction DR1.

[0054] The first scan lines GIL1 to GILn, the second scan lines GWL1 to GWLn, the emission control lines EML1 to EMLn, and the brightness control lines CBL1 to CBLn are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data driving circuit 200 in a direction opposite to the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1.

[0055] exist Figure 2 In the example shown in , the scan drive circuit SD and the emission drive circuit EDC are arranged to face each other, and a plurality of pixels PX are interposed between the scan drive circuit SD and the emission drive circuit EDC, but the embodiments of the present inventive concept are not limited thereto. For example, the scan drive circuit SD and the emission drive circuit EDC may be arranged to be adjacent to each other on the first side or the second side of the display panel DP. In an embodiment, the scan drive circuit SD and the emission drive circuit EDC may be configured as a single circuit.

[0056] The plurality of pixels PX are electrically connected to the first scan lines GIL1 to GILn, the second scan lines GWL1 to GWLn, the emission control lines EML1 to EMLn, the brightness control lines CBL1 to CBLn, and the data lines DL1 to DLm. In one embodiment, each of the plurality of pixels PX may be electrically connected to two scan lines, one brightness control line, and one emission control line. For example, Figure 2 As shown in , the pixels PX in the first row can be connected to the first scan line GIL1, the second scan line GWL1, the brightness control line CBL1, and the emission control line EML1. In addition, the pixels PX in the j-th row can be connected to the first scan line GILj, the second scan line GWLj, the brightness control line CBLj, and the emission control line EMLj. The second scan line GWLj can be connected to a plurality of transistors included in a single pixel PX. For example, Figure 3 As shown in FIG. 1 , it is taken as an example that the second scan line GWLj can be connected to the respective gate electrodes of the second transistor T2 , the third transistor T3 and the seventh transistor T7 .

[0057] Each of the plurality of pixels PX includes a light emitting diode ED and a pixel circuit portion PXC for controlling emission of light from the light emitting diode ED (see Figure 3 ). The pixel circuit portion PXC may include one or more transistors and one or more capacitors. For example, the scan drive circuit SD and the emission drive circuit EDC may include transistors, and the transistors and the transistors used to form the pixel circuit portion PXC may be formed by the same process. In other embodiments, the transistors in the scan drive circuit SD and the emission drive circuit EDC and the transistors in the pixel circuit portion PXC may be formed using different processes.

[0058] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1 , and a second initialization voltage VINT2 from the voltage generator 300 .

[0059] The scan driving circuit SD receives a scan control signal SCS from the driving controller 100. The scan driving circuit SD may output scan signals to the first scan lines GIL1 to GILn, the second scan lines GWL1 to GWLn, and the brightness control lines CBL1 to CBLn in response to the scan control signal SCS. The configuration and operation of the circuits related to the brightness control lines CBL1 to CBLn will be described in detail later.

[0060] Figure 3 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the inventive concept. The pixel PXij may represent a display panel DP (see Figure 2 ) structure of each pixel in .

[0061] Figure 3 exemplarily shown connected to Figure 2 The equivalent circuit diagram of the pixel PXij shows the i-th data line DLi among the data lines DL1 to DLm (also referred to as the data line DLi in this article), the j-th first scan line GILj among the first scan lines GIL1 to GILn (also referred to as the first scan line GILj in this article), the j-th second scan line GWLj among the second scan lines GWL1 to GWLn (also referred to as the second scan line GWLj in this article), the j-th brightness control line CBLj among the brightness control lines CBL1 to CBLn (also referred to as the brightness control line CBLj in this article), and the j-th emission control line EMLj among the emission control lines EML1 to EMLn (also referred to as the emission control line EMLj in this article).

[0062] Figure 2 Each of the plurality of pixels PX shown in FIG. Figure 3 The equivalent circuit diagram of the pixel PXij shown in has the same circuit configuration. In this example, the pixel circuit portion PXC of the pixel PXij may include a (1-1)th transistor T1-1, a (1-2)th transistor T1-2, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8 and one or more capacitors, but may include a different number of transistors and / or capacitors in another embodiment.

[0063] Each of the (1-1)th transistor T1-1 to the eighth transistor T8 may be an N-type transistor including an oxide semiconductor as a semiconductor layer. However, the embodiments of the present invention are not limited thereto, and the (1-1)th transistor T1-1 to the eighth transistor T8 may be P-type transistors. In another embodiment, among the (1-1)th transistor T1-1 to the eighth transistor T8, at least one may be an N-type transistor, and the others may be P-type transistors. In addition, the circuit configuration of the pixel according to the present invention is not limited to Figure 3 . Figure 3 The pixel circuit portion PXC shown in FIG. 1 is merely an example, and the configuration of the pixel circuit portion PXC may be implemented by modification.

[0064] Reference Figure 3 , also refer to Figure 2 According to the embodiment, the pixel PXij of the display device 1000 includes the (1-1)th transistor T1-1 to the eighth transistor T8, the first capacitor C1, the second capacitor C2, and at least one light emitting diode ED. In this embodiment, an example in which one pixel PXij includes one light emitting diode ED is described.

[0065] The first scan line GILj may transmit a first scan signal GIj, the second scan line GWLj may transmit a second scan signal GWj, and the brightness control line CBLj may transmit a brightness signal CBj. The emission control line EMLj may transmit an emission signal EMj, and the data line DLi may transmit a data signal Di. The data signal Di may have a signal similar to that input to the display device 1000 (for example, see Figure 2 ) of the image information RGB. The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3 and the fourth driving voltage line VL4 may transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1 and the second initialization voltage VINT2, respectively (herein, the first driving voltage line VL1 is also referred to as the first voltage line VL1, the second driving voltage line VL2 is also referred to as the second voltage line VL2, the third driving voltage line VL3 is also referred to as the third voltage line VL3, and the fourth driving voltage line VL4 is also referred to as the fourth voltage line VL4).

[0066] The (1-1)th transistor T1-1 may be electrically connected between the first voltage line VL1 and the light emitting diode ED. The (1-1)th transistor T1-1 includes a first electrode electrically connected to the first voltage line VL1 via the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting diode ED via the (1-2)th transistor T1-2 and the sixth transistor T6, and a gate electrode connected to one end of the first capacitor C1. The first electrode may be connected to the first node ND1, the gate electrode may be connected to the second node ND2, and the second electrode may be connected to the third node ND3. Therefore, the (1-1)th transistor T1-1 may be electrically connected between the first node ND1 and the third node ND3. In addition, the first electrode of the (1-1)th transistor T1-1 may be electrically connected to the first electrode of the eighth transistor T8, and the second electrode of the (1-1)th transistor T1-1 may be electrically connected to the second electrode of the eighth transistor T8.

[0067] The (1-2)th transistor T1-2 may be electrically connected between the third node ND3 and the light emitting diode ED via the sixth transistor T6. The (1-2)th transistor T1-2 includes a first electrode connected to the first voltage line VL1 via the fifth transistor T5 and the (1-1)th transistor T1-1, a second electrode electrically connected to the anode of the light emitting diode ED via the sixth transistor T6, and a gate electrode connected to one end of the first capacitor C1, for example, at the second node ND2. The (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may be operably referred to as drive transistors, wherein the (1-1)th transistor T1-1 may be referred to as a first drive sub-transistor, and the (1-2)th transistor T1-2 may be referred to as a second drive sub-transistor. In addition, the (1-1)th transistor T1-1 may be referred to as a first drive transistor, and the (1-2)th transistor T1-2 may be referred to as a second drive transistor. As will be described in more detail below, the (1-1)th transistor T1-1 may be electrically disconnected in certain modes of operation.

[0068] The second transistor T2 may be electrically connected between the data line DLi and the first node ND1. The second transistor T2 operates as a switching transistor and includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the (1-1)th transistor T1-1 at the first node ND1, and a gate electrode connected to the second scan line GWLj. The second transistor T2 may be turned on in response to a second scan signal GWj transmitted through the second scan line GWLj, and may transmit a data signal Di transmitted through the data line DLi to the first electrode of the (1-1)th transistor T1-1.

[0069] The third transistor T3 may be electrically connected between the second node ND2 and the (1-2)th transistor T1-2. The third transistor T3 includes a first electrode connected to the respective gate electrodes of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2, a second electrode connected to the second electrode of the (1-2)th transistor T1-2, and a gate electrode connected to the second scan line GWLj. The third transistor T3 may be turned on in response to a second scan signal GWj transmitted through the second scan line GWLj to connect the gate electrode and the second electrode of each of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2. In this case, the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may each be set in a state of being connected in a diode manner.

[0070] The fourth transistor T4 may be electrically connected between the second node ND2 and the third voltage line VL3. The fourth transistor T4 includes a first electrode connected to respective gate electrodes (e.g., the second node ND2) of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2, a second electrode connected to the third voltage line VL3 transmitting the first initialization voltage VINT1, and a gate electrode connected to the first scan line GILj. The fourth transistor T4 may be turned on in response to a first scan signal GIj transmitted through the first scan line GILj, and may transmit the first initialization voltage VINT1 to respective gate electrodes of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 to perform an initialization operation of initializing the voltage of the gate electrode of each of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2.

[0071] The fifth transistor T5 may be electrically connected between the first voltage line VL1 and the first node ND1. The fifth transistor T5 includes a first electrode connected to the first voltage line VL1, a second electrode connected to the first electrode of the (1-1)th transistor T1-1, and a gate electrode connected to the emission control line EMLj.

[0072] The sixth transistor T6 may be electrically connected between the (1-2)th transistor T1-2 and the light emitting diode ED. The sixth transistor T6 includes a first electrode connected to the second electrode of the (1-2)th transistor T1-2, a second electrode connected to the anode of the light emitting diode ED, and a gate electrode connected to the emission control line EMLj.

[0073] In operation, the fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously in response to the emission signal EMj transmitted through the emission control line EMLj. In this case, a current path may be formed between the first voltage line VL1 and the light emitting diode ED. Therefore, the first driving voltage ELVDD may be compensated and transmitted to the light emitting diode ED through the (1-1)th transistor T1-1 and / or the (1-2)th transistor T1-2 connected in a diode manner.

[0074] The seventh transistor T7 may be electrically connected between the light emitting diode ED and the fourth voltage line VL4. The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth voltage line VL4 transmitting the second initialization voltage VINT2, and a gate electrode connected to the second scan line GWLj. The seventh transistor T7 is turned on in response to the second scan signal GWj transmitted through the second scan line GWLj, so that the current of the anode of the light emitting diode ED is bypassed to the fourth voltage line VL4.

[0075] The eighth transistor T8 may be electrically connected in parallel with the (1-1)th transistor T1-1 between the first node ND1 and the third node ND3. The eighth transistor T8 includes a first electrode electrically connected to the first electrode of the (1-1)th transistor T1-1, a second electrode electrically connected to the second electrode of the (1-1)th transistor T1-1, and a gate electrode connected to a brightness control line CBLj to which a brightness signal CBj is supplied. The eighth transistor T8 may be referred to as a brightness transistor.

[0076] The first capacitor C1 may have one end connected to respective gate electrodes of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 as described above and the second node ND2, and the other end of the first capacitor C1 may be connected to the first voltage line VL1.

[0077] The second capacitor C2 may have one end connected to the cathode of the light emitting diode ED, and the other end of the second capacitor C2 may be connected to the anode of the light emitting diode ED. The second capacitor C2 may be a capacitor formed by the light emitting diode ED.

[0078] The cathode of the light emitting diode ED may be connected to the second voltage line VL2 transmitting the second driving voltage ELVSS. The structure of the pixel PXij according to the embodiment is not limited to Figure 3 The structure shown in FIG. 1 and the number of transistors and capacitors included in one pixel PXij and the connection relationship of the transistors and capacitors can be modified in various ways.

[0079] In an embodiment of the present invention, the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may be turned on in response to a voltage of the second node ND2. A first current path may be formed along the fifth transistor T5, the (1-1)th transistor T1-1, the (1-2)th transistor T1-2, and the sixth transistor T6. The (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may receive a data signal Di transmitted through the data line DLi and supply an emission current Ied to the light emitting diode ED. Here, the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may operate as a single drive transistor. The channel length of the drive transistor may be equal to the sum of the first channel length of the (1-1)th transistor T1-1 and the second channel length of the (1-2)th transistor T1-2. The driving method may be defined as a first mode. A description of the driving method will be made later.

[0080] In an embodiment of the present invention, when the eighth transistor T8 is activated, a second current path may be formed along the fifth transistor T5, the eighth transistor T8, the (1-2)th transistor T1-2 and the sixth transistor T6. The second current path may be different from the first current path. The (1-2)th transistor T1-2 may receive a data signal Di transmitted through the data line DLi and supply an emission current Ied to the light emitting diode ED. Here, because the (1-1)th transistor T1-1 has been electrically short-circuited by the on-state of the eighth transistor T8, only the (1-2)th transistor T1-2 may operate as a driving transistor. The channel length of the driving transistor may be the second channel length of the (1-2)th transistor T1-2. The driving method may be defined as a third mode. A description of the driving method will be made later.

[0081] According to the inventive concept, the channel length of the driving transistor in the third mode may be shorter than the channel length of the driving transistor in the first mode. Therefore, the emission current Ied flowing through the light emitting diode ED in the third mode may be greater than the emission current Ied flowing through the light emitting diode ED in the first mode. The pixel PXij operated in the third mode may have a higher brightness than the pixel PXij operated in the first mode. Therefore, the pixel PXij may be a pixel that is easily driven with high brightness.

[0082] Figure 4 and Figure 5 FIG. 1 is a diagram showing a display device 1000 (see FIG. 1 ) according to an embodiment of the present invention. Figure 2 ) of the brightness driver CBD.

[0083] Reference Figure 2 , Figure 4 and Figure 5The scan driving circuit SD may further include a plurality of brightness drivers CBD that operate sequentially. The plurality of brightness drivers CBD may include a first brightness driver CBD1, a second brightness driver CBD2, and a third brightness driver CBD3. Figure 4 and Figure 5 , but embodiments of the inventive concept are not limited thereto, for example, less than or more than three brightness drivers may be included in the scan driving circuit SD.

[0084] Each of the plurality of brightness drivers CBD may provide a first brightness signal CB1 to the plurality of pixels PX during a first frame. The first brightness signal CB1 may include a (1-1)th brightness signal CB11, a (1-2)th brightness signal CB12, and a (1-3)th brightness signal CB13. Each of the (1-1)th brightness signal CB11, the (1-2)th brightness signal CB12, and the (1-3)th brightness signal CB13 may be activated to have a first pulse width CBW1.

[0085] The first brightness driver CBD1 may provide the (1-1)th brightness signal CB11 to the pixels PX in the first row in response to the scan control signal SCS, and provide the (1-1)th start signal CB1_FLM1 as a carry signal to the second brightness driver CBD2. In one embodiment, the (1-1)th brightness signal CB11 may be the same as the (1-1)th start signal CB1_FLM1.

[0086] The second brightness driver CBD2 may provide the (1-2)th brightness signal CB12 to the pixels PX in the second row in response to the (1-1)th start signal CB1_FLM1, and provide the (1-2)th start signal CB1_FLM2 as a carry signal to the third brightness driver CBD3. In one embodiment, the (1-2)th brightness signal CB12 may be the same as the (1-2)th start signal CB1_FLM2.

[0087] The second brightness driver CBD2 may output a (1-2)th brightness signal CB12 which is activated after the (1-1)th brightness signal CB11 outputted from the first brightness driver CBD1 is activated.

[0088] The third brightness driver CBD3 may provide the (1-3)th brightness signal CB13 to the pixels PX in the third row in response to the (1-2)th start signal CB1_FLM2, and provide the (1-3)th start signal CB1_FLM3 as a carry signal to the next brightness driver. In one embodiment, the (1-3)th brightness signal CB13 may be the same as the (1-3)th start signal CB1_FLM3.

[0089] The third brightness driver CBD3 may output a (1-3)th brightness signal CB13 which is activated after the (1-2)th brightness signal CB12 output from the second brightness driver CBD2 is activated.

[0090] Each of the plurality of brightness drivers CBD may provide a fourth brightness signal CB4 to the plurality of pixels PX during a fourth frame. The fourth brightness signal CB4 may include a (4-1)th brightness signal CB41, a (4-2)th brightness signal CB42, and a (4-3)th brightness signal CB43. Each of the (4-1)th brightness signal CB41, the (4-2)th brightness signal CB42, and the (4-3)th brightness signal CB43 may be activated to have a fourth pulse width CBW4. The fourth pulse width CBW4 may be greater than the first pulse width CBW1.

[0091] The first brightness driver CBD1 may provide the (4-1)th brightness signal CB41 to the pixels PX in the first row in response to the scan control signal SCS, and provide the (4-1)th start signal CB4_FLM1 as a carry signal to the second brightness driver CBD2. In one embodiment, the (4-1)th brightness signal CB41 may be the same as the (4-1)th start signal CB4_FLM1.

[0092] The second brightness driver CBD2 may provide the (4-2)th brightness signal CB42 to the pixels PX in the second row in response to the (4-1)th start signal CB4_FLM1, and provide the (4-2)th start signal CB4_FLM2 as a carry signal to the third brightness driver CBD3. In one embodiment, the (4-2)th brightness signal CB42 may be the same as the (4-2)th start signal CB4_FLM2.

[0093] The second brightness driver CBD2 may output a (4-2)th brightness signal CB42 that is activated after the (4-1)th brightness signal CB41 output from the first brightness driver CBD1 is activated.

[0094] The third brightness driver CBD3 may provide the (4-3)th brightness signal CB43 to the pixels PX in the third row in response to the (4-2)th start signal CB4_FLM2, and provide the (4-3)th start signal CB4_FLM3 as a carry signal to the next brightness driver. In one embodiment, the (4-3)th brightness signal CB43 may be the same as the (4-3)th start signal CB4_FLM3.

[0095] The third brightness driver CBD3 may output a (4-3)th brightness signal CB43 which is activated after the (4-2)th brightness signal CB42 outputted from the second brightness driver CBD2 is activated.

[0096] Figure 6 is a timing diagram illustrating an operation of a pixel PXij according to an embodiment of the inventive concept. Figure 6 The display panel DP (see, for example, Figure 2 ) is a process of sequentially driving in a normal mode, an intermediate mode, and a high brightness mode. For example, Figure 6 An operation when the normal mode is changed to the high brightness mode is shown.

[0097] Reference Figure 2 , Figure 3 and Figure 6 , the display panel DP may be driven in units of frames FR. The frames FR may include a first frame FR1, a second frame FR2, a third frame FR3, a fourth frame FR4, and a fifth frame FR5 which are sequentially ordered.

[0098] The display panel DP may be driven in a first mode MD1, a second mode MD2, and a third mode MD3. The first mode MD1 may be referred to as a normal mode. The second mode MD2 may be referred to as an intermediate mode. The third mode MD3 may be referred to as a high brightness mode. The second mode MD2 may be set between the first mode MD1 and the third mode MD3.

[0099] The display panel DP may be driven in the first mode MD1 for the first frame FR1 , may be driven in the second mode MD2 for the second to fourth frames FR2 to FR4 , and may be driven in the third mode MD3 for the fifth frame FR5 . Figure 6 Three frames in which the display panel DP is driven in the second mode MD2 are shown as an example, but the number of frames in which the display panel DP operates in the second mode (middle mode) MD2 according to an embodiment conceived by the present invention is not limited thereto, and may be a number of frames greater than or less than three frames.

[0100] In operation, an emission signal EMj, a first scan signal GIj, a second scan signal GWj, and a brightness signal CBj may be provided to a pixel PXij. The activation level of each of the emission signal EMj, the first scan signal GIj, the second scan signal GWj, and the brightness signal CBj may be a low level to match the conductivity of a corresponding transistor in the transistor (e.g., a P-type metal oxide semiconductor (PMOS) configuration). However, this is an example, and the activation level of the signal according to an embodiment of the inventive concept is not limited thereto. For example, in an N-type metal oxide semiconductor (NMOS) configuration, it is taken as an example that the activation level of at least one of the emission signal EMj, the first scan signal GIj, the second scan signal GWj, and the brightness signal CBj may be a high level.

[0101] Reference Figure 3 and Figure 6 During the initialization period in the first frame FR1, an activated first scan signal GIj may be provided through the first scan line GILj. In response to the activated first scan signal GIj, the fourth transistor T4 may be turned on, and the first initialization voltage VINT1 may be transmitted through the fourth transistor T4 to the respective gate electrodes of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2, and the second node ND2. As a result, the gate electrodes of the respective transistors of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may be initialized.

[0102] Next, when the activated second scan signal GWj is supplied through the second scan line GWLj during the data programming and compensation period in the first frame FR1, the third transistor T3 is turned on. The (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 are set in a diode-connected state and forward biased by the turned-on third transistor T3. In addition, the second transistor T2 is turned on by the activated second scan signal GWj. Then, a compensation voltage (expressed as Di-Vth) is applied to the second node ND2. The compensation voltage (Di-Vth) is obtained by subtracting the threshold voltage (expressed as Vth) of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 from the data signal Di supplied from the data line DLi. Therefore, the gate voltage applied to the gate electrode of each of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 can become the compensation voltage (Di-Vth).

[0103] The first driving voltage ELVDD and the compensation voltage (Di-Vth) may be applied to respective ends of the first capacitor C1 , and charges corresponding to a voltage difference between the ends may be stored in the first capacitor C1 .

[0104] At the same time, the seventh transistor T7 is turned on by receiving the activated second scan signal GWj through the second scan line GWLj. Due to the seventh transistor T7, a portion of the driving current Id may escape through the seventh transistor T7 as a bypass current.

[0105] Unlike the present invention, if the light emitting diode ED emits light even when the minimum current of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 at which a black image is displayed flows as a driving current, the black image cannot be properly displayed. However, the seventh transistor T7 in the pixel PXij according to the embodiment of the present invention can distribute a part of the minimum current of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 as a bypass current to a current path other than the current path on the light emitting diode side. In one embodiment, since the gate-source voltage (expressed as Vgs) of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 is less than the threshold voltage (Vth), the minimum current of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 can correspond to the current flowing under the condition that the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 are turned off. A minimum driving current (eg, a current of about 10 pA or less) under such a condition that the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 are turned off is transmitted to the light emitting diode ED, and an image having black brightness is displayed.

[0106] It can be said that when the minimum driving current (where a black image is displayed) flows, there is a substantial influence of the bypass transmission of the bypass current, and when a large driving current flows where an image (such as a conventional image or a white image) is displayed, there is almost no influence of the bypass current. Therefore, when the driving current for displaying a black image flows, the emission current Ied of the light emitting diode ED (the emission current Ied of the light emitting diode ED reduces the amount of current of the bypass current escaping from the driving current Id through the seventh transistor T7) has a minimum current amount at a level where a black image can be clearly displayed. Therefore, by using the seventh transistor T7, an accurate black brightness image can be achieved, and the contrast can also be improved. In the present embodiment, the bypass signal is an activated second scanning signal GWj, but the embodiments of the inventive concept are not necessarily limited to this.

[0107] Next, during the emission period in the first frame FR1, the emission signal EMj supplied from the emission control line EMLj changes from a high level to a low level. The period in which the emission signal EMj has a low level may be an emission period. During the emission period, the fifth transistor T5 and the sixth transistor T6 are turned on by the emission signal EMj having a low level. Then, a drive current Id corresponding to the voltage difference between the gate voltage of the gate electrode of each of the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 and the first drive voltage ELVDD is generated and supplied to the light emitting diode ED through the sixth transistor T6. As a result, the emission current Ied flows through the light emitting diode ED. Here, the pixel PXij may emit light having a first brightness value, for example, the display panel DP may have a first brightness value in the first mode MD1.

[0108] In the first mode MD1, the activated brightness signal CBj may not be provided to the gate electrode of the eighth transistor T8 in the first frame FR1. As a result, the eighth transistor T8 may be disabled. That is, the brightness signal CBj may be disabled in the first mode MD1, and as a result, the eighth transistor T8 may be disabled, and since both the (1-1) transistor T1-1 (first drive sub-transistor) and the (1-2) transistor T1-2 (second drive sub-transistor) are turned on, the drive current Id may be generated. In an embodiment, both the (1-1) transistor T1-1 (first drive sub-transistor) and the (1-2) transistor T1-2 (second drive sub-transistor) may also be referred to as a combined drive transistor. As previously noted, in this case, the combined drive transistor has a channel length equal to the sum of the channel lengths of the sub-drive transistors T1-1 and T1-2. As a result, compared with the third mode MD3, the pixel PXij may emit light at a relatively lower brightness. As described in more detail below, during this time, this lower brightness may also be generated by a relatively short pulse width of the brightness signal CBj.

[0109] More specifically, in the first frame FR1 in which the operation is performed in the first mode MD1, the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may be turned on in response to the voltage of the second node ND2. The first current path may be formed along the fifth transistor T5, the (1-1)th transistor T1-1, the (1-2)th transistor T1-2, and the sixth transistor T6. The (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may supply a driving current Id to the light emitting diode ED. Here, the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2 may operate as a single driving transistor. The channel length of the driving transistor may be the sum of the first channel length of the (1-1)th transistor T1-1 and the second channel length of the (1-2)th transistor T1-2. During the first mode MD1, the pixel PXij may emit light having a first (or lower) brightness value.

[0110] The driving of the pixel PXij during the initialization period and the data programming and compensation period in the second frame FR2 to the fifth frame FR5 can be performed in the same manner as the driving of the pixel PXij during the initialization period and the data programming and compensation period in the first frame FR1. Therefore, the description of the driving of the pixel PXij during the initialization period and the data programming and compensation period in the second frame FR2 to the fifth frame FR5 will be omitted.

[0111] During the emission period in the second frame FR2 to the fifth frame FR5, the emission signal EMj supplied from the emission control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on by the emission signal EMj. In addition, during the emission period of the second frame FR2 to the fifth frame FR5, the eighth transistor T8 may be activated. The eighth transistor T8 may be turned on in response to the activated brightness signal CBj. When the eighth transistor T8 is turned on, the (1-1)th transistor T1-1 is effectively short-circuited, but the (1-2)th transistor T1-2 is turned on. As a result, the drive current Id is generated to correspond to the voltage difference between the gate voltage of the gate electrode of the (1-2)th transistor T1-2 and the first drive voltage ELVDD. The generated drive current Id is supplied to the light emitting diode ED through the sixth transistor T6, and the emission current Ied flows through the light emitting diode ED.

[0112] like Figure 6As shown in , the brightness signal CBj may have a pulse width that increases progressively from the second frame FR2 to the fifth frame FR5. For example, the brightness signal CBj may have a first pulse width CBW1 in the second frame FR2, a second pulse width CBW2 in the third frame FR3, and a third pulse width CBW3 in the fourth frame FR4. Here, the second pulse width CBW2 may be greater than the first pulse width CBW1 and less than the third pulse width CBW3. As a result, the display panel DP may have a second brightness value greater than the first brightness value in the first frame FR1 in the second frame FR2, a third brightness value in the third frame FR3, and a fourth brightness value in the fourth frame FR4. Here, the third brightness value may be greater than the second brightness value and less than the fourth brightness value. Therefore, in the second mode MD2, the display panel DP may gradually or progressively brighten from the second brightness value to a fourth brightness value greater than the second brightness value.

[0113] In the third mode MD3, the brightness signal CBj may be activated in the fifth frame FR5 while having the fourth pulse width CBW4. Here, the fourth pulse width CBW4 may be greater than the third pulse width CBW3, for example, the first pulse width CBW1 to the fourth pulse width CBW4 may be gradually increased in a sequential manner. In the subsequent frame FR, the brightness signal CBj may be activated while having the fourth pulse width CBW4. The brightness of the display panel DP may have a fifth brightness value in the fifth frame FR5. The fifth brightness value may be greater than the fourth brightness value. Therefore, the brightness value may increase sequentially from the first mode MD1 to the third mode MD3.

[0114] In the frame in which the operation is performed in the second mode MD2 and the third mode MD3, the second current path can be formed along the fifth transistor T5, the eighth transistor T8, the (1-2)th transistor T1-2 and the sixth transistor T6. This is because when the eighth transistor T8 is turned on, the (1-1)th transistor T1-1 is effectively short-circuited. In this case, the (1-2)th transistor T1-2 can supply the emission current Ied to the light emitting diode ED. Here, only the (1-2)th transistor T1-2 can operate as a driving transistor. As a result, the channel length of the driving transistor can be the second channel length of the (1-2)th transistor T1-2.

[0115] According to the present invention, the channel length of the driving transistor in the third mode MD3 may be less than the channel length of the driving transistor in the first mode MD1. Therefore, the emission current Ied flowing through the light emitting diode ED in the third mode MD3 may be greater than the emission current Ied flowing through the light emitting diode ED in the first mode MD1. As a result, the pixel PXij operated in the third mode MD3 may have a higher brightness than the pixel PXij operated in the first mode MD1. Therefore, the pixel PXij may be a pixel that is easily driven with high brightness in the third mode MD3.

[0116] If the display panel DP is driven continuously in the first mode MD1 and the third mode MD3 without being driven in the second mode MD2, for example, the first frame FR1 and the fifth frame FR5 can be driven continuously. Here, because the brightness of the display panel DP can be quickly changed from the first brightness value to the fifth brightness value, the deviation of the brightness can be visually recognized by the user. However, according to the inventive concept, the display panel DP can be driven in the first mode MD1, the second mode MD2 and the third mode MD3. For example, at least one frame can be inserted between the first frame and the last frame, for example, the first frame FR1 to the fifth frame FR5 can be driven continuously. As the pulse width of the brightness signal CBj gradually increases, the brightness of the pixel PXij can be increased in a corresponding manner. That is, during the second mode MD2, as the frame advances, the brightness of the pixel PXij can be gradually increased. Therefore, the brightness of the display panel DP can be gradually increased from the first brightness value to the higher fifth brightness value. As a result, the deviation of the brightness can not be visually recognized by the user. Therefore, the display device 1000 can be provided as a display panel DP having an improved display quality.

[0117] Figure 7 is a timing diagram illustrating an operation of a pixel PXij according to an embodiment of the inventive concept. Figure 7 The display panel DP (see, for example, Figure 2 ) is a process of sequentially driving in high brightness mode, intermediate mode and normal mode. That is, Figure 7 2 shows the operation when the high brightness mode is changed to the normal mode. Figure 7 In the description of Figure 6 The described components are given the same reference numerals or symbols, and description thereof is omitted.

[0118] Reference Figure 2 , Figure 3 and Figure 7 , also refer to Figure 6 , the display panel DP may be driven in units of frames FR. The frames FR may further include a sixth frame FR6, a seventh frame FR7, an eighth frame FR8, a ninth frame FR9, and a tenth frame FR10.

[0119] The display panel DP may be driven in the third mode MD3 for the sixth frame FR6 , in the second mode MD2 for one or more frames (eg, seventh to ninth frames FR7 to FR9 ), and in the first mode MD1 for the tenth frame FR10 .

[0120] The brightness signal CBj may be activated in the sixth frame FR6 to have a predetermined width, for example, a fourth pulse width CBW4. The display panel DP may have a high brightness value (for example, a fifth brightness value) in the sixth frame FR6.

[0121] When the second mode MD2 has three frames, the brightness signal CBj may have a third pulse width CBW3 in the seventh frame FR7, may have a second pulse width CBW2 in the eighth frame FR8, and may have a first pulse width CBW1 in the ninth frame FR9. During the seventh frame FR7 to the ninth frame FR9, the pulse width of the brightness signal CBj may be gradually reduced. For example, the display panel DP may have a fourth brightness value lower than the fifth brightness value in the seventh frame FR7, may have a third brightness value in the eighth frame FR8, and may have a second brightness value in the ninth frame FR9. Here, the third brightness value may be greater than the second brightness value and less than the fourth brightness value. Therefore, in the second mode MD2, the brightness of the display panel DP may be gradually reduced from the fourth brightness value to the second brightness value.

[0122] The brightness signal CBj activated in the tenth frame FR10 may not be provided to the gate electrode of the eighth transistor T8. As a result, the eighth transistor T8 may be disabled. In this case, the brightness signal CBj may be disabled in the first mode MD1, and the eighth transistor T8 may be disabled. In subsequent frames, the brightness signal CBj may be disabled. In the tenth frame FR10, since both transistors (1-1)th transistor T1-1 and (1-2)th transistor T1-2 are turned on, the display panel DP may emit light having a first brightness value less than a second brightness value.

[0123] According to the present invention, the channel length of the driving transistor of the pixel PXij in the third mode MD3 may be less than the channel length of the driving transistor in the first mode MD1. As a result, the emission current Ied flowing through the light emitting diode ED in the third mode MD3 may be greater than the emission current Ied flowing through the light emitting diode ED in the first mode MD1. The pixel PXij operated in the third mode MD3 may have a higher brightness than the brightness of the pixel PXij operated in the first mode MD1. Therefore, a pixel PXij that is easily driven with high brightness can be provided.

[0124] In the case where the display panel DP is continuously driven in the third mode MD3 and the first mode MD1 but not in the second mode MD2, a perceptible brightness deviation may occur. That is, in the case where the sixth frame FR6 and the tenth frame FR10 are continuously driven, the brightness of the display panel DP may quickly change from the fifth brightness value to the first brightness value. As a result, the deviation in brightness may be visually recognized by the user.

[0125] However, according to the present invention, the display panel DP can be driven in a mode between the third mode MD3 and the first mode MD1, for example, the display panel DP can be driven in the third mode MD3, the second mode MD2 and the first mode MD1. That is, at least one frame can be included between the first frame and the last frame, for example, the sixth frame FR6 to the tenth frame FR10 can be driven continuously. As the pulse width of the brightness signal CBj becomes smaller, the brightness of the pixel PXij can become lower. That is, as the frame progresses during the second mode MD2, the brightness of the pixel PXij can be gradually or progressively reduced. Therefore, the brightness of the display panel DP can be gradually reduced from the fifth brightness value to the first brightness value. As a result, the deviation of the brightness may not be visually recognized by the user. Therefore, a display device 1000 including a display panel DP with improved display quality can be provided.

[0126] According to the above description, the display panel can be driven continuously in the first mode, the second mode and the third mode. As at least one frame advances during the second mode, the brightness of the pixel can be gradually changed. Therefore, the brightness of the display panel can be gradually changed, and the deviation of the brightness can not be visually recognized by the user. Therefore, a display device including a display panel with improved display quality can be provided.

[0127] Although the embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these embodiments, but a person of ordinary skill in the art can make various changes and modifications within the spirit and scope of the inventive concept as claimed below. Therefore, the technical scope of the inventive concept is not limited to the contents described in the detailed description of the specification, but should be defined by the appended claims. The embodiments can be combined to form additional embodiments.

Claims

1. A display device, wherein: The display device comprises: A display panel is driven in units of frames, and the display panel includes pixels, and the pixels include a pixel driving circuit and a light emitting element electrically connected to the pixel driving circuit, wherein the pixel driving circuit includes: a first capacitor connected between the second node and a first voltage line supplied with a first driving voltage; A 1-1 transistor including a first electrode electrically connected to the first voltage line and to a first node, a second electrode electrically connected to a third node, and a gate electrode electrically connected to the second node; A 1-2 transistor including a first electrode electrically connected to the third node, a second electrode electrically connected to the light emitting element, and a gate electrode electrically connected to the second node; and a brightness transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the third node, and a gate electrode configured to receive a brightness signal, wherein the frame includes a first frame and a second frame connected in series, and The brightness signal is activated to have a first pulse width in the first frame and is activated to have a second pulse width different from the first pulse width in the second frame.

2. The display device according to claim 1, wherein: The display panel has a first brightness value in the first frame and has a second brightness value greater than the first brightness value in the second frame, and The second pulse width is greater than the first pulse width.

3. The display device according to claim 2, wherein: The frame further includes a third frame continuous with the second frame and a fourth frame continuous with the third frame, wherein the brightness signal is activated to have a third pulse width in the third frame and is activated to have a fourth pulse width different from the third pulse width in the fourth frame, and The display panel has a third brightness value greater than the second brightness value in the third frame and has a fourth brightness value greater than the third brightness value in the fourth frame.

4. The display device according to claim 3, wherein: The first pulse width to the fourth pulse width increase gradually in sequence.

5. The display device according to claim 1, wherein: The frames also include a fifth frame, a sixth frame, a seventh frame, and an eighth frame which are driven successively, the brightness signal is activated to have a fifth pulse width in the fifth frame, is activated to have a sixth pulse width in the sixth frame, is activated to have a seventh pulse width in the seventh frame, and is activated to have an eighth pulse width in the eighth frame, The fifth pulse width to the eighth pulse width are different from each other, and The display panel has a fifth brightness value in the fifth frame, a sixth brightness value in the sixth frame, a seventh brightness value in the seventh frame, and an eighth brightness value in the eighth frame, and the fifth brightness value to the eighth brightness value decrease progressively in sequence.

6. The display device according to claim 5, wherein: The fifth pulse width to the eighth pulse width gradually decrease in sequence.

7. The display device according to claim 1, wherein: The pixel driving circuit further includes a second transistor including a first electrode electrically connected to a data line provided with a data signal, a second electrode electrically connected to the first node, and a gate electrode configured to receive a first scan signal, and The pixel driving circuit further includes a third transistor, which includes a first electrode electrically connected to the second node, a second electrode electrically connected to the second electrode of the 1-2 transistor, and a gate electrode configured to receive the first scanning signal.

8. The display device according to claim 1, wherein: The pixel driving circuit also includes a fourth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a first initialization voltage line supplied with a first initialization voltage, and a gate electrode configured to receive a second scan signal.

9. A display device comprising a display panel, the display panel being driven in units of frames, and the display panel comprising pixels, the pixels comprising a pixel driving circuit and a light emitting element electrically connected to the pixel driving circuit, wherein: The pixel driving circuit comprises: a 1-1th transistor electrically connected to a first voltage line supplied with a first driving voltage, the 1-1th transistor being electrically connected between a first node and a second node and including a gate electrode; a 1-2 transistor electrically connected between the second node and the light emitting element and including a gate electrode electrically connected to the gate electrode of the 1-1 transistor; and a brightness transistor electrically connected between the first node and the second node and configured to receive a brightness signal, wherein the display panel is driven in a first mode, a second mode and a third mode, In the first mode, the 1-1 transistor and the 1-2 transistor are activated, and the display panel has a first brightness value, In the second mode, the 1-2 transistor and the brightness transistor are activated, and the display panel gradually changes in brightness value from the first brightness value to a second brightness value different from the first brightness value, and In the third mode, the 1-1th transistor and the brightness transistor are activated, and the display panel has the second brightness value.

10. The display device according to claim 9, wherein: The second mode is disposed between the first mode and the third mode.

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