Display panel, display device and driving method

Abstract

The invention relates to the technical field of display, and discloses a display panel, a display device and a driving method.The display panel comprises a plurality of sub-pixels, a plurality of data lines and a plurality of gate control circuits, one column of sub-pixels are correspondingly connected with at least two data lines, the sub-pixels connected with the at least two data lines are different, and the gate control circuits are connected with the data lines. One column of sub-pixels corresponds to one gate control circuit, and one gate control circuit is connected with the at least two data lines and is configured to provide reference voltage for one part of the at least two data lines and provide data voltage for the other part of the data lines, so that in the picture display process of the display panel, the data voltage of the data lines is increased; according to the display panel, the reference voltage in part of the data lines can enable part of pictures to be in a black state, and meanwhile, the data voltage in the other part of the data lines can enable the other part of pictures to be normally displayed, so that the display of different display modes of the display panel can be realized, and the display flexibility of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology and provides a display panel, a display device and a driving method. Background Art

[0002] With the development of technology, the demand for multi-mode display in different application scenarios of display modules is gradually increasing. For example, the in-vehicle central control display needs to realize two display modes: sharing and anti-peeping of different display areas. In the shared display mode, the driver and the front passenger can share the entire central control display; in the anti-peeping mode, part of the central control display can only be used by the front passenger, and the other part can be used by both the driver and the front passenger.

[0003] However, in the related art, the display module is usually only applied to one fixed display mode, and the application scenario is relatively single. Summary of the invention

[0004] The embodiments of the present application provide a display panel, a display device, and a driving method, which are used to realize display of different display modes of the display panel, thereby improving the display flexibility of the display panel.

[0005] The specific technical solutions provided by this application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising: a plurality of sub-pixels, a plurality of data lines, and a plurality of gating control circuits;

[0007] A column of sub-pixels is connected to at least two data lines, and the sub-pixels connected to at least two data lines are different;

[0008] One column of sub-pixels corresponds to one gate control circuit, and one gate control circuit is connected to at least two data lines and is configured to provide a reference voltage to a part of the at least two data lines and provide a data voltage to another part of the data lines.

[0009] Optionally, the gating control circuit includes: a first gating control subcircuit and a second gating control subcircuit;

[0010] The first gate control subcircuit is configured to provide a first data voltage to the first data line and a reference voltage to the second data line in response to a first gate control signal at the first gate control terminal; or

[0011] The second gate control subcircuit is configured to provide a reference voltage to the first data line and a second data voltage to the second data line in response to a second gate control signal at the second gate control terminal;

[0012] The first selection control signal and the second selection control signal are inverted signals.

[0013] Optionally, it further comprises: a first gate control line and a second gate control line;

[0014] The first gate control line is electrically connected to the first gate control terminal and is configured to provide a first gate control signal to the first gate control terminal;

[0015] The second gate control line is electrically connected to the second gate control terminal and is configured to provide a second gate control signal to the second gate control terminal.

[0016] Optionally, it also includes: a voltage input line and a data input line;

[0017] One end of the voltage input line is electrically connected to the first gating control subcircuit and the second gating control subcircuit, and is configured to provide a reference voltage to the first gating control subcircuit and the second gating control subcircuit;

[0018] One end of the data input line is electrically connected to the first gate control subcircuit and the second gate control subcircuit, and is configured to provide a first data voltage to the first gate control subcircuit and a second data voltage to the second gate control subcircuit.

[0019] Optionally, the first gating control subcircuit includes: a first transistor and a second transistor;

[0020] The control terminal of the first transistor is electrically connected to the first selection control terminal, the first terminal of the first transistor is electrically connected to the first data line, and the second terminal of the first transistor is electrically connected to the data input line;

[0021] The control terminal of the second transistor is electrically connected to the first selection control terminal, the first terminal of the second transistor is electrically connected to the second data line, and the second terminal of the second transistor is electrically connected to the voltage input line.

[0022] Optionally, the second gating control subcircuit includes: a third transistor and a fourth transistor;

[0023] The control terminal of the third transistor is electrically connected to the second selection control signal terminal, the first terminal of the third transistor is electrically connected to the first data line, and the second terminal of the third transistor is electrically connected to the voltage input line;

[0024] The control terminal of the fourth transistor is electrically connected to the second selection control terminal, the first terminal of the fourth transistor is electrically connected to the second data line, and the second terminal of the fourth transistor is electrically connected to the data input line.

[0025] Optionally, the sub-pixels in even-numbered rows are electrically connected to the first data line, and the sub-pixels in odd-numbered rows are electrically connected to the second data line.

[0026] Optionally, each sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes: a driving transistor, a light-emitting device, a data writing sub-circuit, a first resetting sub-circuit and a first capacitor;

[0027] The driving transistor is electrically connected to the light emitting device;

[0028] A first terminal of the data writing subcircuit is coupled to the first terminal of the driving transistor, a second terminal of the data writing subcircuit is coupled to the data signal terminal, and is configured to provide a data voltage of the data signal terminal to the first terminal of the driving transistor in response to a signal of the scanning signal terminal;

[0029] The first reset subcircuit is coupled to the control terminal of the driving transistor, and the first reset subcircuit is configured to provide a signal from the first initialization signal terminal to the control terminal of the driving transistor in response to a signal from the reset control signal terminal;

[0030] The first capacitor is electrically connected to the control terminal of the driving transistor and the first power terminal, and is configured to store the first data voltage or the second data voltage.

[0031] Optionally, the data writing sub-circuit includes: a data writing transistor;

[0032] The data signal terminals of the data writing transistors in the even-numbered rows are electrically connected to the first data line, and the data signal terminals of the data writing transistors in the odd-numbered rows are electrically connected to the second data line.

[0033] Optionally, the pixel driving circuit further includes: a conduction control subcircuit, a first light emitting control subcircuit, a second light emitting control subcircuit, and a second reset subcircuit;

[0034] A first terminal of the conduction control subcircuit is electrically connected to the control terminal of the driving transistor, a second terminal of the conduction control subcircuit is electrically connected to the second terminal of the driving transistor, and is configured to conduct the control terminal of the driving transistor with the second terminal of the driving transistor in response to a signal at the conduction control signal terminal;

[0035] A first terminal of the first light emitting control subcircuit is electrically connected to the first power terminal, a second terminal of the first light emitting control subcircuit is electrically connected to the first terminal of the driving transistor, and the first light emitting control subcircuit is configured to conduct the first power terminal with the first terminal of the driving transistor in response to a signal at the light emitting control signal terminal;

[0036] The first terminal of the second light emitting control subcircuit is electrically connected to the second terminal of the driving transistor, the second terminal of the second light emitting control subcircuit is electrically connected to the anode of the light emitting device, and is configured to conduct the second terminal of the driving transistor to the anode of the light emitting device in response to the signal of the light emitting control signal terminal;

[0037] The second reset subcircuit is electrically connected to the anode of the light emitting device, and is configured to provide a signal from the second initialization signal terminal to the anode of the light emitting device in response to a signal from the reset control signal terminal.

[0038] Optionally, the first data line and the second data line both extend along the first direction.

[0039] Optionally, the light emitting structures of the sub-pixels in the even-numbered rows are different from those of the sub-pixels in the odd-numbered rows.

[0040] In a second aspect, an embodiment of the present application further provides a display device, comprising any one of the display panels described above.

[0041] Optionally, it also includes a source driving circuit;

[0042] The source driving circuit is electrically connected to the other end of the data input line and is configured to provide the first data voltage or the second data voltage to the data input line.

[0043] Optionally, it also includes: a power management circuit PMIC, a timing controller TCON and a level conversion unit LS;

[0044] The PMIC is electrically connected to the other end of the voltage input line and is configured to provide a reference voltage to the voltage input line;

[0045] The PMIC is also electrically connected to the source driving circuit and is configured to provide a reference voltage to the source driving circuit to drive the source driving circuit to work;

[0046] The PMIC is also electrically connected to the TCON and configured to provide a driving voltage to the TCON;

[0047] TCON is electrically connected to the source driving circuit and is configured to provide the source driving circuit with a preselected data voltage for generating a first data voltage and a second data voltage, generate a first gating control signal and a second gating control signal based on the driving voltage, and generate a logic voltage signal based on the driving voltage;

[0048] LS is electrically connected to TCON, the first gate control line and the second gate control line, and is configured to perform level conversion on the first gate control signal and the second gate control signal, provide the converted first gate control signal to the first gate control line, and provide the converted second gate control signal to the second gate control line;

[0049] LS is also electrically connected to the gate driving circuit, and is configured to perform level conversion on the logic voltage signal, and provide the converted effective high level signal and effective low level signal to the gate driving circuit.

[0050] Optionally, an inverter is further included, wherein an input end of the inverter is electrically connected to TCON, and an output end of the inverter is electrically connected to LS;

[0051] The inverter is configured to invert the first gate control signal generated by TCON to obtain the second gate control signal, or invert the second gate control signal generated by TCON to obtain the first gate control signal.

[0052] In a third aspect, an embodiment of the present application further provides a method for driving a display panel according to any one of the above items, comprising:

[0053] The gating control circuit provides reference voltages to a portion of data lines corresponding to each sub-pixel; and

[0054] The gate control circuit provides data voltages to another part of the data lines corresponding to each sub-pixel.

[0055] The beneficial effects of this application are as follows:

[0056] In summary, a display panel, a display device and a driving method are provided in an embodiment of the present application. The display panel includes: multiple sub-pixels, multiple data lines and multiple selection control circuits. A column of sub-pixels corresponds to at least two data lines, and the sub-pixels connected to at least two data lines are different. A column of sub-pixels corresponds to a selection control circuit, and a selection control circuit is connected to at least two data lines and is configured to provide a reference voltage to a part of the at least two data lines and provide a data voltage to another part of the data lines. In this way, during the picture display process of the display panel, the reference voltage in some data lines can make part of the picture appear black, and at the same time, the data voltage in another part of the data lines can make another part of the picture display normally, thereby realizing the display of different display modes of the display panel and improving the display flexibility of the display panel.

[0057] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0059] Figure 1 This is a schematic diagram of the connection of the first display panel in the embodiment of the present application;

[0060] Figure 2 This is a schematic diagram of the structure of a second display panel in an embodiment of the present application;

[0061] Figure 3is a schematic structural diagram of a third display panel in an embodiment of the present application;

[0062] Figure 4 is a schematic structural diagram of a fourth display panel in an embodiment of the present application;

[0063] Figure 5 This is a connection diagram of the first gating control circuit in the embodiment of the present application;

[0064] Figure 6 This is a connection diagram of a second gating control circuit in an embodiment of the present application;

[0065] Figure 7 This is a connection diagram of a third gating control circuit in an embodiment of the present application;

[0066] Figure 8 This is a schematic diagram of the connection between the first gating control circuit and the pixel driving circuit in the embodiment of the present application;

[0067] Fig. 9 This is a schematic diagram of the connection between the second gating control circuit and the pixel driving circuit in the embodiment of the present application;

[0068] Fig.10 This is a connection diagram of a pixel driving circuit in an embodiment of the present application;

[0069] Fig.11 is a circuit connection diagram of a pixel driving circuit in an embodiment of the present application;

[0070] Fig.12 A schematic diagram of a light emitting structure of a sub-pixel in an embodiment of the present application;

[0071] Fig.13 This is a schematic diagram of a display panel displaying in full screen mode 1 in an embodiment of the present application;

[0072] Fig.14 This is a timing diagram of the display panel displaying in full screen mode 1 in the embodiment of the present application;

[0073] Fig.15 A schematic diagram of a display panel displaying in full screen mode 2 in an embodiment of the present application;

[0074] Fig.16 This is a timing diagram of the display panel displaying in full screen mode 2 in the embodiment of the present application;

[0075] Fig.17 A schematic diagram of an upper and lower screen of a display panel in an embodiment of the present application displaying in display mode 1 and display mode 2 respectively;

[0076] Fig.18A timing diagram showing that the upper and lower screens of the display panel in the embodiment of the present application are displayed in display mode 1 and display mode 2 respectively;

[0077] Fig.19 A schematic diagram showing that the left and right screens of a display panel in an embodiment of the present application display in display mode 1 and display mode 2 respectively;

[0078] Fig. 20 This is a timing diagram of the left and right screens of the display panel in the embodiment of the present application being displayed in display mode 1 and display mode 2 respectively;

[0079] Fig.21 Schematic diagram of a flexible area of ​​a display panel in an embodiment of the present application being displayed in display mode 1 and display mode 2 respectively;

[0080] Fig. 22 A timing diagram showing that the flexible area of ​​the display panel in the embodiment of the present application is displayed in display mode 1 and display mode 2 respectively;

[0081] Fig.23 This is a connection diagram of a display device in an embodiment of the present application;

[0082] Fig.24 Schematic diagram of the connection of an inverter in an embodiment of the present application. DETAILED DESCRIPTION

[0083] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the technical solution of the present application, rather than all of the embodiments. Based on the embodiments recorded in the application documents, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the technical solution of the present application.

[0084] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented using sequences other than those illustrated or described herein.

[0085] With the development of technology, the demand for multi-mode display in different application scenarios of display modules is gradually increasing. For example, the in-vehicle central control display needs to realize two display modes: sharing and anti-peeping of different display areas. In the shared display mode, the driver and the front passenger can share the entire central control display; in the anti-peeping mode, part of the central control display can only be used by the front passenger, and the other part can be used by both the driver and the front passenger.

[0086] However, in the related art, the display module is usually only applied to a fixed display mode, and the application scenario is relatively single. The reason is that the light-emitting structures of each sub-pixel included in the display module are the same, and a single sub-pixel is electrically connected to a gate line and a data line respectively. During the display process, when the scanning signal in the gate line corresponding to a sub-pixel is valid, the data voltage in the data line is provided to a pixel driving circuit included in the sub-pixel, and then drives the light-emitting device in the pixel driving circuit to perform light-emitting display. When the data voltage in the data line is different, the brightness of the picture presented by the sub-pixel is different, but the display mode of the entire frame is fixed, and a display panel cannot present different display modes in different application scenarios.

[0087] The implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0088] See also Figure 1 As shown, a display panel proposed in an embodiment of the present application includes: a plurality of sub-pixels, a plurality of data lines and a plurality of gating control circuits.

[0089] A column of sub-pixels is correspondingly connected to at least two data lines, and the sub-pixels connected to the at least two data lines are different.

[0090] Different from the solution in the related art where the number of columns of sub-pixels corresponds to the number of data lines, in the embodiment of the present application, one column of sub-pixels is connected to at least two data lines. Figure 1 As shown, a column of sub-pixels is connected to two data lines respectively. For example, the sub-pixels in the first column are electrically connected to data line 1 and data line 2, respectively, the sub-pixels in the second column are electrically connected to data line 3 and data line 4, respectively, the sub-pixels in the third column are electrically connected to data line 5 and data line 6, respectively, and the sub-pixels in the Mth column are electrically connected to data line 2M-1 and data line 2M, respectively.

[0091] Exemplarily, when there are two display modes, one column of sub-pixels is connected to two data lines; when there are three display modes, one column of sub-pixels is connected to three data lines, and so on.

[0092] It should also be noted that different data lines are connected to different sub-pixels. Since one data line is shared by a column of sub-pixels, each sub-pixel in a column of sub-pixels is electrically connected to a corresponding data line of at least two data lines.

[0093] Exemplarily, when a column of sub-pixels is connected to two data lines, the sub-pixels in the even-numbered rows are electrically connected to one of the data lines, and the sub-pixels in the odd-numbered rows are electrically connected to the other data line. Figure 1As shown, the sub-pixel 11 located in the first row in the first column and the sub-pixel L1 in the 2n+1th row are electrically connected to the data line 1, and the sub-pixel 21 located in the second row in the first column and the sub-pixel N1 in the 2nth row are electrically connected to the data line 2; the sub-pixel 12 located in the first row in the second column and the sub-pixel L2 in the 2n+1th row are electrically connected to the data line 3, and the sub-pixel 22 located in the second row in the second column and the sub-pixel N2 in the 2nth row are electrically connected to the data line 4; the sub-pixel 13 located in the first row in the third column and the sub-pixel L3 in the 2n+1th row are electrically connected to the data line 5, the sub-pixel 23 located in the second row in the third column and the sub-pixel N3 in the 2nth row are electrically connected to the data line 6, and so on, where n is a natural number.

[0094] Exemplarily, when a column of sub-pixels is connected to three data lines, the sub-pixels in the 3n-2th row are electrically connected to the first data line, the sub-pixels in the 3n-1th row are electrically connected to the second data line, and the sub-pixels in the 3nth row are electrically connected to the third data line, where n is a natural number.

[0095] It should be supplemented that, from the perspective that the display panel includes multiple pixel units, in order to realize the display of multiple display modes, the number of sub-pixels included in a pixel unit is doubled in the embodiment of the present application.

[0096] For example, see Figure 2 As shown, when a pixel unit in a display panel that can only display one display mode includes sub-pixel R, sub-pixel G, and sub-pixel B, a pixel unit in the embodiment of the present application includes not only sub-pixel R, sub-pixel G, and sub-pixel B located in the first row, but also sub-pixel R, sub-pixel G, and sub-pixel B located in the second row. During implementation, sub-pixel R, sub-pixel G, and sub-pixel B located in the first row are used for displaying the screen of display mode 1, and sub-pixel R, sub-pixel G, and sub-pixel B located in the second row are used for displaying the screen of display mode 2. The other pixel units of the display panel in the embodiment of the present application are similar, and will not be described one by one here.

[0097] For example, see Figure 3As shown, when a pixel unit in a display panel that can only display one display mode includes sub-pixel R, sub-pixel G and sub-pixel B, a pixel unit in the embodiment of the present application includes not only sub-pixel R, sub-pixel G and sub-pixel B located in the first row, but also sub-pixel B, sub-pixel G and sub-pixel R located in the second row. During implementation, sub-pixel R, sub-pixel G and sub-pixel B located in the first row are used for displaying the screen of display mode 1, and sub-pixel B, sub-pixel G and sub-pixel R located in the second row are used for displaying the screen of display mode 2, that is, the arrangement order of sub-pixels in the pixel unit is not limited during the screen display process of different display modes. In addition, in the embodiment of the present application, other pixel units in the display panel are similar, and will not be repeated here one by one.

[0098] For example, see Figure 4 As shown, when a pixel unit in a display panel that can only display one display mode includes sub-pixel R, sub-pixel G, sub-pixel B and sub-pixel W, a pixel unit in the embodiment of the present application includes not only sub-pixel R, sub-pixel G, sub-pixel B and sub-pixel W located in the first row, but also sub-pixel R, sub-pixel G, sub-pixel B and sub-pixel W located in the second row. During implementation, sub-pixel R, sub-pixel G, sub-pixel B and sub-pixel W located in the first row are used for displaying the screen of display mode 1, and sub-pixel R, sub-pixel G, sub-pixel B and sub-pixel W located in the second row are used for displaying the screen of display mode 2, that is, the arrangement order of sub-pixels in the pixel unit is not limited during the screen display process of different display modes. In addition, in the embodiment of the present application, other pixel units in the display panel are similar, and will not be repeated here one by one.

[0099] When the number of sub-pixels included in a pixel unit increases, the number of data lines connected to the sub-pixels will increase accordingly. In the embodiments of the present application, for ease of description, the explanation is unified from the perspective of the display panel including sub-pixels.

[0100] One column of sub-pixels corresponds to one gate control circuit, and one gate control circuit is connected to at least two data lines and is configured to provide a reference voltage to a part of the at least two data lines and provide a data voltage to another part of the data lines.

[0101] See also Figure 5 As shown, in the embodiment of the present application, a gate control circuit is newly added, and the number of the gate control circuits is the same as the number of columns of sub-pixels. The gate control circuit is electrically connected to each of the at least two data lines.

[0102] During the implementation, the gating control circuit is used to provide a reference voltage to a part of the data lines, so that each sub-pixel electrically connected to the part of the data lines can display under the action of the reference voltage. At the same time, the gating control circuit is also used to provide a data voltage to another part of the data lines, so that each sub-pixel electrically connected to the other part of the data lines can display under the action of the data voltage.

[0103] It should be supplemented that the data voltage in the embodiment of the present application is similar to the data voltage in the related art, that is, the driving current used to generate the light-emitting device OLED in the pixel driving circuit that drives the sub-pixel to emit light.

[0104] In addition, the reference voltage in the embodiment of the present application is a direct current of a fixed value, and the reference voltage is adapted to the power supply terminal in the pixel driving circuit of the sub-pixel. Exemplarily, the reference voltage is the AVDD, AVSS or GND voltage used to enable the pixel driving circuit to display a black state, that is, the driving transistor DTFT in the pixel driving circuit of the sub-pixel is cut off under the action of the reference voltage, thereby presenting an effect of "no picture displayed".

[0105] The following describes in detail the electrical connection between a column of sub-pixels and two data lines as an example.

[0106] When a column of sub-pixels is electrically connected to two data lines, the gate control circuit is also electrically connected to the two data lines at the same time, and provides data voltages and / or reference voltages to the two data lines respectively, which is described in detail below.

[0107] See also Figure 6 As shown, the gating control circuit includes: a first gating control sub-circuit and a second gating control sub-circuit.

[0108] First, the first gate control signal and the second gate control signal are inverted signals.

[0109] It should be explained here that, in the embodiment of the present application, when the gating control circuit includes a first gating control subcircuit and a second gating control subcircuit, the first gating control signal for controlling the first gating control subcircuit and the second gating control signal for controlling the second gating control subcircuit are mutually inverted signals. Exemplarily, when the first gating control signal is at a high level, the second gating control signal is at a low level; when the first gating control signal is at a low level, the second gating control signal is at a high level.

[0110] In addition, considering that the circuit structures constituting the first gating control subcircuit and the second gating control subcircuit are the same, during the implementation, when the first gating control signal is valid, the corresponding first gating control subcircuit is turned on, in this case, when the second gating control signal is invalid, the corresponding second gating control subcircuit is turned off; when the first gating control signal is invalid, the corresponding first gating control subcircuit is turned off, in this case, when the second gating control signal is valid, the corresponding second gating control subcircuit is turned on. That is, only one of the first gating control subcircuit and the second gating control subcircuit can be turned on.

[0111] The first gate control subcircuit is configured to provide a first data voltage to the first data line and a reference voltage to the second data line in response to a first gate control signal at the first gate control terminal.

[0112] During implementation, when the first selection control signal of the first selection control terminal is valid, the first selection control subcircuit is turned on, the first selection control subcircuit provides the received first data voltage to the first data line, and the first selection control subcircuit provides the received reference voltage to the second data line.

[0113] In the above case, the sub-pixel electrically connected to the first data line displays a normal picture, and the sub-pixel electrically connected to the second data line displays a black state. That is, the setting of the first selection control sub-circuit can make the sub-pixel electrically connected to the first data line and the sub-pixel electrically connected to the second data line present two display states at the same time, thereby providing a guarantee for the display panel to present at least two display modes.

[0114] The second gate control subcircuit is configured to provide a reference voltage to the first data line and a second data voltage to the second data line in response to a second gate control signal at the second gate control terminal.

[0115] During implementation, when the second selection control signal of the second selection control terminal is valid, the second selection control subcircuit is turned on, the second selection control subcircuit provides the received reference voltage to the first data line, and the second selection control subcircuit provides the received second data voltage to the second data line.

[0116] In the above case, the sub-pixel electrically connected to the second data line displays a normal picture, and the sub-pixel electrically connected to the first data line displays a black state. Similarly, the setting of the second selection control sub-circuit can make the sub-pixel electrically connected to the first data line and the sub-pixel electrically connected to the second data line present two display states at the same time, thereby providing a guarantee for the display panel to present at least two display modes.

[0117] See also Figure 5 and Figure 6As shown, the display panel further includes: a first gate control line and a second gate control line.

[0118] The first gate control line is electrically connected to the first gate control terminal and is configured to provide a first gate control signal to the first gate control terminal.

[0119] The second gate control line is electrically connected to the second gate control terminal and is configured to provide a second gate control signal to the second gate control terminal.

[0120] In order to provide the first gate control signal and the second gate control signal to the gate control circuit, the display panel in the embodiment of the present application further includes: a first gate control line and a second gate control line.

[0121] The first selection control line is electrically connected to the first selection control terminal of the selection control circuit. During the implementation process, the first selection control line provides the first selection control terminal with a first selection control signal.

[0122] The second gate control line is electrically connected to the second gate control terminal of the gate control circuit. During implementation, the second gate control line provides a second gate control signal to the second gate control terminal.

[0123] In addition, see Figure 5 and Figure 6 As shown, the above display panel further includes: a voltage input line and a data input line.

[0124] One end of the voltage input line is electrically connected to the first gate control subcircuit and the second gate control subcircuit, and is configured to provide a reference voltage to the first gate control subcircuit and the second gate control subcircuit.

[0125] In order to provide a reference voltage to the selection control circuit, the display panel in the embodiment of the present application also includes: a voltage input line, and the first selection control sub-circuit and the second selection control sub-circuit are both electrically connected to one end of the above-mentioned voltage input line. During implementation, the voltage input line provides a reference voltage to the first selection control sub-circuit, or the voltage input line provides a reference voltage to the second selection control sub-circuit.

[0126] One end of the data input line is electrically connected to the first gate control subcircuit and the second gate control subcircuit, and is configured to provide a first data voltage to the first gate control subcircuit and a second data voltage to the second gate control subcircuit.

[0127] In order to provide the first data voltage and the second data voltage to the strobe control circuit in a time-sharing manner, the display panel in the embodiment of the present application further includes: a data input line, and the first strobe control subcircuit and the second strobe control subcircuit are both electrically connected to one end of the data input line. During implementation, the data input line provides the first data voltage to the first strobe control subcircuit, or the data input line provides the second data voltage to the second strobe control subcircuit.

[0128] The circuit structures of the first gating control subcircuit and the second gating control subcircuit are respectively described in detail below. Figure 7 As shown, the first gating control subcircuit includes: a first transistor M1 and a second transistor M2.

[0129] A control terminal of the first transistor M1 is electrically connected to the first selection control terminal, a first terminal of the first transistor M1 is electrically connected to the first data line, and a second terminal of the first transistor M1 is electrically connected to the data input line.

[0130] In the embodiment of the present application, the first transistor M1 is arranged between the data input line and the first data line, that is, after the source driving circuit transmits the first data voltage to the data input line, the data input line provides the first data voltage to the first data line through the turned-on first transistor M1, and then the first data line provides the first data voltage to the corresponding connected sub-pixel.

[0131] Exemplarily, the first transistor M1 can be turned on under the control of the effective level of the first gating control signal of the first gating control terminal, and can be turned off under the control of the ineffective level of the first gating control signal of the first gating control terminal. Exemplarily, the first transistor M1 is set as an N-type transistor, then the effective level of the signal of the first gating control signal of the first gating control terminal is a high level, and the ineffective level of the signal of the first gating control signal of the first gating control terminal is a low level. Alternatively, the first transistor M1 is set as a P-type transistor, then the effective level of the signal of the first gating control signal of the first gating control terminal is a low level, and the ineffective level of the signal of the first gating control signal of the first gating control terminal is a high level.

[0132] See also Figure 7 As shown, the first transistor M1 is a P-type transistor. When the first selection control signal of the first selection control terminal is at a low level, the first transistor M1 is turned on, and the first data voltage in the data input line is provided to the first data line through the first transistor M1.

[0133] The control terminal of the second transistor M2 is electrically connected to the first selection control terminal, the first terminal of the second transistor M2 is electrically connected to the second data line, and the second terminal of the second transistor M2 is electrically connected to the voltage input line.

[0134] In the embodiment of the present application, the second transistor M2 is arranged between the voltage input line and the second data line, that is, the voltage input line provides the reference voltage to the second data line through the turned-on second transistor M2, and then the second data line provides the reference voltage to the corresponding connected sub-pixel.

[0135] Exemplarily, the second transistor M2 can be turned on under the control of the effective level of the first gating control signal of the first gating control terminal, and can be turned off under the control of the ineffective level of the first gating control signal of the first gating control terminal. Exemplarily, the second transistor M2 is set as an N-type transistor, then the effective level of the signal of the first gating control signal of the first gating control terminal is a high level, and the ineffective level of the signal of the first gating control signal of the first gating control terminal is a low level. Alternatively, the second transistor M2 is set as a P-type transistor, then the effective level of the signal of the first gating control signal of the first gating control terminal is a low level, and the ineffective level of the signal of the first gating control signal of the first gating control terminal is a high level.

[0136] See also Figure 7 As shown, the second transistor M2 is a P-type transistor. When the first selection control signal of the first selection control terminal is at a low level, the second transistor M2 is turned on, and the reference voltage in the voltage input line is provided to the second data line through the second transistor M2.

[0137] See also Figure 7 As shown, the second gating control subcircuit includes: a third transistor M3 and a fourth transistor M4.

[0138] A control terminal of the third transistor M3 is electrically connected to the second gate control signal terminal, a first terminal of the third transistor M3 is electrically connected to the first data line, and a second terminal of the third transistor M3 is electrically connected to the voltage input line.

[0139] In the embodiment of the present application, the third transistor M3 is arranged between the voltage input line and the first data line, that is, the voltage input line provides the reference voltage to the first data line through the turned-on third transistor M3, and then the first data line provides the reference voltage to the corresponding connected sub-pixel.

[0140] Exemplarily, the third transistor M3 can be turned on under the control of the effective level of the second gating control signal of the second gating control terminal, and can be turned off under the control of the ineffective level of the second gating control signal of the second gating control terminal. Exemplarily, the third transistor M3 is set as an N-type transistor, then the effective level of the second gating control signal of the second gating control terminal is a high level, and the ineffective level of the second gating control signal of the second gating control terminal is a low level. Alternatively, the third transistor M3 is set as a P-type transistor, then the effective level of the second gating control signal of the second gating control terminal is a low level, and the ineffective level of the second gating control signal of the second gating control terminal is a high level.

[0141] See also Figure 7 As shown, the third transistor M3 is a P-type transistor. When the second selection control signal of the second selection control terminal is at a low level, the third transistor M3 is turned on, and the reference voltage in the voltage input line is provided to the first data line through the third transistor M3.

[0142] A control terminal of the fourth transistor M4 is electrically connected to the second selection control terminal, a first terminal of the fourth transistor M4 is electrically connected to the second data line, and a second terminal of the fourth transistor M4 is electrically connected to the data input line.

[0143] In the embodiment of the present application, the fourth transistor M4 is arranged between the data input line and the second data line, that is, the data input line provides the second data voltage to the second data line through the turned-on fourth transistor M4, and then the second data line provides the second data voltage to the corresponding connected sub-pixel.

[0144] Exemplarily, the fourth transistor M4 can be turned on under the control of the effective level of the second gating control signal of the second gating control terminal, and can be turned off under the control of the ineffective level of the second gating control signal of the second gating control terminal. Exemplarily, the fourth transistor M4 is set as an N-type transistor, then the effective level of the second gating control signal of the second gating control terminal is a high level, and the ineffective level of the second gating control signal of the second gating control terminal is a low level. Alternatively, the fourth transistor M4 is set as a P-type transistor, then the effective level of the second gating control signal of the second gating control terminal is a low level, and the ineffective level of the second gating control signal of the second gating control terminal is a high level.

[0145] See also Figure 7 As shown, the fourth transistor M4 is a P-type transistor. When the second selection control signal of the second selection control terminal is at a low level, the fourth transistor M4 is turned on, and the second data voltage in the data input line is provided to the second data line through the fourth transistor M4.

[0146] In addition, the first data line and the second data line both extend along the first direction.

[0147] It should be noted that the first direction is parallel to the column direction of the sub-pixels. In the embodiment of the present application, the arrangement direction of the first data line and the second data line is the first direction, and the first data line and the second data line extend in the first direction. It should be noted that the first direction is a direction parallel to the column direction of the sub-pixels, and illustratively, the first direction is a vertical direction.

[0148] For the first data line and the second data line electrically connected to a column of sub-pixels, the first data line and the second data line can be respectively distributed on both sides of the above-mentioned column of sub-pixels for wiring, and the above-mentioned first data line and the second data line can also be distributed on the same side of the above-mentioned column of sub-pixels (for example, the left side or the right side of the above-mentioned column of sub-pixels) for wiring. The specific wiring method needs to be flexibly set according to the actual scene, and will not be described here one by one. That is, the setting of the above-mentioned first data line and the second data line is based on the first data line and the second data line, so that wiring can be convenient, the direction of the signal is more convenient, and the wiring space is further saved.

[0149] See also Figure 8 and Fig. 9 As shown, the even-numbered rows of sub-pixels are electrically connected to the first data line, and the odd-numbered rows of sub-pixels are electrically connected to the second data line.

[0150] In order to achieve better display effects when the display panel switches between different display modes, in an embodiment of the present application, the sub-pixels in the even-numbered rows are electrically connected to the first data line, that is, for each column of sub-pixels, all the sub-pixels in the even-numbered rows are electrically connected to the first data line, and the first data line provides the first data voltage to each sub-pixel in the even-numbered rows for normal display.

[0151] Similarly, sub-pixels in odd rows are electrically connected to the second data line, that is, for each column of sub-pixels, all sub-pixels in odd rows are electrically connected to the second data line, and the second data line provides the second data voltage to each sub-pixel in the odd rows for normal display.

[0152] The above-mentioned sub-pixels are arranged in an alternating manner according to even-numbered rows and odd-numbered rows, so that the display picture is arranged more evenly in the display panel and the display effect is better.

[0153] It should be noted that, in the embodiment of the present application, the circuit structure of the pixel driving circuit included in each different sub-pixel is the same, but in the embodiment of the present application, even the data lines connected to the data signal terminals Vdata in different pixel driving circuits corresponding to the same column of sub-pixels are different. For example, the pixel driving circuit 1 in the sub-pixel 1 in the same column is electrically connected to the data line 1, and the pixel driving circuit 2 in the sub-pixel 2 in the same column is electrically connected to the data line 2. In this way, in display mode 1, the data line 1 can provide the pixel driving circuit 1 with the data voltage 1, and in display mode 2, the data line 2 can provide the pixel driving circuit 2 with the data voltage 2.

[0154] The circuit structure of the pixel driving circuit in the embodiment of the present application is introduced below. Fig.10 As shown, the pixel driving circuit includes: a driving transistor DTFT, a conduction control subcircuit 10, a data writing subcircuit 20, a first light-emitting control subcircuit 30, a second light-emitting control subcircuit 40, a first reset subcircuit 50, a second reset subcircuit 60, a first capacitor C1 and a light-emitting device OLED. In the embodiment of the present application, each sub-pixel includes a pixel driving circuit.

[0155] See also Fig.10 and Fig.11 As shown, the first end of the conduction control subcircuit 10 is electrically connected to the control end of the driving transistor DTFT, and the second end of the conduction control subcircuit 10 is electrically connected to the second end of the driving transistor DTFT, and is configured to conduct the control end of the driving transistor DTFT with the second end of the driving transistor DTFT in response to the signal of the conduction control signal terminal GT.

[0156] During implementation, when the signal at the conduction control signal terminal GT is valid, the conduction control subcircuit 10 is turned on, and the control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT.

[0157] See also Fig.11 As shown, the conduction control subcircuit 10 includes: a first switch transistor T1.

[0158] The control end of the first switch transistor T1 is electrically connected to the conduction control signal end GT, the first end of the first switch transistor T1 is electrically connected to the control end of the driving transistor DTFT, and the second end of the first switch transistor T1 is electrically connected to the second end of the driving transistor DTFT.

[0159] Exemplarily, the first switch transistor T1 can be turned on under the control of the effective level of the conduction control signal terminal GT, and can be turned off under the control of the ineffective level of the conduction control signal terminal GT. Exemplarily, the first switch transistor T1 is set as an N-type transistor, then the effective level of the signal of the conduction control signal terminal GT is a high level, and the ineffective level of the signal of the conduction control signal terminal GT is a low level. Alternatively, the first switch transistor T1 is set as a P-type transistor, then the effective level of the signal of the conduction control signal terminal GT is a low level, and the ineffective level of the signal of the conduction control signal terminal GT is a high level.

[0160] See also Fig.11 As shown, the first switch transistor T1 is a P-type transistor. When the signal of the conduction control signal terminal GT is at a low level, the first switch transistor T1 is turned on, and the control terminal of the driving transistor DTFT is turned on through the first switch transistor T1 and the second terminal of the driving transistor DTFT.

[0161] See also Fig.11 As shown, the first end of the data writing sub-circuit 20 is electrically connected to the first end of the driving transistor DTFT, and the second end of the data writing sub-circuit 20 is electrically connected to the data signal terminal Vdata, and is configured to respond to the signal of the scanning signal terminal GT and provide the data voltage of the data signal terminal Vdata to the first end of the driving transistor DTFT.

[0162] During implementation, when the signal at the scanning signal terminal GT is valid, the data writing sub-circuit 20 is turned on, and the data voltage at the data signal terminal Vdata is provided to the first terminal of the driving transistor DTFT via the data writing sub-circuit 20 .

[0163] See also Fig.10 and Fig.11 As shown, the data writing sub-circuit 20 includes: a data writing transistor T0.

[0164] The control end of the data writing transistor T0 is electrically connected to the scanning signal end GT, the first end of the data writing transistor T0 is electrically connected to the first end of the driving transistor DTFT, and the second end of the data writing transistor T0 is electrically connected to the data signal end Vdata.

[0165] Exemplarily, the data writing transistor T0 can be turned on under the control of the effective level of the scanning signal terminal GT, and can be turned off under the control of the ineffective level of the scanning signal terminal GT. Exemplarily, the data writing transistor T0 is set as an N-type transistor, then the effective level of the signal of the scanning signal terminal GT is a high level, and the ineffective level of the signal of the scanning signal terminal GT is a low level. Alternatively, the data writing transistor T0 is set as a P-type transistor, then the effective level of the signal of the scanning signal terminal GT is a low level, and the ineffective level of the signal of the scanning signal terminal GT is a high level.

[0166] See also Fig.11 As shown, the data writing transistor T0 is a P-type transistor. When the signal at the scanning signal terminal GT is at a low level, the data writing transistor T0 is turned on, and the data voltage at the data signal terminal Vdata is provided to the first terminal of the driving transistor DTFT via the data writing transistor T0.

[0167] In the embodiment of the present application, the data signal end Vdata of the even-numbered row data writing transistor T0 is electrically connected to the first data line, and the data signal end Vdata of the odd-numbered row data writing transistor T0 is electrically connected to the second data line.

[0168] During the implementation process, the first data line provides the first data voltage or the reference voltage to the data signal terminal Vdata of the even-numbered row data writing transistor T0, so that the even-numbered row sub-pixels are displayed normally or in a black state. The second data line provides the second data voltage or the reference voltage to the data signal terminal Vdata of the odd-numbered row data writing transistor T0, so that the odd-numbered row sub-pixels are displayed normally or in a black state.

[0169] See also Fig.10 and Fig.11 As shown, a first end of the first light emitting control subcircuit 30 is electrically connected to the first power supply end VDD, and a second end of the first light emitting control subcircuit 30 is electrically connected to a first end of the driving transistor DTFT.

[0170] The first light emitting control sub-circuit 30 is configured to connect the first power supply terminal VDD and the first terminal of the driving transistor DTFT in response to the signal of the light emitting control signal terminal EM.

[0171] During implementation, when the signal of the light emitting control signal terminal EM is valid, the first light emitting control sub-circuit 30 is turned on, and the first power supply terminal VDD is turned on through the first light emitting control sub-circuit 30 and the first terminal of the driving transistor DTFT.

[0172] See also Fig.11 As shown, the first light emitting control subcircuit 30 includes: a second switch transistor T2.

[0173] The control end of the second switch transistor T2 is electrically connected to the light emitting control signal end EM, the first end of the second switch transistor T2 is electrically connected to the first power supply end VDD, and the second end of the second switch transistor T2 is electrically connected to the first end of the driving transistor DTFT.

[0174] Exemplarily, the second switch transistor T2 can be turned on under the control of the effective level of the light emitting control signal terminal EM, and can be turned off under the control of the ineffective level of the light emitting control signal terminal EM. Exemplarily, the second switch transistor T2 is set as an N-type transistor, then the effective level of the signal of the light emitting control signal terminal EM is a high level, and the ineffective level of the signal of the light emitting control signal terminal EM is a low level. Alternatively, the second switch transistor T2 is set as a P-type transistor, then the effective level of the signal of the light emitting control signal terminal EM is a low level, and the ineffective level of the signal of the light emitting control signal terminal EM is a high level.

[0175] See also Fig.11 As shown, the second switch transistor T2 is a P-type transistor. When the signal of the light emitting control signal terminal EM is at a low level, the second switch transistor T2 is turned on, and the first power supply terminal VDD is turned on through the second switch transistor T2 and the first terminal of the driving transistor DTFT.

[0176] See also Fig.10 and Fig.11 As shown, the first end of the second light-emitting control subcircuit 40 is electrically connected to the second end of the driving transistor DTFT, the second end of the second light-emitting control subcircuit 40 is electrically connected to the anode of the light-emitting device OLED, and the second light-emitting control subcircuit 40 is configured to respond to the signal of the light-emitting control signal terminal EM to connect the second end of the driving transistor DTFT to the anode of the light-emitting device OLED.

[0177] During implementation, when the signal at the light emitting control signal terminal EM is valid, the second light emitting control sub-circuit 40 is turned on, and the second end of the driving transistor DTFT is connected to the anode of the light emitting device OLED via the second light emitting control sub-circuit 40 .

[0178] See also Fig.11 As shown, the second light emitting control sub-circuit 40 includes: a third switch transistor T3.

[0179] The control end of the third switch transistor T3 is electrically connected to the light emitting control signal end EM, the first end of the third switch transistor T3 is electrically connected to the second end of the driving transistor DTFT, and the second end of the third switch transistor T3 is electrically connected to the anode of the light emitting device OLED.

[0180] Exemplarily, the third switch transistor T3 can be turned on under the control of the effective level of the light emitting control signal terminal EM, and can be turned off under the control of the ineffective level of the light emitting control signal terminal EM. Exemplarily, the third switch transistor T3 is set as an N-type transistor, then the effective level of the signal of the light emitting control signal terminal EM is a high level, and the ineffective level of the signal of the light emitting control signal terminal EM is a low level. Alternatively, the third switch transistor T3 is set as a P-type transistor, then the effective level of the signal of the light emitting control signal terminal EM is a low level, and the ineffective level of the signal of the light emitting control signal terminal EM is a high level.

[0181] See also Fig.11 As shown, the third switch transistor T3 is a P-type transistor. When the signal of the light emitting control signal terminal EM is at a low level, the third switch transistor T3 is turned on, and the second end of the driving transistor DTFT is connected to the anode of the light emitting device OLED through the third switch transistor T3.

[0182] See also Fig.10 and Fig.11 As shown, the first reset sub-circuit 50 is electrically connected to the control terminal of the driving transistor DTFT.

[0183] The first reset sub-circuit 50 is configured to provide a signal of the first initialization signal terminal Vinit1 to the control terminal of the driving transistor DTFT in response to a signal of the reset control signal terminal Re.

[0184] During implementation, when the signal at the reset control signal terminal Re is valid, the signal at the first initialization signal terminal Vinit1 is provided to the control terminal of the driving transistor DTFT via the first reset sub-circuit 50 , thereby resetting the control terminal of the driving transistor DTFT.

[0185] See also Fig.11 As shown, the first reset sub-circuit 50 includes: a fourth switch transistor T4.

[0186] The control end of the fourth switch transistor T4 is electrically connected to the reset control signal end Re, the first end of the fourth switch transistor T4 is electrically connected to the control end of the driving transistor DTFT, and the second end of the fourth switch transistor T4 is electrically connected to the first initialization signal end Vinit1.

[0187] Exemplarily, the fourth switch transistor T4 can be turned on under the control of the effective level of the reset control signal terminal Re, and can be turned off under the control of the ineffective level of the reset control signal terminal Re. Exemplarily, the fourth switch transistor T4 is set as an N-type transistor, then the effective level of the signal of the reset control signal terminal Re is a high level, and the ineffective level of the signal of the reset control signal terminal Re is a low level. Alternatively, the fourth switch transistor T4 is set as a P-type transistor, then the effective level of the signal of the reset control signal terminal Re is a low level, and the ineffective level of the signal of the reset control signal terminal Re is a high level.

[0188] See also Fig.11 As shown, the fourth switch transistor T4 is a P-type transistor. When the signal at the reset control signal terminal Re is at a low level, the fourth switch transistor T4 is turned on, and the signal at the first initialization signal terminal Vinit1 is provided to the control terminal of the driving transistor DTFT via the fourth switch transistor T4, thereby resetting the control terminal of the driving transistor DTFT.

[0189] See also Fig.11 As shown, the second reset subcircuit 60 is electrically connected to the anode of the light emitting device OLED.

[0190] The second reset sub-circuit 60 is configured to provide a signal of a second initialization signal terminal Vinit2 to the anode of the light emitting device OLED in response to a signal of the reset control signal terminal Re.

[0191] During implementation, when the signal at the reset control signal terminal Re is valid, the signal at the second initialization signal terminal Vinit2 is provided to the anode of the light emitting device OLED via the second reset sub-circuit 60, thereby resetting the anode of the light emitting device OLED.

[0192] See also Fig.11 As shown, the second reset sub-circuit 60 includes: a fifth switch transistor T5.

[0193] The control end of the fifth switch transistor T5 is electrically connected to the reset control signal end Re, the first end of the fifth switch transistor T5 is electrically connected to the anode of the light emitting device OLED, and the second end of the fifth switch transistor T5 is electrically connected to the second initialization signal end Vinit2.

[0194] Exemplarily, the fifth switch transistor T5 can be turned on under the control of the effective level of the reset control signal terminal Re, and can be turned off under the control of the ineffective level of the reset control signal terminal Re. Exemplarily, the fifth switch transistor T5 is set as an N-type transistor, then the effective level of the signal at the reset control signal terminal Re is a high level, and the ineffective level of the signal at the reset control signal terminal Re is a low level. Alternatively, the fifth switch transistor T5 is set as a P-type transistor, then the effective level of the signal at the reset control signal terminal Re is a low level, and the ineffective level of the signal at the reset control signal terminal Re is a high level.

[0195] See also Fig.11 As shown, the fifth switch transistor T5 is a P-type transistor. When the signal at the reset control signal terminal Re is at a low level, the fifth switch transistor T5 is turned on, and the signal at the second initialization signal terminal Vinit2 is provided to the anode of the light-emitting device OLED via the fifth switch transistor T5, thereby resetting the anode of the light-emitting device OLED.

[0196] The first capacitor C1 is used to store the first data voltage or the second data voltage. In some embodiments, the first capacitor C1 is also used to store the threshold voltage of the driving transistor, which is not specifically limited here.

[0197] Here, it is also necessary to add that, although the sub-pixel R, sub-pixel G and sub-pixel B in different display modes include their own pixel driving circuits, each reset control signal terminal Re in the above-mentioned at least two pixel driving circuits can be provided with a signal by the same gate driving circuit, namely, Re GOA, each conduction control signal terminal GT in the above-mentioned at least two pixel driving circuits can also be provided with a signal by the same gate driving circuit, namely, GT GOA, each scanning signal terminal GT in the above-mentioned at least two pixel driving circuits can also be provided with a signal by the same gate driving circuit, namely, GT GOA, and each light-emitting control signal terminal EM in the above-mentioned at least two pixel driving circuits can also be provided with a signal by the same gate driving circuit, namely, EM GOA. The above-mentioned configuration can effectively reduce the number of wirings in the display panel and reduce the number of gate driving circuits used, thereby reducing the space occupied by the gate driving circuit, which is more conducive to the realization of a narrow frame of the display panel.

[0198] It should also be noted that the structure of the pixel driving circuit provided in the embodiment of the present application is only exemplary, that is, the structure of the pixel driving circuit in the embodiment of the present application is not limited to Fig.11 As shown, the present application is also applicable to other pixel driving circuits.

[0199] See also Fig.12 As shown, the light emitting structures of the sub-pixels in the even-numbered rows are different from those of the sub-pixels in the odd-numbered rows.

[0200] In order to enable the display panel to display certain special display modes, such as the anti-peeping mode, in the embodiment of the present application, the light emitting structure of the even-numbered sub-pixels is different from that of the odd-numbered sub-pixels. For example, when the even-numbered sub-pixels are used in the normal display mode, the light emitting structure of the even-numbered sub-pixels is referred to in FIG. Fig.12 As shown in the sub-pixel K in FIG. 1 , that is, no microlens array is added to the light emitting structure of the sub-pixel K; when the odd-numbered rows of sub-pixels are used as the anti-peeping mode, the light emitting structure of the odd-numbered rows of sub-pixels refers to Fig.12 As shown in the sub-pixel L in the figure, a microlens array is added to the light output structure of the sub-pixel L. The microlens array is hemispherical in shape and can focus light and control the light output angle during the display process, thereby achieving the purpose of anti-peeping.

[0201] The following is a description of the working process of the display panel in different display modes in conjunction with a specific timing diagram. It should be noted that, for ease of description, display mode 1 and display mode 2 are used to represent the two display modes of the display panel. In addition, the even-numbered row sub-pixels are electrically connected to the first data line, the odd-numbered row sub-pixels are electrically connected to the second data line, the even-numbered row sub-pixels are not added to the light-emitting structure of the microlens array, and the odd-numbered row sub-pixels are added to the light-emitting structure of the microlens array. The following five situations are specifically included.

[0202] (1) See Fig. 9 , Fig.13 and Fig.14 As shown, the entire display panel displays images in display mode 1.

[0203] When the display panel displays images in the display mode 1 in full screen, the second selection control signal is a constant high level signal, that is, the second selection control signal is an invalid signal, and the third transistor M3 and the fourth transistor M4 are turned off.

[0204] The first selection control signal and the second selection control signal are switched within the duration of Blank. After the switching, the first selection control signal is a constant low-level signal, that is, the first selection control signal is a valid signal, the first transistor M1 and the second transistor M2 are turned on, and the data input line provides the first data voltage to the first data line via the first transistor M1, and the sub-pixel corresponding to the first data line is displayed normally, and all the even-numbered sub-pixels in the entire display panel display the picture; the voltage input line provides the reference voltage to the second data line via the second transistor M2, and the sub-pixel corresponding to the second data line is displayed in a black state, and all the odd-numbered sub-pixels in the entire display panel do not display the picture.

[0205] (2) See Fig. 9 , Fig.15 and Fig.16As shown, the entire display panel displays images in display mode 2.

[0206] When the display panel displays images in the display mode 2 in full screen, the first selection control signal is a constant high level signal, that is, the first selection control signal is an invalid signal, and the first transistor M1 and the second transistor M2 are turned off.

[0207] The first selection control signal and the second selection control signal are switched during the duration of Blank. After the switching, the second selection control signal is a constant low-level signal, that is, the second selection control signal is a valid signal. The third transistor M3 and the fourth transistor M4 are turned on, and the data input line provides the second data voltage to the second data line via the fourth transistor M4. The sub-pixels corresponding to the second data line are displayed normally, and all the odd-numbered sub-pixels in the entire display panel display the picture; the voltage input line provides the reference voltage to the first data line via the third transistor M3, and the sub-pixels corresponding to the first data line are displayed in a black state, and all the even-numbered sub-pixels in the entire display panel do not display the picture.

[0208] (3) See Fig. 9 , Fig.17 and Fig.18 As shown, the first to Kth rows of the display panel display images in display mode 1, and the K+1th to Nth rows display images in display mode 2.

[0209] During the display process of the sub-pixels from the first row to the Kth row, the first selection control signal and the second selection control signal are switched during the duration of Blank. After the switching, the first selection control signal is a low-level signal, that is, the first selection control signal is a valid signal, the first transistor M1 and the second transistor M2 are turned on, the data input line provides the first data voltage to the first data line through the first transistor M1, and the sub-pixels corresponding to the first data line are displayed normally, that is, all the even-numbered sub-pixels in the first row to the Kth row display the picture; the voltage input line provides the reference voltage to the second data line through the second transistor M2, and the sub-pixels corresponding to the second data line are displayed in a black state, and all the odd-numbered sub-pixels in the first row to the Kth row do not display the picture. The second selection control signal is a constant high-level signal, that is, the second selection control signal is an invalid signal, and the third transistor M3 and the fourth transistor M4 are turned off.

[0210] During the display process of the sub-pixels in the K+1th row to the Nth row, the first selection control signal is a high-level signal, that is, the first selection control signal is an invalid signal, and the first transistor M1 and the second transistor M2 are turned off. At the same time, the first selection control signal and the second selection control signal are switched during the duration of Blank, and after the switching, the second selection control signal is a low-level signal, that is, the second selection control signal is a valid signal, the third transistor M3 and the fourth transistor M4 are turned on, and the data input line provides the second data voltage to the second data line through the fourth transistor M4, and the sub-pixels corresponding to the second data line are displayed normally, and all the odd-numbered sub-pixels in the K+1th row to the Nth row display the picture; the voltage input line provides the reference voltage to the first data line through the third transistor M3, and the sub-pixels corresponding to the first data line are displayed in a black state, and all the even-numbered sub-pixels in the K+1th row to the Nth row do not display the picture.

[0211] (4) See Fig. 9 , Fig.19 and Fig. 20 As shown, the first to Kth columns of the display panel display images in display mode 1, and the K+1th to Mth columns display images in display mode 2.

[0212] The first selection control signal and the second selection control signal are switched during the duration of Blank. After the switching, the first selection control signal is a low-level signal and the second selection control signal is a high-level signal during the display process of the sub-pixels from the first column to the Kth column. The first selection control signal is a high-level signal and the second selection control signal is a low-level signal during the display process of the sub-pixels from the K+1th column to the Nth column.

[0213] When the first selection control signal is a low level signal, that is, the first selection control signal is a valid signal, the first transistor M1 and the second transistor M2 are turned on, the data input line provides the first data voltage to the first data line through the first transistor M1, and the sub-pixels of the first column to the Kth column corresponding to the first data line are displayed normally, that is, all the even-numbered sub-pixels in the first column to the Kth column display the picture; the voltage input line provides a reference voltage to the second data line through the second transistor M2, and the sub-pixels of the second data line corresponding to the second data line are displayed in a black state, and all the odd-numbered sub-pixels in the first column to the Kth column do not display the picture. The second selection control signal is a high level signal, that is, the second selection control signal is an invalid signal, and the third transistor M3 and the fourth transistor M4 are turned off.

[0214] During the display process of the sub-pixels in the K+1th column to the Nth column, the first selection control signal is a high-level signal, that is, the first selection control signal is an invalid signal, and the first transistor M1 and the second transistor M2 are turned off. At the same time, the second selection control signal is a low-level signal, that is, the second selection control signal is a valid signal, the third transistor M3 and the fourth transistor M4 are turned on, the data input line provides the second data voltage to the second data line through the fourth transistor M4, the sub-pixels corresponding to the second data line are displayed normally, and all the odd-numbered sub-pixels in the K+1th column to the Nth column display the picture; the voltage input line provides the reference voltage to the first data line through the third transistor M3, the sub-pixels corresponding to the first data line are displayed in a black state, and all the even-numbered sub-pixels in the K+1th column to the Nth column are not displayed.

[0215] (5) See Fig. 9 , Fig.21 and Fig. 22 As shown, the first to Kth columns of the display panel display images in display mode 1; the 1st to Hth rows in the K+1th to K+Lth columns display images in display mode 1, the H+1th to H+Jth rows in the K+1th to K+Lth columns display images in display mode 2, and the H+J+1th to Nth rows in the K+1th to K+Lth columns display images in display mode 1; the K+L+1th to Mth columns display images in display mode 1.

[0216] During the display process of the sub-pixels from the first column to the Kth column, the first selection control signal and the second selection control signal are switched during the duration of Blank. After the switching, the first selection control signal is a low-level signal, that is, the first selection control signal is a valid signal, the first transistor M1 and the second transistor M2 are turned on, the data input line provides the first data voltage to the first data line through the first transistor M1, and the sub-pixels from the first column to the Kth column corresponding to the first data line are displayed normally, that is, all the even-numbered sub-pixels in the first column to the Kth column display the picture; the voltage input line provides the reference voltage to the second data line through the second transistor M2, and the sub-pixels from the second data line corresponding to the connection are displayed in a black state, and all the odd-numbered sub-pixels in the first column to the Kth column do not display the picture. The second selection control signal is a high-level signal, that is, the second selection control signal is an invalid signal, and the third transistor M3 and the fourth transistor M4 are turned off.

[0217] The 1st to Hth rows in the K+1th to K+Lth columns display the picture in display mode 1, the first selection control signal is at a low level, that is, the first selection control signal is a valid signal, the first transistor M1 and the second transistor M2 are turned on, the data input line provides the first data voltage to the first data line via the first transistor M1, and the sub-pixels in the 1st to Hth rows corresponding to the first data line are displayed normally, that is, all the even-numbered sub-pixels in the 1st to Hth rows display the picture; the voltage input line provides the reference voltage to the second data line via the second transistor M2, and the sub-pixels in the 1st to Hth rows corresponding to the second data line are displayed in a black state, that is, all the odd-numbered sub-pixels in the 1st to Hth rows do not display the picture. The second selection control signal is at a high level, that is, the second selection control signal is an invalid signal, and the third transistor M3 and the fourth transistor M4 are turned off.

[0218] The H+1th row to the H+Jth row in the K+1th column to the K+Lth column display the picture in display mode 2. The first selection control signal is at a high level, that is, the first selection control signal is an invalid signal, and the first transistor M1 and the second transistor M2 are turned off. The second selection control signal is at a low level, that is, the third transistor M3 and the fourth transistor M4 are turned on, and the data input line provides the second data voltage to the second data line through the fourth transistor M4, and the sub-pixels corresponding to the second data line are displayed normally, and all the odd-numbered sub-pixels in the H+1th row to the H+Jth row display the picture; the voltage input line provides the reference voltage to the first data line through the third transistor M3, and the sub-pixels corresponding to the first data line are displayed in a black state, and all the even-numbered sub-pixels in the H+1th row to the H+Jth row do not display the picture.

[0219] The H+J+1th row to the Nth row in the K+1th column to the K+Lth column display the picture in display mode 1. The first selection control signal is at a low level, that is, the first selection control signal is a valid signal, the first transistor M1 and the second transistor M2 are turned on, the data input line provides the first data voltage to the first data line through the first transistor M1, and the sub-pixels of the H+J+1th row to the Nth row corresponding to the first data line are displayed normally, that is, all the even-numbered sub-pixels in the H+J+1th row to the Nth row display the picture; the voltage input line provides the reference voltage to the second data line through the second transistor M2, and the sub-pixels of the second data line corresponding to the second data line are displayed in a black state, that is, all the odd-numbered sub-pixels in the H+J+1th row to the Nth row do not display the picture. The second selection control signal is at a high level, that is, the second selection control signal is an invalid signal, and the third transistor M3 and the fourth transistor M4 are turned off.

[0220] During the display process of the sub-pixels in the K+L+1th column to the Mth column, the first selection control signal is a low-level signal, and the second selection control signal is a high-level signal, that is, the first selection control signal is a valid signal, the first transistor M1 and the second transistor M2 are turned on, the data input line provides the first data voltage to the first data line through the first transistor M1, and the sub-pixels in the K+L+1th column to the Mth column corresponding to the first data line are displayed normally, that is, all the even-numbered sub-pixels in the K+L+1th column to the Mth column display the picture; the voltage input line provides the reference voltage to the second data line through the second transistor M2, and the sub-pixels in the second data line corresponding to the second data line are displayed in a black state, and all the odd-numbered sub-pixels in the K+L+1th column to the Mth column do not display the picture. The second selection control signal is a high-level signal, that is, the second selection control signal is an invalid signal, and the third transistor M3 and the fourth transistor M4 are turned off.

[0221] In an embodiment of the present application, the selection control circuit is connected to at least two data lines. During the implementation process, the selection control circuit provides different voltage signals to each data line. Exemplarily, the selection control circuit provides a reference voltage to a part of the data lines and provides a data voltage to another part of the data lines, so that different data lines can present at least two display states at the same time, thereby enabling the entire display panel to present different display modes and switch between different display modes, thereby improving the display flexibility of the display panel.

[0222] Based on the same inventive concept, a display device is provided in an embodiment of the present application, comprising any one of the above-mentioned display panels.

[0223] See also Fig.23 As shown, the above-mentioned display device also includes a source driving circuit.

[0224] The source driving circuit is electrically connected to the other end of the data input line and is configured to provide the first data voltage or the second data voltage to the data input line.

[0225] In the embodiment of the present application, the source driving circuit is mainly used to generate the first data voltage and the second data voltage. The other end of the above-mentioned data input line is electrically connected to the source driving circuit. During the implementation process, when the data input line is electrically connected to the first transistor M1, the source driving circuit provides the first data voltage to the data input line, and then the data input line provides the first data voltage to the first transistor M1, and the first transistor M1 provides the first data voltage to the first data line; when the data input line is electrically connected to the fourth transistor M4, the source driving circuit provides the second data voltage to the data input line, and then the data input line provides the second data voltage to the fourth transistor M4, and the fourth transistor M4 provides the second data voltage to the second data line.

[0226] See also Fig.23 As shown, the display device further includes: a power management circuit (Power Management Integrated Circuit, PMIC), a timing controller (Timing Controller, TCON) and a level shifter (Level Shifter, LS).

[0227] Signal flow 1: PMIC to voltage input line.

[0228] The PMIC is electrically connected to the other end of the voltage input line and is configured to provide a reference voltage to the voltage input line.

[0229] In order to enable the voltage input line to provide a reference voltage to the outside, in an embodiment of the present application, the PMIC is electrically connected to the other end of the voltage input line, so that the PMIC can provide a reference voltage to the voltage input line, and then the voltage input line provides the reference voltage to the data line via the selection control circuit.

[0230] It should be noted that the specific voltage value of the reference voltage is associated with the pixel driving circuit, that is, the specific voltage value of the reference voltage needs to be flexibly set according to the driving transistor DTFT, the first power supply voltage and the second power supply voltage of the pixel driving circuit.

[0231] For example, see Fig.11 In the 7T1C pixel driving circuit shown in FIG. 1 , the voltage of VDD is usually 4.6V, and the voltage of VSS is usually -2.5V. Based on this, Fig.11 The reference voltage provided by the pixel driving circuit shown is greater than 4.6V, and considering the threshold voltage of the driving transistor DTFT, the voltage range of the above reference voltage is usually between 7.5V and 8V. In this way, the driving transistor DTFT is cut off under the action of the above reference voltage, and the corresponding sub-pixel then presents a black display.

[0232] Signal flow 2: PMIC to source driver circuit.

[0233] The PMIC is also electrically connected to the source driving circuit, and is configured to provide a reference voltage to the source driving circuit to drive the source driving circuit to operate.

[0234] In order to ensure that the source driving circuit can work normally, in an embodiment of the present application, when the PMIC is electrically connected to the source driving circuit, the PMIC will also provide the above-mentioned reference voltage to the source driving circuit, that is, the above-mentioned reference voltage is the analog working voltage required by the source driving circuit, and the source driving circuit works under the drive of the above-mentioned reference voltage.

[0235] Signal flow 3: PMIC to TCON to source driver circuit.

[0236] In this case, the source driving circuit can generate the first data voltage and the second data voltage under the action of the PMIC and the TCON.

[0237] First, the PMIC is also electrically connected to the TCON and is configured to provide a driving voltage to the TCON.

[0238] In order to ensure that TCON can work normally, in an embodiment of the present application, when PMIC is electrically connected to TCON, PMIC will also provide a driving voltage to TCON. Usually, the driving voltage is different from the voltage value of the above-mentioned reference voltage, and TCON starts to work under the drive of the above-mentioned driving voltage.

[0239] After TCON starts working, TCON will generate a preselected data voltage and provide the preselected data voltage to the source driving circuit, so that the source driving circuit can further generate a first data voltage and a second data voltage according to the preselected data voltage, and then the source driving circuit will provide the first data voltage to the first data line and the second data voltage to the second data line.

[0240] Signal flow 4: PMIC to TCON to LS to enable control circuit.

[0241] Similarly, the PMIC provides a driving voltage to the TCON. Usually, the driving voltage is different from the voltage value of the reference voltage. The TCON starts to work under the driving of the driving voltage.

[0242] After TCON starts working, TCON will also transform the above-mentioned driving voltage to generate a first selection control signal and a second selection control signal. Usually, the voltage values ​​of the first selection control signal and the second selection control signal generated by TCON are within 0 to 1.8V. TCON will further provide the generated first selection control signal and the second selection control signal within 0 to 1.8V to LS.

[0243] LS is also electrically connected to the enable control circuit via the first enable control line and the second enable control line. In the embodiment of the present application, LS will also perform level conversion on the first enable control signal and the second enable control signal, that is, convert the first enable control signal and the second enable control signal with a voltage value within 0 to 1.8V into the first enable control signal and the second enable control signal with a voltage value between -7V and +7V, and LS provides the converted first enable control signal to the first enable control line, so that the first enable control terminal obtains the first enable control signal, and LS provides the converted second enable control signal to the second enable control line, so that the second enable control terminal obtains the second enable control signal.

[0244] Signal flow 5: PMIC to TCON to LS to gate drive circuit.

[0245] Similarly, the PMIC provides a driving voltage to the TCON. Usually, the driving voltage is different from the voltage value of the reference voltage. The TCON starts to work under the driving of the driving voltage.

[0246] After TCON starts working, TCON can also generate a logic voltage signal according to the driving voltage. Usually, the above logic voltage signal is a logic voltage timing valid signal required for the gate driving circuit to work, but its voltage value within 0 to 1.8V cannot make the gate driving circuit work normally, and LS needs to perform level conversion.

[0247] In the embodiment of the present application, LS is also electrically connected to the gate drive circuit. After receiving the above-mentioned logic voltage signal, LS performs level conversion on the above-mentioned logic voltage signal, and obtains a valid high level signal (i.e., the common VGH) and a valid low level signal (i.e., the common VGL) after voltage conversion. It should be noted that the voltage values ​​of the above-mentioned valid high level signal and the valid low level signal are usually between -7V and +7V. LS provides the converted valid high level signal and the valid low level signal to the gate drive circuit, so that the gate drive circuit generates a scan signal according to the valid high level signal and the valid low level signal. Even if the gate drive circuit generates a scan signal under the action of the valid high level signal and the valid low level signal.

[0248] It should be noted that the above-mentioned voltage range of 0 to 1.8V and the voltage range of -7V to +7V are related to the type of light-emitting device in the pixel driving circuit and the process structure of the display device. In the specific implementation process, the above-mentioned voltage range can be flexibly set according to the actual usage scenario.

[0249] See also Fig.24 As shown, the display device further includes an inverter, an input end of the inverter is electrically connected to TCON, and an output end of the inverter is electrically connected to LS.

[0250] The inverter is configured to invert the first gate control signal generated by TCON to obtain the second gate control signal, or invert the second gate control signal generated by TCON to obtain the first gate control signal.

[0251] Considering that the number of general-purpose input / output pins (GPIO) of TCON is limited, in order to save the use of GPIO, in the embodiment of the present application, an inverter is also electrically connected between LS and TCON.

[0252] In one embodiment, after TCON generates a first selection control signal and outputs it through a GPIO port, the inverter can invert the first selection control signal to obtain a second selection control signal, so that the first selection control signal and the second selection control signal can be obtained by using a GPIO_1 port. Compared with the solution of outputting the first selection control signal through the GPIO_1 port and outputting the second selection control signal through the GPIO_2 port, the number of GPIO ports used is effectively saved.

[0253] Taking into account that the first selection control signal and the second selection control signal are inverted signals, in another embodiment, TCON can also generate the second selection control signal and output it through a GPIO port, and the inverter can invert the above-mentioned second selection control signal to obtain the first selection control signal. In this way, the first selection control signal and the second selection control signal can also be obtained through the use of a GPIO port.

[0254] In the embodiments of the present application, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art and are not described in detail herein, nor should they be used as limitations to the present application.

[0255] Based on the same inventive concept, an embodiment of the present application provides a method for driving a display panel, including:

[0256] The gating control circuit provides reference voltages to a portion of data lines corresponding to each sub-pixel; and

[0257] In the embodiment of the present application, the sub-pixels in the display panel are electrically connected to the data lines accordingly.

[0258] During the implementation process, the selection control circuit responds to the first selection control signal and the second selection control signal to connect a part of the data lines with the voltage input line, that is, to provide the reference voltage in the voltage input line to the above-mentioned part of the data lines, so that the pixel driving circuit of the corresponding part of the sub-pixels is displayed in a black state under the action of the reference voltage.

[0259] The gate control circuit provides data voltages to another part of the data lines corresponding to each sub-pixel.

[0260] During the implementation process, the selection control circuit responds to the first selection control signal and the second selection control signal to connect another part of the data lines with the data input line, that is, to provide the data voltage in the data input line to the above-mentioned other part of the data lines, so that the pixel driving circuit of the corresponding other part of the sub-pixels displays under the action of the data voltage.

[0261] Exemplarily, the sub-pixels in the even-numbered rows are electrically connected to the first data line, and the sub-pixels in the odd-numbered rows are electrically connected to the second data line, and the light emitting structures of the sub-pixels in the even-numbered rows are different from those of the sub-pixels in the odd-numbered rows.

[0262] During the implementation, the first strobe control subcircuit is turned on in response to the first strobe control signal, the first data voltage in the data input line is provided to the first data line, and the even-numbered row subpixels display the picture in display mode 1, and the reference voltage is provided to the second data line, and the odd-numbered row subpixels display the picture in the black state. Since the first strobe control signal and the second strobe control signal are mutually inverted signals, the second strobe control subcircuit is turned off in response to the second strobe control signal.

[0263] Alternatively, the second strobe control subcircuit is turned on in response to the second strobe control signal, and the second data voltage in the data input line is provided to the second data line, and the odd-numbered row subpixels display the picture in display mode 2, and the reference voltage is provided to the first data line, and the even-numbered row subpixels display the picture in the black state. Since the first strobe control signal and the second strobe control signal are mutually inverted signals, the first strobe control subcircuit is turned off in response to the first strobe control signal.

[0264] In summary, in an embodiment of the present application, a display panel, a display device and a driving method are provided, wherein the display panel comprises: a plurality of sub-pixels, a plurality of data lines and a plurality of gate control circuits, wherein a column of sub-pixels corresponds to at least two data lines, and the sub-pixels connected to at least two data lines are different, a column of sub-pixels corresponds to a gate control circuit, and a gate control circuit is connected to at least two data lines, and is configured to provide a reference voltage to a part of the at least two data lines and to provide a data voltage to another part of the data lines. In this way, during the picture display process of the display panel, the reference voltage in some data lines can make part of the picture appear black, and at the same time, the data voltage in another part of the data lines can make another part of the picture display normally, thereby realizing the display of different display modes of the display panel and improving the display flexibility of the display panel.

[0265] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program product systems. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product system implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0266] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0267] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0268] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0269] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: A plurality of sub-pixels, a plurality of data lines and a plurality of gate control circuits; A column of the sub-pixels is correspondingly connected to at least two of the data lines, and the sub-pixels connected to the at least two data lines are different; One column of the sub-pixels corresponds to one of the gate control circuits, and one of the gate control circuits is connected to the at least two data lines and is configured to provide a reference voltage to a portion of the at least two data lines and provide a data voltage to another portion of the data lines.

2. The display panel according to claim 1, wherein: The gating control circuit comprises: a first gating control subcircuit and a second gating control subcircuit; The first gate control subcircuit is configured to provide the first data voltage to the first data line and the reference voltage to the second data line in response to a first gate control signal at the first gate control terminal; or The second gate control subcircuit is configured to provide the reference voltage to the first data line and provide the second data voltage to the second data line in response to a second gate control signal at the second gate control terminal; The first gating control signal and the second gating control signal are inverted signals.

3. The display panel according to claim 2, wherein: Also included: a first gate control line and a second gate control line; The first gate control line is electrically connected to the first gate control terminal and is configured to provide the first gate control signal to the first gate control terminal; The second gate control line is electrically connected to the second gate control terminal, and is configured to provide the second gate control signal to the second gate control terminal.

4. The display panel according to claim 2, wherein: Also includes: Voltage input line and data input line; One end of the voltage input line is electrically connected to the first gating control subcircuit and the second gating control subcircuit, and is configured to provide the reference voltage to the first gating control subcircuit and the second gating control subcircuit; One end of the data input line is electrically connected to the first gate control subcircuit and the second gate control subcircuit, and is configured to provide the first data voltage to the first gate control subcircuit and provide the second data voltage to the second gate control subcircuit.

5. The display panel according to any one of claims 2 to 4, wherein: The first gating control subcircuit includes: a first transistor and a second transistor; The control terminal of the first transistor is electrically connected to the first selection control terminal, the first terminal of the first transistor is electrically connected to the first data line, and the second terminal of the first transistor is electrically connected to the data input line; The control terminal of the second transistor is electrically connected to the first selection control terminal, the first terminal of the second transistor is electrically connected to the second data line, and the second terminal of the second transistor is electrically connected to the voltage input line.

6. The display panel according to any one of claims 2 to 4, wherein: The second gating control subcircuit includes: a third transistor and a fourth transistor; The control terminal of the third transistor is electrically connected to the second gate control signal terminal, the first terminal of the third transistor is electrically connected to the first data line, and the second terminal of the third transistor is electrically connected to the voltage input line; The control terminal of the fourth transistor is electrically connected to the second selection control terminal, the first terminal of the fourth transistor is electrically connected to the second data line, and the second terminal of the fourth transistor is electrically connected to the data input line.

7. The display panel according to any one of claims 2 to 6, wherein: The sub-pixels in even-numbered rows are electrically connected to the first data line, and the sub-pixels in odd-numbered rows are electrically connected to the second data line.

8. The display panel according to any one of claims 2 to 7, wherein: Each of the sub-pixels includes a pixel driving circuit, and the pixel driving circuit includes: a driving transistor, a light-emitting device, a data writing sub-circuit, a first reset sub-circuit and a first capacitor; The driving transistor is electrically connected to the light emitting device; The first end of the data writing sub-circuit is coupled to the first end of the driving transistor, the second end of the data writing sub-circuit is coupled to the data signal end, and is configured to provide a data voltage of the data signal end to the first end of the driving transistor in response to a signal of the scanning signal end; The first reset sub-circuit is coupled to the control terminal of the driving transistor, and the first reset sub-circuit is configured to provide a signal from a first initialization signal terminal to the control terminal of the driving transistor in response to a signal from a reset control signal terminal; The first capacitor is electrically connected to the control terminal and the first power supply terminal of the driving transistor, and is configured to store a first data voltage or a second data voltage.

9. The display panel according to claim 8, wherein: The data writing sub-circuit comprises: a data writing transistor; The data signal terminals of the data writing transistors in the even-numbered rows are electrically connected to the first data line, and the data signal terminals of the data writing transistors in the odd-numbered rows are electrically connected to the second data line.

10. The display panel according to claim 8, wherein: The pixel driving circuit further includes: a conduction control subcircuit, a first light emitting control subcircuit, a second light emitting control subcircuit, and a second reset subcircuit; The first end of the conduction control subcircuit is electrically connected to the control end of the driving transistor, and the second end of the conduction control subcircuit is electrically connected to the second end of the driving transistor, and is configured to conduct the control end of the driving transistor with the second end of the driving transistor in response to a signal at the conduction control signal end; The first terminal of the first light emitting control subcircuit is electrically connected to the first power terminal, the second terminal of the first light emitting control subcircuit is electrically connected to the first terminal of the driving transistor, and the first light emitting control subcircuit is configured to conduct the first power terminal with the first terminal of the driving transistor in response to the signal of the light emitting control signal terminal; The first terminal of the second light emitting control subcircuit is electrically connected to the second terminal of the driving transistor, the second terminal of the second light emitting control subcircuit is electrically connected to the anode of the light emitting device, and is configured to conduct the second terminal of the driving transistor to the anode of the light emitting device in response to the signal of the light emitting control signal terminal; The second reset subcircuit is electrically connected to the anode of the light emitting device, and is configured to provide a signal from a second initialization signal terminal to the anode of the light emitting device in response to a signal from a reset control signal terminal.

11. The display panel according to any one of claims 2 to 10, wherein: The first data line and the second data line both extend along a first direction.

12. The display panel according to any one of claims 2 to 11, wherein: The light emitting structures of the sub-pixels in the even-numbered rows are different from those of the sub-pixels in the odd-numbered rows.

13. A display device, wherein: include: A display panel as claimed in any one of claims 1 to 12.

14. The display device according to claim 13, wherein: Also included is a source driver circuit; The source driving circuit is electrically connected to the other end of the data input line, and is configured to provide a first data voltage or a second data voltage to the data input line.

15. The display device according to claim 14, wherein: Also includes: Power management circuit PMIC, timing controller TCON and level conversion unit LS; The PMIC is electrically connected to the other end of the voltage input line and is configured to provide the reference voltage to the voltage input line; The PMIC is also electrically connected to the source driving circuit, and is configured to provide the reference voltage to the source driving circuit to drive the source driving circuit to work; The PMIC is also electrically connected to the TCON and configured to provide a driving voltage to the TCON; The TCON is electrically connected to the source driving circuit, and is configured to provide the source driving circuit with a preselected data voltage for generating the first data voltage and the second data voltage, generate a first gating control signal and a second gating control signal based on the driving voltage, and generate a logic voltage signal based on the driving voltage; The LS is electrically connected to the TCON, the first gate control line and the second gate control line, and is configured to perform level conversion on the first gate control signal and the second gate control signal, provide the converted first gate control signal to the first gate control line, and provide the converted second gate control signal to the second gate control line; The LS is also electrically connected to the gate driving circuit, and is configured to perform level conversion on the logic voltage signal, and provide the converted valid high level signal and valid low level signal to the gate driving circuit.

16. The display device according to claim 15, wherein: It also includes an inverter, wherein an input end of the inverter is electrically connected to the TCON, and an output end of the inverter is electrically connected to the LS; The inverter is configured to invert the first gate control signal generated by the TCON to obtain the second gate control signal, or to invert the second gate control signal generated by the TCON to obtain the first gate control signal.

17. A driving method for a display panel according to any one of claims 1 to 12, wherein: include: The gating control circuit provides reference voltages to a portion of data lines corresponding to each of the sub-pixels; as well as The gating control circuit provides data voltages to another part of the data lines corresponding to each of the sub-pixels.

Images