Driving circuit, driving module and display device

Abstract

The invention provides a driving circuit, a driving module and a display device. The driving circuit comprises a first control circuit and a second control circuit; the first control circuit is electrically connected with a first control node and a first node and is used for controlling the potential of the first node under the control of the potential of the first control node; the second control circuit is electrically connected with a first node, a second node, a first signal end and a first clock signal end, and is used for writing a first signal provided by the first signal end into the second node under the control of the potential of the first node and a first clock signal provided by the first clock signal end; the first control node is an input end; and / or the first signal end is a second clock signal end. According to the invention, in the output reset stage, the potential of the output reset node is stable, and the driving signal output by the driving circuit is stable.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a driving module and a display device. Background Art

[0002] The existing driving circuit cannot stabilize the potential of the output reset node during the output reset phase, and cannot ensure the stability of the driving signal output by the driving circuit. Summary of the invention

[0003] The main purpose of the present invention is to provide a driving circuit, a driving module and a display device to solve the problem that the existing driving circuit cannot stabilize the potential of the output reset node in the output reset stage and cannot ensure the stability of the driving signal output by the driving circuit.

[0004] In one aspect, an embodiment of the present invention provides a driving circuit, including a first control circuit and a second control circuit;

[0005] The first control circuit is electrically connected to the first control node and the first node respectively, and is used to control the potential of the first node under the control of the potential of the first control node;

[0006] The second control circuit is electrically connected to the first node, the second node, the first signal terminal and the first clock signal terminal respectively, and is used to write the first signal provided by the first signal terminal into the second node under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal;

[0007] The first control node is an input terminal; and / or the first signal terminal is a second clock signal terminal.

[0008] Optionally, the second control circuit is also electrically connected to a third node, and is used to write the first signal to the third node under the control of the potential of the first node, and to control the connection or disconnection between the third node and the second node under the control of the first clock signal.

[0009] Optionally, the driving circuit further includes a second node setting circuit; the second node setting circuit is electrically connected to the second control node, the first voltage terminal and the second node respectively, and is used to write the first voltage signal provided by the first voltage terminal into the second node under the control of the potential of the second control node;

[0010] The second control node is an input terminal or a second node.

[0011] Optionally, the driving circuit described in at least one embodiment of the present invention further includes an input circuit, an on / off control circuit and an output reset circuit;

[0012] The input circuit is electrically connected to the second clock signal terminal, the input terminal and the second node respectively, and is used to write the input signal provided by the input terminal into the second node under the control of the second clock signal provided by the second clock signal terminal;

[0013] The on-off control circuit is electrically connected to the second voltage terminal, the second node and the output reset node respectively, and is used to control the connection or disconnection between the second node and the output reset node under the control of the second voltage signal provided by the second voltage terminal;

[0014] The output reset circuit is electrically connected to the output reset node, the third voltage terminal and the drive signal output terminal respectively, and is used to write the third voltage signal provided by the third voltage terminal into the drive signal output terminal under the control of the potential of the output reset node.

[0015] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a third energy storage circuit, an output node control circuit, a second node control circuit and an output circuit;

[0016] The first end of the third energy storage circuit is electrically connected to the first node, and the second end of the third energy storage circuit is electrically connected to the first clock signal end;

[0017] The output node control circuit is electrically connected to the first node, the fourth node, the first clock signal terminal and the output node respectively, and is used to write the first clock signal provided by the first clock signal terminal into the fourth node under the control of the potential of the first node, and control the connection or disconnection between the fourth node and the output node under the control of the first clock signal;

[0018] The second node control circuit is electrically connected to the second node, the sixth voltage terminal and the output node respectively, and is used to write the sixth voltage signal provided by the sixth voltage terminal into the output node under the control of the potential of the second node;

[0019] The output circuit is electrically connected to the output node, the seventh voltage terminal and the drive signal output terminal respectively, and is used to write the seventh voltage signal provided by the seventh voltage terminal into the drive signal output terminal under the control of the potential of the output node.

[0020] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first node setting circuit, and the first control circuit is further electrically connected to the second clock signal terminal;

[0021] The first control circuit is used to control the connection or disconnection between the first node and the first clock signal terminal under the control of the potential of the first control node;

[0022] The first node setting circuit is electrically connected to the second clock signal terminal, the fourth voltage terminal and the first node respectively, and is used to write the fourth voltage signal provided by the fourth voltage terminal into the first node under the control of the second clock signal provided by the second clock signal terminal.

[0023] Optionally, the first control circuit is further electrically connected to a fifth voltage terminal, and is used to control the connection or disconnection between the first node and the fifth voltage terminal under the control of the potential of the first control node;

[0024] The driving circuit also includes a first node setting circuit, a second energy storage circuit and a sixth control circuit;

[0025] The first node setting circuit is electrically connected to the fifth node, the second clock signal terminal and the first node respectively, and is used to write the second clock signal provided by the second clock signal terminal into the first node under the control of the potential of the fifth node;

[0026] A first terminal of the second energy storage circuit is electrically connected to the second clock signal terminal, and a second terminal of the second energy storage circuit is electrically connected to the fifth node;

[0027] The sixth control circuit is electrically connected to the input terminal, the fifth node and the fifth voltage terminal respectively, and is used to write a fifth voltage signal provided by the fifth voltage terminal into the fifth node under the control of an input signal provided by the input terminal.

[0028] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a carry output circuit, a carry reset circuit and a carry signal output terminal;

[0029] The carry output circuit is electrically connected to the output node, the carry signal output terminal and the eighth voltage terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the eighth voltage terminal under the control of the potential of the output node;

[0030] The carry reset circuit is electrically connected to the output reset node, the carry signal output terminal and the ninth voltage terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the ninth voltage terminal under the control of the potential of the output reset node.

[0031] Optionally, the first control circuit includes a first transistor;

[0032] The gate of the first transistor is electrically connected to the first control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second clock signal terminal;

[0033] The first node setting circuit includes a second transistor;

[0034] A gate of the second transistor is electrically connected to the second clock signal terminal, a first electrode of the second transistor is electrically connected to the fourth voltage terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0035] Optionally, the second node setting circuit includes a third transistor;

[0036] A gate of the third transistor is electrically connected to the second control node, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the second node.

[0037] Optionally, the second control circuit includes a fourth transistor and a fifth transistor;

[0038] The gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first signal terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

[0039] A gate of the fifth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

[0040] Optionally, the input circuit includes a sixth transistor, the on-off control circuit includes a seventh transistor, and the output reset circuit includes an eighth transistor;

[0041] The gate of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the input terminal, and the second electrode of the sixth transistor is electrically connected to the second node;

[0042] The gate of the seventh transistor is electrically connected to the second voltage terminal, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the output reset node;

[0043] A gate of the eighth transistor is electrically connected to the output reset node, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the drive signal output terminal.

[0044] Optionally, the first control circuit includes a first transistor;

[0045] The gate of the first transistor is electrically connected to the first control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fifth voltage terminal;

[0046] The first node setting circuit includes a second transistor, the second energy storage circuit includes a fourth capacitor, and the sixth control circuit includes a twelfth transistor;

[0047] The gate of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the second clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0048] A first end of the fourth capacitor is electrically connected to the second clock signal end, and a second end of the fourth capacitor is electrically connected to the fifth node;

[0049] A gate of the twelfth transistor is electrically connected to the input terminal, a first electrode of the twelfth transistor is electrically connected to the fifth node, and a second electrode of the twelfth transistor is electrically connected to the fifth voltage terminal.

[0050] Optionally, the third energy storage circuit includes a third capacitor, the output node control circuit includes a thirteenth transistor and a fourteenth transistor; the second node control circuit includes a fifteenth transistor, and the output circuit includes a sixteenth transistor;

[0051] The first end of the third capacitor is electrically connected to the first node, and the second end of the third capacitor is electrically connected to the first clock signal end;

[0052] The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the fourth node;

[0053] The gate of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the fourth node, and the second electrode of the fourteenth transistor is electrically connected to the output node;

[0054] The gate of the fifteenth transistor is electrically connected to the second node, the first electrode of the fifteenth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the output node;

[0055] A gate of the sixteenth transistor is electrically connected to the output node, a first electrode of the sixteenth transistor is electrically connected to the seventh voltage terminal, and a second electrode of the sixteenth transistor is electrically connected to the drive signal output terminal.

[0056] In a second aspect, an embodiment of the present invention provides a driving module, comprising multiple levels of the above-mentioned driving circuits.

[0057] In a third aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned driving module.

[0058] The driving circuit, driving module and display device described in the embodiments of the present invention can stabilize the potential of the output reset node during the output reset phase, and stabilize the driving signal output by the driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0060] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0061] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0062] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0063] Figure 5 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0064] Figure 6 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0065] Figure 7 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0066] Figure 8 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0067] Fig.9A is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0068] Fig. 9B is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0069] Fig.10 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0070] Fig.11 yes Fig.10 A simulation operation timing diagram of at least one embodiment of the driving circuit shown;

[0071] Fig.12 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0072] Fig.13 yes Fig.12 A simulation operation timing diagram of at least one embodiment of the driving circuit shown;

[0073] Fig.14A is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0074] Fig. 14B is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0075] Fig.15 yes Fig.14A A simulation operation timing diagram of at least one embodiment of the driving circuit shown;

[0076] Fig.16 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0077] Fig.17 yes Fig.16 A simulation operation timing diagram of at least one embodiment of the driving circuit shown;

[0078] Fig.18A is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0079] Fig.18B is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0080] Fig.19 yes Fig.18A A simulation operation timing diagram of at least one embodiment of the driving circuit shown;

[0081] Fig. 20 yes Fig.18A An operation timing diagram of at least one embodiment of the driving circuit shown;

[0082] Fig.21A is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0083] Fig.21B is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0084] Fig. 21C is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0085] Fig.21D is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0086] Fig.21E is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0087] Fig.21F is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0088] Figure 21Gis a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0089] Fig.21H is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0090] Fig.21I is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0091] Fig. 22 yes Fig.21A A simulation operation timing diagram of at least one embodiment of the driving circuit shown;

[0092] Fig.23 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0093] Fig.24 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0094] Fig.25 yes Fig.24 A simulation operation timing diagram of at least one embodiment of the driving circuit shown;

[0095] Fig.26 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0096] Fig. 27 yes Fig.26 The working timing diagram of at least one embodiment of the driving module shown. DETAILED DESCRIPTION

[0097] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0098] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0099] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0100] The driving circuit described in the embodiment of the present invention includes a first control circuit and a second control circuit;

[0101] The first control circuit is electrically connected to the first control node and the first node respectively, and is used to control the potential of the first node under the control of the potential of the first control node;

[0102] The second control circuit is electrically connected to the first node, the second node, the first signal terminal and the first clock signal terminal respectively, and is used to write the first signal provided by the first signal terminal into the second node under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal;

[0103] The first control node is an input terminal; and / or the first signal terminal is a second clock signal terminal.

[0104] like Figure 1 As shown, the driving circuit according to at least one embodiment of the present invention includes a first control circuit 11 and a second control circuit 12;

[0105] The first control circuit 11 is electrically connected to the input terminal STV and the first node N1 respectively, and is used to control the potential of the first node N1 under the control of the input signal provided by the input terminal STV;

[0106] The second control circuit 12 is electrically connected to the first node N1, the second node N2, the first signal terminal S1 and the first clock signal terminal CB, respectively, and is used to write the first signal provided by the first signal terminal S1 into the second node N2 under the control of the potential of the first node N1 and the first clock signal provided by the first clock signal terminal CB.

[0107] In the present invention Figure 1 In at least one embodiment of the driving circuit shown, the first control node is an input terminal STV, so as to reduce the load of the second node N2 in the output reset stage, stabilize the potential of the output reset node, and stabilize the driving signal output by the driving circuit.

[0108] exist Figure 1 In at least one embodiment shown, the first control node is an input terminal STV;

[0109] The first signal terminal S1 may be a second clock signal terminal or a low voltage terminal.

[0110] like Figure 2 As shown, the driving circuit according to the embodiment of the present invention includes a first control circuit 11 and a second control circuit 12;

[0111] The first control circuit 11 is electrically connected to the first control node NC1 and the first node N1 respectively, and is used to control the potential of the first node N1 under the control of the potential of the first control node NC1;

[0112] The second control circuit 12 is electrically connected to the first node N1, the second node N2, the second clock signal terminal CK and the first clock signal terminal CB, respectively, and is used to write the second clock signal provided by the second clock signal terminal CK into the second node N2 under the control of the potential of the first node N1 and the first clock signal provided by the first clock signal terminal CB.

[0113] exist Figure 2 In at least one embodiment shown, the first signal terminal is a second clock signal terminal CK.

[0114] The present invention Figure 2 When at least one embodiment of the driving circuit shown is in operation, in the output reset stage, when the transistor whose gate is electrically connected to the first node included in the second control circuit is turned on, the high voltage provided by the second clock signal terminal CK can further stabilize the potential of the second node, and then stabilize the potential of the output reset node, so that the driving signal output by the driving circuit is stable.

[0115] exist Figure 2 In at least one embodiment of the driving circuit shown, the first control node may be an input terminal or a second node.

[0116] In at least one embodiment of the present invention, the second control circuit is also electrically connected to a third node, and is used to write the first signal into the third node under the control of the potential of the first node, and to control the connection or disconnection between the third node and the second node under the control of the first clock signal.

[0117] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown,

[0118] The second control circuit 12 is also electrically connected to the third node N3, and is used to write the second clock signal into the third node N3 under the control of the potential of the first node N1, and control the connection or disconnection between the third node N3 and the second node N2 under the control of the first clock signal.

[0119] The present invention Figure 3 When at least one embodiment of the driving circuit shown is in operation, in the output reset stage, when the gate and the transistor of the first node included in the second control circuit are turned on, the second clock signal terminal CK provides a high voltage signal to the third node N3, and the potential of the third node N3 is pulled up to a high potential, which can further stabilize the potential of the second node, and then stabilize the potential of the output reset node, so that the driving signal output by the driving circuit is stable.

[0120] like Figure 4 As shown, the driving circuit according to at least one embodiment of the present invention includes a first control circuit 11 and a second control circuit 12;

[0121] The first control circuit 11 is electrically connected to the first control node NC1 and the first node N1 respectively, and is used to control the potential of the first node N1 under the control of the potential of the first control node NC1;

[0122] The second control circuit 12 is electrically connected to the first node N1, the second node N2, the third node N3, the first signal terminal S1 and the first clock signal terminal CB, respectively, and is used to write the first signal provided by the first signal terminal S1 into the third node N3 under the control of the potential of the first node N1, and control the connection or disconnection between the third node N3 and the second node N2 under the control of the first clock signal provided by the first clock signal terminal CB.

[0123] exist Figure 4 In at least one embodiment of the driving circuit shown, the first control node NC1 is an input terminal, and / or the first signal terminal is a second clock signal terminal.

[0124] In at least one embodiment of the present invention, the driving circuit further includes a second node setting circuit; the second node setting circuit is electrically connected to the second control node, the first voltage terminal and the second node respectively, and is used to write the first voltage signal provided by the first voltage terminal into the second node under the control of the potential of the second control node;

[0125] The second control node is an input terminal or a second node.

[0126] Optionally, the first voltage terminal may be a first high voltage terminal.

[0127] In a specific implementation, the driving circuit may further include a second node setting circuit. In the output reset stage, the second node setting circuit writes the first voltage signal to the second node under the control of the potential of the second control node, and the second control node is the input terminal or the second node; when a high voltage signal is input to the input terminal, or the potential of the second node is a high voltage, the second node setting circuit writes the first voltage signal to the second node, so that the potential of the second node is maintained at a high voltage.

[0128] The driving circuit described in at least one embodiment of the present invention further includes an input circuit, an on / off control circuit and an output reset circuit;

[0129] The input circuit is electrically connected to the second clock signal terminal, the input terminal and the second node respectively, and is used to write the input signal provided by the input terminal into the second node under the control of the second clock signal provided by the second clock signal terminal;

[0130] The on-off control circuit is electrically connected to the second voltage terminal, the second node and the output reset node respectively, and is used to control the connection or disconnection between the second node and the output reset node under the control of the second voltage signal provided by the second voltage terminal;

[0131] The output reset circuit is electrically connected to the output reset node, the third voltage terminal and the drive signal output terminal respectively, and is used to write the third voltage signal provided by the third voltage terminal into the drive signal output terminal under the control of the potential of the output reset node.

[0132] In a specific implementation, the drive circuit may further include an input circuit, an on-off control circuit and an output reset circuit; the input circuit writes the input signal into the second node under the control of a second clock signal; the on-off control circuit controls the on-off between the second node and the output reset node under the control of a second voltage signal; the output reset circuit writes a third voltage signal into the drive signal output end under the control of the potential of the output reset node.

[0133] Optionally, the second voltage terminal may be a second high voltage terminal, and the third voltage terminal may be a third high voltage terminal.

[0134] Optionally, the first voltage value and the second voltage value may be different, but not limited thereto; in a specific implementation, the first voltage value and the second voltage value may be the same.

[0135] Optionally, the second voltage value and the third voltage value may be different, but not limited to this; in a specific implementation, the second voltage value and the third voltage value may be the same.

[0136] In at least one embodiment of the present invention, the first voltage value is the voltage value of the first voltage signal, the second voltage value is the voltage value of the second voltage signal, and the third voltage value is the voltage value of the third voltage signal.

[0137] like Figure 5 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown in the figure, the driving circuit according to at least one embodiment of the present invention further includes an input circuit 51, an on / off control circuit 52 and an output reset circuit 53;

[0138] The input circuit 51 is electrically connected to the second clock signal terminal CK, the input terminal STV and the second node N2 respectively, and is used to write the input signal provided by the input terminal STV into the second node N2 under the control of the second clock signal provided by the second clock signal terminal CK;

[0139] The on-off control circuit 52 is electrically connected to the second voltage terminal V2, the second node N2 and the output reset node NF respectively, and is used to control the connection or disconnection between the second node N2 and the output reset node NF under the control of the second voltage signal provided by the second voltage terminal V2;

[0140] The output reset circuit 53 is electrically connected to the output reset node NF, the third voltage terminal V3 and the drive signal output terminal OT respectively, and is used to write the third voltage signal provided by the third voltage terminal V3 into the drive signal output terminal OT under the control of the potential of the output reset node NF.

[0141] In the present invention Figure 5 In at least one embodiment of the driving circuit shown, the second voltage value may be the same as the third voltage value, or the second voltage value may be different from the third voltage value.

[0142] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a second node setting circuit 61;

[0143] The second node setting circuit 61 is electrically connected to the second control node NC2, the first voltage terminal V1 and the second node N2 respectively, and is used to write the first voltage signal provided by the first voltage terminal V1 into the second node N2 under the control of the potential of the second control node NC2.

[0144] exist Figure 6 In at least one embodiment shown, the second control node may be an input terminal or a second node.

[0145] Optionally, the first voltage terminal may be a first high voltage terminal.

[0146] In a specific implementation, the drive circuit may further include a second node setting circuit 61. In the output reset stage, the second node setting circuit 61 writes the first voltage signal to the second node N2 under the control of the potential of the second control node NC2, and the second control node is the input terminal STV or the second node N2; when the input terminal STV inputs a high voltage signal, or the potential of the second node N2 is a high voltage, the second node setting circuit 61 writes the first voltage signal to the second node N2, so that the potential of the second node N2 is maintained at a high voltage, so that the potential of the output reset node NF is stable, and the drive signal at the output end of the drive circuit is stable without drop (voltage drop).

[0147] In at least one embodiment of the present invention, the first voltage value may be equal to the second voltage value, or the first voltage value may be unequal to the second voltage value;

[0148] The first voltage value is a voltage value of the first voltage signal, and the second voltage value is a voltage value of the second voltage signal.

[0149] The driving circuit according to at least one embodiment of the present invention further includes a first node setting circuit, and the first control circuit is further electrically connected to the second clock signal terminal;

[0150] The first control circuit is used to control the connection or disconnection between the first node and the first clock signal terminal under the control of the potential of the first control node;

[0151] The first node setting circuit is electrically connected to the second clock signal terminal, the fourth voltage terminal and the first node respectively, and is used to write the fourth voltage signal provided by the fourth voltage terminal into the first node under the control of the second clock signal provided by the second clock signal terminal.

[0152] Optionally, the fourth voltage terminal may be a fourth high voltage terminal.

[0153] The driving circuit described in at least one embodiment of the present invention further includes a third energy storage circuit, an output node control circuit, a second node control circuit and an output circuit;

[0154] The first end of the third energy storage circuit is electrically connected to the first node, and the second end of the third energy storage circuit is electrically connected to the first clock signal end;

[0155] The output node control circuit is electrically connected to the first node, the fourth node, the first clock signal terminal and the output node respectively, and is used to write the first clock signal provided by the first clock signal terminal into the fourth node under the control of the potential of the first node, and control the connection or disconnection between the fourth node and the output node under the control of the first clock signal;

[0156] The second node control circuit is electrically connected to the second node, the sixth voltage terminal and the output node respectively, and is used to write the sixth voltage signal provided by the sixth voltage terminal into the output node under the control of the potential of the second node;

[0157] The output circuit is electrically connected to the output node, the seventh voltage terminal and the drive signal output terminal respectively, and is used to write the seventh voltage signal provided by the seventh voltage terminal into the drive signal output terminal under the control of the potential of the output node.

[0158] Optionally, the sixth voltage terminal may be the second low voltage terminal, and the seventh voltage terminal may be the third low voltage terminal.

[0159] Optionally, the sixth voltage value may be equal to the seventh voltage value; or, the sixth voltage value may be unequal to the seventh voltage value;

[0160] The sixth voltage value is the voltage value of the sixth voltage signal, and the seventh voltage value is the voltage value of the seventh voltage signal.

[0161] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown in FIG. 1 , the driving circuit according to at least one embodiment of the present invention further includes a first node setting circuit 71, and the first control circuit 11 is also electrically connected to the second clock signal terminal CK;

[0162] The first control circuit 11 is used to control the connection or disconnection between the first node N1 and the first clock signal terminal CK under the control of the potential of the first control node NC1;

[0163] The first node setting circuit 71 is electrically connected to the second clock signal terminal CK, the fourth voltage terminal V4 and the first node N1 respectively, and is used to write the fourth voltage signal provided by the fourth voltage terminal V4 into the first node N1 under the control of the second clock signal provided by the second clock signal terminal CK;

[0164] The driving circuit according to at least one embodiment of the present invention further includes a third energy storage circuit 72, an output node control circuit 73, a second node control circuit 74 and an output circuit 75;

[0165] The first end of the third energy storage circuit 72 is electrically connected to the first node N1, and the second end of the third energy storage circuit 72 is electrically connected to the first clock signal terminal CB;

[0166] The output node control circuit 73 is electrically connected to the first node N1, the fourth node N4, the first clock signal terminal CB and the output node NS respectively, and is used to write the first clock signal provided by the first clock signal terminal CB into the fourth node N4 under the control of the potential of the first node N1, and control the connection or disconnection between the fourth node N4 and the output node NS under the control of the first clock signal;

[0167] The second node control circuit 74 is electrically connected to the second node N2, the sixth voltage terminal V6 and the output node NS respectively, and is used to write the sixth voltage signal provided by the sixth voltage terminal V6 into the output node NS under the control of the potential of the second node N2;

[0168] The output circuit 75 is electrically connected to the output node NS, the seventh voltage terminal V7 and the drive signal output terminal OT respectively, and is used to write the seventh voltage signal provided by the seventh voltage terminal V7 into the drive signal output terminal OT under the control of the potential of the output node NS.

[0169] like Figure 8 As shown, in Figure 6 Based on at least one embodiment of the driving circuit shown in FIG. 1 , the driving circuit according to at least one embodiment of the present invention further includes a first node setting circuit 71, and the first control circuit is also electrically connected to the second clock signal terminal CK;

[0170] The first control circuit 11 is used to control the connection or disconnection between the first node N1 and the first clock signal terminal CK under the control of the potential of the first control node NC1;

[0171] The first node setting circuit 71 is electrically connected to the second clock signal terminal CK, the fourth voltage terminal V4 and the first node N1 respectively, and is used to write the fourth voltage signal provided by the fourth voltage terminal V4 into the first node N1 under the control of the second clock signal provided by the second clock signal terminal CK;

[0172] The driving circuit according to at least one embodiment of the present invention further includes a third energy storage circuit 72, an output node control circuit 73, a second node control circuit 74 and an output circuit 75;

[0173] The first end of the third energy storage circuit 72 is electrically connected to the first node N1, and the second end of the third energy storage circuit 72 is electrically connected to the first clock signal terminal CB;

[0174] The output node control circuit 73 is electrically connected to the first node N1, the fourth node N4, the first clock signal terminal CB and the output node NS respectively, and is used to write the first clock signal provided by the first clock signal terminal CB into the fourth node N4 under the control of the potential of the first node N1, and control the connection or disconnection between the fourth node N4 and the output node NS under the control of the first clock signal;

[0175] The second node control circuit 74 is electrically connected to the second node N2, the sixth voltage terminal V6 and the output node NS respectively, and is used to write the sixth voltage signal provided by the sixth voltage terminal V6 into the output node NS under the control of the potential of the second node N2;

[0176] The output circuit 75 is electrically connected to the output node NS, the seventh voltage terminal V7 and the drive signal output terminal OT respectively, and is used to write the seventh voltage signal provided by the seventh voltage terminal V7 into the drive signal output terminal OT under the control of the potential of the output node NS.

[0177] In at least one embodiment of the present invention, the first control circuit is further electrically connected to the fifth voltage terminal, and is used to control the connection or disconnection between the first node and the fifth voltage terminal under the control of the potential of the first control node;

[0178] The driving circuit also includes a first node setting circuit, a second energy storage circuit and a sixth control circuit;

[0179] The first node setting circuit is electrically connected to the fifth node, the second clock signal terminal and the first node respectively, and is used to write the second clock signal provided by the second clock signal terminal into the first node under the control of the potential of the fifth node;

[0180] A first terminal of the second energy storage circuit is electrically connected to the second clock signal terminal, and a second terminal of the second energy storage circuit is electrically connected to the fifth node;

[0181] The sixth control circuit is electrically connected to the input terminal, the fifth node and the fifth voltage terminal respectively, and is used to write a fifth voltage signal provided by the fifth voltage terminal into the fifth node under the control of an input signal provided by the input terminal.

[0182] Optionally, the fifth voltage terminal may be the first low voltage terminal.

[0183] In a specific implementation, the driving circuit may also include a first node setting circuit, a second energy storage circuit and a sixth control circuit; the first node setting circuit writes a second clock signal into the first node under the control of the potential of the fifth node; the second energy storage circuit controls the potential of the fifth node according to the second clock signal; the sixth control circuit writes a fifth voltage signal into the fifth node under the control of the input signal.

[0184] like Fig.9A As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the first control circuit 11 is further electrically connected to the fifth voltage terminal V5, and is used to control the connection or disconnection between the first node N1 and the fifth voltage terminal V5 under the control of the potential of the first control node NC1;

[0185] The driving circuit further includes a first node setting circuit 71, a second energy storage circuit 91 and a sixth control circuit 92;

[0186] The first node setting circuit 71 is electrically connected to the fifth node N5, the second clock signal terminal CK and the first node N1 respectively, and is used to write the second clock signal provided by the second clock signal terminal CK into the first node N1 under the control of the potential of the fifth node N5;

[0187] A first end of the second energy storage circuit 91 is electrically connected to the second clock signal terminal CK, and a second end of the second energy storage circuit 91 is electrically connected to the fifth node N5;

[0188] The sixth control circuit 92 is electrically connected to the input terminal STV, the fifth node N5 and the fifth voltage terminal V5, respectively, and is used to write the fifth voltage signal provided by the fifth voltage terminal V5 into the fifth node N5 under the control of the input signal provided by the input terminal STV.

[0189] The driving circuit described in at least one embodiment of the present invention further includes a carry output circuit, a carry reset circuit and a carry signal output terminal;

[0190] The carry output circuit is electrically connected to the output node, the carry signal output terminal and the eighth voltage terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the eighth voltage terminal under the control of the potential of the output node.

[0191] The carry reset circuit is electrically connected to the output reset node, the carry signal output terminal and the ninth voltage terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the ninth voltage terminal under the control of the potential of the output reset node.

[0192] Optionally, the eighth voltage terminal may be a low voltage terminal, and the ninth voltage terminal may be a high voltage terminal.

[0193] In each embodiment of the present invention, a carry output circuit, a carry reset circuit and a carry signal output terminal may be provided. The embodiments provided by the present invention are only for illustration and do not limit the protection scope of the present invention.

[0194] Fig. 9B At least one embodiment of the driving circuit shown is Fig.9A The differences of at least one embodiment of the driving circuit shown are as follows:

[0195] It also includes a carry output circuit 901, a carry reset circuit 902 and a carry signal output terminal CY;

[0196] The carry output circuit 901 is electrically connected to the output node NS, the carry signal output terminal CY and the eighth voltage terminal V8 respectively, and is used to control the connection or disconnection between the carry signal output terminal CY and the eighth voltage terminal V8 under the control of the potential of the output node NS;

[0197] The carry reset circuit 902 is electrically connected to the output reset node NF, the carry signal output terminal CY and the ninth voltage terminal V9 respectively, and is used to control the connection or disconnection between the carry signal output terminal CY and the ninth voltage terminal V9 under the control of the potential of the output reset node NF.

[0198] In at least one embodiment of the present invention, the driving circuit may further include a carry output circuit, a carry reset circuit and a carry signal output terminal, and the carry signal output by the carry signal output terminal is cascaded, and the driving signal provided by the driving signal output terminal is used to drive the corresponding row pixel circuit to reduce the load of the driving signal output terminal.

[0199] Optionally, the first control circuit includes a first transistor;

[0200] The gate of the first transistor is electrically connected to the first control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second clock signal terminal;

[0201] The first node setting circuit includes a second transistor;

[0202] A gate of the second transistor is electrically connected to the second clock signal terminal, a first electrode of the second transistor is electrically connected to the fourth voltage terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0203] Optionally, the second node setting circuit includes a third transistor;

[0204] A gate of the third transistor is electrically connected to the second control node, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the second node.

[0205] Optionally, the second control circuit includes a fourth transistor and a fifth transistor;

[0206] The gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first signal terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

[0207] A gate of the fifth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

[0208] Optionally, the input circuit includes a sixth transistor, the on-off control circuit includes a seventh transistor, and the output reset circuit includes an eighth transistor;

[0209] The gate of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the input terminal, and the second electrode of the sixth transistor is electrically connected to the second node;

[0210] The gate of the seventh transistor is electrically connected to the second voltage terminal, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the output reset node;

[0211] A gate of the eighth transistor is electrically connected to the output reset node, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the drive signal output terminal.

[0212] Optionally, the first control circuit includes a first transistor;

[0213] The gate of the first transistor is electrically connected to the first control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fifth voltage terminal;

[0214] The first node setting circuit includes a second transistor, the second energy storage circuit includes a fourth capacitor, and the sixth control circuit includes a twelfth transistor;

[0215] The gate of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the second clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0216] A first end of the fourth capacitor is electrically connected to the second clock signal end, and a second end of the fourth capacitor is electrically connected to the fifth node;

[0217] A gate of the twelfth transistor is electrically connected to the input terminal, a first electrode of the twelfth transistor is electrically connected to the fifth node, and a second electrode of the twelfth transistor is electrically connected to the fifth voltage terminal.

[0218] Optionally, the third energy storage circuit includes a third capacitor, the output node control circuit includes a thirteenth transistor and a fourteenth transistor; the second node control circuit includes a fifteenth transistor, and the output circuit includes a sixteenth transistor;

[0219] The first end of the third capacitor is electrically connected to the first node, and the second end of the third capacitor is electrically connected to the first clock signal end;

[0220] The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the fourth node;

[0221] The gate of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the fourth node, and the second electrode of the fourteenth transistor is electrically connected to the output node;

[0222] The gate of the fifteenth transistor is electrically connected to the second node, the first electrode of the fifteenth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the output node;

[0223] A gate of the sixteenth transistor is electrically connected to the output node, a first electrode of the sixteenth transistor is electrically connected to the seventh voltage terminal, and a second electrode of the sixteenth transistor is electrically connected to the drive signal output terminal.

[0224] like Fig.10 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, the first control circuit includes a first transistor T1;

[0225] The gate of the first transistor T1 is electrically connected to the input terminal STV, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the second clock signal terminal CK;

[0226] The first node setting circuit includes a second transistor T2;

[0227] The gate of the second transistor T2 is electrically connected to the second clock signal terminal CK, the source of the second transistor T2 is electrically connected to the high voltage terminal VGH, and the drain of the second transistor T2 is electrically connected to the first node N1;

[0228] The second control circuit includes a fourth transistor T4 and a fifth transistor T5;

[0229] The gate of the fourth transistor T4 is electrically connected to the first node N1, the source of the fourth transistor T4 is electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor T4 is electrically connected to the source of the fifth transistor T5;

[0230] The gate of the fifth transistor T5 is electrically connected to the first clock signal terminal CB, and the drain of the fifth transistor T5 is electrically connected to the second node N2;

[0231] The input circuit includes a sixth transistor T6, the on-off control circuit includes a seventh transistor T7, and the output reset circuit includes an eighth transistor T8;

[0232] The gate of the sixth transistor T6 is electrically connected to the second clock signal terminal CK, the source of the sixth transistor T6 is electrically connected to the input terminal STV, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0233] The gate of the seventh transistor T7 is electrically connected to the high voltage terminal VGH, the source of the seventh transistor T7 is electrically connected to the second node N2, and the second electrode of the seventh transistor is electrically connected to the output reset node NF;

[0234] The gate of the eighth transistor T8 is electrically connected to the output reset node NF, the source of the eighth transistor T8 is electrically connected to the high voltage terminal VGH, and the drain of the eighth transistor T8 is electrically connected to the drive signal output terminal OT;

[0235] The third energy storage circuit includes a third capacitor C3, the output node control circuit includes a thirteenth transistor T13 and a fourteenth transistor T14; the second node control circuit includes a fifteenth transistor T15, and the output circuit includes a sixteenth transistor T16;

[0236] A first end of the third capacitor C3 is electrically connected to the first node N1, and a second end of the third capacitor C3 is electrically connected to the first clock signal terminal CB;

[0237] The gate of the thirteenth transistor T13 is electrically connected to the first node N1, the source of the thirteenth transistor T13 is electrically connected to the first clock signal terminal CB, and the drain of the thirteenth transistor T13 is electrically connected to the fourth node N4;

[0238] The gate of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CB, the source of the fourteenth transistor T14 is electrically connected to the fourth node N4, and the drain of the fourteenth transistor T14 is electrically connected to the output node NS;

[0239] The gate of the fifteenth transistor T15 is electrically connected to the second node N2, the source of the fifteenth transistor T15 is electrically connected to the low voltage terminal VGL, and the drain of the fifteenth transistor T15 is electrically connected to the output node NS;

[0240] The gate of the sixteenth transistor T16 is electrically connected to the output node NS, the source of the sixteenth transistor T16 is electrically connected to the low voltage terminal VGL, and the drain of the sixteenth transistor T16 is electrically connected to the driving signal output terminal OT;

[0241] The driving circuit according to at least one embodiment of the present invention may further include a first capacitor C1 and a second capacitor C2;

[0242] A first end of C2 is electrically connected to the output node NS, and a second end of C2 is electrically connected to the low voltage terminal VGL;

[0243] A first end of C1 is electrically connected to the output reset node NF, and a second end of C1 is electrically connected to the driving signal output terminal OT.

[0244] exist Fig.10 In at least one embodiment shown, all transistors are n-type transistors, but the present invention is not limited thereto. In a specific implementation, the transistors may be replaced by p-type transistors.

[0245] exist Fig.10 In at least one embodiment shown, the second voltage terminal is a high voltage terminal VGH, the third voltage terminal is a high voltage terminal VGH, the fourth voltage terminal is a high voltage terminal VGH, the sixth voltage terminal is a low voltage terminal VGL, and the seventh voltage terminal is a low voltage terminal VGL.

[0246] In the present invention Fig.10 In at least one embodiment of the driving circuit shown, the gate of T1 is electrically connected to the input terminal STV, and in the output reset stage, the load of the second node N2 can be reduced to maintain the potential of the second node N2 stable. When T7 is turned on, the potential of the output reset node NF can be stabilized, and the driving signal output by the driving circuit is stable without drop (voltage drop).

[0247] Fig.11 The present invention Fig.10 The simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. Fig.11As shown, the potential of the output reset node NF is stable, and the driving signal output by the driving circuit is stable.

[0248] Fig.12 At least one embodiment of the driving circuit shown is Fig.10 The differences of at least one embodiment of the driving circuit shown are as follows:

[0249] The gate of T1 is electrically connected to the second node N2, and the source of T4 is electrically connected to the second clock signal terminal CK.

[0250] exist Fig.12 In at least one embodiment of the driving circuit shown, the source of T4 is electrically connected to the second clock signal terminal CK, so that in the output reset stage, when T8 needs to be turned on to control OT to output a high voltage signal, when T4 is turned on, the potential of the third node N3 is a high voltage, which is conducive to maintaining the potential of the second node N2 stable. When T7 is turned on, the potential of the output reset node NF can be stabilized, and the driving signal output by the driving circuit is stable without drop (voltage drop).

[0251] Fig.13 The present invention Fig.12 The simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. Fig.13 As shown, the potential of the output reset node NF is stable, and the driving signal output by the driving circuit is stable.

[0252] Fig.14A At least one embodiment of the driving circuit shown is Fig.10 The difference of at least one embodiment of the driving circuit shown is as follows: it also includes a second node setting circuit; the second node setting circuit includes a third transistor T3;

[0253] A gate of the third transistor T3 is electrically connected to the input terminal STV, a source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and a drain of the third transistor T3 is electrically connected to the second node N2.

[0254] exist Fig.14A In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto. In a specific implementation, the transistors may be replaced by p-type transistors.

[0255] exist Fig.14A In at least one embodiment shown, the first voltage terminal may be a high voltage terminal VGH.

[0256] exist Fig.14AIn at least one embodiment of the driving circuit shown, a third transistor T3 is added. When the input terminal STV provides a high voltage signal, T3 is turned on and a high voltage is written to the second node N2, so that the potential of the second node N2 is maintained at a high level, and the potential of the output reset node NF is further stabilized. The driving signal output by the driving circuit is stable without drops.

[0257] Fig.15 The present invention Fig.14A The simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. Fig.15 As shown, the potential of the output reset node NF is stable, and the driving signal output by the driving circuit is stable.

[0258] Fig. 14B At least one embodiment of the driving circuit shown is Fig.14A The difference of at least one embodiment of the driving circuit shown is as follows: it also includes a second node setting circuit; the second node setting circuit includes a third transistor T3;

[0259] A gate of the third transistor T3 is electrically connected to the second node N2 , a source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and a drain of the third transistor T3 is electrically connected to the second node N2 .

[0260] exist Fig. 14B In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto. In a specific implementation, the transistors may be replaced by p-type transistors.

[0261] exist Fig. 14B In at least one embodiment of the driving circuit shown, a third transistor T3 is added. When the potential of the second node N2 is a high voltage signal, T3 is turned on and a high voltage is written to the second node N2, so that the potential of the second node N2 is maintained at a high level, and the potential of the output reset node NF is further stabilized. The driving signal output by the driving circuit is stable without drops.

[0262] Fig.16 At least one embodiment of the driving circuit shown is Fig.14A The difference of at least one embodiment of the driving circuit shown is as follows: the gate of T1 is electrically connected to the second node N2, and the source of T4 is electrically connected to the second clock signal terminal CK.

[0263] exist Fig.16In at least one embodiment of the driving circuit shown, the source of T4 is electrically connected to the second clock signal terminal CK, so that in the output reset stage, when T8 needs to be turned on to control OT to output a high voltage signal, when T4 is turned on, the potential of the third node N3 is a high voltage, and when T5 is turned on, the high potential of the third node N3 is written to the second node N2, which can stabilize the potential of the second node, and when T7 is turned on, the potential of the output reset node NF can be stabilized, and the driving signal output by the driving circuit is stable without drop (voltage drop).

[0264] Fig.17 The present invention Fig.16 The simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. Fig.17 As shown, the potential of the output reset node NF is stable, and the driving signal output by the driving circuit is stable.

[0265] Fig.18A At least one embodiment of the driving circuit shown is Fig.16 The difference of at least one embodiment of the driving circuit shown is as follows: the gate of T1 is electrically connected to the input terminal STV.

[0266] In the present invention Fig.18A In at least one embodiment of the driving circuit shown, the gate of T1 is electrically connected to the input terminal STV, and in the output reset stage, the load of the second node N2 can be reduced to maintain the potential of the second node N2 stable. When T7 is turned on, the potential of the output reset node NF can be stabilized, and the driving signal output by the driving circuit is stable without drop (voltage drop).

[0267] The present invention Fig.18B At least one embodiment of the driving circuit shown in the figure is consistent with the present invention Fig.18A At least one embodiment of the driving circuit shown is different in that T3 is not included.

[0268] exist Fig.18B In at least one embodiment of the driving circuit shown, the gate of T1 is electrically connected to the input terminal STV, and in the output reset stage, the load of the second node N2 can be reduced to maintain the potential of the second node N2 stable. When T7 is turned on, the potential of the output reset node NF can be stabilized, and the driving signal output by the driving circuit is stable.

[0269] The source of T4 is electrically connected to the second clock signal terminal CK, so that in the output reset stage, when T8 needs to be turned on to control OT to output a high voltage signal, when T4 is turned on, the potential of the third node N3 is a high voltage, which is conducive to maintaining the potential stability of the second node N2. When T7 is turned on, the potential of the output reset node NF can be stabilized, and the drive signal output by the drive circuit is stable.

[0270] Fig.19 The present invention Fig.18A The simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. Fig.19 As shown, the potential of the output reset node NF is stable, and the driving signal output by the driving circuit is stable.

[0271] like Fig. 20 As shown, Fig.18A At least one embodiment of the driving circuit shown in the figure is in operation.

[0272] In the first stage t1, STV provides a low voltage signal, CB provides a low voltage signal, CK provides a high voltage signal, T2 is turned on, the first node N1 is connected to VGH, and the potential of the first node N1 is a high voltage, T6 is turned on, the second node N2 is connected to STV, and the potential of the second node N2 is a low voltage, T7 is turned on, the potential of the output reset node NF is a low voltage, and T8 is turned off; T4 is turned on, the third node N3 is connected to CK, and the potential of the third node N3 is a high voltage, T5 is turned off, T3 is turned off, T13 is turned on, the fourth node N4 is connected to CB, and the potential of the fourth node N4 is a low voltage, T14 is turned off, T15 is turned off, the potential of the output node NS maintains the state of the previous stage, and the driving signal output by OT also maintains the state of the previous stage, and OT continues to output a high voltage signal;

[0273] In the second stage t2, STV provides a low voltage signal, CB provides a high voltage signal, CK provides a low voltage signal, T6 and T2 are closed, T1 is closed, CB further pulls up the potential of the first node N1 through the bootstrap effect of C3, the potential of the first node N1 is high voltage, T4 is opened, the third node N3 is connected to CK, the potential of the third node N3 is low voltage, T5 is opened, the second node N2 is connected to the third node N3, the potential of the second node N2 is low voltage, T3 and T15 are closed, T7 is opened, the second node N2 is connected to the output reset node NF, the potential of the output reset node NF is low voltage, T8 is continuously closed, because the potential of the first node N1 becomes high, T13 is opened, the fourth node N4 is connected to CB, the potential of the fourth node N4 is high voltage, T14 is opened, the fourth node N4 is connected to the output node NS, the potential of the output node NS is high voltage, T16 is opened, and OT outputs a low voltage signal;

[0274] In the third stage t3, STV provides a low voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, T2 and T6 are turned on, T1 is turned off, the first node N1 is connected to VGH, the potential of the first node N1 is high voltage, the second node N2 is connected to STV, and the potential of the second node N2 is low voltage; T4 and T13 are turned on, the third node N3 is connected to CK, the fourth node N4 is connected to CB, the potential of the third node N3 is high voltage, the potential of the fourth node N4 is low voltage, T3, T5, T14 and T15 are turned off, T7 is turned on, the second node N2 is connected to the output reset node NF, the potential of the output reset node NF is low voltage, the potential of the output node NS maintains the state of the previous stage, the potential of the output node NS is high voltage, T16 is continuously turned on, T8 is turned off, and OT outputs a low voltage signal;

[0275] In the fourth stage t4, STV provides a low voltage signal, CB provides a high voltage signal, CK provides a low voltage signal, T1, T2, T3 and T6 are closed, CB further pulls up the potential of the first node N1 through the bootstrap effect of C3, the potential of the first node N1 is a high voltage, T4 is continuously opened, the third node N3 is connected to CK, T5 is opened, the third node N3 is connected to the second node N2, the potential of the second node N2 is a low voltage, T7 is opened, the potential of the output reset node NF is a low voltage, and T8 is continuously closed; due to the high potential of the first node N1, T13 is opened, the fourth node N4 is connected to CB, the potential of the fourth node N4 is a high voltage, T14 is opened, the fourth node N4 is connected to the output node NS, the potential of the output node NS is a high voltage, T16 is opened, and OT outputs a low voltage signal;

[0276] After that, the states of the third and second stages are repeated until the fifth stage t5;

[0277] In the fifth stage t5, STV provides a high voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, T1 and T2 are turned on, the first node N1 is connected to VGH, the first node N1 is connected to CK, and the potential of the first node N1 is high voltage, T4 and T13 are turned on, the third node N3 is connected to CK, and the potential of the third node N3 is high voltage; T5 is turned off; T14 is turned off; T3 and T6 are turned on, the second node N2 is connected to STV, the second node N2 is connected to VGH, and the potential of the second node N2 is high voltage; T15 is turned on, the output node NS is connected to VGL, and the potential of the output node NS is low voltage, T16 is turned off; T7 is turned on, the second node N2 is connected to the output reset node NF, and the potential of the output reset node NF is high voltage, T8 is turned on, and OT outputs a high voltage signal;

[0278] In the sixth stage t6, STV provides a high voltage signal, CB provides a high voltage signal, CK provides a low voltage signal, T6 and T2 are closed, T1 and T3 are opened, the first node N1 is connected to CK, and the potential of the first node N1 is low voltage, T4 and T13 are closed, the second node N2 is connected to VGH, and the potential of the second node N2 is high voltage; T5 is opened, the second node N2 is connected to the third node N3, and the high level of the third node N3 is written into the second node N2, T3 is opened, and the potential of the second node N2 is further increased, T7 is closed, and the potential of the output reset node NF is maintained at the high voltage of the previous stage, T8 is continuously opened, and OT outputs a high voltage signal; T14 and T15 are opened, the fourth node N4 is connected to the output node NS, the output node NS is connected to VGL, the potential of the fourth node N4 and the potential of the output node NS are low voltage, and T16 is closed;

[0279] In the seventh stage t7, STV provides a high voltage signal, CB provides a low voltage signal, CK provides a high voltage signal, T1, T2, T3 and T6 are all turned on, the first node N1 is connected to VGH, the first node N1 is connected to CK, and the potential of the first node N1 is a high voltage, T4 and T13 are turned on, the third node N3 is connected to CK, and the potential of the third node N3 is a high voltage, the second node N2 is connected to STV, the second node N2 is connected to VGH, and the potential of the second node N2 is a high voltage, T15 is turned on, the output node NS is connected to VGL, and the potential of the output node NS is a low voltage, T16 is turned off; T7 is turned on, the potential of the output reset node NF is maintained at the high voltage of the previous stage, T8 is turned on, and OT outputs a high voltage signal;

[0280] Subsequently, the states of the sixth stage t6 and the seventh stage t7 are repeated, and OT outputs a high voltage signal.

[0281] exist Fig.18A In at least one embodiment of the driving circuit shown, the voltage value of the high voltage signal connected to the source of T3 is equal to the voltage value of the high voltage signal connected to the gate of T7;

[0282] In at least one embodiment of the present invention, the voltage value of the high voltage signal connected to the source of T3 may be equal to the voltage value of the high voltage signal connected to the gate of T7, or the voltage value of the high voltage signal connected to the source of T3 may be unequal to the voltage value of the high voltage signal connected to the gate of T7;

[0283] exist Fig.18A In at least one embodiment of the driving circuit shown, the voltage value of the high voltage signal connected to the gate of T7 is equal to the voltage value of the high voltage signal connected to the drain of T8;

[0284] In at least one embodiment of the present invention, the voltage value of the high voltage signal connected to the gate of T7 may be equal to the voltage value of the high voltage signal connected to the drain of T8, or the voltage value of the high voltage signal connected to the gate of T7 may be unequal to the voltage value of the high voltage signal connected to the drain of T8.

[0285] exist Fig.18A In at least one embodiment of the driving circuit shown, the voltage value of the low voltage signal connected to the drain of T15 is equal to the voltage value of the low voltage signal connected to the source of T16.

[0286] In at least one embodiment of the present invention, the voltage value of the low voltage signal connected to the drain of T15 may be equal to the voltage value of the low voltage signal connected to the source of T16, or the voltage value of the low voltage signal connected to the drain of T15 may be unequal to the voltage value of the low voltage signal connected to the source of T16.

[0287] Fig.21A At least one embodiment of the driving circuit shown is Fig.18A The difference of at least one embodiment of the driving circuit shown is as follows: the driving circuit does not include T3; the source of T2 is electrically connected to the second clock signal terminal CK; the drain of T1 is electrically connected to the low voltage terminal VGL; the source of T4 is electrically connected to the low voltage terminal VGL;

[0288] The driving circuit also includes a second energy storage circuit and a sixth control circuit;

[0289] The second energy storage circuit includes a fourth capacitor C4, and the sixth control circuit includes a twelfth transistor T12;

[0290] A first end of C4 is electrically connected to the second clock signal end CK, and a second end of C4 is electrically connected to the fifth node N5;

[0291] A gate of T12 is electrically connected to the input terminal STV, a source of T12 is electrically connected to the fifth node N5, and a drain of T12 is electrically connected to the low voltage terminal VGL.

[0292] exist Fig.21A In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto. In a specific implementation, the transistors may be replaced by p-type transistors.

[0293] Fig.21AIn at least one embodiment of the driving circuit shown, T12 and C4 are additionally provided. In the output reset stage, during the time period when OT continuously outputs a high voltage signal, STV provides a high voltage signal, T1 and T12 are turned on, T2 is turned off, the first node N1 is connected to VGL, the potential of the first node N1 is a low voltage, the load of the second node N2 is reduced, and the potential of the second node N2 is maintained stable. When T7 is turned on, the potential of the output reset node NF can be stabilized, and the driving signal output by the driving circuit is stable without drop (voltage drop).

[0294] Fig. 22 yes Fig.21A FIG. 1 is a timing diagram of a simulated operation of at least one embodiment of the driving circuit shown.

[0295] Fig.21B At least one embodiment of the driving circuit shown is Fig.21A The differences of at least one embodiment of the driving circuit shown are as follows:

[0296] The source of T4 is electrically connected to the second clock signal terminal CK.

[0297] exist Fig.21B In at least one embodiment of the driving circuit shown, the source of T4 is electrically connected to the second clock signal terminal CK, so that in the output reset stage, when T8 needs to be turned on to control OT to output a high voltage signal, when T4 is turned on, the potential of the third node N3 is a high voltage, and when T5 is turned on, the high potential of the third node N3 is written to the second node N2, which can stabilize the potential of the second node, and when T7 is turned on, the potential of the output reset node NF can be stabilized, and the driving signal output by the driving circuit is stable without drop (voltage drop).

[0298] Fig. 21C At least one embodiment of the driving circuit shown is Fig.21B The differences of at least one embodiment of the driving circuit shown are as follows:

[0299] The gate of T1 is electrically connected to the second node N2.

[0300] Fig.21D At least one embodiment of the driving circuit shown is Fig.21A The difference of at least one embodiment of the driving circuit shown is as follows: it also includes a second node setting circuit; the second node setting circuit includes a third transistor T3;

[0301] A gate of the third transistor T3 is electrically connected to the input terminal STV, a source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and a drain of the third transistor T3 is electrically connected to the second node N2.

[0302] exist Fig.21DIn at least one embodiment of the driving circuit shown, a third transistor T3 is added. When the input terminal STV provides a high voltage signal, T3 is turned on and a high voltage is written to the second node N2, so that the potential of the second node N2 is maintained at a high level, and the potential of the output reset node NF is further stabilized. The driving signal output by the driving circuit is stable without drops.

[0303] Fig.21E At least one embodiment of the driving circuit shown is Fig.21A The difference of at least one embodiment of the driving circuit shown is as follows: it also includes a second node setting circuit; the second node setting circuit includes a third transistor T3;

[0304] A gate of the third transistor T3 is electrically connected to the second node N2 , a source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and a drain of the third transistor T3 is electrically connected to the second node N2 .

[0305] exist Fig.21E In at least one embodiment of the driving circuit shown, a third transistor T3 is added. When the potential of the second node N2 is a high voltage signal, T3 is turned on and a high voltage is written to the second node N2, so that the potential of the second node N2 is maintained at a high level, and the potential of the output reset node NF is further stabilized. The driving signal output by the driving circuit is stable without drops.

[0306] Fig.21F At least one embodiment of the driving circuit shown is Fig. 21C The difference of at least one embodiment of the driving circuit shown is as follows: it also includes a second node setting circuit; the second node setting circuit includes a third transistor T3;

[0307] A gate of the third transistor T3 is electrically connected to the input terminal STV, a source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and a drain of the third transistor T3 is electrically connected to the second node N2.

[0308] exist Fig.21F In at least one embodiment of the driving circuit shown, a third transistor T3 is added. When the input terminal STV provides a high voltage signal, T3 is turned on and a high voltage is written to the second node N2, so that the potential of the second node N2 is maintained at a high level, and the potential of the output reset node NF is further stabilized. The driving signal output by the driving circuit is stable without drops.

[0309] Figure 21G At least one embodiment of the driving circuit shown is Fig. 21CThe difference of at least one embodiment of the driving circuit shown is as follows: it also includes a second node setting circuit; the second node setting circuit includes a third transistor T3;

[0310] A gate of the third transistor T3 is electrically connected to the second node N2 , a source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and a drain of the third transistor T3 is electrically connected to the second node N2 .

[0311] exist Figure 21G In at least one embodiment of the driving circuit shown, a third transistor T3 is added. When the potential of the second node N2 is a high voltage signal, T3 is turned on and a high voltage is written to the second node N2, so that the potential of the second node N2 is maintained at a high level, and the potential of the output reset node NF is further stabilized. The driving signal output by the driving circuit is stable without drops.

[0312] Fig.21H At least one embodiment of the driving circuit shown is Fig.21B The difference of at least one embodiment of the driving circuit shown is as follows: it also includes a second node setting circuit; the second node setting circuit includes a third transistor T3;

[0313] A gate of the third transistor T3 is electrically connected to the input terminal STV, a source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and a drain of the third transistor T3 is electrically connected to the second node N2.

[0314] exist Fig.21H In at least one embodiment of the driving circuit shown, a third transistor T3 is added. When the input terminal STV provides a high voltage signal, T3 is turned on and a high voltage is written to the second node N2, so that the potential of the second node N2 is maintained at a high level, and the potential of the output reset node NF is further stabilized. The driving signal output by the driving circuit is stable without drops.

[0315] Fig.21I At least one embodiment of the driving circuit shown is Fig.21B The difference of at least one embodiment of the driving circuit shown is as follows: it also includes a second node setting circuit; the second node setting circuit includes a third transistor T3;

[0316] A gate of the third transistor T3 is electrically connected to the second node N2 , a source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and a drain of the third transistor T3 is electrically connected to the second node N2 .

[0317] exist Fig.21IIn at least one embodiment of the driving circuit shown, a third transistor T3 is added. When the potential of the second node N2 is a high voltage signal, T3 is turned on and a high voltage is written to the second node N2, so that the potential of the second node N2 is maintained at a high level, and the potential of the output reset node NF is further stabilized. The driving signal output by the driving circuit is stable without drops.

[0318] In a specific implementation, in the output reset stage, when the drive signal output terminal OT outputs a high voltage signal, the high voltage signal connected to the gate of T7 may be different from other high voltage signals in the drive circuit, and the high voltage signal connected to the gate of T7 may be adjusted to ensure that T7 is completely turned off, so that the potential of the output reset node NF will not be affected by the potential of the second node N2, so that the potential of the output reset node NF is stable, and the drive signal output by the drive circuit is stable without drop (voltage drop).

[0319] Fig.23 At least one embodiment of the driving circuit shown is Fig.10 The differences of at least one embodiment of the driving circuit shown are as follows:

[0320] The driving circuit also includes a carry output circuit, a carry reset circuit and a carry signal output terminal CY;

[0321] The carry output circuit comprises a seventeenth transistor T17, and the carry reset circuit comprises an eighteenth transistor T18;

[0322] The gate of T17 is electrically connected to the output node NS, the source of T17 is electrically connected to the low voltage terminal VGL, and the drain of T17 is electrically connected to the carry signal output terminal CY;

[0323] The gate of T18 is electrically connected to the output reset node NF, the source of T18 is electrically connected to the carry signal output terminal CY, and the drain of T18 is electrically connected to the high voltage terminal VGH.

[0324] exist Fig.23 In at least one embodiment shown, the eighth voltage terminal is a low voltage terminal VGL, and the ninth voltage terminal is a high voltage terminal VGH.

[0325] exist Fig.23 In at least one embodiment shown, a carry output circuit, a carry reset circuit and a carry signal output terminal are additionally provided, and the carry signal output by the carry signal output terminal is cascaded, and the drive signal provided by the drive signal output terminal is used to drive the corresponding row pixel circuit to reduce the load of the drive signal output terminal.

[0326] Fig.24 At least one embodiment of the driving circuit shown is Fig.10The difference of at least one embodiment of the driving circuit is as follows:

[0327] The driving circuit further includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a fifth capacitor C5;

[0328] The gate of T9 is electrically connected to the second clock signal terminal CK, the source of T9 is electrically connected to the input terminal STV, and the drain of T9 is electrically connected to the source of T10;

[0329] The gate of T10 is electrically connected to the high voltage terminal VGH, and the drain of T10 is electrically connected to the source of T11;

[0330] The gate of T11 is electrically connected to the gate of T5, and the drain of T11 is electrically connected to the output reset node NF;

[0331] The drain of T5 is electrically connected to the first clock signal terminal CB;

[0332] A first end of C5 is electrically connected to the third node N3 , and a second end of C5 is electrically connected to the gate of T11 .

[0333] exist Fig.24 , the node labeled N6 is the sixth node, the node labeled N7 is the seventh node, and the node labeled N8 is the eighth node; the sixth node N6 is electrically connected to the drain of T12, the seventh node N7 is electrically connected to the drain of T10, and the eighth node N8 is electrically connected to the second end of C5.

[0334] exist Fig.24 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto. In a specific implementation, the transistors may be replaced by p-type transistors.

[0335] exist Fig.24 In at least one embodiment of the driving circuit shown, T12, T13, T14 and C5 are added, and the drain of T5 is changed to be electrically connected to CB, so that during the output reset stage, the potential of the second node N2 will not be pulled down by the third node N3, so that the potential of the second node N2 is stable, and the driving signal output by the driving circuit is stable.

[0336] Fig.25 yes Fig.24 FIG. 1 is a timing diagram of a simulated operation of at least one embodiment of the driving circuit shown.

[0337] In at least one embodiment of the present invention, the gate of T1 is electrically connected to the input terminal STV, the source of T4 is electrically connected to the second clock signal terminal CB, T3 is added (the gate of T3 is electrically connected to the input terminal or the second node, the source of T3 is electrically connected to the high voltage terminal, and the drain of T3 is electrically connected to the second node), T12 and C4 are added, and the above improvements can be used in combination with each other. A technical solution combining at least two of the above improvements is also within the protection scope of the present invention.

[0338] The driving module described in at least one embodiment of the present invention may include multiple levels of the above-mentioned driving circuits.

[0339] In at least one embodiment of the present invention, in the odd-numbered stage driving circuit, the first clock signal terminal may be electrically connected to the first clock signal line, and the second clock signal terminal may be electrically connected to the second clock signal line;

[0340] In the even-numbered stage driving circuit, the first clock signal terminal may be electrically connected to the third clock signal line, and the second clock signal terminal may be electrically connected to the fourth clock signal line.

[0341] like Fig.26 As shown, the driving module described in at least one embodiment of the present invention includes a first-stage driving circuit LS1, a second-stage driving circuit LS2, a third-stage driving circuit LS3 and a fourth-stage driving circuit LS4;

[0342] The first clock signal terminal of LS1 is electrically connected to the first clock signal line CKB, and the second clock signal terminal of LS1 is electrically connected to the second clock signal line CLK;

[0343] The first clock signal terminal of LS2 is electrically connected to the third clock signal line CKB2, and the second clock signal terminal of LS2 is electrically connected to the fourth clock signal line CLK2;

[0344] The first clock signal terminal of LS3 is electrically connected to the first clock signal line CKB, and the second clock signal terminal of LS3 is electrically connected to the second clock signal line CLK;

[0345] The first clock signal terminal of LS4 is electrically connected to the third clock signal line CKB2, and the second clock signal terminal of LS4 is electrically connected to the fourth clock signal line CLK2;

[0346] Fig. 27 Waveform diagram of the clock signal provided by CKB, the clock signal provided by CLK, the clock signal provided by CKB2 and the clock signal provided by CLK2.

[0347] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: comprising a first control circuit and a second control circuit; The first control circuit is electrically connected to the first control node and the first node respectively, and is used to control the potential of the first node under the control of the potential of the first control node; The second control circuit is electrically connected to the first node, the second node, the first signal terminal and the first clock signal terminal respectively, and is used to write the first signal provided by the first signal terminal into the second node under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal; The first control node is an input terminal; and / or the first signal terminal is a second clock signal terminal.

2. The driving circuit according to claim 1, characterized in that: The second control circuit is also electrically connected to the third node, and is used to write the first signal into the third node under the control of the potential of the first node, and to control the connection or disconnection between the third node and the second node under the control of the first clock signal.

3. The driving circuit according to claim 2, characterized in that: The driving circuit further includes a second node setting circuit; the second node setting circuit is electrically connected to the second control node, the first voltage terminal and the second node respectively, and is used to write the first voltage signal provided by the first voltage terminal into the second node under the control of the potential of the second control node; The second control node is an input terminal or a second node.

4. The driving circuit according to claim 1, wherein: It also includes an input circuit, an on-off control circuit and an output reset circuit; The input circuit is electrically connected to the second clock signal terminal, the input terminal and the second node respectively, and is used to write the input signal provided by the input terminal into the second node under the control of the second clock signal provided by the second clock signal terminal; The on-off control circuit is electrically connected to the second voltage terminal, the second node and the output reset node respectively, and is used to control the connection or disconnection between the second node and the output reset node under the control of the second voltage signal provided by the second voltage terminal; The output reset circuit is electrically connected to the output reset node, the third voltage terminal and the drive signal output terminal respectively, and is used to write the third voltage signal provided by the third voltage terminal into the drive signal output terminal under the control of the potential of the output reset node.

5. The driving circuit according to claim 1, characterized in that: Also includes a third energy storage circuit, an output node control circuit, a second node control circuit and an output circuit; The first end of the third energy storage circuit is electrically connected to the first node, and the second end of the third energy storage circuit is electrically connected to the first clock signal end; The output node control circuit is electrically connected to the first node, the fourth node, the first clock signal terminal and the output node respectively, and is used to write the first clock signal provided by the first clock signal terminal into the fourth node under the control of the potential of the first node, and control the connection or disconnection between the fourth node and the output node under the control of the first clock signal; The second node control circuit is electrically connected to the second node, the sixth voltage terminal and the output node respectively, and is used to write the sixth voltage signal provided by the sixth voltage terminal into the output node under the control of the potential of the second node; The output circuit is electrically connected to the output node, the seventh voltage terminal and the drive signal output terminal respectively, and is used to write the seventh voltage signal provided by the seventh voltage terminal into the drive signal output terminal under the control of the potential of the output node.

6. The driving circuit according to any one of claims 1 to 5, characterized in that: It also includes a first node setting circuit, and the first control circuit is also electrically connected to the second clock signal terminal; The first control circuit is used to control the connection or disconnection between the first node and the first clock signal terminal under the control of the potential of the first control node; The first node setting circuit is electrically connected to the second clock signal terminal, the fourth voltage terminal and the first node respectively, and is used to write the fourth voltage signal provided by the fourth voltage terminal into the first node under the control of the second clock signal provided by the second clock signal terminal.

7. The driving circuit according to any one of claims 1 to 5, characterized in that: The first control circuit is also electrically connected to the fifth voltage terminal, and is used to control the connection or disconnection between the first node and the fifth voltage terminal under the control of the potential of the first control node; The driving circuit also includes a first node setting circuit, a second energy storage circuit and a sixth control circuit; The first node setting circuit is electrically connected to the fifth node, the second clock signal terminal and the first node respectively, and is used to write the second clock signal provided by the second clock signal terminal into the first node under the control of the potential of the fifth node; A first terminal of the second energy storage circuit is electrically connected to the second clock signal terminal, and a second terminal of the second energy storage circuit is electrically connected to the fifth node; The sixth control circuit is electrically connected to the input terminal, the fifth node and the fifth voltage terminal respectively, and is used to write a fifth voltage signal provided by the fifth voltage terminal into the fifth node under the control of an input signal provided by the input terminal.

8. The driving circuit according to any one of claims 1 to 5, characterized in that: It also includes a carry output circuit, a carry reset circuit and a carry signal output terminal; The carry output circuit is electrically connected to the output node, the carry signal output terminal and the eighth voltage terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the eighth voltage terminal under the control of the potential of the output node; The carry reset circuit is electrically connected to the output reset node, the carry signal output terminal and the ninth voltage terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the ninth voltage terminal under the control of the potential of the output reset node.

9. The driving circuit according to claim 6, characterized in that: The first control circuit includes a first transistor; The gate of the first transistor is electrically connected to the first control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second clock signal terminal; The first node setting circuit includes a second transistor; A gate of the second transistor is electrically connected to the second clock signal terminal, a first electrode of the second transistor is electrically connected to the fourth voltage terminal, and a second electrode of the second transistor is electrically connected to the first node.

10. The driving circuit according to claim 3, characterized in that: The second node setting circuit includes a third transistor; A gate of the third transistor is electrically connected to the second control node, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the second node.

11. The driving circuit according to claim 1 or 2, characterized in that: The second control circuit includes a fourth transistor and a fifth transistor; The gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first signal terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; A gate of the fifth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

12. The driving circuit according to claim 4, characterized in that: The input circuit includes a sixth transistor, the on-off control circuit includes a seventh transistor, and the output reset circuit includes an eighth transistor; The gate of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the input terminal, and the second electrode of the sixth transistor is electrically connected to the second node; The gate of the seventh transistor is electrically connected to the second voltage terminal, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the output reset node; A gate of the eighth transistor is electrically connected to the output reset node, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the drive signal output terminal.

13. The driving circuit according to claim 7, characterized in that: The first control circuit includes a first transistor; The gate of the first transistor is electrically connected to the first control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fifth voltage terminal; The first node setting circuit includes a second transistor, the second energy storage circuit includes a fourth capacitor, and the sixth control circuit includes a twelfth transistor; The gate of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the second clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node; A first end of the fourth capacitor is electrically connected to the second clock signal end, and a second end of the fourth capacitor is electrically connected to the fifth node; A gate of the twelfth transistor is electrically connected to the input terminal, a first electrode of the twelfth transistor is electrically connected to the fifth node, and a second electrode of the twelfth transistor is electrically connected to the fifth voltage terminal.

14. The driving circuit according to claim 5, characterized in that: The third energy storage circuit includes a third capacitor, the output node control circuit includes a thirteenth transistor and a fourteenth transistor; the second node control circuit includes a fifteenth transistor, and the output circuit includes a sixteenth transistor; The first end of the third capacitor is electrically connected to the first node, and the second end of the third capacitor is electrically connected to the first clock signal end; The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the fourth node; The gate of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the fourth node, and the second electrode of the fourteenth transistor is electrically connected to the output node; The gate of the fifteenth transistor is electrically connected to the second node, the first electrode of the fifteenth transistor is electrically connected to the sixth voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the output node; A gate of the sixteenth transistor is electrically connected to the output node, a first electrode of the sixteenth transistor is electrically connected to the seventh voltage terminal, and a second electrode of the sixteenth transistor is electrically connected to the drive signal output terminal.

15. A driving module, characterized in that: The drive circuit comprises a plurality of stages as claimed in any one of claims 1 to 14.

16. A display device, characterized in that: Comprising the driving module as claimed in claim 15.

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