Gate drive circuit

Abstract

The invention provides a gate driving circuit. The gate driving circuit comprises a logic circuit, a first voltage partitioning circuit, a first gate line output circuit, a second voltage partitioning circuit, a first sequential circuit and a first voltage feedback circuit. The logic circuit provides a control voltage and a pull-down control signal. The first voltage partitioning circuit receives a control voltage and provides a first gate voltage. The first gate line output circuit outputs a current scan signal based on a first gate voltage and a first modulation pulse signal. The second voltage partitioning circuit receives the control voltage and provides a second gate voltage. The first timing circuit outputs a current timing signal based on the second gate voltage and the first clock signal. The first voltage feedback circuit switches on the current time sequence signal and the control voltage when the current time sequence signal is different from the control voltage.

Description

Technical Field

[0001] The present invention relates to a driving circuit, and in particular to a gate driving circuit for driving a display panel. Background Art

[0002] In the existing active display technology, the gate driver provides sequentially enabled scanning signals to the gate lines coupled to the pixel circuits in the display panel to turn on the pixel circuits in the display panel row by row, thereby performing a full screen update on all the pixel circuits in the display panel. However, full screen update not only takes a long time, but also consumes more power. Therefore, how to improve the driving / data writing method of the display panel is still a key point in the development of display panels. Summary of the invention

[0003] The present invention provides a gate driving circuit, which can generate corresponding scanning signals for full-screen or partial-screen updating of a display panel, and can optimize the overall quality of the gate driving circuit by changing the transistor structure of the internal node.

[0004] The gate drive circuit of the present invention is used to drive a display panel. The gate drive circuit includes a logic circuit, a first voltage segmentation circuit, a first gate line output circuit, a second voltage segmentation circuit, a first timing circuit, a pull-down circuit and a first voltage feedback circuit. The logic circuit receives a forward scan signal, a reverse scan signal, a first timing signal and a second timing signal to provide a control voltage and a pull-down control signal. The first voltage segmentation circuit is coupled to the logic circuit to receive the control voltage and provide a first gate voltage. The first gate line output circuit is coupled to the first voltage segmentation circuit to receive the first gate voltage and receive a first modulation pulse signal to output a current scan signal based on the first modulation pulse signal. The second voltage segmentation circuit is coupled to the logic circuit to receive the control voltage and provide a second gate voltage. The first timing circuit is coupled to the second voltage segmentation circuit to receive the second gate voltage and receive a first clock signal to output a current timing signal based on the second gate voltage and the first clock signal. The pull-down circuit receives a control voltage, a pull-down control signal, a current scan signal, a current timing signal, and a third timing signal, and pulls the control voltage, the current scan signal, and the current timing signal down to a system low voltage based on the control voltage, the pull-down control signal, and the third timing signal. The first voltage feedback circuit is coupled to the control voltage and the current timing signal, and connects the current timing signal and the control voltage when the current timing signal is an enable voltage.

[0005] Based on the above, in the gate drive circuit of the embodiment of the present invention, the waveform of the first modulated pulse signal forms a waveform portion that is the same as the first clock signal in the partial horizontal period for screen update, so that only a portion of the pixel circuits in the display panel are updated. In addition, the voltage stability of the control voltage is enhanced by transmitting the current timing signal of the enable voltage to the node of the control voltage. Therefore, by adjusting the pulse of the modulated pulse signal, the gate drive circuit generates a corresponding scan signal for the partial screen update of the display panel, and by changing the transistor structure of the internal node, the overall physical condition of the gate drive circuit can be optimized.

[0006] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A circuit diagram of a gate driving circuit according to an embodiment of the present invention is shown.

[0008] Figure 2 A signal timing diagram showing a display panel performing partial screen update according to an embodiment of the present invention is shown.

[0009] Figure 3 A circuit diagram of a gate driving circuit according to an embodiment of the present invention is shown.

[0010] Figure 4 A circuit diagram showing a gate driving circuit according to another embodiment of the present invention is shown.

[0011] Figure 5 A circuit diagram showing a gate driving circuit according to another embodiment of the present invention is shown.

[0012] Figure 6 A system schematic diagram of a gate driver according to an embodiment of the present invention is shown.

[0013] Description of reference numerals:

[0014] 10: Gate Driver

[0015] 100, 300, 400, 500, 100_1, 100_2, 100_3, 100_4, 100_5, 100_6, 100_7, 100_8, 100_9: Gate drive circuit

[0016] 110, 310, 510: Logic circuits

[0017] 120, 320, 520: First voltage separation circuit

[0018] 130, 330, 530: first gate line output circuit

[0019] 140, 340, 540: Second voltage separation circuit

[0020] 150, 350, 550: First sequential circuit

[0021] 160, 360, 560: Pull-down circuit

[0022] 170, 370, 470, 570: First voltage feedback circuit

[0023] 520: Third voltage separation circuit

[0024] 530: Second gate line output circuit

[0025] 540: Fourth voltage separation circuit

[0026] 550: Second sequential circuit

[0027] 570: Second voltage feedback circuit

[0028] U2D: forward scanning signal

[0029] D2U: Reverse scanning signal

[0030] ST(n-2)~ST(n+4), ST(1)~ST(12): Timing signal

[0031] VP: Control voltage

[0032] VI: Pull-down control signal

[0033] P, Q1, Q2, Q3, Q4, I: Node

[0034] VQ1, VQ2, VQ3, VQ4: Gate voltage

[0035] ENB_HC1, ENB_HC2, ENB_HC3, ENB_HC4, ENB_HC5, ENB_HC6: modulated pulse signal

[0036] M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28: transistors

[0037] HC1, HC2, HC3, HC4, HC5, HC6: clock signal

[0038] XDONB: System low voltage

[0039] SR(n-2)~SR(n+3),SR(1)~SR(8): scanning signal

[0040] VGH: Gate high voltage

[0041] RST: reset signal

[0042] R: Resistance DETAILED DESCRIPTION

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0044] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

[0045] The terms used herein are only for the purpose of describing specific embodiments and are not restrictive. As used herein, unless the content clearly indicates, the singular forms "one", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that when used in this specification, the terms "include" and / or "include" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0046] Figure 1 FIG. 2 is a circuit diagram showing a gate drive circuit according to an embodiment of the present invention. Figure 1In this embodiment, the gate driving circuit 100 includes a logic circuit 110, a first voltage segmentation circuit 120, a first gate line output circuit 130, a second voltage segmentation circuit 140, a first timing circuit 150, a pull-down circuit 160, and a first voltage feedback circuit 170. The logic circuit 110 is coupled to the first voltage segmentation circuit 120, the second voltage segmentation circuit 140, and the pull-down circuit 160, the first voltage segmentation circuit 120 is coupled to the first gate line output circuit 130, the second voltage segmentation circuit 140 is coupled to the first timing circuit 150, and the first voltage feedback circuit 170 is coupled between the first timing circuit 150 and the logic circuit 110.

[0047] The logic circuit 110 receives a forward scan signal U2D, a reverse scan signal D2U, a timing signal ST(n-2) (corresponding to the first timing signal) and a timing signal ST(n+4) (corresponding to the second timing signal) to provide a control voltage VP to the first voltage segmentation circuit 120, the second voltage segmentation circuit 140 and the pull-down circuit 160, and provides a pull-down control signal VI to the pull-down circuit 160, wherein n is a pilot number, the timing signal ST(n-2) can be generated by the first two stages of the gate driving circuit 100, and the timing signal ST(n+4) can be generated by the last four stages of the gate driving circuit 100, but the embodiments of the present invention are not limited thereto.

[0048] The first voltage segmentation circuit 120 is coupled to the logic circuit 110 to receive the control voltage VP and provide a gate voltage VQ1 (corresponding to the first gate voltage) according to the control voltage VP. The second voltage segmentation circuit 140 is coupled to the logic circuit 110 to receive the control voltage VP and provide a gate voltage VQ2 (corresponding to the second gate voltage) according to the control voltage VP.

[0049] The first gate line output circuit 130 is coupled to the first voltage segmentation circuit 120 to receive the gate voltage VQ1. Furthermore, the first gate line output circuit 130 receives the modulation pulse signal ENB_HC1 (corresponding to the first modulation pulse signal) to output the scanning signal SR(n) (corresponding to the current scanning signal) based on the modulation pulse signal ENB_HC1 and the gate voltage VQ1, for example, outputting the received modulation pulse signal ENB_HC1 as the scanning signal SR(n), wherein the scanning signal SR(n) is provided to the gate line (not shown) coupled to the pixel circuit (not shown) in the display panel (not shown) to drive the pixel circuit (not shown) of the corresponding column in the display panel (not shown).

[0050] The first timing circuit 150 is coupled to the second voltage segmentation circuit 140 to receive the gate voltage VQ2. Furthermore, the first timing circuit 150 receives the clock signal HC1 to output the timing signal ST(n) (corresponding to the current timing signal) based on the clock signal HC1 and the gate voltage VQ2, for example, outputting the received clock signal HC1 as the timing signal ST(n), wherein the timing signal ST(n) can be provided to the gate driving circuit of the next stage so that the gate driving circuits of the cascade can be driven one by one. The first voltage feedback circuit 170 is coupled to the control voltage VP and the timing signal ST(n), and connects the timing signal ST(n) and the control voltage VP when the timing signal ST(n) is an enable voltage (for example, a high voltage level).

[0051] The pull-down circuit 160 is coupled to the logic circuit 110 and receives the control voltage VP, the pull-down control signal VI, the scan signal SR(n), the timing signal ST(n), and the timing signal ST(n+2) (corresponding to the third timing signal). Based on the control voltage VP, the pull-down control signal VI, and the timing signal ST(n+2), the pull-down circuit 160 pulls the control voltage VP, the scan signal SR(n), and the timing signal ST(n) down to the system low voltage XDONB, so that the gate driving circuit 100 is turned off.

[0052] In an embodiment, when the display panel (not shown) performs full screen update, the waveform of the modulation pulse signal ENB_HC1 is the same as the waveform of the first clock signal HC1, so that all pixel circuits (not shown) in the display panel (not shown) are driven (or turned on) column by column to update all pixel circuits. In addition, when the display panel (not shown) performs partial screen update, the modulation pulse signal ENB_HC1 is different from the clock signal HC1. For example, the waveform of the modulation pulse signal ENB_HC1 forms a waveform portion that is the same as the clock signal HC1 in a portion of the horizontal period during which the screen is updated, that is, the modulation pulse signal ENB_HC1 does not periodically form pulses, so that only a portion of the pixel circuits in the display panel (not shown) are updated. In addition, by transmitting the timing signal ST(n) of the enable voltage back to the node P, the voltage stability of the control voltage VP of the node P is enhanced. Therefore, by adjusting the pulse of the modulation pulse signal ENB_HC1, the gate driving circuit 100 generates a corresponding scanning signal SR(n) for full-screen update and partial-screen update of the display panel (not shown), and by changing the transistor structure of the back-up node P, the overall physical condition of the gate driving circuit 100 can be optimized.

[0053] In this embodiment, the first voltage isolating circuit 120 and the second voltage isolating circuit 140 can be used to isolate the node P between the logic circuit 110, the first voltage isolating circuit 120 and the second voltage isolating circuit 140 from the node Q1 between the first voltage isolating circuit 120 and the first gate line output circuit 130 and the node Q2 between the second voltage isolating circuit 140 and the first timing circuit 150, so that the gate voltage VQ1 and the gate voltage VQ2 on the node Q2 will not be fed back to (or affect) the node P, that is, the gate voltage VQ1 and the gate voltage VQ2 can be separated from each other.

[0054] In the embodiment of the present invention, according to the scanning direction of the display panel (not shown), the forward scanning signal U2D and the reverse scanning signal D2U may be at a high voltage level and a low voltage level, respectively.

[0055] Figure 2 The signal timing diagram of the display panel for partial screen update according to an embodiment of the present invention is shown. Figure 1 and Figure 2 In this embodiment, six clock signals HC1 to HC6 and six modulation pulse signals ENB_HC1 to ENB_HC6 are taken as an example. Figure 2 As shown, the pulses of the clock signals HC1-HC6 are continuously formed and each of the clock signals HC1-HC6 partially overlaps with the previous and the next one, that is, the clock signals HC1-HC6 are different from each other by a fixed phase difference (e.g., 1 horizontal period). In addition, in the case of partial screen update, the modulated pulse signals ENB_HC1-ENB_HC6 do not continuously form pulses during one frame period of partial screen update, but generate pulses corresponding to the columns to be updated, so that the pulsed parts of the modulated pulse signals ENB_HC1-ENB_HC6 are respectively the same as the waveforms of the corresponding parts of the clock signals HC1-HC6. In contrast, in the case of full screen update, the modulated pulse signals ENB_HC1-ENB_HC6 are the same as the clock signals HC1-HC6 during one frame period of full screen update.

[0056] Figure 3 FIG. 2 is a circuit diagram showing a gate drive circuit according to an embodiment of the present invention. Figure 1 and Figure 3 In this embodiment, the gate driving circuit 100 can be implemented with reference to the gate driving circuit 300, that is, the gate driving circuit 300 can be regarded as an implementation example of the gate driving circuit 100, wherein the same or similar elements use the same or similar reference numerals. Figure 3In the embodiment, the gate driving circuit 300 includes a logic circuit 310, a first voltage segmentation circuit 320, a first gate line output circuit 330, a second voltage segmentation circuit 340, a first timing circuit 350, a pull-down circuit 360 and a first voltage feedback circuit 370.

[0057] In the present embodiment, the logic circuit 310 includes a transistor M1 (corresponding to the first transistor), a transistor M2 (corresponding to the second transistor), a transistor M3 (corresponding to the third transistor), a transistor M4 (corresponding to the fourth transistor), and a resistor R. The first end of the transistor M1 receives the forward scan signal U2D, the control end of the transistor M1 receives the timing signal ST(n-2), and the second end of the transistor M1 provides the control voltage VP. The first end of the transistor M2 is coupled to the second end of the transistor M1, the control end of the transistor M2 receives the timing signal ST(n+4), and the second end of the transistor M2 receives the reverse scan signal D2U. The first end of the transistor M3 receives the gate high voltage VGH, the control end of the transistor M3 receives the clock signal HC5 (corresponding to another clock signal), and the second end of the transistor M3 is coupled to the resistor R. The first end and the control end of the transistor M4 receive the reset signal RST, and the second end of the transistor M4 is coupled to the node I (i.e., coupled to the pull-down control signal VI). The resistor R is coupled between the second end of the transistor M3 and the node I.

[0058] The first voltage segmentation circuit 320 includes a transistor M5 (corresponding to a fifth transistor). A first terminal of the transistor M5 receives a control voltage VP, a control terminal of the transistor M5 receives a gate high voltage VGH, and a second terminal of the transistor M5 outputs a gate voltage VQ1.

[0059] The first gate line output circuit 330 includes a transistor M6 (corresponding to the sixth transistor) and a transistor M7 (corresponding to the seventh transistor). The first end of the transistor M6 receives the modulation pulse signal ENB_HC1, the control end of the transistor M6 receives the gate voltage VQ1, and the second end of the transistor M6 provides a scan signal SR(n). The first end and the second end of the transistor M7 are coupled to the second end of the transistor M6 and receive the scan signal SR(n). The control end of the transistor M7 is coupled to the control end of the transistor M6 and receives the gate voltage VQ1. Among them, the transistor M7 is coupled to form a capacitor.

[0060] The second voltage segmentation circuit 340 includes a transistor M8 (corresponding to an eighth transistor). A first terminal of the transistor M8 receives a control voltage VP, a control terminal of the transistor M8 receives a gate high voltage VGH, and a second terminal of the transistor M8 outputs a gate voltage VQ2.

[0061] The first timing circuit 350 includes a transistor M9 (corresponding to the ninth transistor) and a transistor M10 (corresponding to the tenth transistor). The first end of the transistor M9 receives the clock signal HC1, the control end of the transistor M9 receives the gate voltage VQ2, and the second end of the transistor M9 outputs the current timing signal ST(n) according to the clock signal HC1 and the gate voltage VQ2. The first end and the second end of the transistor M10 are coupled to the second end of the transistor M9 and receive the timing signal ST(n), and the control end of the transistor M10 is coupled to the control end of the transistor M9 and receives the gate voltage VQ2. Among them, the transistor M10 is coupled to form a capacitor.

[0062] The first voltage feedback circuit 370 includes a transistor M16 (corresponding to the first feedback transistor). The transistor M16 has a first end coupled to the control voltage VP, a control end coupled to the timing signal ST(n), and a second end coupled to the timing signal ST(n). Therefore, when the timing signal ST(n) rises to an enable voltage (e.g., a high voltage level) to a voltage higher than the threshold voltage of the transistor M16, the transistor M16 coupled in a diode form will charge the control voltage VP to accelerate the rise of the control voltage VP. Furthermore, when the timing signal ST(n) is maintained at the enable voltage, the voltage level of the associated control voltage VP will be maintained at the enable voltage.

[0063] The pull-down circuit 360 includes a transistor M11 (corresponding to the eleventh transistor), a transistor M12 (corresponding to the twelfth transistor), a transistor M13 (corresponding to the thirteenth transistor), a transistor M14 (corresponding to the fourteenth transistor) and a transistor M15 (corresponding to the fifteenth transistor). The first end of the transistor M11 is coupled to the resistor R to receive the pull-down control signal VI, the control end of the transistor M11 receives the control voltage VP, and the second end of the transistor M11 receives the system low voltage XDONB. The first end of the transistor M12 receives the control voltage VP, the control end of the transistor M12 receives the pull-down control signal VI, and the second end of the transistor M12 receives the system low voltage XDONB. The first end of the transistor M13 receives the scan signal SR(n), the control end of the transistor M13 receives the pull-down control signal VI, and the second end of the transistor M13 receives the system low voltage XDONB. The first end of the transistor M14 receives the timing signal ST(n), the control end of the transistor M14 receives the pull-down control signal VI, and the second end of the transistor M14 receives the system low voltage XDONB. A first terminal of the transistor M15 receives the scan signal SR(n), a control terminal of the transistor M15 receives the timing signal ST(n+2), and a second terminal of the transistor M15 receives the system low voltage XDONB.

[0064] In this embodiment, the transistors M1 - M16 are taken as N-type transistors, but the embodiment of the present invention is not limited thereto.

[0065] Figure 4 FIG. 2 is a circuit diagram showing a gate drive circuit according to another embodiment of the present invention. Figure 3 and Figure 4 The gate driving circuit 400 is substantially the same as the gate driving circuit 300 , and the difference lies in the first voltage feedback circuit 470 , wherein the first voltage feedback circuit 470 includes a transistor M17 (corresponding to the second feedback transistor) and a transistor M18 (corresponding to the second feedback transistor).

[0066] exist Figure 4 In the embodiment, the transistor M17 has a first terminal, a control terminal coupled to the timing signal ST(n), and a second terminal coupled to the timing signal ST(n). The transistor M18 has a first terminal coupled to the control voltage VP, a control terminal coupled to the timing signal ST(n), and a second terminal coupled to the first terminal of the transistor M17.

[0067] In this embodiment, the transistors M1 - M15 , M17 , and M18 are taken as N-type transistors, but the embodiment of the present invention is not limited thereto.

[0068] Figure 5 FIG. 2 is a circuit diagram showing a gate drive circuit according to another embodiment of the present invention. Figure 1 , Figure 3 and Figure 5 The gate driving circuit 500 is substantially the same as the gate driving circuit 300, wherein the same or similar elements are numbered the same or similarly. The difference is that, in addition to the logic circuit 310, the first voltage segmentation circuit 320, the first gate line output circuit 330, the second voltage segmentation circuit 340, the first timing circuit 350, the first voltage feedback circuit 370 and the pull-down circuit 560, the gate driving circuit 500 also includes a third voltage segmentation circuit 520, a second gate line output circuit 530, a fourth voltage segmentation circuit 540, a second timing circuit 550 and a second voltage feedback circuit 570, wherein the pull-down circuit 560 is substantially the same as the pull-down circuit 360, and the difference is that it also includes transistors M25, M26 and M27.

[0069] The third voltage partitioning circuit 520 receives the control voltage VP and provides a gate voltage VQ3 according to the control voltage VP. In this embodiment, the third voltage partitioning circuit 520 may include a transistor M19. A first terminal of the transistor M19 receives the control voltage VP, a control terminal of the transistor M19 receives a gate high voltage VGH, and a second terminal of the transistor M19 provides the gate voltage VQ3.

[0070] The second gate line output circuit 530 includes transistors M20 and M21 (corresponding to the sixteenth transistor to the seventeenth transistor). The first end of the transistor M20 receives the modulation pulse signal ENB_HC2 (corresponding to the second modulation pulse signal), the control end of the transistor M20 receives the gate voltage VQ3, and the second end of the transistor M20 outputs the scan signal SR(n+1) (corresponding to the first current scan signal). The first end and the second end of the transistor M21 are coupled to the second end of the transistor M20 and receive the scan signal SR(n+1), and the control end of the transistor M21 is coupled to the control end of the transistor M20 and receives the gate voltage VQ3. Among them, the transistor M21 is coupled to form a capacitor.

[0071] The fourth voltage segmentation circuit 540 receives the control voltage VP, generates a gate voltage VQ4 according to the control voltage VP, and then outputs the gate voltage VQ4. The fourth voltage segmentation circuit 540 includes a transistor M22. A first terminal of the transistor M22 receives the control voltage VP, a control terminal of the transistor M22 receives a gate high voltage VGH, and a second terminal of the transistor M22 provides the gate voltage VQ4.

[0072] The second timing circuit 550 includes a transistor M23 and a transistor M24 (corresponding to the eighteenth transistor and the nineteenth transistor). The first end of the transistor M23 receives the clock signal HC2 (corresponding to the second clock), the control end of the transistor M23 is coupled to receive the gate voltage VQ4, and the second end of the transistor M23 outputs the timing signal ST(n+1). Specifically, the first end and the second end of the transistor M24 are coupled to the second end of the transistor M23 and receive the timing signal ST(n+1), and the control end of the transistor M24 is coupled to the control end of the transistor M23 and receives the gate voltage VQ4. The transistor M24 is coupled to form a capacitor.

[0073] Compared with the pull-down circuit 360, Figure 5 The pull-down circuit 560 also includes transistors M25, M26, and M27 (corresponding to the twentieth transistor to the twenty-second transistor). The first end of the transistor M25 receives the scan signal SR(n+1), the control end of the transistor M25 receives the pull-down control signal VI, and the second end of the transistor M25 receives the system low voltage XDONB. The first end of the transistor M26 receives the timing signal ST(n+1), the control end of the transistor M26 receives the pull-down control signal VI, and the second end of the transistor M26 receives the system low voltage XDONB. The first end of the transistor M27 receives the scan signal SR(n+1), the control end of the transistor M27 receives the timing signal ST(n+3), and the second end of the transistor M27 receives the system low voltage XDONB.

[0074] The second voltage feedback circuit 570 includes a transistor M28 having a first terminal coupled to the control voltage VP, a control terminal coupled to the timing signal ST(n+1), and a second terminal coupled to the timing signal ST(n+1).

[0075] In this embodiment, the transistors M1 - M16 and M19 - M28 are taken as N-type transistors, but the embodiment of the present invention is not limited thereto.

[0076] Figure 6 A schematic diagram of a gate driver system according to an embodiment of the present invention is shown. Figure 1 , Figure 2 and Figure 6 In this embodiment, the gate driver 10 includes a plurality of gate driving circuits (such as 100_1 to 100_8), wherein the gate driving circuits 100_1 to 100_8 can refer to Figure 1 The gate driving circuit 100 is shown and will not be described in detail herein.

[0077] In this embodiment, each of the gate driving circuits 100_1 to 100_8 receives a corresponding clock signal (such as HC1 to HC6), a corresponding modulation pulse signal (such as ENB_HC1 to ENB_HC2), a timing signal of a previous stage (such as ST(1) to ST(12)), and a timing signal of a subsequent stage (such as ST(1) to ST(12)) to generate a corresponding timing signal (such as ST(1) to ST(12)) and a corresponding scan signal (such as SR(1) to SR(8)).

[0078] In summary, in the gate drive circuit of the embodiment of the present invention, the waveform of the first modulated pulse signal forms a waveform portion that is the same as the first clock signal in a portion of the horizontal period for screen update, so that only a portion of the pixel circuits in the display panel are updated. In addition, the voltage stability of the control voltage is enhanced by transmitting the current timing signal of the enable voltage to the node of the control voltage. Therefore, by adjusting the pulse of the modulated pulse signal, the gate drive circuit generates a corresponding scan signal for updating a portion of the display panel screen, and by changing the transistor structure of the internal node, the overall physical condition of the gate drive circuit can be optimized.

[0079] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A gate driving circuit for driving a display panel, comprising: A logic circuit receives a forward scanning signal, a reverse scanning signal, a first timing signal and a second timing signal to provide a control voltage and a pull-down control signal; A first voltage segmentation circuit is coupled to the logic circuit to receive the control voltage and provide a first gate voltage; a first gate line output circuit coupled to the first voltage segmentation circuit to receive the first gate voltage and a first modulation pulse signal to output a current scanning signal based on the first modulation pulse signal; a second voltage segmentation circuit coupled to the logic circuit to receive the control voltage and provide a second gate voltage; a first timing circuit coupled to the second voltage segmentation circuit to receive the second gate voltage and a first clock signal to output a current timing signal based on the second gate voltage and the first clock signal; a pull-down circuit receiving the control voltage, the pull-down control signal, the current scan signal, the current timing signal, and receiving a third timing signal, so as to pull down the control voltage, the current scan signal, and the current timing signal to a system low voltage based on the control voltage, the pull-down control signal, and the third timing signal; as well as A first voltage feedback circuit is coupled to the control voltage and the current timing signal, and connects the current timing signal and the control voltage when the current timing signal is an enabling voltage.

2. The gate driving circuit as claimed in claim 1, wherein the first voltage feedback circuit comprises: A first feedback transistor has a first terminal coupled to the control voltage, a control terminal coupled to the current timing signal, and a second terminal coupled to the current timing signal.

3. The gate driving circuit as claimed in claim 1, wherein the first voltage feedback circuit comprises: a second feedback transistor having a first terminal, a control terminal coupled to the current timing signal, and a second terminal coupled to the current timing signal; as well as A third feedback transistor has a first end coupled to the control voltage, a control end coupled to the current timing signal, and a second end coupled to the first end of the second feedback transistor.

4. The gate driving circuit as claimed in claim 1, wherein the logic circuit comprises: a first transistor having a first terminal for receiving the forward scanning signal, a control terminal for receiving the first timing signal, and a second terminal for providing the control voltage; a second transistor having a first end coupled to the second end of the first transistor, a control end receiving the second timing signal, and a second end receiving the reverse scanning signal; a third transistor having a first terminal receiving a gate high voltage, a control terminal receiving another clock signal, and a second terminal; a resistor coupled between the second terminal of the third transistor and the pull-down control signal; and A fourth transistor has a first terminal receiving a reset signal, a control terminal receiving the reset signal, and a second terminal coupled to the pull-down control signal.

5. The gate driving circuit as claimed in claim 1, wherein the first voltage segmentation circuit comprises: A fifth transistor has a first terminal receiving the control voltage, a control terminal receiving the gate high voltage, and a second terminal providing the first gate voltage.

6. The gate driving circuit as claimed in claim 1, wherein the first gate line output circuit comprises: a sixth transistor having a first terminal receiving the first modulation pulse signal, a control terminal receiving the first gate voltage, and a second terminal outputting the current scanning signal; and A seventh transistor has a first end coupled to the second end of the sixth transistor, a control end of the control end of the sixth transistor, and a second end coupled to the second end of the sixth transistor.

7. The gate driving circuit as claimed in claim 1, wherein the second voltage segmentation circuit comprises: An eighth transistor has a first terminal receiving the control voltage, a control terminal receiving the gate high voltage, and a second terminal providing the second gate voltage.

8. The gate driving circuit as claimed in claim 1, wherein the first timing circuit comprises: a ninth transistor having a first terminal for receiving the first clock signal, a control terminal for receiving the second gate voltage, and a second terminal for outputting the current timing signal; as well as A tenth transistor has a first end coupled to the second end of the ninth transistor, a control end of the control end of the ninth transistor, and a second end coupled to the second end of the ninth transistor.

9. The gate driving circuit as claimed in claim 1, wherein the pull-down circuit comprises: an eleventh transistor having a first terminal coupled to the pull-down control signal, a control terminal receiving the control voltage, and a second terminal receiving the system low voltage; a twelfth transistor having a first terminal receiving the control voltage, a control terminal receiving the pull-down control signal, and a second terminal receiving the system low voltage; a thirteenth transistor having a first terminal receiving the current scanning signal, a control terminal receiving the pull-down control signal, and a second terminal receiving the system low voltage; a fourteenth transistor having a first terminal receiving the current timing signal, a control terminal receiving the pull-down control signal, and a second terminal receiving the system low voltage; and A fifteenth transistor has a first end receiving the current scanning signal, a control end receiving the third timing signal, and a second end receiving the system low voltage.

10. The gate driving circuit according to claim 9, further comprising: a third voltage segmentation circuit coupled to the logic circuit to receive the control voltage and provide a third gate voltage; a second gate line output circuit coupled to the third voltage segmentation circuit to receive the third gate voltage and a second modulation pulse signal to output a first current scanning signal based on the second modulation pulse signal; a fourth voltage segmentation circuit coupled to the logic circuit to receive the control voltage and provide a fourth gate voltage; as well as a second timing circuit coupled to the fourth voltage segmentation circuit to receive the fourth gate voltage and a second clock signal to output a first current timing signal based on the fourth gate voltage and the second timing signal; and a second voltage feedback circuit coupled to the control voltage and the first current timing signal, and connected to the first current timing signal and the control voltage when the first current timing signal is an enabling voltage.

11. The gate driving circuit as claimed in claim 10, wherein the second gate line output circuit comprises: a sixteenth transistor having a first end receiving the second modulation pulse signal, a control end receiving the third gate voltage, and a second end outputting the first current scanning signal; and A seventeenth transistor has a first end coupled to the second end of the sixteenth transistor, a control end receiving the third gate voltage, and a second end coupled to the second end of the sixteenth transistor.

12. The gate driving circuit as claimed in claim 10, wherein the second timing circuit comprises: an eighteenth transistor having a first terminal receiving the second clock signal, a control terminal receiving the fourth gate voltage, and a second terminal outputting the first current timing signal; and A nineteenth transistor has a first end coupled to the second end of the eighteenth transistor, a control end receiving the fourth gate voltage, and a second end coupled to the second end of the eighteenth transistor.

13. The gate driving circuit as claimed in claim 10, wherein the pull-down circuit further comprises: a twentieth transistor having a first terminal receiving the first current scanning signal, a control terminal receiving the pull-down control signal, and a second terminal receiving the system low voltage; a twenty-first transistor having a first terminal receiving the first current timing signal, a control terminal receiving the pull-down control signal, and a second terminal receiving the system low voltage; and A twenty-second transistor has a first end receiving the first current scanning signal, a control end receiving a fourth timing signal, and a second end receiving the system low voltage.

14. The gate driving circuit as claimed in claim 10, wherein when the display panel is updated in full screen, the second modulation pulse signal is the same as the second clock signal, and when the display panel is updated in partial screen, the second modulation pulse signal is different from the second clock signal.

15. The gate driving circuit as claimed in claim 1, wherein when the display panel is updated in full screen, the first modulation pulse signal is the same as the first clock signal, and when the display panel is updated in partial screen, the first modulation pulse signal is different from the first clock signal.

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