Splicing display panel and splicing display device

Abstract

The embodiment of the invention provides a tiled display panel and a tiled display device. According to the tiled display panel, one row of light-emitting units and at least two rows of sub-pixel units are correspondingly arranged, and the write-in time period of a first control signal of each row of light-emitting units is located in the write-in time period of scanning signals of the corresponding at least two rows of sub-pixel units; therefore, when one row of light-emitting units write light-emitting data, at least two rows of sub-pixel units corresponding to one row of light-emitting units write display data, that is, when one row of light-emitting units is refreshed, the two rows of sub-pixel units corresponding to one row of light-emitting units are refreshed synchronously; therefore, each row of light-emitting units and each corresponding row of sub-pixel units in the sub-display panel can be refreshed synchronously, and display dislocation is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a spliced ​​display panel and a spliced ​​display device. Background Art

[0002] TFT-LCD (thin film transistor-liquid crystal display) is widely used due to its advantages such as long life, mature technology and low price. In order to achieve large-screen display, current display devices will form a display device by splicing multiple display panels. Since the liquid crystal display panel has a frame, there will be a problem of a large frame at the splicing of two liquid crystal display panels, resulting in the appearance of splicing dark lines. In order to solve the problem of splicing dark lines, current spliced ​​display devices will set LED (light-emitting diode) light strips at the splicing of two liquid crystal display panels. However, during the display process of the spliced ​​display device, it is found that the display screen of the spliced ​​display device will be misaligned. This is because the refresh speed of the LED light strip is faster than the refresh speed of the liquid crystal display panel, resulting in the refresh of the liquid crystal display panel and the LED light strip being out of sync, resulting in display abnormality.

[0003] Therefore, the current spliced ​​display device has a technical problem of display abnormality caused by the asynchronous refreshing of the liquid crystal display panel and the LED light bar. Summary of the invention

[0004] The embodiments of the present application provide a spliced ​​display panel and a spliced ​​display device, which are used to solve the technical problem of abnormal display caused by the asynchronous refreshing of the liquid crystal display panel and the LED light bar in the current spliced ​​display device.

[0005] In order to achieve the above object, according to a first aspect of the present application, a spliced ​​display panel is provided, the spliced ​​display panel comprising:

[0006] At least two sub-display panels are spliced ​​together, each of the sub-display panels comprises a plurality of rows of sub-pixel units and a plurality of rows of scan lines, the plurality of rows of scan lines are electrically connected to the plurality of rows of sub-pixel units respectively, and the sub-pixel units are configured to write display data when a scan signal is input to the scan line;

[0007] A display unit, located at the joint of the two sub-display panels, the display unit includes a driving chip and at least one row of light-emitting units, the light-emitting units are electrically connected to the driving chip, and the light-emitting units are configured to write light-emitting data when the driving chip inputs a first control signal;

[0008] Among them, one row of the light-emitting units is arranged correspondingly to at least two rows of the sub-pixel units, and the writing time period of the first control signal of each row of the light-emitting units is located within the writing time period of the scanning signal of the corresponding at least two rows of the sub-pixel units.

[0009] According to a second aspect of the present application, a spliced ​​display device is provided, and the spliced ​​display device includes a spliced ​​display panel as described in any one of the above embodiments.

[0010] The embodiments of the present application provide a spliced ​​display panel and a spliced ​​display device; the spliced ​​display panel is configured such that a row of light-emitting units corresponds to at least two rows of sub-pixel units, and a writing time period of a first control signal of each row of light-emitting units is located within a writing time period of a scanning signal of at least two corresponding rows of sub-pixel units, so that when a row of light-emitting units writes light-emitting data, at least two rows of sub-pixel units corresponding to the row of light-emitting units write display data, that is, when a row of light-emitting units is refreshed, two rows of sub-pixel units corresponding to the row of light-emitting units are synchronously refreshed, so that each row of light-emitting units can be synchronously refreshed with each row of sub-pixel units corresponding to the sub-display panel to avoid display misalignment.

[0011] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0013] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0014] Figure 1 This is a first schematic diagram of a spliced ​​display panel provided in an embodiment of the present application.

[0015] Figure 2 A second schematic diagram of a spliced ​​display panel provided in an embodiment of the present application.

[0016] Figure 3 A first schematic diagram of a display unit provided in an embodiment of the present application.

[0017] Figure 4 A second schematic diagram of a display unit provided in an embodiment of the present application.

[0018] Figure 5A first timing diagram of a scan signal and a first control signal of a spliced ​​display panel provided in an embodiment of the present application.

[0019] Figure 6 A second timing diagram of the scanning signal and the first control signal of the spliced ​​display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0021] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "electrically connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] In order to illustrate the principle of the technical problem of the embodiment of the present application, the embodiment of the present application provides a comparative display device. It can be understood that the comparative display device cannot be used as the prior art in the embodiment of the present application. Compared with some display devices that only use liquid crystal display panels for splicing, which will lead to larger seams, some display devices only use LED light strips for splicing, which leads to higher costs. In order to achieve large size, seamless splicing and low cost, some comparative display devices generally use liquid crystal display panels for splicing, and set LED light strips between adjacent liquid crystal display panels, so as to take into account both low cost and seamless splicing, and can be infinitely expanded. However, in the comparison display device, since the LCD panel is scanned line by line from top to bottom, the LED light bar updates the screen according to the cascade status of the driver chip, and the general splicing system refreshes the data of multiple LED light bars at the same time, the amount of data displayed by the LED light bar is less than that of the LCD panel, resulting in a faster refresh rate of the LED light bar than the LCD panel. Then, in the screen spliced ​​and displayed by the LCD panel and the LED light bar, there will be a problem of asynchronous refresh within a frame, resulting in screen misalignment under dynamic images, and then display abnormality. Therefore, the current splicing display device has a technical problem of display abnormality caused by asynchronous refresh of the LCD panel and the LED light bar.

[0023] In view of the above technical problems, the embodiments of the present application provide a spliced ​​display panel and a spliced ​​display device to solve the above technical problems.

[0024] Figure 1 This is a first schematic diagram of a spliced ​​display panel provided in an embodiment of the present application. Figure 2 A second schematic diagram of a spliced ​​display panel provided in an embodiment of the present application. Figure 3 A first schematic diagram of a display unit provided in an embodiment of the present application. Figure 4 A second schematic diagram of a display unit provided in an embodiment of the present application. Figure 5 A first timing diagram of a scan signal and a first control signal of a spliced ​​display panel provided in an embodiment of the present application. Figure 6 A second timing diagram of the scanning signal and the first control signal of the spliced ​​display panel provided in an embodiment of the present application.

[0025] like Figures 1 to 6 As shown, an embodiment of the present application provides a spliced ​​display panel, the spliced ​​display panel 1 includes at least two spliced ​​sub-display panels 11 and a display unit 12 located at the splicing of the two sub-display panels 11, each of the sub-display panels 11 includes a plurality of rows of sub-pixel units 111 and a plurality of rows of scan lines 112, the plurality of rows of scan lines 112 are electrically connected to the plurality of rows of sub-pixel units 111, respectively, the sub-pixel units 111 are configured to write display data when the scan lines 112 input a scan signal; the display unit 12 includes a driving chip 121 and at least one row of light-emitting units 122, the driving chip 121 is electrically connected to the light-emitting units 122, the light-emitting units 122 are configured to write light-emitting data when the driving chip 121 inputs a first control signal;

[0026] Among them, a row of the light-emitting units 122 is correspondingly arranged with at least two rows of the sub-pixel units 111, and the writing time period T1 of the first control signal of each row of the light-emitting units 122 is located in the writing time period of the scanning signal of the corresponding at least two rows of the sub-pixel units 111 (for example Figure 5The writing time period of the scanning signal of the two rows of sub-pixel units 111 is the sum of the writing time period T3 of the first scanning signal and the writing time period T4 of the second scanning signal. The embodiment of the present application provides a spliced ​​display panel; the spliced ​​display panel 1 is configured by making a row of the light-emitting units 122 correspond to at least two rows of the sub-pixel units 111, and the writing time period of the first control signal of each row of the light-emitting units 122 is located within the writing time period of the scanning signal of the corresponding at least two rows of the sub-pixel units 111, so that when a row of light-emitting units 122 writes light-emitting data, at least two rows of sub-pixel units 111 corresponding to a row of light-emitting units write display data, that is, when a row of light-emitting units is refreshed, the two rows of sub-pixel units corresponding to a row of light-emitting units are synchronously refreshed, so that each row of light-emitting units can be synchronously refreshed with each row of sub-pixel units corresponding to the sub-display panel to avoid display misalignment.

[0027] Specifically, Figure 5 For example, the writing time period of the scanning signals of the corresponding at least two rows of the sub-pixel units 111 is the sum of the writing time period T3 of the first scanning signal and the writing time period T4 of the second scanning signal. It can be seen that the writing time period T1 of the first control signal of a row of the light-emitting units 122 is located within the writing time period T3 of the first scanning signal and the writing time period T4 of the second scanning signal.

[0028] like Figures 1 to 6 As shown, an embodiment of the present application provides a spliced ​​display panel, the spliced ​​display panel 1 includes at least two spliced ​​sub-display panels 11 and a plurality of display units 12 located at the splicing of the two sub-display panels 11, each of the display units 12 includes a light-emitting unit 122 and a driving chip 121, and the driving chip 121 is electrically connected to the light-emitting unit 122;

[0029] Among them, the driving chip 121 includes a first cache module 21, a second cache module 23 and a control module 22, the first cache module 21 is configured to cache light-emitting data, the second cache module 23 is electrically connected to the light-emitting unit 122, the control module 22 is electrically connected to the first cache module 21, the control module 22 is electrically connected to the second cache module 23, and the control module 22 is configured to transfer the light-emitting data in the first cache module 21 to the second cache module 23 in response to a first control signal.

[0030] The embodiment of the present application provides a spliced ​​display panel. The spliced ​​display panel 1 includes a first cache module 21, a second cache module 23 and a control module 22 through a driving chip 121. The first cache module 21 is configured to cache light-emitting data, the second cache module 23 is electrically connected to the light-emitting unit 122, the control module 22 is electrically connected to the first cache module 21, and the control module 22 is electrically connected to the second cache module 23. The control module 22 is configured to transfer the light-emitting data in the first cache module 21 to the second cache module 23 in response to a first control signal; so that after each driving chip 121 receives the light-emitting data, the light-emitting data can be temporarily stored in the first cache module 21. When the light-emitting unit needs to be lit, the light-emitting data is transferred from the first cache module 21 to the second cache module 23 through the control module to make the light-emitting unit emit light, so that the turn-on time of the light-emitting unit connected to each driving chip can be controlled, so that each light-emitting unit and the sub-pixel unit in the sub-display panel can be refreshed synchronously to avoid display misalignment.

[0031] Specifically, Figure 1 As shown, the embodiment of the present application is described by taking the spliced ​​display panel 1 including two sub-display panels 11 and four display units 12 located at the splicing of the two sub-display panels 11 as an example, but the embodiment of the present application is not limited to this. The number of sub-display panels of the spliced ​​display panel 1 can be more. For example, the spliced ​​display panel 1 can include four sub-display panels, and the four sub-display panels can be arranged in sequence from left to right, or the four sub-display panels can be arranged in two rows and two columns.

[0032] At the same time, as for the number of display units, a corresponding number of display units 12 can be set according to the difference between the size of the sub-display panel 11 and the size of the display unit 12. For example, the width of each display unit 12 is 1, the width of the sub-display panel 11 is 10, and the width of the non-display area of ​​the sub-display panel 11 is 1, then 9 display units can be set.

[0033] At the same time, for the arrangement of the two sub-display panels, Figure 1 In the figure, two sub-display panels 11 are arranged left and right as an example for explanation, but the embodiments of the present application are not limited to this. The two sub-display panels 11 can be arranged up and down, and the display unit 12 is disposed between the upper and lower frames of the two adjacent sub-display panels 11.

[0034] Specifically, Figure 1 As shown, each sub-display panel 11 may include a display area 101 and a non-display area 102 , and the display unit 12 may be disposed in the non-display area 102 .

[0035] Specifically, compared with the comparison display device, the cache module of each driver chip is directly connected to the light-emitting unit, so that when the signal is input, each light-emitting unit directly emits light and cannot be controlled. The number of light-emitting units is relatively small relative to the number of pixels, so that the data volume is small and the refresh rate of the light-emitting unit is fast, resulting in asynchronous refresh. The embodiment of the present application sets a control module 22 so that the control module 22 can control the time when the data sent to the driver chip is output to the light-emitting unit 122, so that the light-emitting unit 122 can be refreshed synchronously with the sub-pixel unit 111 in the sub-display panel 11 to avoid image misalignment.

[0036] Specifically, at least one light-emitting unit 122 and at least one driver chip 121 may be provided in each display unit 12. More specifically, multiple light-emitting units 122 and multiple driver chips 121 may be provided in each display unit 12, and each driver chip 121 is connected to at least one light-emitting unit 122. The embodiment of the present application is described by taking one driver chip 121 connected to multiple light-emitting units 122 as an example.

[0037] Specifically, the luminous data is the display data of one or more luminous units connected to a driver chip. For example, if a driver chip is connected to two luminous units, the luminous data may be the brightness data or grayscale data of the two luminous units, through which the luminous units can display the required brightness and color.

[0038] Specifically, the first control signal refers to a control signal that controls whether the first cache module and the second cache module transmit data. A unit that responds to the first control signal may be provided in the control module, so that the control module can transmit the data in the first cache module to the second cache module in response to the first control signal.

[0039] Specifically, transferring the light emitting data in the first cache module to the second cache module means that the light emitting data can be directly sent to the second cache module through the first cache module, or that the light emitting data is transferred to the second cache module through the control module. For example, the control module is regarded as a transistor, one electrode of the transistor is connected to the first cache module, the other electrode of the transistor is connected to the second cache module, and the gate of the transistor is controlled by a first control signal. When the transistor is turned on by the first control signal, the light emitting data can be directly sent from the first cache module to the second cache module; in another case, the light emitting data in the first cache module is obtained by the control module and then sent to the second cache module.

[0040] In some embodiments, Figures 1 to 6As shown, the spliced ​​display panel 1 includes a plurality of display units 12, each of the display units 12 includes a plurality of rows of driving chips 121, each of the driving chips 121 includes a first cache module 21, a second cache module 23 and a control module 22, the first cache module 21 is configured to cache light emitting data, the second cache module 23 is electrically connected to the light emitting unit 122, the control module 22 is electrically connected to the first cache module 21, the control module 22 is electrically connected to the second cache module 23, and the control module 22 is configured to transmit the light emitting data in the first cache module 21 to the second cache module 23 in response to a first control signal;

[0041] The spliced ​​display panel 1 is configured such that when the control module 22 of each row of the driving chips 121 responds to a first control signal, the scan lines 112 electrically connected to at least two rows of the sub-pixel units 111 corresponding to a row of the light-emitting units 122 input scan signals.

[0042] Specifically, the driving chip 121 includes a first cache module 21, a second cache module 23 and a control module 22, the first cache module 21 is configured to cache light-emitting data, the second cache module 23 is electrically connected to the light-emitting unit 122, the control module 22 is electrically connected to the first cache module 21, the control module 22 is electrically connected to the second cache module 23, and the control module 22 is configured to transfer the light-emitting data in the first cache module 21 to the second cache module 23 in response to a first control signal; so that after each driving chip 121 receives the light-emitting data, the light-emitting data can be temporarily stored in the first cache module 21, and when the light-emitting unit needs to be lit, the light-emitting data is transferred from the first cache module 21 to the second cache module 23 through the control module to make the light-emitting unit emit light, so that the turn-on time of the light-emitting unit connected to each driving chip can be controlled, so that each light-emitting unit and the sub-pixel unit in the sub-display panel can be refreshed synchronously to avoid display misalignment.

[0043] Specifically, the spliced ​​display panel 1 is configured to input a scan signal to the scan line 112 electrically connected to at least two rows of sub-pixel units 111 corresponding to a row of the light-emitting units 122 when the control module 22 of the driving chip 121 in each row responds to a first control signal, so that when a row of light-emitting units emits light, at least two rows of sub-pixel units corresponding to a row of light-emitting units also emit light, so that each light-emitting unit and the sub-pixel unit in the sub-display panel can be refreshed synchronously to avoid display misalignment.

[0044] In some embodiments, Figure 4As shown, the first cache module 21 includes a data receiving unit 211, a data sending unit 212 and a first register 213; the data sending unit 212 is electrically connected to the data receiving unit 211; the first register 213 is electrically connected to the data receiving unit 211, and the first register 213 is electrically connected to the control module 22;

[0045] The data receiving unit 211 is configured to receive initial data, and parse the initial data to obtain light emitting data, so as to send the light emitting data to the first register 213 .

[0046] Specifically, the initial data refers to display data of all light-emitting units in all display units.

[0047] Specifically, since each driver chip is cascaded together, the data sent from the control board to the driver chip is the data of all light-emitting units, so each driver chip only needs to intercept the display data corresponding to the light-emitting unit connected to the driver chip. Therefore, in the embodiment of the present application, the first cache module 21 includes a data receiving unit 211, a data sending unit 212 and a first register 213, so that after receiving the initial data, the data receiving unit 211 can parse the initial data to obtain the light-emitting data, and send the light-emitting data to the first register, so that each driver chip can drive the corresponding light-emitting unit to display.

[0048] Specifically, for example, the initial data includes display data of 10 light-emitting units. A driver chip drives two light-emitting units, and the light-emitting data stored in the first register of the driver chip is the display data of the two light-emitting units. Another driver chip drives the other two light-emitting units, and the light-emitting data stored in the first register of the other driver chip is the display data of the other two light-emitting units. Similarly, the specific content of the light-emitting data in the first register of each driver chip can be determined.

[0049] Specifically, the first register may include multiple registers.

[0050] Specifically, the data receiving unit 211 may include a parsing unit, and the initial data is parsed into the luminescence data by the parsing unit.

[0051] Specifically, the data sent from the data receiving unit 211 to the data sending unit 212 are initial data, that is, the data transmitted between each driving chip are initial data.

[0052] In some embodiments, Figure 4As shown, the second cache module 23 includes a second register 231, and the second register 231 is electrically connected to the control module 22. By making the second cache module 23 include the second register 231, and the second register 231 is electrically connected to the control module 22, when the control module 22 is connected to the first cache module 21 and the second cache module 23, the light emitting data can be sent to the second register.

[0053] Specifically, the second register may include multiple registers.

[0054] In some embodiments, Figure 4 As shown, the control module 22 includes a control receiving unit 221, a control sending unit 222, a control interpretation unit 223 and a cache transfer unit 224, the control receiving unit 221 is configured to receive a second control signal; the control sending unit 222 is electrically connected to the control receiving unit 221; the control interpretation unit 223 is electrically connected to the control receiving unit 221, and is configured to receive the second control signal and parse the second control signal to obtain a first control signal; the cache transfer unit 224 is electrically connected to the control interpretation unit 223;

[0055] The cache transfer unit 224 is electrically connected to the first register 213 , and the cache transfer unit 224 is electrically connected to the second register 231 . The cache transfer unit 224 is configured to send the light emitting data in the first register 213 to the second register 231 according to the first control signal.

[0056] Specifically, the second control signal refers to the sum of the first control signals to which each driver chip responds. For example, since the embodiment of the present application needs to control the light-emitting time of the light-emitting units 122 of different rows to be synchronized with the sub-pixel units of the sub-display panel 11, the light-emitting units 122 of different rows cannot be directly displayed in sequence, and their turn-on time needs to be controlled by the first control signal. Then, for the light-emitting units 122 connected to different driver chips 121, different first control signals are required to enable them to be turned on within a predetermined time, and the control signal is transmitted from one driver chip 121 to another driver chip 121. Therefore, the second control signal needs to include the first control signal to which each driver chip 121 responds, so that each driver chip 121 responds to its corresponding first control signal to drive the light-emitting unit to emit light.

[0057] For example, the time for one frame of the spliced ​​display panel is 10 seconds, and it takes 10 seconds for all the sub-pixel units in the sub-display panel to refresh, while it only takes 5 seconds for the driver chips 121 in all the display units 12 to directly output data to the corresponding light-emitting units 122. Then, the second control signal can be used to control the turn-on time of the light-emitting units 122 corresponding to each driver chip 121. For example, all the display units 12 include a total of five rows of driver chips 121. The second control signal can be used to control the interval at which each row of driver chips 121 transmits data to the second register 231. The data output of each row of driver chips 121 can be controlled to take 2 seconds. For example, the driver chip 121 of the first row transmits the data output to the second register 231 at the beginning of this frame to make the light-emitting unit 122 emit light, and the driver chip 121 of the second row transmits the data output to the second register 231 in the third second of this frame, so that the light-emitting units 122 connected to each row of driver chips 121 are refreshed synchronously with the sub-pixel units in the sub-display panel 11. In this process, the second control signal is a control signal that controls whether the driver chips 121 of all rows transfer the luminous data in the first cache module 21 to the second cache module 23, and the first control signal is a control signal that controls whether each driver chip 121 transfers the luminous data in the first cache module 21 to the second cache module 23.

[0058] Specifically, since the control receiving unit 221 receives control signals from all driver chips 121, the control interpretation unit needs to parse the second control signal to obtain the first control signal corresponding to each driver chip so that the light-emitting units connected to each driver chip are turned on at the corresponding time.

[0059] Specifically, the signal sent by the control receiving unit 221 to the control sending unit 222 is the second control signal.

[0060] Specifically, the cache transfer unit 224 may be controlled by a first control signal. When the first control signal controls the cache transfer unit to work, the cache transfer unit 224 may transfer the light emitting data in the first register 213 to the second register 231 .

[0061] In some embodiments, Figures 2 to 4As shown, the driver chip 121 also includes at least two data transmission interfaces 24, one of the data transmission interfaces 24 is electrically connected to the previous driver chip 121 and the first cache module 21 of the driver chip 121 at the current level, and the other data transmission interface 24 is electrically connected to the next driver chip 121 and the first cache module 21 of the driver chip 121 at the current level. By providing the data transmission interface 24, when the control board transmits data to the driver chip 121, each driver chip 121 can transmit data, so that each driver chip 121 drives the light-emitting unit to display according to the corresponding data signal.

[0062] Specifically, Figure 2 As shown, it can be seen that the driver chips 121 in a display unit 12 are cascaded. After the control board outputs data to the first driver chip 121, the first driver chip 121 will transmit the data to the second driver chip 121, and transmit it to all the driver chips 121 in the same row in sequence, and then transmit it to all the driver chips 121 in the next row. Between two adjacent display units 12, after all the driver chips in one display unit 12 complete the data transmission, the data will be transmitted to the driver chip in the next display unit 12 until the driver chips in all the display units have completed the data transmission.

[0063] Specifically, the data transmission interface of the first driving chip 121 may be connected to the control board, and the data transmission interface of the last driving chip 121 may be left floating.

[0064] Specifically, Figure 3 As shown, it can be seen that in each driver chip 121, data will be transmitted from a data transmission interface 24 to the first cache module 21 and then to another data transmission interface 24. Between adjacent driver chips 121, data will be transmitted from the data transmission interface 24 of the previous driver chip 121 to the data transmission interface 24 of the next driver chip 121.

[0065] Specifically, Figure 4 As shown, it can be seen that in each driving chip 121, data is transmitted in sequence along a data transmission interface 24, a data receiving unit 211, a data sending unit 212 and another data transmission interface 24, and what is transmitted at this time is initial data.

[0066] Specifically, the data transmission interface 24 may be one or more interfaces and circuits connected to the interfaces in an actual structure.

[0067] In some embodiments, Figures 2 to 4As shown, the driver chip 121 also includes at least two control transmission interfaces 25, one of the control transmission interfaces 25 is electrically connected to the previous driver chip 121 and the control module 22 of the driver chip 121 at this level, and the other control transmission interface 25 is electrically connected to the next driver chip 121 and the control module 22 of the driver chip 121 at this level. By setting the control transmission interface 25, when the control board transmits the control signal to the driver chip 121, each driver chip 121 can transmit the control signal, so that each driver chip 121 sequentially drives the light-emitting unit to display according to the corresponding control signal.

[0068] Specifically, Figure 2 As shown, it can be seen that the driver chips 121 in a display unit 12 are cascaded. After the control board outputs the control signal to the first driver chip 121, the first driver chip 121 will transmit the control signal to the second driver chip 121, and transmit it to all the driver chips 121 in the same row in sequence, and then transmit it to all the driver chips 121 in the next row. Between two adjacent display units 12, after all the driver chips in one display unit 12 complete the control signal transmission, the control signal will be transmitted to the driver chip in the next display unit 12 until all the driver chips in all the display units have completed the control signal transmission.

[0069] Specifically, the control transmission interface of the first driving chip 121 may be connected to the control board, and the control transmission interface of the last driving chip 121 may be left floating.

[0070] Specifically, Figure 3 As shown, it can be seen that within each driver chip 121, the control signal will be transmitted from one control transmission interface 25 to the control module 22 and then to another control transmission interface 25. Between adjacent driver chips 121, the control signal will be transmitted from the control transmission interface 25 of the previous driver chip 121 to the control transmission interface 25 of the next driver chip 121.

[0071] Specifically, Figure 4 As shown, it can be seen that in each driving chip 121, the control signal is transmitted in sequence along a control transmission interface 25, a control receiving unit 221, a control sending unit 222 and another control transmission interface 25, and what is transmitted at this time is the second control signal.

[0072] Specifically, the control transmission interface 25 may be one or more interfaces and circuits connected to the interfaces in an actual structure.

[0073] Specifically, in the embodiment of the present application, the first cache module, the second cache module and the control module may have a specific circuit structure.

[0074] Specifically, the data receiving unit, the data sending unit, the control receiving unit, the control sending unit, the control interpretation unit and the cache transport unit may have a specific circuit structure.

[0075] In some embodiments, Figure 2 , Figure 3 , Figure 5 As shown, the sub-display panel 11 includes a plurality of rows of sub-pixel units 111 and a plurality of rows of scan lines 112 electrically connected to the sub-pixel units 111, and the sub-pixel units 111 are configured to write display data when the scan lines 112 input scan signals;

[0076] Among them, each of the display units 12 includes at least one row of the driving chips 121 and at least one row of the light-emitting units 122, and a row of the light-emitting units 122 is arranged corresponding to at least two rows of the sub-pixel units 111. The spliced ​​display panel 1 is configured to input a scanning signal to the scanning line 112 electrically connected to at least two rows of the sub-pixel units 111 corresponding to a row of the light-emitting units 122 when the control module 22 of each row of the driving chips 121 responds to a first control signal.

[0077] Specifically, Figure 2 As shown, the sub-display panel 11 further includes data lines 113 , through which corresponding data signals can be input to each sub-pixel unit to make each sub-pixel unit emit light.

[0078] Specifically, since the resolution of the sub-display panel 11 is generally higher than the resolution of the display unit 12, the space occupied by each row of light-emitting units 122 is actually equal to the space occupied by two rows of sub-pixel units 111 or even more rows of sub-pixel units 111, so that a row of light-emitting units 122 can be set corresponding to two or more rows of sub-pixel units 111. When displaying, when a row of light-emitting units 122 emits light, the corresponding two or more rows of sub-pixel units 111 are displayed, and when the next row of light-emitting units 122 emits light, the corresponding two or more rows of sub-pixel units 111 are displayed, thereby avoiding the misalignment of the picture. Therefore, by making the control module 22 of each row of the driving chip 121 respond to the first control signal, the scanning line 112 electrically connected to at least two rows of sub-pixel units 111 corresponding to a row of the light-emitting units 122 inputs the scanning signal, it can be achieved that every time a row of light-emitting units 122 is refreshed, two rows of sub-pixel units will be refreshed synchronously.

[0079] Specifically, each row of driving chips 121 is connected to a row of light-emitting units 122 and drives the light-emitting units 122 in the corresponding row.

[0080] Specifically, when the spliced ​​display panel displays, the first control signal can be controlled so that after each driver chip 121 receives the luminous data, the luminous data is first stored in the first register. When the corresponding time is reached, the luminous data is sent to the second register through the first control signal, so that each row of the luminous unit 122 is synchronously refreshed with the corresponding sub-pixel unit 111.

[0081] In some embodiments, Figure 2 , Figure 3 , Figure 5 As shown, one row of the light-emitting units 122 is arranged corresponding to two rows of the sub-pixel units 111, and the length of the writing time period T1 of the first control signal responded by the control module 22 of each row of the driving chip 121 is equal to the length of the writing time period T3 of the scanning signal input by the scanning line 112 connected to each row of the sub-pixel units 111, and an invalid time period T2 is provided between the writing time period T1 of the first control signal responded by the control module 22 of two adjacent rows of the driving chip 121, and the length of the invalid time period T2 is equal to the length of the writing time period T3 of the scanning signal input by the scanning line 112 connected to each row of the sub-pixel units 111. By setting an invalid time period T2 between the write time periods T1 of the first control signal responded to by the control module 22 of two adjacent rows of driver chips 121, and making the length of the invalid time period T2 equal to the length of the write time period of the scan signal input by the scan line 112 connected to each row of sub-pixel units 111, the refresh time occupied by the light-emitting units connected to each row of driver chips is equal to the refresh time of the multiple rows of sub-pixel units corresponding to one row of driver chips, so that each row of light-emitting units is refreshed synchronously with the corresponding multiple rows of sub-pixel units.

[0082] Specifically, Figure 5 As shown, taking the example that the length of the write time period T3 of the first scanning signal is equal to the length of the write time period T3 of the second scanning signal, the length of the write time period T1 of the first control signal is equal to the length of the write time period T3 of the first scanning signal, and the length of the invalid time period T2 is equal to the length of the write time period T4 of the second scanning signal.

[0083] Specifically, Figure 5As shown, taking the first scan signal driving the sub-pixel units 111 of the first row, the second scan signal driving the sub-pixel units 111 of the second row, and the first control signal responded by a row of driver chips controlling the control module 22 of the first row of driver chips as an example, it can be seen that within the writing time period T1 of the first control signal, the sub-pixel units 111 of the first row complete the data writing, and the control modules 22 of the driver chips 121 of the first row are all turned on, so that the light-emitting units 122 connected to the driver chips 121 of the first row all complete the data writing, and within the invalid time period T2 of the first control signal, the sub-pixel units 111 of the second row complete the data writing, and the light-emitting units 122 connected to the driver chips 121 of the first row are continuously lit; then the light-emitting units 122 connected to the driver chips 121 of the second row are synchronously written with the sub-pixel units 111 of the third row, and when the sub-pixel units 111 of the fourth row are written with data, the light-emitting units 122 connected to the driver chips 121 of the second row are continuously lit, thereby realizing the synchronous refresh of the light-emitting units 122 of each row and the corresponding two or even multiple rows of sub-pixel units 111.

[0084] Specifically, the write time period refers to the time for writing a valid level, and the invalid time period refers to the time for not writing a valid level. It can be understood that during the time for writing a valid level, an invalid level will be set between each valid level, but it is still considered to belong to the write time period.

[0085] Specifically, it can be understood that when a row of driver chips includes multiple driver chips, the first control signal responded by each driver chip is a part of the first control signal responded by a row of driver chips 121. This is for the purpose of illustrating that a row of driver chips 121 connects the light-emitting unit 122 with the corresponding two or even multiple rows of sub-pixel units 111 for synchronous refresh. In fact, the first control signal responded by each driver chip is a part of the first control signal responded by a row of driver chips 121.

[0086] Specifically, the embodiment of the present application is described by taking a high level as a valid level and a low level as an invalid level as an example.

[0087] Specifically, Figure 5 In the example, the first control signal responded by a row of driver chips 121 is not output during the invalid time period. The first control signal responded by a row of driver chips 121 can output a low level during the invalid time period. Then, the first control signal of the last driver chip in a row of driver chips 121 can include a high level output during the writing time period and a low level output during the invalid time period.

[0088] In some embodiments, Figure 2 , Figure 3 , Figure 6As shown, a row of the light-emitting units 122 is arranged correspondingly to two rows of the sub-pixel units 111, and the duration of the writing time period T1 of the first control signal responded by the control module 22 of each row of the driving chip 121 is equal to the duration of the writing time period of the scanning signal input by the scanning line 112 connected to each two rows of the sub-pixel units 111. By making the duration of the writing time period T1 of the first control signal responded by the control module 22 of each row of the driving chip 121 equal to the duration of the writing time period of the scanning signal input by the scanning line 112 connected to each two rows of the sub-pixel units 111, the refresh time occupied by the light-emitting units connected to each row of the driving chip is equal to the refresh time of the multiple rows of sub-pixel units corresponding to one row of the driving chip, so that each row of the light-emitting units is refreshed synchronously with the corresponding multiple rows of sub-pixel units.

[0089] Specifically, Figure 6 As shown, the duration of the writing time period T1 of the first control signal is equal to the sum of the duration of the writing time period T3 of the first scanning signal and the duration of the writing time period T4 of the second scanning signal.

[0090] Specifically, the driving chip 121 further includes a digital-to-analog conversion unit 26 , an amplifier (not shown) and other components, which will not be described in detail here.

[0091] Specifically, the light emitting unit may be a light emitting diode.

[0092] Specifically, the sub-display panel may be a liquid crystal display panel.

[0093] Specifically, when driving the spliced ​​display panel, when each driving chip receives the data of the next frame through the data transmission interface, the luminous data can be stored in the first register, waiting for the control transmission interface to receive the control signal, and when the control signal sending time arrives, the luminous data is updated from the first register to the second register through the control module to drive the light-emitting unit.

[0094] The sending time of the control signal needs to be aligned with the sending time of the scanning signal of the scanning line corresponding to the sub-pixel unit. For example, when a row of light-emitting units is set corresponding to two rows of sub-pixel units, the duration occupied by the sending time of the first control signal in each row of the driving chip is equal to the duration occupied by the sending time of the scanning signal of the scanning line corresponding to the two rows of sub-pixel units, thereby achieving synchronous refresh of each row of light-emitting units and the corresponding multiple rows of sub-pixel units.

[0095] Specifically, the above-mentioned embodiments have provided a detailed description of the spliced ​​display panel from aspects of the sub-display panel, the display unit, the timing, etc. of the spliced ​​display panel. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the second cache module includes a second register, the second register is electrically connected to the control module, and the light-emitting unit can be a light-emitting diode.

[0096] At the same time, an embodiment of the present application provides a spliced ​​display device, which includes a spliced ​​display panel as described in any of the above embodiments.

[0097] Specifically, the spliced ​​display device may include a control board, which may be connected to a driving chip to send display data and control signals to the driving chip.

[0098] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0099] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0100] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0101] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A spliced ​​display panel, characterized in that: include: At least two sub-display panels are spliced ​​together, each of the sub-display panels comprises a plurality of rows of sub-pixel units and a plurality of rows of scan lines, the plurality of rows of scan lines are electrically connected to the plurality of rows of sub-pixel units respectively, and the sub-pixel units are configured to write display data when a scan signal is input to the scan line; A display unit, located at the joint of the two sub-display panels, the display unit includes a driving chip and at least one row of light-emitting units, the light-emitting units are electrically connected to the driving chip, and the light-emitting units are configured to write light-emitting data when the driving chip inputs a first control signal; Among them, one row of the light-emitting units is arranged correspondingly to at least two rows of the sub-pixel units, and the writing time period of the first control signal of each row of the light-emitting units is located within the writing time period of the scanning signal of the corresponding at least two rows of the sub-pixel units.

2. The spliced ​​display panel according to claim 1, characterized in that: The spliced ​​display panel includes a plurality of display units, each of the display units includes a plurality of rows of driver chips, each of the driver chips includes a first cache module, a second cache module and a control module, the first cache module is configured to cache light emitting data, the second cache module is electrically connected to the light emitting unit, the control module is electrically connected to the first cache module, the control module is electrically connected to the second cache module, and the control module is configured to transmit the light emitting data in the first cache module to the second cache module in response to a first control signal; The spliced ​​display panel is configured such that when the control module of each row of the driving chip responds to a first control signal, the scan lines electrically connected to at least two rows of sub-pixel units corresponding to a row of the light-emitting units input scan signals.

3. The spliced ​​display panel according to claim 2, characterized in that: The first cache module includes: Data receiving unit; A data sending unit, electrically connected to the data receiving unit; a first register electrically connected to the data receiving unit, and the first register electrically connected to the control module; The data receiving unit is configured to receive initial data, and parse the initial data to obtain light emitting data, so as to send the light emitting data to the first register.

4. The spliced ​​display panel according to claim 3, characterized in that: The second cache module includes a second register, and the second register is electrically connected to the control module.

5. The spliced ​​display panel according to claim 4, characterized in that: The control module comprises: A control receiving unit, configured to receive a second control signal; A control sending unit, electrically connected to the control receiving unit; a control interpretation unit, electrically connected to the control receiving unit, configured to receive the second control signal and analyze the second control signal to obtain a first control signal; A cache transport unit, electrically connected to the control and interpretation unit; The cache transfer unit is electrically connected to the first register, the cache transfer unit is electrically connected to the second register, and the cache transfer unit is configured to transfer the light emitting data in the first register to the second register according to the first control signal.

6. The spliced ​​display panel according to any one of claims 2 to 5, characterized in that: The driver chip also includes at least two data transmission interfaces, one of which is electrically connected to the previous driver chip and the first cache module of the driver chip at this level, and the other of which is electrically connected to the next driver chip and the first cache module of the driver chip at this level.

7. The spliced ​​display panel according to any one of claims 2 to 5, characterized in that: The driver chip also includes at least two control transmission interfaces, one of which is electrically connected to the previous driver chip and the control module of the driver chip at this level, and the other is electrically connected to the next driver chip and the control module of the driver chip at this level.

8. The spliced ​​display panel according to any one of claims 2 to 5, characterized in that: A row of the light-emitting units is arranged corresponding to two rows of the sub-pixel units, and the length of the writing time period of the first control signal responded by the control module of each row of the driving chip is equal to the length of the writing time period of the scanning signal input by the scanning line connected to each row of the sub-pixel units, and an invalid time period is provided between the writing time periods of the first control signal responded by the control modules of the driving chips of two adjacent rows, and the length of the invalid time period is equal to the length of the writing time period of the scanning signal input by the scanning line connected to each row of the sub-pixel units.

9. The spliced ​​display panel according to any one of claims 2 to 5, characterized in that: One row of the light-emitting units is arranged correspondingly to two rows of the sub-pixel units, and the length of the writing time period of the first control signal responded by the control module of each row of the driving chip is equal to the length of the writing time period of the scanning signal input by the scanning line connecting every two rows of the sub-pixel units.

10. A splicing display device, characterized in that: It comprises a spliced ​​display panel as claimed in any one of claims 1 to 9.

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