Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, relates to the technical field of display, and is used for avoiding the splash screen problem of the display panel when abnormal power failure of the display panel occurs. In the display panel, a light-emitting control unit comprises an output module which responds to a signal of a first node and is electrically connected with a first level signal end and an output end of the output module; and in response to the signal of the second node, electrically connecting a second level signal end and the output end of the output module, the first control module responds to a signal of a first control signal end and is electrically connected with a second level signal end and the first node; the light-emitting control circuit further comprises a second control module which responds to a signal of a second control signal end and is electrically connected with the first adjusting signal end and the first control signal end. When the display panel works, the first control signal end and the second control signal end both provide disable levels; the potential of the first adjusting signal end is smaller than the potential of a signal on the first control signal line.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, consumers' requirements for display screens are constantly increasing. At present, various types of displays, including organic light-emitting display screens, are emerging in an endless stream and have been developing rapidly. On this basis, display technologies such as 3D display, touch display technology, curved display, and ultra-high resolution display are also emerging.

[0003] Currently, the display panel has a screen flickering phenomenon when an abnormal power outage occurs. Summary of the invention

[0004] In view of this, the present application provides a display panel and a driving method thereof, and a display device to improve the screen flickering problem of the display panel when abnormal power failure occurs.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including a light emitting control circuit, the light emitting control circuit including a plurality of cascaded light emitting control units, the light emitting control unit including: an output module, in response to a signal of a first node, electrically connecting a first level signal terminal and an output terminal of the output module; and, in response to a signal of a second node, electrically connecting a second level signal terminal and an output terminal of the output module; A first control module, in response to a signal at the first control signal terminal, electrically connects the second level signal terminal and the first node; The light emitting control circuit further includes a second control module, which is electrically connected to the first level signal terminal and the first control signal terminal in response to a second control signal; When the display panel is working, the first control signal terminal and the second control signal terminal both provide a non-enable level, and the potential of the signal at the first adjustment signal terminal is smaller than the potential of the signal at the first control signal terminal.

[0006] In a second aspect, an embodiment of the present invention provides a driving method for the above display panel, the driving method comprising: When the display panel is working, a non-enable level is provided to both the first control signal terminal and the second control signal terminal, and the potential of the first adjustment signal terminal is controlled to be smaller than the potential of the signal at the first control signal terminal.

[0007] In a third aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0008] By adopting the scheme provided by the embodiment of the present invention, when the display panel is abnormally powered off, such as when the power supply is suddenly cut off, the potential of the signal on the second control signal end drops rapidly, and the second control module is controlled to be turned on. Since the potential of the first adjustment signal end at the moment when the display panel is abnormally powered off is the potential of the display panel when it is working normally, that is, at the moment when the abnormal power off occurs, the potential of the first adjustment signal end is lower than the potential of the signal on the first control signal end, therefore, the charge at the first control signal end can flow to the first adjustment signal end through the turned-on second control module, thereby forming a charge discharge path. In other words, the signal at the first adjustment signal end can be quickly written to the first control signal end through the turned-on second control module, so that the voltage at the first control signal end is reduced.

[0009] Under the control of the signal at the first control signal end, the first control module is turned on, thereby quickly providing the voltage provided by the second level signal end to the first node, so as to prevent the voltage provided by the first level signal end from being output to the output end of the light-emitting control unit, thereby preventing the light-emitting control module of the pixel driving circuit from being turned on, thereby preventing the light-emitting element from lighting up, and preventing display abnormalities such as screen flickering from occurring on the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention; Figure 2 A schematic diagram of a sub-pixel circuit provided by an embodiment of the present invention; Figure 3 A schematic diagram of a light emitting control circuit provided by an embodiment of the present invention; Figure 4 A circuit diagram of a light emitting control unit provided by an embodiment of the present invention; Figure 5 A working timing diagram of a light emitting control unit provided by an embodiment of the present invention; Figure 6 A schematic diagram of the positional relationship between a light emitting control unit, a second control module and a chip binding area provided in an embodiment of the present invention; Figure 7 A schematic diagram of another light emitting control circuit provided by an embodiment of the present invention; Figure 8 A schematic diagram of another light emitting control circuit provided by an embodiment of the present invention; Fig. 9 A schematic diagram of another light emitting control circuit provided by an embodiment of the present invention; Fig.10 A schematic diagram of another display panel provided by an embodiment of the present invention; Fig.11 A schematic diagram of another light emitting control circuit provided by an embodiment of the present invention; Fig.12 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0012] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0013] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0015] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0016] An embodiment of the present invention provides a display panel, such as Figure 1 As shown, Figure 1 Schematic diagram of a display panel provided by an embodiment of the present invention, the display panel includes a plurality of sub-pixels 1 and a light emitting control circuit 2. The light emitting control circuit 2 can generate a light emitting control signal for controlling the sub-pixels 1 to light up or turn off. Figure 1 As shown, the sub-pixel 1 is located in the display area AA of the display panel, and the light emitting control circuit 2 is located in the non-display area NA of the display panel.

[0017] Combination Figure 2 As shown, Figure 2A circuit diagram of a sub-pixel provided in an embodiment of the present invention, the sub-pixel 1 includes an electrically connected pixel driving circuit 11 and a light-emitting element 12. The pixel driving circuit 11 is used to receive a data voltage Data, a first power supply voltage PVDD, and a second power supply voltage PVEE, and generate a driving current. When the light-emitting control signal E is at an enable level, the driving current flows through the light-emitting element 12 to light up the light-emitting element 12. When the light-emitting control signal E is at a non-enable level, the driving current cannot flow through the light-emitting element 12, thereby controlling the light-emitting element 12 to extinguish. Exemplarily, the light-emitting element 12 includes any one of an organic light-emitting diode (OLED), a micro light-emitting diode (Micro-LED), and a quantum dot light-emitting diode (QLED), which is not limited in the embodiment of the present invention.

[0018] Optional, such as Figure 2 As shown, the pixel driving circuit 11 includes a storage capacitor Cst, a driving transistor M11, a first reset module 111, a data writing module 112, a threshold compensation module 113, a light emitting control module 114 and a second reset module 115.

[0019] Among them, the two plates of the storage capacitor Cst are electrically connected to the first power supply voltage terminal PVDD and the gate of the driving transistor M11 respectively. The first reset module 111 responds to the first scan signal to reset the potential of the gate of the driving transistor M11 during the reset period. The data writing module 112 responds to the second scan signal to write the data voltage to the first electrode of the driving transistor M11 during the data writing and threshold compensation period. The threshold compensation module 113 compensates the threshold voltage of the driving transistor M11 during the data writing and threshold compensation period. The second reset module 115 responds to the first scan signal to reset the electrode of the light-emitting element 12 during the reset period. The light-emitting control module 114 responds to the above-mentioned light-emitting control signal to control the light-emitting element 12 to light up during the light-emitting period; and, in the above-mentioned reset period and data writing and threshold compensation period, control the light-emitting element 12 to extinguish.

[0020] Optional, such as Figure 2As shown, the first reset module 111 includes a first reset transistor M12, whose gate is electrically connected to the first scan signal terminal S1, and whose first and second electrodes are electrically connected to the reset signal terminal Vref and the gate of the driving transistor M11 respectively. The data writing module 112 includes a data writing transistor M13, whose gate is electrically connected to the second scan signal terminal S2, and whose first and second electrodes are electrically connected to the data signal terminal Data and the first electrode of the driving transistor M11 respectively. The threshold compensation module 113 includes a threshold compensation transistor M14, whose gate is electrically connected to the second scan signal terminal S2, whose first electrode is electrically connected to the second electrode of the driving transistor M11, and whose second electrode is electrically connected to the gate of the driving transistor M11. The light emitting control module 114 includes a first light emitting control transistor M15 and a second light emitting control transistor M16, whose gates are both electrically connected to the light emitting control signal terminal E, whose first electrode is electrically connected to the first power supply voltage terminal PVDD, and whose second electrode is electrically connected to the first electrode of the driving transistor M11. The first electrode of the second light emitting control transistor M16 is electrically connected to the second electrode of the driving transistor M11, and whose second electrode is electrically connected to the first electrode of the light emitting element 12. The second reset module 115 includes a second reset transistor M17, whose gate is electrically connected to the first scan signal terminal S1, the first electrode is electrically connected to the reset signal terminal Vref, and the second electrode is electrically connected to the first electrode of the light emitting element 12. The second electrode of the light emitting element 12 is electrically connected to the second power supply voltage terminal PVEE.

[0021] For example, Figure 1 As shown, the display panel also includes a plurality of light-emitting control lines EL, which electrically connect the light-emitting control circuit 2 and the sub-pixel 1 to provide the light-emitting control signal generated by the light-emitting control circuit 2 to the light-emitting control signal terminal E of the sub-pixel 1.

[0022] It should be noted that Figure 2 The pixel driving circuit 11 shown is only a schematic diagram. The embodiment of the present invention can also adjust the structure of the pixel driving circuit 11 according to different display requirements. For example, the embodiment of the present invention can also set the pixel driving circuit 11 to include other numbers of transistors, which is not limited by the embodiment of the present invention.

[0023] In addition, the display panel also includes a scanning control circuit for providing the first scanning signal and the second scanning signal, and a scanning line electrically connecting the scanning control circuit and the sub-pixel. Figure 1 The schematic diagram of other structures other than the light emitting control circuit 2, the light emitting control signal line EL and the sub-pixel 1, such as the scanning control circuit and the scanning line, is omitted.

[0024] Optional, such as Figure 3 As shown, Figure 3It is a schematic diagram of a light emitting control circuit provided by an embodiment of the present invention. The light emitting control circuit 2 includes a plurality of cascaded light emitting control units 21 .

[0025] Combination Figure 4 As shown, Figure 4 The circuit diagram of a light emitting control unit provided by an embodiment of the present invention is as follows: the light emitting control unit 21 includes an output module 211 and a first control module 212. The output module 211 is electrically connected to an output terminal OUT of the light emitting control unit 21.

[0026] like Figure 4 As shown, the output module 211 includes a first output transistor M21 and a second output transistor M22. The gate of the first output transistor M21 is electrically connected to the first node N1, the first electrode is electrically connected to the first level signal terminal VGL, and the second electrode is electrically connected to the output terminal OUT. The gate of the second output transistor M22 is electrically connected to the second node N2, the first electrode is electrically connected to the second level signal terminal VGH, and the second electrode is electrically connected to the output terminal OUT.

[0027] The potential of the signal provided by the first level signal terminal VGL is less than the potential of the signal provided by the second level signal terminal VGH. Figure 3 The light emitting control module 114 in the pixel driving circuit 11 shown in the figure is turned on. The signal provided by the second level signal terminal VGH can control Figure 3 The light emission control module 114 in the pixel driving circuit 11 is shown to be turned off.

[0028] like Figure 4 As shown, the first control module 212 electrically connects the second level signal terminal VGH and the first node N1 in response to the signal of the first control signal terminal RST1.

[0029] like Figure 3 As shown, the light emitting control circuit 2 further includes a second control module 22 , which responds to a signal of the second control signal terminal RST2 and electrically connects the first adjustment signal terminal V1 and the first control signal terminal RST1 of the multi-stage light emitting control unit 21 .

[0030] When the display panel is working normally, the first control signal terminal RST1 and the second control signal terminal RST2 both provide a non-enable level. In the embodiment of the present invention, the non-enable level of the first control signal terminal RST1 refers to a level that can control the first control module 212 to be turned off. The non-enable level of the second control signal terminal RST2 refers to a level that can control the second control module 22 to be turned off. The first adjustment signal terminal V1 receives a DC voltage, and illustratively, the potential of the first adjustment signal terminal V1 is less than the potential of the signal of the first control signal terminal RST1.

[0031] Exemplarily, the disabling level of the first control signal terminal RST1 and the disabling level of the second control signal terminal RST2 may be equal to the voltage of the signal provided by the second level signal terminal VGH.

[0032] By adopting the solution provided by the embodiment of the present invention, when the display panel is abnormally powered off, such as when the power supply is suddenly cut off, the potential of the signal on the second control signal terminal RST2 drops rapidly, and the second control module 22 is controlled to be turned on. Since the potential of the first adjustment signal terminal V1 at the moment when the display panel is abnormally powered off is the potential of the display panel when it is working normally, that is, at the moment when the abnormal power off occurs, the potential of the first adjustment signal terminal V1 is lower than the potential of the signal on the first control signal terminal RST1, therefore, the charge on the first control signal terminal RST1 can flow to the first adjustment signal terminal V1 through the turned-on second control module 22, thereby forming a charge discharge path. In other words, the signal of the first adjustment signal terminal V1 can be quickly written into the first control signal terminal RST1 through the turned-on second control module 22, so that the voltage of the first control signal terminal RST1 is quickly reduced.

[0033] Combination Figure 4 As shown, under the control of the signal of the first control signal terminal RST1, the first control module 212 is turned on, so that the voltage provided by the second level signal terminal VGH is quickly provided to the first node N1, so as to control the first output transistor M21 to be quickly turned off, so as to prevent the voltage provided by the first level signal terminal VGL from being output to the output terminal OUT of the light emitting control unit 21, thereby preventing Figure 2 The light emitting control module 114 of the pixel driving circuit 11 shown is turned on, thereby preventing the light emitting element 12 from lighting up and preventing abnormal display problems such as screen flickering on the display panel.

[0034] Optional, such as Figure 4 As shown, the light emitting control unit 21 further includes a first processing module 213 and a second processing module 214, wherein the first processing module 213 is electrically connected to the input terminal IN and the second clock signal terminal XCK, and provides a signal to the first node N1. The second processing module 214 is electrically connected to the first clock signal terminal CK, the second level signal terminal VGH, the first level signal terminal VGL, and the second clock signal terminal XCK, and provides a signal to the second node N2.

[0035] Combination Figure 5 As shown, Figure 5 The present invention provides a timing diagram of a light emitting control unit, wherein the signals of the first clock signal terminal CK and the second clock signal terminal XCK are both pulse signals. Exemplarily, the periods of the two signals may be the same.

[0036] For example, Figure 4As shown, the first processing module 213 includes a first transistor M31, a fourth transistor M34 and an eighth transistor M38. Among them, the gate of the first transistor M31 is electrically connected to the first node N1, the first electrode is electrically connected to the second clock signal terminal XCK, and the second electrode is electrically connected to the third node N3; the gate of the fourth transistor M34 is electrically connected to the first clock signal terminal CK, the first electrode is electrically connected to the input terminal IN, and the second electrode is electrically connected to the first node N1; the gate of the eighth transistor M38 is electrically connected to the fourth node N4, the first electrode is electrically connected to the second level signal terminal VGH, and the second electrode is electrically connected to the third node N3.

[0037] like Figure 4 As shown, the first processing module 213 also includes a second capacitor C22, and two plates of the second capacitor C22 are respectively connected to the third node N3 and the first node N1. When the second clock signal terminal XCK jumps from a high level to a low level, the potential of the first node N1 changes from a low level to a third level smaller than the low level under the action of the second capacitor C22, and the first output transistor M21 can be stably turned on, and the signal of the first level signal terminal VGL is stably provided to the output terminal OUT.

[0038] For example, Figure 4 As shown, the second processing module 214 includes a second transistor M32, a third transistor M33, a fifth transistor M35, a sixth transistor M36 and a seventh transistor M37: wherein the gate of the second transistor M32 is electrically connected to the first node N1, the first electrode and the second electrode are electrically connected to the first clock signal terminal CK and the fourth node N4 respectively, and the second transistor M32 may include two transistors connected in series. The gate of the fifth transistor M35 is electrically connected to the first clock signal terminal CK, the first electrode is electrically connected to the first level signal terminal VGL, and the second electrode is electrically connected to the fourth node N4.

[0039] like Figure 4 As shown, the second processing module 214 further includes a first capacitor C21, a first plate of the first capacitor C21 is electrically connected to the fourth node N4, and a second plate of the first capacitor C21 is electrically connected to the fifth node N5.

[0040] like Figure 4 As shown, the gate of the third transistor M33 is electrically connected to the fourth node N4, the first electrode is electrically connected to the second clock signal terminal XCK, and the second electrode is electrically connected to the fifth node N5. When the fourth node N4 is low and the second clock signal terminal XCK jumps from a high level to a low level, the low level signal provided by the second clock signal terminal XCK writes the fifth node N5 low through the turned-on third transistor M23. The fourth node N4 is pulled lower under the action of the first capacitor C21, so that the third transistor M33 is stably kept in the turned-on state.

[0041] like Figure 4As shown, the gate of the seventh transistor M37 is electrically connected to the second clock signal terminal XCK, the first electrode is electrically connected to the fifth node N5, and the second electrode is electrically connected to the second node N2; the gate of the sixth transistor M36 is electrically connected to the first node N1, the first electrode is electrically connected to the second level signal terminal VGH, and the second electrode is electrically connected to the second node N2; For example, Figure 4 As shown, the light emitting control unit 21 further includes a first protection transistor M41 and a second protection transistor M42, and the gates of both are electrically connected to the first level signal terminal VGL.

[0042] Optional, such as Figure 4 As shown, the first node N1 includes a first subnode N11 and a second subnode N12. The first subnode N11 is electrically connected to the gate of the first output transistor M21 and the second capacitor C2. The second subnode N12 is electrically connected to the gate of the second transistor M32 and the second electrode of the fourth transistor M34.

[0043] The first electrode of the first protection transistor M31 is electrically connected to the second subnode N12, and the second electrode is electrically connected to the first subnode N11. When the potential of the first subnode N11 is coupled to a potential lower than the potential of the first level signal terminal VGL by the second capacitor C2, the first protection transistor M31 can be disconnected, thereby preventing the potential of the second subnode N12 from being too low, thereby improving the reliability of the second transistor M32 and the fourth transistor M34 electrically connected to the second subnode N12.

[0044] For example, Figure 4 As shown, the fourth node N4 includes a third subnode N41 and a fourth subnode N42, the third subnode N41 is electrically connected to the first capacitor C21 and the gate of the third transistor M33, and the fourth subnode N42 is electrically connected to the gate of the eighth transistor M38 and the second electrode of the fifth transistor M35.

[0045] The first electrode of the second protection transistor M42 is electrically connected to the fourth subnode N42, and the second electrode is electrically connected to the third subnode N41. When the potential of the third subnode N41 is coupled to a potential lower than the potential of the first level signal terminal VGL by the first capacitor C1, the second protection transistor M32 can be disconnected, thereby preventing the potential of the fourth subnode N42 from being too low, and further improving the reliability of the eighth transistor M38 and the fifth transistor M35 electrically connected to the fourth subnode N42.

[0046] Optional, such as Figure 4 As shown, the light emitting control unit 21 further includes a third capacitor C23, and two plates of the third capacitor C23 are electrically connected to the second level signal terminal VGH and the second node N2 respectively.

[0047] For example, Figure 3 As shown, the display panel further includes a start signal line STV, a first level signal line LL, a second level signal line LH, a first clock signal line LK1, a second clock signal line LK2, a first control signal line LR1, a second control signal line LR2 and a first adjustment signal line LV1.

[0048] The input terminal IN of the first-stage light emitting control unit 21 is electrically connected to the start signal line STV, and the input terminals IN of the other-stage light emitting control units 21 are electrically connected to the output terminals OUT of the previous-stage light emitting control unit 21 .

[0049] The first clock signal line LK1 electrically connects the first clock signal terminal CK of the odd-numbered stage light emitting control unit 21 and the second clock signal terminal XCK of the even-numbered stage light emitting control unit 21 .

[0050] The second clock signal line LK2 electrically connects the second clock signal terminal XCK of the odd-numbered stage light emitting control unit 21 and the first clock signal terminal CK of the even-numbered stage light emitting control unit 21 .

[0051] The first level signal line LL is electrically connected to the first level signal terminal VGL of the multi-level light emitting control unit 21 ; the second level signal line LH is electrically connected to the second level signal terminal VGH of the multi-level light emitting control unit 21 .

[0052] The first control signal line LR1 is electrically connected to the first control signal terminal RST1 of the multi-stage light emitting control unit 21. The second control signal line LR2 is electrically connected to the second control signal terminal RST2 of the second light emitting control module 22. The first adjustment signal line LV1 is electrically connected to the first adjustment signal terminal V1 of the second light emitting control module 22.

[0053] Exemplarily, in the embodiment of the present invention, the length of the second control signal line LR2 is less than the length of the first control signal line LR1. Based on this setting, the coupling capacitance between the second control signal line LR2 and other structures in the display panel can be made smaller than the coupling capacitance between the first control signal line LR1 and other structures in the display panel, so that when the display panel is abnormally powered off, the signal on the second control signal line LR2 can be quickly reduced.

[0054] Exemplarily, the length of the first control signal line LR1 is L1, the length of the second control signal line LR2 is L2, and L2 / L1≤1 / 10.

[0055] For example, Figure 6 As shown, Figure 6A schematic diagram of the positional relationship of a light-emitting control unit, a second control module and a chip binding area provided in an embodiment of the present invention, the display panel also includes a chip binding area BA, the chip binding area BA is used to set the driver chip 3, and at least one of the above-mentioned start signal line STV, the first level signal line LL, the second level signal line LH, the first clock signal line LK1, the second clock signal line LK2, the first control signal line LR1, the second control signal line LR2 and the first adjustment signal line LV1 is electrically connected to the driver chip 3 to receive the corresponding required electrical signal from the driver chip 3. Figure 6 As an example, the start signal line STV, the first level signal line LL, the second level signal line LH, the first clock signal line LK1, the second clock signal line LK2, the first control signal line LR1, the second control signal line LR2 and the first adjustment signal line LV1 are all electrically connected to the driving chip 3. For example, Figure 6 As shown, at least part of the second control module 22 is located on the side of the light-emitting control unit 21 close to the chip binding area BA. Based on this setting, the distance between the second control module 22 and the driving chip 3 can be shortened, which is beneficial to shorten the length of the second control signal line LR2 and reduce the parasitic capacitance of the second control signal line LR2. When the display panel is abnormally powered off, it is beneficial to allow the signal on the second control signal line LR2 to change quickly.

[0056] Optional, such as Figure 4 As shown, the first control module 212 includes a first control transistor M51, whose gate is electrically connected to the first control signal terminal RST1, the first electrode is electrically connected to the second level signal terminal VGH, and the second electrode is electrically connected to the first node N1. Optionally, the first control transistor M51 includes a P-type transistor.

[0057] like Figure 7 As shown, Figure 7 A schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention, wherein the second control module 22 includes a second control transistor M52, a gate of which is electrically connected to the second control signal terminal RST2, the second control signal terminal RST2 is electrically connected to the second control signal line LR2, a first pole is electrically connected to the first adjustment signal terminal V1, and a second pole is electrically connected to the first control signal line LR1, that is, the second pole of the second control transistor M52 is electrically connected to the first control signal terminal RST1 of the multi-stage light-emitting control unit 21.

[0058] Optional, such as Figure 3As shown, in the embodiment of the present invention, the second control signal line LR2 is only connected to one second control transistor M52, and the first control signal line LR1 is connected to multiple first control transistors M51. That is to say, the parasitic capacitance of the second control signal line LR2 is smaller than the parasitic capacitance of the first control signal line LR1. Therefore, when the display panel is abnormally powered off, the potential drop speed of the signal on the second control signal line LR2 is greater than the potential drop speed of the signal on the first control signal line LR1. Therefore, in the embodiment of the present invention, the second control transistor M52 can be quickly turned on under the control of the second control signal line LR2, so that the charge on the first control signal line LR1 can be quickly flowed into the first adjustment signal terminal V1 through the turned-on second control transistor M52 and released, that is, the first adjustment signal terminal V1 can quickly write down the potential on the first control signal line LR1, so as to solve the problem that the signal potential on the first control signal line LR1 cannot drop quickly when the display panel is abnormally powered off due to the large parasitic capacitance of the first control signal line LR1.

[0059] Exemplarily, the second control transistor M52 may include a P-type transistor.

[0060] In an optional implementation, the first level signal terminal VGL can be reused as the first adjustment signal terminal V1, that is, the second electrode of the second control module 22 can be electrically connected to the first level signal terminal VGL. Alternatively, the embodiment of the present invention can also make the ground terminal GND of the display panel reuse as the first adjustment signal terminal V1.

[0061] In another optional embodiment, Figure 3 Any one of the second power supply voltage terminal PVEE and the reset signal terminal Vref of the pixel driving circuit 11 shown can be multiplexed as the first adjustment signal terminal V1.

[0062] Based on the above configuration, the signals required for the display panel to work can be fully utilized without adding a new signal as the signal of the first adjustment signal terminal V1, which is beneficial to reducing the number of signals required by the light emitting control circuit 2 and simplifying the structure of the display panel.

[0063] When the display panel is abnormally powered off, the potential of the signal on the second control signal terminal RST2 drops rapidly, controlling the second control transistor M52 to turn on. Since the potentials of the first level signal terminal VGL, the ground terminal GND, the second power supply voltage terminal PVEE and the reset signal terminal Vref at the moment when the display panel is abnormally powered off are their respective low potentials when the display panel is working normally, the charge accumulated on the first control signal terminal RST1 can flow to the first adjustment signal terminal V1 multiplexed by any one of the first level signal terminal VGL, the ground terminal GND, the second power supply voltage terminal PVEE and the reset signal terminal Vref through the turned-on second control transistor M52, thereby forming a charge discharge path. In other words, the signal of the first adjustment signal terminal V1 can be quickly written into the first control signal terminal RST1 through the turned-on second control transistor M52, so as to realize a rapid reduction in the potential of the first control signal terminal RST1, thereby controlling the first control transistor M51 to be turned on quickly, so that the high potential of the second level signal terminal VGH is quickly provided to the first node N1, thereby controlling the first output transistor M21 to be quickly cut off, avoiding the light-emitting control unit 21 from outputting a low level, thereby avoiding the sub-pixel from lighting up and avoiding the screen flickering problem on the display panel.

[0064] Moreover, for a transistor, the charge on its gate is generally stable and not easy to change due to the lack of a discharge path. Compared with the gate, the charge accumulated on the first and second electrodes of the transistor is more likely to flow from one to the other and be released. Therefore, in the embodiment of the present invention, by electrically connecting the first control signal line LR1 to the second electrode of the second control transistor M52, compared with the method of not providing the second control transistor M52, when the display panel is abnormally powered off, the leakage path between the second electrode and the first electrode of the second control transistor M52 can be used to further accelerate the potential drop speed of the signal on the first control signal line LR1.

[0065] Optionally, the width-to-length ratio of the channel of the second control transistor M52 is greater than or equal to the width-to-length ratio of the channel of at least one transistor in the first processing module 213 and the second processing module 214. For example, the width-to-length ratio of the channel of the second control transistor M52 may be greater than Figure 4 The width-to-length ratio of a channel of any one of the first transistor M31, the second transistor M32, the third transistor M33, the fourth transistor M34, the fifth transistor M35, the sixth transistor M36, the seventh transistor M37, and the eighth transistor M38 is shown.

[0066] As mentioned above, since the first control signal line LR1 is connected to a plurality of light emitting control units 21, the parasitic capacitance of the first control signal line LR1 is relatively large, and when the display panel is abnormally powered off, a large amount of charge is stored on the first control signal line LR1. In the embodiment of the present invention, the signal transmission speed of the second control transistor M52 can be increased by setting the width-to-length ratio of the channel of the second control transistor M52 relatively large. When the display panel is abnormally powered off, the transmission speed of the charge between the first adjustment signal terminal V1 and the first control signal line LR1 can be increased, thereby enabling the potential on the first control signal line LR1 to drop more quickly.

[0067] Exemplarily, the channel width-to-length ratio of the second control transistor M52 is less than or equal to the channel width-to-length ratio of the first output transistor M21 or the second output transistor M22. Based on this configuration, it is possible to avoid excessively increasing the space occupied by the second control transistor M52 and to avoid increasing the width of the border region of the display panel where the second control transistor M52 is located.

[0068] For example, Figure 8 As shown, Figure 8 A schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention, the light-emitting control circuit 2 also includes a third control transistor M53, a gate of which is electrically connected to the third control signal terminal RST3, the third control signal terminal RST3 is electrically connected to the third control signal line LR3, a first pole is electrically connected to the second adjustment signal terminal V2, and a second pole is electrically connected to the second control signal line LR2.

[0069] When the display panel is working, the third control signal terminal RST3 provides a non-enable level, wherein the non-enable level of the third control signal terminal RST3 refers to a level that can control the third control transistor M53 to be turned off. Exemplarily, the third control transistor M53 may include a P-type transistor, and the non-enable level of the third control signal terminal RST3 may be a high level.

[0070] When the display panel is working, the second adjustment signal terminal V2 can receive a DC signal. Exemplarily, the potential of the second adjustment signal terminal V2 is less than the potential of the signal on the second control signal line LR2.

[0071] Exemplarily, the length of the third control signal line LR3 is shorter than the length of the first control signal line LR1.

[0072] When the display panel is abnormally powered off, the potential of the signal on the third control signal terminal RST3 drops rapidly, controlling the third control transistor M53 to turn on. Since the potential of the second adjustment signal terminal V2 at the moment the display panel is abnormally powered off is a low potential when the display panel is working normally, the charge accumulated on the second control signal line LR2 can flow to the second adjustment signal terminal V2 through the turned-on third control transistor M53, thereby forming a charge discharge path. In other words, the signal of the second adjustment signal terminal V2 can be quickly written into the second control signal line LR2 through the turned-on third control transistor M53, so as to realize a rapid decrease in the potential of the second control signal terminal RST2, so as to overcome the problem of a slow drop in the gate signal of the second control transistor M52 caused by a large coupling capacitance formed between the gate and the second pole of the second control transistor M52, and thus the second control transistor M52 can be controlled to be turned on quickly, so that the low-level signal on the first adjustment signal terminal V1 can be quickly provided to the first control signal line LR1 through the turned-on second control transistor M52, so as to control the first control transistor M51 in each level of light-emitting control unit 21 to be turned on quickly, so as to control the high-level signal provided by the second level signal terminal VGH to be quickly provided to the gate of the first output transistor M21 through the turned-on first control transistor M51, so as to control the first output transistor M21 to be quickly cut off, so as to avoid the output terminal OUT of each level of light-emitting control unit 21 outputting a signal for controlling the light emission of the sub-pixel.

[0073] Optionally, the potential of the second adjustment signal terminal V2 is less than or equal to the potential of the first adjustment signal terminal V1.

[0074] Exemplarily, the width-to-length ratio of the channel of the third control transistor M53 is less than or equal to the width-to-length ratio of the channel of the second control transistor M52. Compared with the first control signal line LR1, the parasitic capacitance of the second control signal line LR2 is smaller. Therefore, when the display panel is abnormally powered off, less charge is accumulated on the second control signal line LR2. The embodiment of the present invention sets the width-to-length ratio of the channel of the third control transistor M53 to be less than or equal to the width-to-length ratio of the channel of the second control transistor M52, which ensures that the charge on the second control signal line LR2 can be quickly discharged, while helping to reduce the area occupied by the third control transistor M53.

[0075] Exemplarily, the first adjustment signal terminal V1 may be multiplexed as the second adjustment signal terminal V2.

[0076] In an optional implementation, the first level signal terminal VGL can be multiplexed as the second adjustment signal terminal V2, that is, the second electrode of the third control transistor M53 can be electrically connected to the first level signal terminal VGL. Figure 3Any one of the second power supply voltage terminal PVEE and the reset signal terminal Vref of the pixel driving circuit 11 shown can be reused as the second adjustment signal terminal V2. Alternatively, the embodiment of the present invention can also reuse the ground terminal GND as the second adjustment signal terminal V2.

[0077] Based on the above configuration, the signals required for the display panel to work can be fully utilized without adding a new signal as the signal of the second adjustment signal terminal V2, which is beneficial to reducing the number of signals required by the light emitting control circuit 2 and simplifying the structure of the display panel.

[0078] Optional, such as Fig. 9 As shown, Fig. 9 A schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention, the light-emitting control circuit 2 further includes an adjustment capacitor C3, a first plate of the adjustment capacitor C3 is electrically connected to a third adjustment signal terminal V3, and a second plate is electrically connected to a second control signal line LR2.

[0079] When the display panel works normally, the third adjustment signal terminal V3 can receive a DC signal. Exemplarily, the potential of the third adjustment signal terminal V3 is greater than the potential of the first level signal terminal VGL.

[0080] When the display panel experiences an abnormal power outage, the signal on the third adjustment signal terminal V3 changes from a high potential to a low potential. This potential change will lower the potential on the second control signal line LR2 through the coupling effect of the adjustment capacitor C3, thereby accelerating the reduction of the voltage on the second control signal line LR2, and further accelerating the start-up of the second control module 22.

[0081] Exemplarily, in the embodiment of the present invention, the capacitance value of the adjustment capacitor C3 is less than 500 fF.

[0082] In an optional implementation, the second level signal terminal VGH may be multiplexed as the third adjustment signal terminal V3, that is, the first electrode plate of the first adjustment capacitor C31 may be electrically connected to the second level signal terminal.

[0083] In another optional embodiment, Figure 3 The first power supply voltage terminal PVDD of the pixel driving circuit 11 shown can be multiplexed as the third adjustment signal terminal V3.

[0084] In yet another optional embodiment, in combination Fig. 9 and Fig.10 As shown, Fig.10 Schematic diagram of another display panel provided by an embodiment of the present invention, the display panel also includes a driver chip 3, the driver chip 3 includes a power reference power supply terminal VCI for receiving a power reference voltage, and the driver chip 3 outputs a power reference voltage according to the power reference voltage. Figure 4The first level voltage received by the first level signal terminal VGL and the second level voltage VGH received by the second level signal terminal VGH are shown, and the output Figure 2 The first power supply voltage terminal PVDD receives a first power supply voltage and the second power supply voltage terminal PVEE receives a second power supply voltage.

[0085] Exemplarily, the power reference voltage terminal VCI may be multiplexed as the third adjustment signal terminal V3, that is, the first plate of the first adjustment capacitor C31 may be electrically connected to the power input voltage terminal VCI.

[0086] Based on the above configuration, the signals required for the display panel to work can be fully utilized without adding a new signal as the signal of the third adjustment signal terminal V3, which is beneficial to reducing the number of signals required by the light emitting control circuit 2 and simplifying the structure of the display panel.

[0087] For example, Fig. 9 As shown, in the embodiment of the present invention, the adjustment capacitor C3 may include only one capacitor.

[0088] Alternatively, the embodiment of the present invention may also make the light emitting control circuit 2 include at least two regulating capacitors connected in series; and the second plates of the at least two regulating capacitors are electrically connected to the third regulating signal terminals in a one-to-one correspondence. Fig.11 As shown, Fig.11 A schematic diagram of another light-emitting control circuit provided by an embodiment of the present invention, wherein the light-emitting control circuit 2 includes three mutually connected regulating capacitors, and the second plates of the three mutually connected regulating capacitors are respectively electrically connected to the three third regulating signal terminals one by one as an example. Fig.11 As shown, the three adjustment capacitors are marked as C3_1, C3_2 and C3_3, respectively, and the three third adjustment signal terminals V3 are marked as V3_1, V3_2 and V3_3, respectively.

[0089] Among them, the regulating capacitor C3_1 is electrically connected to the second control signal line LR2 and the third regulating signal terminal V3_1; the regulating capacitor C3_2 is electrically connected to the third regulating signal terminal V3_1 and the third regulating signal terminal V3_2; and the regulating capacitor C3_3 is electrically connected to the third regulating signal terminal V3_2 and the third regulating signal terminal V3_3.

[0090] When the display panel works normally, the third adjustment signal terminal V3_1 , the third adjustment signal terminal V3_2 and the third adjustment signal terminal V3_3 all receive a DC signal, and their potentials are all greater than the potential of the first level signal terminal VGL.

[0091] Exemplarily, the potentials of the third adjustment signal terminal V3_1 , the third adjustment signal terminal V3_2 , and the third adjustment signal terminal V3_3 may be equal, or may be unequal.

[0092] When the display panel experiences an abnormal power outage, the signals on the above-mentioned multiple third adjustment signal terminals V3 will change from high to low, and the multiple changes will cumulatively affect the potential change on the second control signal line LR2, thereby playing a role in more quickly reducing the voltage on the second control signal line LR2, which can help to further accelerate the start-up of the second control module 22.

[0093] Exemplarily, the third adjustment signal terminal V3_1 can reuse any one of the second level signal terminal VGH, the first power supply voltage terminal PVDD, and the power supply reference voltage terminal VCI. The third adjustment signal terminal V3_2 can reuse any one of the second level signal terminal VGH, the first power supply voltage terminal PVDD, and the power supply reference voltage terminal VCI. The third adjustment signal terminal V3_3 can reuse any one of the second level signal terminal VGH, the first power supply voltage terminal PVDD, and the power supply reference voltage terminal VCI.

[0094] Optionally, the capacitance values ​​of the at least two regulating capacitors C3 may be equal, or, in the embodiment of the present invention, the capacitance value of the regulating capacitor C3 close to the second control signal terminal RST2 may be smaller than the capacitance values ​​of other regulating capacitors C3. Fig.11 For example, in the embodiment of the present invention, the capacitance value of the regulating capacitor C3_1 directly electrically connected to the second control signal line LR2 can be made smaller than the capacitance value of the regulating capacitor C3_2, or the capacitance value of the regulating capacitor C3_1 can be made smaller than the capacitance value of the regulating capacitor C3_3. With this setting, the voltage stabilizing effect of the regulating capacitor C3_1 on the second control signal line LR2 can be weakened, and when the display panel is abnormally powered off, it is more conducive to quickly lowering the potential of the signal on the second control signal line LR2 under the action of the regulating capacitor C3.

[0095] The embodiment of the present invention further provides a driving method for the above display panel, Figure 3 and Figure 4 As shown, the driving method includes: When the display panel is working, the first control signal terminal RST1 and the second control signal terminal RST2 are controlled to provide a non-enable level. Under the effect of the non-enable level provided by the first control signal terminal RST1, the first control module 212 is turned off, thereby preventing the first control module 212 from affecting the potential of the first node N1 during the normal operation of the display panel.

[0096] Under the effect of the disabled level provided by the second control signal terminal RST2, the second control module 22 is turned off, thereby preventing the second control module 22 from affecting the potential on the first control signal terminal RST1 of each level of light emitting control unit 21 during normal operation of the display panel.

[0097] Optionally, when the display panel is working, the timing sequence of the first clock signal terminal CK and the second clock signal terminal XCK of the first-level light emitting control unit 21 can be as follows: Figure 5 As shown, the arrangement is performed so that the output terminals OUT of the light emitting control units 21 of each stage can be output step by step.

[0098] Exemplarily, when the display panel is working, the driving method further includes: The potential of the first adjustment signal terminal V1 is controlled to be smaller than the potential of the signal of the first control signal terminal RST1. Exemplarily, the first adjustment signal terminal V1 receives a DC voltage.

[0099] When the display panel is abnormally powered off, such as when the power is suddenly cut off, the potential of the signal on the second control signal terminal RST2 drops rapidly, and the second control module 22 is controlled to be turned on. Since the potential of the first adjustment signal terminal V1 at the moment when the display panel is abnormally powered off is the potential of the display panel when it is working normally, that is, at the moment when the abnormal power off occurs, the potential of the first adjustment signal terminal V1 is lower than the potential of the signal on the first control signal terminal RST1, the charge of the first control signal terminal RST1 can flow to the first adjustment signal terminal V1 through the turned-on second control module 22, thereby forming a charge discharge path. In other words, the signal of the first adjustment signal terminal V1 can be quickly written into the first control signal terminal RST1 through the turned-on second control module 22, so that the voltage of the first control signal terminal RST1 is reduced.

[0100] Combination Figure 4 As shown, under the control of the signal of the first control signal terminal RST1, the first control module 212 is turned on, so that the voltage provided by the second level signal terminal VGH is quickly provided to the first node N1, so as to control the first output transistor M21 to be quickly turned off, so as to prevent the voltage provided by the first level signal terminal VGL from being output to the output terminal OUT of the light emitting control unit 21, thereby preventing Figure 2 The light emitting control module 114 of the pixel driving circuit 11 shown is turned on, thereby preventing the light emitting element 12 from lighting up and preventing abnormal display problems such as screen flickering on the display panel.

[0101] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.12 As shown, Fig.12The following is a schematic diagram of a display device provided by an embodiment of the present invention, wherein the display device includes the above-mentioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above-mentioned embodiment, and will not be repeated here. Fig.12 The display device shown is only for illustration, and the display device may be any device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-book, a television, a smart watch, etc. The embodiments of the present invention are not limited to this.

[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The invention comprises a light emitting control circuit, wherein the light emitting control circuit comprises a plurality of cascaded light emitting control units, and the light emitting control unit comprises: an output module, in response to a signal of a first node, electrically connecting a first level signal terminal and an output terminal of the output module; and, in response to a signal of a second node, electrically connecting a second level signal terminal and an output terminal of the output module; A first control module, in response to a signal at a first control signal terminal, electrically connecting the second level signal terminal and the first node; The light emitting control circuit further comprises a second control module, which is responsive to a signal at a second control signal terminal and electrically connects the first regulating signal terminal and the first control signal terminal; When the display panel is working, the first control signal terminal and the second control signal terminal both provide a non-enable level; and the potential of the first adjustment signal terminal is less than the potential of the signal on the first control signal line.

2. The display panel according to claim 1, characterized in that: The display panel further includes a ground terminal, and any one of the first level signal terminal and the ground terminal is multiplexed as the first adjustment signal terminal.

3. The display panel according to claim 1, characterized in that: The display panel further includes a pixel driving circuit, the pixel driving circuit including a first power supply voltage terminal, a second power supply voltage terminal and a reset signal terminal, the potential of the signal at the first power supply voltage terminal is greater than the potential of the signal at the second power supply voltage terminal, and the potential of the signal at the first power supply voltage terminal is greater than the potential of the signal at the reset signal terminal; Any one of the second power supply voltage terminal and the reset signal terminal is multiplexed as the first adjustment signal terminal.

4. The display panel according to claim 1, characterized in that: The display panel comprises a first control signal line and a second control signal line, wherein the first control signal line is electrically connected to the first control signal terminals of the plurality of light emitting control units; The second control signal line is electrically connected to the second control signal terminal; The length of the second control signal line is shorter than the length of the first control signal line.

5. The display panel according to claim 1, characterized in that: The display panel further includes a chip binding area, and at least a portion of the second control module is located on a side of the light emitting control unit close to the chip binding area.

6. The display panel according to claim 1, characterized in that: The first control module comprises a first control transistor, a gate of which is electrically connected to the first control signal terminal, a first electrode of which is electrically connected to the second level signal terminal, and a second electrode of which is electrically connected to the first node; The second control module includes a second control transistor, a gate of which is electrically connected to the second control signal terminal, a first electrode of which is electrically connected to the first adjustment signal terminal, and a second electrode of which is electrically connected to the first control signal terminal.

7. The display panel according to claim 6, characterized in that: The light emitting control unit further includes a first processing module and a second processing module. The first processing module is electrically connected to the input terminal and the second clock signal terminal, and provides a signal to the first node; The second processing module is electrically connected to the first clock signal terminal, the second level signal terminal, the first level signal terminal, and the second clock signal terminal, and provides a signal to the second node; The first processing module and the second processing module each include a plurality of transistors; A width-to-length ratio of a channel of the second control transistor is greater than or equal to a width-to-length ratio of a channel of at least one of the transistors in the first processing module and the second processing module.

8. The display panel according to claim 6, characterized in that: The output module includes a first output transistor and a second output transistor; wherein, The gate of the first output transistor is electrically connected to the first node, the first electrode is electrically connected to the first level signal terminal, and the second electrode is electrically connected to the output terminal; The gate of the second output transistor is electrically connected to the second node, the first electrode is electrically connected to the second level signal terminal, and the second electrode is electrically connected to the output terminal; The width-to-length ratio of the channel of the second control transistor is less than or equal to the width-to-length ratio of the channel of the first output transistor; or the width-to-length ratio of the channel of the second control transistor is less than or equal to the width-to-length ratio of the channel of the second output transistor.

9. The display panel according to claim 6, characterized in that: The light emitting control circuit further comprises a third control transistor, wherein a gate of the third control transistor is electrically connected to a third control signal terminal, a first electrode is electrically connected to a second regulating signal terminal, and a second electrode is electrically connected to the second control signal terminal; When the display panel is working, the third control signal terminal provides a non-enable level, and the potential of the second adjustment signal terminal is less than the potential of the second control signal terminal.

10. The display panel according to claim 9, characterized in that: A width-to-length ratio of a channel of the third control transistor is less than or equal to a width-to-length ratio of a channel of the second control transistor.

11. The display panel according to claim 9, characterized in that: The potential of the second adjustment signal terminal is less than or equal to the potential of the first adjustment signal terminal.

12. The display panel according to claim 9, characterized in that: The first adjustment signal terminal is multiplexed as the second adjustment signal terminal.

13. The display panel according to claim 1, characterized in that: The light emitting control circuit further comprises an adjusting capacitor, wherein a first plate of the adjusting capacitor is electrically connected to a third adjusting signal terminal, and a second plate of the adjusting capacitor is electrically connected to the second control signal terminal; When the display panel is working, the potential of the third adjustment signal terminal is greater than the potential of the first level signal terminal.

14. The display panel according to claim 13, characterized in that: The second level signal terminal is multiplexed as the third adjustment signal terminal.

15. The display panel according to claim 13, characterized in that: The display panel further includes a pixel driving circuit, the pixel driving circuit including a first power supply voltage terminal, a second power supply voltage terminal and a reset signal terminal, the potential of the first power supply voltage terminal is greater than the potential of the second power supply voltage terminal, the potential of the first power supply voltage terminal is greater than the potential of the reset signal terminal, The first power supply voltage terminal is multiplexed as the third adjustment signal terminal.

16. The display panel according to claim 13, characterized in that: The display panel further includes a driving chip, the driving chip includes a power reference voltage terminal, and the power reference voltage terminal is multiplexed as the third adjustment signal terminal.

17. The display panel according to claim 13, characterized in that: The capacitance of the adjustment capacitor is less than or equal to 500fF.

18. The display panel according to claim 13, characterized in that: The light emitting control circuit comprises at least two of the regulating capacitors; At least two of the regulating capacitors are electrically connected to the third regulating signal terminals in a one-to-one correspondence, and at least two of the regulating capacitors are connected in series with each other.

19. The display panel according to claim 18, characterized in that: The capacitance value of the regulating capacitor close to the second control signal terminal is smaller than the capacitance values ​​of the other regulating capacitors.

20. A driving method for a display panel according to any one of claims 1 to 19, characterized in that: The driving method comprises: When the display panel is working, a non-enable level is provided to the first control signal terminal and the second control signal terminal, and the potential of the signal at the first adjustment signal terminal is controlled to be less than or equal to the potential of the signal at the first control signal terminal.

21. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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