Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises pixel circuits arranged in an array; the pixel circuit comprises a light emitting module, a driving module and a bias adjusting module. The driving module is used for driving the light-emitting module to emit light; the driving module comprises a driving transistor; the bias adjusting module receives a bias adjusting signal and a first scanning control signal; the bias adjusting module is used for outputting a bias adjusting signal to the driving module when the first scanning control signal outputs an effective level; the driving period of the pixel circuit comprises a data refreshing frame and m holding frames; m > = 0; the number of effective levels output by the first scanning control signal in the data refreshing frame is N1; when m is greater than or equal to 1, the number of effective levels output by the first scanning control signal in the holding frame is N2; n1 is larger than or equal to 1 and smaller than or equal to N2, the flicker problem in a low-frequency refreshing mode can be improved on the basis of improving the afterimage problem, and therefore the display effect of the display panel can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the pixel circuit of the organic light-emitting display panel, there is leakage current in the driving transistor during the process of driving the light-emitting element to emit light. Especially in low-frequency display, the leakage time is long when the driving transistor remains in the on state for a long time, causing its gate potential to change and thus causing the driving current to decrease. As a result, the light-emitting brightness of the light-emitting element at the beginning and end of each frame of display is different, resulting in obvious flickering on the display panel.

[0003] In order to improve the flicker problem caused by the drift of the output characteristics of the driving transistor, the driving transistor is usually biased and adjusted before initializing the driving transistor and after writing the data signal to the gate of the driving transistor to stabilize the gate potential of the driving transistor so that the driving transistor can provide a stable driving current during the conduction period, thereby improving the flicker phenomenon during low-frequency display and switching refresh frequency.

[0004] However, multiple bias adjustments will cause the bias degree of the driving transistor to be relatively large, which is not conducive to the conversion of the state of the driving transistor, resulting in a relatively long afterimage when switching the display screen. Summary of the invention

[0005] The present invention provides a display panel and a display device to improve the problem of a long retention time of an afterimage and enhance the display effect of the display panel.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising: pixel circuits arranged in an array;

[0007] The pixel circuit includes a light emitting module, a driving module and a bias adjustment module;

[0008] The driving module is used to drive the light-emitting module to emit light; the driving module includes a driving transistor;

[0009] The bias adjustment module is electrically connected to the driving module, and the bias adjustment module receives a bias adjustment signal and a first scanning control signal; the bias adjustment module is used to output the bias adjustment signal to the driving module when the first scanning control signal outputs a valid level;

[0010] The driving cycle of the pixel circuit includes a data refresh frame and m holding frames; m ≥ 0, and m is an integer;

[0011] The number of valid levels output by the first scanning control signal in the data refresh frame is N1;

[0012] When m≥1, the number of valid level outputs of the first scanning control signal in the holding frame is N2;

[0013] 1≤N1≤N2, and N1 and N2 are both integers.

[0014] According to another aspect of the present invention, a display device is provided, comprising: the above-mentioned display panel.

[0015] The technical solution provided by the present invention is to set a pixel circuit including a light-emitting module, a driving module and a bias adjustment module. The light-emitting module is driven by the driving module to emit light. The bias adjustment module provides a bias adjustment signal to the driving module under the control of a first scanning signal, so as to adjust the bias of the driving transistor in the driving module, thereby improving the problem of output characteristic deviation caused by the driving transistor being in a bias state for a long time, thereby effectively improving the problem of low-frequency flicker. At the same time, in the case where the driving cycle of the pixel circuit includes at least one holding frame, by setting the number N1 of the first scanning control signal outputting an effective level in the data refresh frame to be less than or equal to the number N2 of the first scanning control signal outputting an effective level in the holding frame The number of effective levels N2 makes the degree of bias adjustment of the driving transistor in the data refresh frame smaller, which can avoid excessive bias adjustment of the driving transistor and the problem of a long retention time of the afterimage of the previous frame when switching the screen, especially improving the problem of a long retention time of the afterimage in the high-frequency refresh mode; and, by performing N2 bias adjustments on the driving transistor in the maintaining frame, the problem of output characteristic deviation caused by long-term conduction of the driving transistor in the low-frequency refresh mode can be solved, the degree of output characteristic deviation of the driving transistor can be reduced, and the flicker problem in the low-frequency refresh mode can be improved on the basis of improving the afterimage problem, thereby effectively improving the display effect of the display panel.

[0016] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a structural schematic diagram of a display panel in the prior art;

[0019] Figure 2is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0020] Figure 3 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0021] Figure 4 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0022] Figure 5 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0023] Figure 6 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0024] Figure 7 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0025] Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0026] Fig. 9 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0027] Fig.10 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0028] Fig.11 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0029] Fig.12 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0030] Fig.13 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0031] Fig.14 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] As introduced in the background art, the display panel has a flickering problem during display, especially the flickering phenomenon is particularly obvious during low-frequency display and switching refresh frequency, which affects the display effect of the display panel. The inventor has found that the cause of this problem is that during the period of providing driving current to the light-emitting module, there is a certain voltage difference between the gate and the source of the driving transistor, which makes the driving transistor in a biased state for a long time. In particular, when the pixel circuit has a low refresh frequency, the driving transistor needs to maintain the biased state for a longer time, causing the output characteristic deviation of the driving transistor to be more serious. As time goes by, the driving current provided by the driving transistor continues to decrease, and the luminous brightness of the light-emitting module gradually decreases, resulting in the next driving cycle. When the data signal is written again, the driving current provided by the driving transistor suddenly increases, and the brightness of the light-emitting module changes suddenly, resulting in low-frequency display flickering; at the same time, due to different refresh frequencies, the driving transistor maintains the biased state for different lengths of time, so that the driving transistor has different output characteristic deviation degrees, so that when the driving transistor is refreshed at a low frequency, the luminous brightness of the light-emitting element at the beginning and the end of each frame display picture are different due to long-term leakage, so that the display luminous brightness of the light-emitting module changes suddenly when the data is refreshed, and obvious flickering occurs when the refresh frequency is switched, affecting the display effect of the display panel.

[0035] The prior art generally adopts a method of biasing the driving transistor to improve the bias of the driving transistor, specifically, before writing data into the gate of the driving transistor and after writing the data signal into the gate of the driving transistor, the driving transistor is biased and adjusted, and the driving transistor is also biased in the holding frame. In this way, the driving transistor can be biased and adjusted before and after the data writing stage to reduce the degree of deviation of the output characteristics of the driving transistor, improve the leakage of the driving transistor, thereby improving the brightness difference of each frame and improving the display uniformity. However, too many times of bias adjustment process make the bias degree of the driving transistor too large, resulting in a long time for the driving transistor to switch the state, which is not conducive to the conversion of the driving transistor state, resulting in a long time of residual image when switching the display screen. And because the same bias adjustment process is used during high-frequency refresh and low-frequency refresh, the long residual problem (i.e., the long-term residual image problem) caused by the excessive bias degree of the driving transistor when switching the display screen in the high-frequency refresh mode is more obvious, affecting the display effect.

[0036] To solve the above technical problems, an embodiment of the present invention provides a display panel, comprising: an array-arranged pixel circuit; the pixel circuit comprises a light-emitting module, a driving module and a bias adjustment module; the driving module is used to drive the light-emitting module to emit light; the driving module comprises a driving transistor; the bias adjustment module is electrically connected to the driving module, and the bias adjustment module receives a bias adjustment signal and a first scanning control signal; the bias adjustment module is used to output the bias adjustment signal to the driving module when the first scanning control signal outputs a valid level; the driving cycle of the pixel circuit comprises a data refresh frame and m holding frames; m≥0, and m is an integer; the number of valid levels output by the first scanning control signal in the data refresh frame is N1; when m≥1, the number of valid levels output by the first scanning control signal in the holding frame is N2; 1≤N1≤N2, and N1 and N2 are both integers.

[0037] By adopting the above technical solution, a pixel circuit is provided including a light-emitting module, a driving module and a bias adjustment module. The light-emitting module is driven by the driving module to emit light. The bias adjustment module provides a bias adjustment signal to the driving module under the control of the first scanning signal, so as to adjust the bias of the driving transistor in the driving module, thereby improving the problem of output characteristic deviation caused by the driving transistor being in a bias state for a long time, thereby effectively improving the problem of low-frequency flicker. At the same time, in the case where the driving cycle of the pixel circuit includes at least one holding frame, by setting the number N1 of the first scanning control signal outputting a valid level in the data refresh frame to be less than or equal to the number N2 of the first scanning control signal outputting a valid level in the holding frame The number of levels N2 makes the degree of bias adjustment of the driving transistor in the data refresh frame smaller, which can avoid excessive bias adjustment of the driving transistor and the problem of a long retention time of the afterimage of the previous frame when switching the screen, especially improving the problem of a long retention time of the afterimage in the high-frequency refresh mode; and, by performing N2 bias adjustments on the driving transistor in the maintaining frame, the problem of output characteristic deviation caused by the driving transistor being turned on for a long time in the low-frequency refresh mode can be solved, the degree of output characteristic deviation of the driving transistor can be reduced, and the flicker problem in the low-frequency refresh mode can be improved on the basis of improving the afterimage problem, thereby effectively improving the display effect of the display panel.

[0038] The above is the core idea of ​​this application. The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, such as Figure 1 As shown, the display panel 100 includes pixel circuits 10 arranged in an array; in order to achieve full-color display of the display panel, the pixel circuits 10 arranged in an array may include a pixel circuit for emitting green light, a pixel circuit for emitting blue light, and a pixel circuit for emitting red light.

[0040] Figure 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention, Figure 3 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 1 , Figure 2 and Figure 3The pixel circuit 10 includes a light-emitting module 11, a driving module 12 and a bias adjustment module 13; the driving module 12 is used to drive the light-emitting module 11 to emit light; the driving module 12 includes a driving transistor M1; the bias adjustment module 13 is electrically connected to the driving module 12, and the bias adjustment module 13 receives a bias adjustment signal DVH and a first scanning control signal S1; the bias adjustment module 13 is used to output the bias adjustment signal DVH to the driving module 12 when the first scanning control signal S1 outputs a valid level.

[0041] The light-emitting module 11 may include a light-emitting element, which may include a current-type driving element such as an organic light-emitting diode; the driving module 12 may receive a data signal, and provide a driving current to the light-emitting module 11 according to the data signal received, so as to drive the light-emitting module 11 to display light. The driving module 12 includes a driving transistor M1, and the driving transistor M1 and the light-emitting module 11 may be connected in series between a first power supply VDD and a second power supply VSS. When the light-emitting module 11 needs to be controlled to emit light, the gate signal of the driving transistor M1 may include the data signal received by the driving module 12. The first electrode of the driving transistor M1 may receive the first power supply signal VDD or the second power supply signal VSS, and the second electrode of the driving transistor M1 may be coupled to the anode or cathode of the light-emitting element in the light-emitting module 110; at this time, there is a certain voltage difference between the gate of the driving transistor M1 and its first electrode, and / or between the gate of the driving transistor M1 and its second electrode, so that the driving transistor M1 generates a certain driving current according to the voltage difference, and provides the driving current to the anode or cathode of the light-emitting element in the light-emitting module 11, so as to drive the light-emitting element in the light-emitting module 11 to display light.

[0042] It can be understood that there is also a certain voltage difference between the first power signal VDD and the second power signal VSS, so that when the light-emitting module 11 needs to be controlled to emit light, a current path can be formed between the first power signal VDD and the second power signal VSS, wherein the first power signal VDD can be set as a positive power signal and the second power signal VSS can be set as a negative power signal. At this time, the anode of the light-emitting element in the light-emitting module 11 can receive the first power signal VDD, and the cathode can receive the second power signal VSS (such as Figure 2 Alternatively, the first power signal VDD may be set to be a negative power signal, and the second power signal VSS may be set to be a positive power signal. In this case, the anode of the light-emitting element in the light-emitting module 110 may receive the second power signal VSS, and the cathode of the light-emitting element may receive the first power signal VDD (as shown in FIG. Figure 3As shown), it can be designed according to actual needs, and the embodiments of the present invention do not make specific limitations on this. For the convenience of description, without special limitations, the embodiments of the present invention take the anode of the light-emitting element in the light-emitting module 110 coupled to the second electrode of the driving transistor T2, and the cathode of the light-emitting element in the light-emitting module 110 receiving the second power signal VSS as an example to exemplarily illustrate the technical solution of the embodiments of the present invention.

[0043] refer to Figure 2 , the first electrode of the driving transistor M1 may be a source electrode, and the second electrode of the driving transistor M1 may be a drain electrode, or the first electrode of the driving transistor M1 may be a drain electrode and the second electrode may be a source electrode, which is not specifically limited in this embodiment. The driving transistor M1 may be a P-type transistor or an N-type transistor, and may be specifically designed according to actual needs. When the driving transistor M1 is a P-type transistor, when the voltage difference between the gate voltage of the driving transistor M1 and its source electrode is less than its threshold voltage Vth, the conduction condition of the driving transistor M1 may be satisfied, so that a current path is formed between the first power signal VDD and the second power signal VSS, and the driving current generated by the driving transistor M1 may be provided to the light-emitting module 11, and at this time, the driving transistor M1 may be in a negative bias state; and when the driving transistor M1 is an N-type transistor, when the voltage difference Vgs between the gate voltage of the driving transistor M1 and its source electrode is greater than its threshold voltage Vth, the conduction condition of the driving transistor M1 may be satisfied, so that a current path is formed between the first power signal VDD and the second power signal VSS, and the driving current generated by the driving transistor M1 may be provided to the light-emitting module 11, and at this time, the driving transistor M1 may be in a positive bias state. For the convenience of description, unless otherwise specified, the embodiments of the present invention all take the driving transistor M1 as a P-type transistor as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0044] Continue to refer Figure 2The first end of the bias adjustment module 13 can receive the bias adjustment signal DVH, the second end of the bias adjustment module 13 can be electrically connected to the driving module 12, and the control end of the bias adjustment module 13 can receive the first scanning control signal S1, so that the bias adjustment module 13 can be turned on or off under the control of the first scanning control signal S1. When the bias adjustment module 13 is turned on by the first scanning control signal S1, the bias adjustment signal DVH can be provided to the driving module 12, so that the signal of the first electrode and / or the second electrode of the driving transistor M1 in the driving module 12 can be consistent with the bias adjustment signal DVH. The bias adjustment signal DVH can be a signal different from the first power signal VDD and / or the second power signal VSS, so that the first electrode signal of the driving transistor M1 is changed from the first power signal VDD to the bias adjustment signal DVH, and / or the second electrode signal of the driving transistor M1 is changed from the sum of the second power signal VSS and the start-up voltage of the light-emitting element in the light-emitting module 11 to the bias adjustment signal DVH, so as to change the bias state of the driving transistor M1, thereby adjusting the bias state of the driving transistor M1, preventing the driving transistor M1 from being in the same bias state for a long time, so that the driving transistor M1 has a large degree of output characteristic deviation, and thus can improve the accuracy of the driving current provided due to the output characteristic bias of the driving transistor M1, which is beneficial to improving the display light emission accuracy of the light-emitting element in the light-emitting module 11. In particular, when the pixel circuit has a lower refresh frequency, the gate of the driving transistor M1 needs to maintain the same voltage signal for a long time, so that when the voltage of the first electrode and / or the second electrode of the driving transistor M1 remains unchanged, the driving transistor M1 will be in the same bias state for a long time, which makes the output characteristic deviation degree of the driving transistor M1 continue to increase, and the gate potential changes greatly. By providing a bias adjustment signal DVH to the first electrode or the second electrode of the driving transistor M1, the bias state of the driving transistor M1 can be improved, thereby improving the output characteristic deviation degree of the driving transistor M1, and then improving the problem of low-frequency flicker.

[0045] For example, Figure 4 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention, referring to Figure 2 or Figure 4 The bias adjustment module 13 includes a bias adjustment transistor M2; a gate of the bias adjustment transistor M2 receives a first scanning control signal S1, a first electrode of the bias adjustment transistor M2 receives a bias adjustment signal DVH, and a second electrode of the bias adjustment transistor M2 is electrically connected to a first electrode or a second electrode of the driving transistor M1.

[0046] The gate of the bias adjustment transistor M2 can receive the first scanning control signal S1, so that the bias adjustment transistor M2 can be turned on or off under the control of the first scanning control signal S1. The bias adjustment transistor M2 can be an N-type transistor or a P-type transistor. When the bias adjustment transistor M2 is an N-type transistor, when the first scanning control signal S1 is at a high level, the bias adjustment transistor M2 can be controlled to be turned on. When the bias adjustment transistor M2 is a P-type transistor, when the first scanning control signal S1 is at a low level, the bias adjustment transistor M2 can be controlled to be turned on.

[0047] In an exemplary embodiment, taking the bias adjustment transistor M2 as a P-type transistor as an example, when the first scanning control signal S1 is at a low level, the bias adjustment transistor M2 is turned on, and the bias adjustment signal DVH is transmitted to its second electrode through the first electrode of the bias adjustment transistor M2, and is provided to the first electrode or the second electrode of the driving transistor M1; when the first scanning control signal S1 is at a high level, the bias adjustment transistor M2 is turned off, and the bias adjustment signal DVH cannot be provided to the first electrode or the second electrode of the driving transistor M1, so that when the driving transistor M1 receives the bias adjustment signal DVH, the bias state of the driving transistor M1 can be changed, and the degree of deviation of the output characteristics of the driving transistor M1 can be adjusted.

[0048] In other optional embodiments, Figure 5 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, such as Figure 5 As shown, the bias adjustment module 13 may include a first bias adjustment transistor M21 and a second bias adjustment transistor M22, the gates of the first bias adjustment transistor M21 and the second bias adjustment transistor M22 may receive the first scanning control signal S1, the first electrodes of the first bias adjustment transistor M21 and the second bias adjustment transistor M22 may receive the bias adjustment signal DVH, the second electrode of the first bias adjustment transistor M21 may be electrically connected to the first electrode of the driving transistor M1, and the second electrode of the second bias adjustment transistor M22 may be electrically connected to the second electrode of the driving transistor M1. At this time, when the first scanning control signal S1 controls the first bias adjustment transistor M21 and the second bias adjustment transistor M22 to be turned on, the bias adjustment signal DVH may be provided to the first electrode and the second electrode of the driving transistor M1 at the same time, so that the voltage difference between the gate of the driving transistor M1 and the first electrode and the second electrode thereof can change, and the bias state of the driving transistor M1 can also be adjusted.

[0049] It can be understood that the above respectively exemplifies the connection between the bias adjustment module 13 and the first electrode and / or the second electrode of the driving transistor M1, and the specific connection between the bias adjustment module 13 and the driving transistor M1 can be designed according to actual needs, and the embodiment of the present invention does not specifically limit this. For the convenience of description, under the premise of no special limitation, the embodiments of the present invention take the electrical connection between the bias adjustment module 13 and the first electrode of the driving transistor M1 as an example to exemplify the technical solution of the embodiments of the present invention.

[0050] The refresh frequency of the pixel circuit 10 is the number of times the data signal Vdata is written to the pixel circuit 10 per unit time, so that the higher the refresh frequency of the pixel circuit 10, the more times the data signal Vdata is written to the pixel circuit 10 per unit time, the shorter the driving cycle of the pixel circuit 10, and the fewer the number of holding frames it includes; conversely, the lower the refresh frequency of the pixel circuit 10, the fewer the number of times the data signal Vdata is written to the pixel circuit 10 per unit time, the longer the driving cycle of the pixel circuit 10, and the more the number of holding frames it includes. It can be seen that when the pixel circuit 10 has a higher refresh frequency, the voltage difference between the gate of the driving transistor M1 and its first pole is kept for a shorter time, so that the output characteristic deviation of the driving transistor M1 is lower; conversely, when the pixel circuit 10 has a lower refresh frequency, the voltage difference between the gate of the driving transistor M1 and its first pole is kept for a longer time, so that the output characteristic deviation of the driving transistor M1 is higher. Thus, when the pixel circuit 10 has different refresh frequencies, its driving transistor M1 has different characteristic offset degrees, so that when the same data signal is written under different refresh frequencies, the driving transistor M1 may also generate different driving currents, thereby making the light-emitting module 11 have different display brightness.

[0051] Figure 6 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention, Figure 7 is another driving timing diagram of a pixel circuit provided by an embodiment of the present invention, combined with reference Figure 6 and Figure 7 , the driving cycle of the pixel circuit includes a data refresh frame T1 and m holding frames T2; m≥0, and m is an integer; the number of valid levels output by the first scanning control signal S1 in the data refresh frame T1 is N1; when m≥1, the number of valid levels output by the first scanning control signal S1 in the holding frame T2 is N2; 1≤N1≤N2, and N1 and N2 are both integers.

[0052] When the driving period T of the pixel circuit 10 includes at least one holding frame T2, the number N1 of the first scanning control signal S1 outputting a valid level in the data refresh frame T1 can be set to be less than or equal to the number N2 of the first scanning control signal S1 outputting a valid level in the holding frame T2. Figure 6 and Figure 7 The case where N1=1 and N2=2, i.e., N1<N2, is shown as an example. In the data refresh frame T1, the first scan control signal S1 outputs a valid level at the t1 stage. In the hold frame T2, the first scan control signal S1 outputs a valid level at the t5 stage and the t6 stage. In this way, the number of times the bias adjustment of the driving transistor M1 is performed in the data refresh frame T1 is small, so the degree of bias adjustment of the driving transistor M1 can be small, and excessive bias adjustment of the driving transistor M1 can be avoided, resulting in the problem that the state of the driving transistor M1 is not easy to switch when switching the display screen, thereby avoiding the long retention time of the afterimage of the previous frame when switching the screen in the high-frequency refresh mode, and improving the display effect in the high-frequency refresh mode; at the same time, the bias adjustment of the driving transistor M1 N1 times or N2 times in the maintaining frame T2 can solve the problem of output characteristic deviation caused by the long-term conduction of the driving transistor M1, and can reduce the degree of output characteristic deviation of the driving transistor M1, so as to ensure that the degree of output characteristic deviation of the driving transistor M1 remains consistent under different refresh frequencies, and can improve the flicker problem in the low-frequency refresh mode on the basis of improving the afterimage problem. In addition, the first scanning control signal S1 of the data refresh frame T1 is set to output N1 valid levels, so that the number of times the bias adjustment of the driving transistor M1 is performed is reduced. For the high-frequency refresh mode that only includes the data refresh frame T1, since the output characteristic offset of the driving transistor M1 is relatively low, the degree of bias adjustment of the driving transistor M1 can be relatively small. Similarly, excessive bias adjustment of the driving transistor M1 can be avoided, resulting in the problem that the state of the driving transistor M1 is not easy to switch when switching the display screen. This can avoid the long retention time of the afterimage of the previous frame when switching the screen in the high-frequency refresh mode, and can improve the display effect in the high-frequency refresh mode.

[0053] The display panel provided by the embodiment of the present invention is provided with a pixel circuit including a light-emitting module, a driving module and a bias adjustment module. The light-emitting module is driven by the driving module to emit light. The bias adjustment module provides a bias adjustment signal to the driving module under the control of a first scanning signal, so as to adjust the bias of the driving transistor in the driving module, thereby improving the problem of output characteristic deviation caused by the driving transistor being in a bias state for a long time, thereby effectively improving the problem of low-frequency flicker. At the same time, in the case where the driving cycle of the pixel circuit includes at least one holding frame, by setting the number N1 of the first scanning control signal outputting an effective level in the data refresh frame to be less than or equal to the number N2 of the first scanning control signal outputting an effective level in the holding frame The number of effective levels N2 is output, so that the degree of bias adjustment of the driving transistor in the data refresh frame is small, which can avoid excessive bias adjustment of the driving transistor, and can avoid the problem of a long retention time of the afterimage of the previous frame when switching the screen, especially can improve the problem of a long retention time of the afterimage in the high-frequency refresh mode; and, by performing N2 bias adjustments on the driving transistor in the maintaining frame, the problem of output characteristic deviation caused by the driving transistor being turned on for a long time in the low-frequency refresh mode can be solved, the degree of output characteristic deviation of the driving transistor can be reduced, and the flicker problem in the low-frequency refresh mode can be improved on the basis of improving the afterimage problem, thereby effectively improving the display effect of the display panel.

[0054] Based on the above embodiment, optionally, continue to refer to Figure 2 The pixel circuit 10 may further include a data writing module 14, which receives a data signal Vdata and a second scanning control signal S2, and is used to turn off and on under the control of the second scanning control signal S2, and write the data signal Vdata to the gate of the driving transistor M1 in the driving module 12 when turned on.

[0055] Exemplarily, the data writing module 14 includes a data writing transistor M3; the gate of the data writing transistor M3 receives the second gate driving signal S2, the first electrode of the data writing transistor M3 receives the data signal Vdata, and the second electrode of the data writing transistor M3 is electrically connected to the first electrode of the driving transistor M1. The data writing transistor M3 is turned on or off under the control of the second gate driving signal S2, and the data signal Vdata can be written to the driving transistor M1 when the data writing transistor M3 is turned on, and the data signal Vdata cannot be written to the driving transistor M1 when the data writing transistor M3 is turned off.

[0056] Exemplary, reference Figure 6 or Figure 7 The data refresh frame T1 at least includes a data writing phase t3; in the data refresh frame T1, after the data writing phase t3, the first scanning control signal S1 is maintained at an invalid level.

[0057] Specifically, during the data refresh frame T1, the bias adjustment of the driving transistor M1 after the data writing stage t3 will make the bias degree of the driving transistor M1 larger. By setting the first scanning control signal S1 to be kept at an invalid level after the data writing stage t3 of the data refresh frame T1, the bias adjustment of the driving transistor M1 is no longer performed after the data writing stage t3 of the data refresh frame T1, which can avoid the problem of the bias degree of the driving transistor M1 being larger and the state switching time being longer, thereby improving the problem of the afterimage remaining for a long time.

[0058] Optional, combined with reference Figure 2 , Figure 6 and Figure 7 The second scanning control signal S2 outputs a valid level in the data writing phase t3, so that the data writing module 14 outputs the data signal Vdata to the driving module 12; the first scanning control signal S1 includes a first valid level EP1 in the data writing frame T1, and the first valid level EP1 is located before the data writing phase t3.

[0059] Specifically, by setting the first effective level EP1 before the data writing stage t3, the bias adjustment signal DVH can be written to the driving transistor T1 before the data signal Vdata is written to the driving transistor M1, so as to perform bias adjustment on the output characteristic deviation caused by the long-term conduction of the driving transistor T1 in the previous driving cycle T, thereby ensuring the accuracy of the data signal Vdata written in the data writing stage t3, thereby improving the flicker phenomenon while avoiding the bias adjustment transition, which is beneficial to improving the display effect.

[0060] Continue to refer Figure 2 The pixel circuit 10 may further include an initialization module 15, a threshold compensation module 16 and a storage module 17; the initialization module 15 is electrically connected to the driving module 12, and the initialization module 15 receives the initialization signal Vref1 and the third scanning control signal S3; the initialization module 15 is used to output the initialization signal Vref1 to the driving module 12 when the third scanning control signal S3 outputs a valid level; the threshold compensation module 16 is electrically connected to the driving module 12, and the threshold compensation module 16 receives the fourth scanning control signal S4; the threshold compensation module 16 is used to provide a compensation voltage to the driving module 12 when the fourth scanning control signal S4 outputs a valid level; the storage module 17 is electrically connected to the driving module 12, and the storage module 17 is used to store data signals.

[0061] The initialization module 15 may include an initialization transistor M4, the gate of which receives the third scanning control signal S3, the first electrode of which receives the initialization signal Vref1, and the second electrode of which is electrically connected to the gate of the driving transistor M1. The initialization transistor M4 may be turned on or off under the control of the third scanning control signal S3, and when the initialization transistor M4 is turned on, the initialization signal Vref1 can be written to the gate of the driving transistor M1, and the gate signal of the driving transistor M1 can be initialized. The threshold compensation module 16 may include a threshold compensation transistor M5; the gate of the threshold compensation transistor M4 receives the third gate drive signal S3, the first electrode of the threshold compensation transistor M5 is electrically connected to the second electrode of the driving transistor M1, and the second electrode of the threshold compensation transistor M5 is electrically connected to the gate of the driving transistor M1. The storage module 17 may include a storage capacitor Cst, which is electrically connected between the first power supply VDD and the gate of the driving transistor M1, and is used to store the gate signal of the driving transistor M1 to ensure that the driving transistor M1 can continuously provide the driving current data signal to the light emitting module 11.

[0062] Optional, continue to refer to Figure 2 The pixel circuit also includes a first light-emitting control module 18, a second light-emitting control module 19 and a reset module 110; the first light-emitting control module 18, the driving module 12, the second light-emitting control module 19 and the light-emitting module 11 are electrically connected between the first power supply terminal VDD and the second power supply terminal VSS in sequence, and the first light-emitting control module 18 and the second light-emitting control module 19 both receive a light-emitting control signal EM; the reset module 110 is electrically connected to the light-emitting module 11, and the reset module 110 receives a reset signal Vref2 and a fifth scanning control signal S5; the reset module 110 is used to output the reset signal Vref2 to the light-emitting module 11 when the fifth scanning control signal S5 outputs a valid level.

[0063] Specifically, the first light-emitting control module 18 includes a first light-emitting control transistor M6, and the second light-emitting control module 19 includes a second light-emitting control transistor M7. The gate of the first light-emitting control transistor M6 and the gate of the second light-emitting control transistor M6 receive the light-emitting control signal EM, the first electrode of the first light-emitting control transistor M7 is electrically connected to the first power source VDD, the second electrode of the first light-emitting control transistor M6 is electrically connected to the first electrode of the driving transistor M1, the first electrode of the second light-emitting control transistor M7 is electrically connected to the second electrode of the driving transistor M1, and the second electrode of the second light-emitting control transistor M7 is electrically connected to the light-emitting module 11. When the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are both turned on, the first power source VDD can be provided to the first electrode of the driving transistor M1, so that the gate of the driving transistor M1 and the first electrode thereof meet the turn-on condition of the driving transistor M1, so that a current path is formed between the first power source VDD and the second power source VSS, so that the driving current provided by the driving transistor M1 can be transmitted to the light-emitting element 11, and the light-emitting module 11 is driven to emit light.

[0064] The reset module 110 includes a reset transistor M8, a gate of the reset transistor M8 receives the fifth gate drive signal S5, a first electrode of the reset transistor M8 receives the reset signal Vref2, and a second electrode of the reset transistor M8 is electrically connected to the light emitting module 11. The reset transistor M8 can be turned on or off under the control of the fifth gate drive signal S5, and when the reset transistor M8 is turned on, the reset signal Vref2 is transmitted to the first end of the light emitting module 11, so that the light emitting module 11 can be reset.

[0065] It should be noted that the above exemplary 8T1C example is used to illustrate the results of the pixel circuit provided by the embodiment of the present invention. Under the premise of being able to achieve the core invention of the embodiment of the present invention, the embodiment of the present invention does not limit the specific structure of the pixel circuit. Figure 2 Taking the structure of the pixel circuit shown as an example, taking the driving transistor M1, the bias adjustment transistor M2, the data writing transistor M3, the first light-emitting control transistor M6, the second light-emitting control transistor M7 and the reset transistor M8 as P-type transistors, and the threshold compensation transistor M5 and the initialization transistor M4 as N-type transistors as an example, the working process of the pixel circuit provided in an embodiment of the present invention is exemplarily described.

[0066] Combined with reference Figure 1 , Figure 2 , Figure 6 and Figure 7 In the data refresh frame T1, the working process of the pixel circuit 10 includes a first bias adjustment phase t1, an initialization phase t2, a data writing phase t3, and a light emitting phase, wherein:

[0067] In the first bias adjustment t1, the light-emitting control signal EM, the second scan control signal S2 and the fourth scan control signal S4 are at a high level, the first scan control signal S1, the third scan control signal S3, and the fifth scan control signal S5 are at a low level, the light-emitting control signal EM controls the first light-emitting control transistor M6 and the second light-emitting control transistor M7 to turn off, the second scan control signal S2 controls the data writing transistor M3 to turn off, the third scan control signal S3 controls the initialization transistor M4 to turn off, and the fourth scan control signal S4 controls the threshold compensation transistor M5 to turn off, while the first scan control signal S1 controls the bias adjustment transistor M2 to turn on, the fourth scan control signal S4 controls the threshold compensation transistor M5 to turn on, and the fifth scan control signal S5 controls the reset transistor M8 to turn on. The turned-on reset transistor M8 transmits the reset signal Vref2 to the first end of the light-emitting module 11 to reset the light-emitting module 11, thereby preventing the charge retained in the previous driving cycle T from affecting the luminous brightness of the current driving cycle T; at the same time, the turned-on bias adjustment transistor M2 transmits the bias adjustment signal DVH to the first electrode of the driving transistor M1. Since the gate of the driving transistor M1 is not initialized before the first bias adjustment stage t1, the gate voltage of the driving transistor M1 is the data signal Vdata written in the previous frame. The driving transistor M1 is turned on in the first bias adjustment stage t1, and the bias adjustment signal DVH can be written to the second electrode of the driving transistor M1 and is turned on through the threshold value of the conduction. The compensation transistor M5 is written to the gate of the driving transistor M1, so that the gate voltage, the voltage of the first electrode and the voltage of the second electrode of the driving transistor M1 can be adjusted before the data signal Vdata is written into the gate of the driving transistor M1, thereby adjusting the bias state of the driving transistor M1, ensuring the consistency of the output characteristics of each driving transistor M1 in each pixel circuit 10, and ensuring that before entering the light-emitting stage t4, the first electrode signal of the driving transistor M1 of each pixel circuit 10 is maintained as the bias adjustment signal DVH, preventing the accuracy of the driving current provided by the driving transistor M1 from being affected by the different written data signals Vdata, which is beneficial to improving the light-emitting accuracy of the light-emitting module 11.

[0068] In the initialization stage t2, the light-emitting control signal EM, the first scanning control signal S1, the second scanning control signal S2, the third scanning control signal S3, and the fifth scanning control signal S5 are at a high level, and the fourth scanning control signal S4 is at a low level. The light-emitting control signal EM controls the first light-emitting control transistor M6 and the second light-emitting control transistor M7 to be turned off, the first scanning control signal S1 controls the bias adjustment transistor M2 to be turned off, the second scanning control signal S2 controls the data writing transistor M3 to be turned off, the fourth scanning control signal S3 controls the threshold compensation transistor M5 to be turned off, and the fifth scanning control signal S5 controls the reset transistor M8 to be turned off, while the third scanning control signal S3 controls the initialization transistor M4 to be turned on. The turned-on initialization transistor M4 transmits the initialization signal Vref1 to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1 to prepare for the writing of the data signal.

[0069] In the data writing stage t3, the light emitting control signal EM, the first scanning control signal S1, the fourth scanning control signal S4, and the fifth scanning control signal S5 are at high levels, the second scanning control signal S2 and the third scanning control signal S3 are at low levels, the light emitting control signal EM controls the first light emitting control transistor M6 and the second light emitting control transistor M7 to be turned off, the first scanning control signal S1 controls the bias adjusting transistor M2 to be turned off, the third scanning control signal S3 controls the initialization transistor M4 to be turned off, and the fifth scanning control signal S5 controls the reset transistor M8 to be turned off, while the second scanning control signal S2 controls The data writing transistor M3 is turned on, and the fourth scanning control signal S4 controls the threshold compensation transistor M5 to be turned on. The turned-on data writing transistor M3 transmits the data signal Vdata to the first electrode of the driving transistor M1, and transmits it to the first electrode of the threshold compensation transistor M5 through the turned-on driving transistor M1; the turned-on threshold compensation transistor M5 transmits the voltage of the second electrode of the driving transistor M1 to the gate of the driving transistor M1 until the gate voltage of the driving transistor M1 is charged to be equal to the sum of the data signal Vdata and the threshold voltage of the driving transistor M1, and the driving transistor M1 is in a critical state of conduction.

[0070] In the light-emitting stage t4, the light-emitting control signal EM, the third scanning control signal S3 and the fourth scanning control signal S4 are at a low level, the first scanning control signal S1, the second scanning control signal S2 and the fifth scanning control signal S5 are at a high level, the first scanning control signal S1 controls the bias adjustment transistor M2 to be turned off, the second scanning control signal S2 controls the data writing transistor M3 to be turned off, the third scanning control signal S3 controls the initialization transistor M4 to be turned off, the fourth scanning control signal S4 controls the threshold compensation transistor M5 to be turned off, and the fifth scanning control signal S5 controls the reset transistor M8 to be turned off, and the light-emitting control signal EM controls the first light-emitting control transistor M5 and the second light-emitting control transistor M6 to be turned on; the turned-on first light-emitting control transistor M5 transmits the first power supply voltage provided by the first power supply VDD to the first electrode of the driving transistor M1, and the driving transistor M1 generates a driving current according to the voltage of the first electrode and the gate thereof, and transmits the driving current to the second power supply VSS through the turned-on second light-emitting control transistor M6 through the light-emitting module 11, so that the first power supply VDD and the second power supply VSS form a current path to drive the light-emitting module 11 to emit light.

[0071] Exemplarily, the first scan control signal S1 is multiplexed into the fifth scan control signal S5, which can reset the anode of the light emitting module 11 while writing the bias adjustment signal DVH to the driving transistor M1. This can reduce the number of signals provided by the driving IC, which is conducive to simplifying the control process of the driving IC.

[0072] refer to Figure 7 , the holding frame T2 may include the second bias adjustment stage t5 and the third bias adjustment stage t6 and the light-emitting stage t4, the light-emitting control signal EM and the second scanning control signal S2 are at a high level, the first scanning control signal S1, the third scanning control signal S3, the fourth scanning control signal S4, and the fifth scanning control signal S5 are at a low level, so that the data writing transistor M3, the initialization transistor M4, the threshold compensation transistor M5, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are turned off, and the bias adjustment transistor M2 and the reset transistor M8 are turned on. The turned-on reset transistor M8 transmits the reset signal Vref2 to the first end of the light-emitting module 11 to reset the light-emitting module 11, thereby preventing the charge retained in the previous driving cycle T from affecting the luminous brightness of the current driving cycle T; at the same time, the turned-on bias adjustment transistor M2 transmits the bias adjustment signal DVH to the first electrode of the driving transistor M1, so that the first electrode signal of the driving transistor M1 can be consistent with the bias adjustment signal DVH, ensuring that before entering the light-emitting stage t4, the first electrode signal of the driving transistor M1 of each pixel circuit 10 is maintained as the bias adjustment signal DVH, preventing the accuracy of the driving current provided by the driving transistor M1 from being affected by the different written data signals Vdata, thereby facilitating improving the light-emitting accuracy of the light-emitting module 11.

[0073] In this embodiment, N1=1 and N2=2, i.e., N1<N2, are exemplarily shown, i.e., the first scanning control signal S1 outputs only one valid level in the data refresh frame T1, so that the data refresh frame T1 only includes one bias adjustment stage T1 (i.e., the first bias adjustment stage t1), and the bias adjustment of the driving transistor M1 is only performed once in the data refresh frame T1. In this way, for the high-frequency refresh mode including only the data refresh frame T1, since the output characteristic deviation of the driving transistor M1 is relatively low, the bias adjustment of the driving transistor M1 is performed only once, so that the bias adjustment of the driving transistor M1 is relatively small, and the excessive bias adjustment of the driving transistor M1 can be avoided, resulting in the problem that the state of the driving transistor M1 is not easy to switch when switching the display screen, thereby avoiding the long retention time of the display screen afterimage of the previous frame when switching the screen in the high-frequency refresh mode, and improving the display effect in the high-frequency refresh mode. In addition, in the low-frequency refresh mode including the holding frame T2, the first scanning control signal S1 also outputs only one valid level in the data refresh frame T1, and outputs two valid levels in the holding frame T2, that is, N1<N2 is set, so that the data refresh frame T1 includes one bias adjustment stage, and the holding frame T2 includes two bias adjustment stages (i.e., the second bias adjustment stage t5 and the third bias adjustment stage t6). In this way, it is possible to avoid excessive bias adjustment of the driving transistor M1 in the data refresh frame T1 to avoid the problem of a long retention time of the afterimage of the switching screen, and at the same time, in order to address the problem of output characteristic deviation caused by the long-term conduction of the driving transistor M1, the driving transistor M1 can be sufficiently biased in the holding frame T2 to reduce the degree of output characteristic deviation of the driving transistor M1, so as to ensure that the degree of output characteristic deviation of the driving transistor M1 remains consistent under different refresh frequencies, and the flicker problem in the low-frequency refresh mode can be improved on the basis of improving the afterimage problem.

[0074] Exemplarily, the pixel circuit 10 may also be a 7T1C circuit. Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention, Fig. 9 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.10 is another driving timing diagram of a pixel circuit provided by an embodiment of the present invention, and is combined with reference to Figure 8 to Figure 10 , the bias adjustment module 13 is multiplexed as the data writing module 12, and the first scanning control signal S1 includes a second effective level EP2 in the data refresh frame T1; the second effective level EP2 is located in the data writing phase t3.

[0075] In this way, the bias adjustment transistor M2 in the bias adjustment module 13 can be multiplexed as the data writing transistor M3 in the data writing module 12, and the corresponding bias adjustment signal DVH is multiplexed as the data signal Vdata, and the first scanning control signal S1 is multiplexed as the second scanning control signal S2 and the fifth scanning control signal S5. By setting the second effective level EP2 to be located in the data writing stage t3, the first scanning control signal S1 can control the bias adjustment transistor M2 to be turned on in the data writing stage t3, so that the bias adjustment transistor M2 can drive the transistor M1 to write the data signal Vdata.

[0076] For example, continue to refer to Figure 8 to Figure 10 , when the second effective level EP2 is in the data writing stage t3, N1 can be set to 1, that is, the first scanning control signal S1 outputs an effective level only once in the data writing stage t3 in the data refresh frame T1, and does not output an effective level in other time periods of the data refresh frame T1, so that in the data refresh frame T1, only the first scanning control signal S1 controls the bias adjustment transistor M2 to be turned on to realize the writing of the data signal Vdata, and the bias adjustment signal DVH is not written, and the bias adjustment of the driving transistor M1 is not performed. It can avoid writing the bias adjustment signal DVH to the driving transistor M1 in the data refresh frame T1, so that the bias degree of the driving transistor M1 is large, and the problem of the residual image remaining for a long time can be avoided.

[0077] Continue to refer Figure 8 to Figure 10 , N2=2 can also be set, then N1<N2 is satisfied at this time, so that the first scan control signal S1 outputs two valid levels in the holding frame T2, and can perform two bias adjustments on the driving transistor M1 in the holding frame T2, so as to improve the flicker problem in the low-frequency refresh mode. Exemplarily, the stages in which the first scan control signal S1 outputs two valid levels in the holding frame T2 are the third bias adjustment stage t6 and the fourth bias adjustment stage t7. Among them, the time interval between the fourth bias adjustment stage t7 and the light-emitting stage t4 in the holding frame T2 can be the same as the time interval between the data writing stage t3 and the light-emitting stage t4 in the data refresh frame T1, and the third bias adjustment stage t6 in the holding frame T2 is located between the fourth bias adjustment stage t7 and the light-emitting stage t4, so that the jump of the first scan control signal S1 before the third bias adjustment stage t6 in the holding frame T2 stage can be the same as its jump in the same time period of the data refresh frame T1, which is conducive to simplifying the control process of the first scan control signal S1.

[0078] Fig.11 is another driving timing diagram of a pixel circuit provided by an embodiment of the present invention, and is combined with reference to Figure 8 and Fig.11, N1=N2, the duration of the first scanning control signal S1 outputting the valid level in the data refresh frame T1 is the first duration ta, and the duration of the first scanning control signal S1 outputting the valid level in the holding frame T2 is the second duration tb; the first duration ta is shorter than the second duration tb.

[0079] Specifically, in the case of N1=1, N2=1 can also be set so that N1=N2, so that the first scanning control signal S1 outputs a valid level in the holding frame T2, and writes the bias adjustment signal DVH to the driving transistor M1 when the first scanning control signal S1 outputs the valid level, so as to bias the driving transistor M1, so as to avoid the driving transistor being on for a long time T1 so that the output characteristic is greatly offset and the driving current is inaccurate, which can improve the flicker problem in the low-frequency refresh mode. When the first scanning control signal S1 outputs a valid level in the holding frame T2, the duration (i.e., the second duration tb) of the first scanning control signal S1 outputting the valid level in the holding frame T2 can be made longer, so as to avoid the short-time bias adjustment being unable to meet the output characteristic offset caused by the long-term conduction of the driving transistor M1, so as to ensure that the driving transistor M1 generates an accurate driving current, thereby ensuring that the light-emitting module 11 emits light accurately.

[0080] Fig.12 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.13 is another driving timing diagram of a pixel circuit provided by an embodiment of the present invention, and is combined with reference to Figure 8 , Fig.12 and Fig.13 , the first scan control signal S1 further includes a third effective level S3 in the data refresh frame T1; the third effective level EP3 is located before the second effective level EP2.

[0081] Specifically, when the bias adjustment module 12 is multiplexed as the data writing module 13, the first scanning control signal S1 can also be controlled to output the third effective level EP3 before the data writing phase t3, so that when the first scanning control signal S1 outputs the third effective level EP3, the bias adjustment signal DVH can be written to the driving transistor M1 to achieve bias adjustment of the driving transistor M1. Exemplarily, when the first scanning control signal S1 outputs the third effective level EP3 (i.e., low level), the third scanning control signal S3 is low level, the light emitting control signal EM and the fourth scanning control signal S4 are high level, then the bias adjustment transistor M2, the reset transistor M8 and the threshold compensation transistor M5 are turned on, and the initialization transistor M4 is turned off. The turned-on reset transistor M8 transmits the reset signal Vref2 to the first end of the light emitting module 11, thereby resetting the light emitting module 11 and preventing the charge retained in the previous driving cycle T from affecting the luminous brightness of the current driving cycle T; at the same time, the turned-on bias adjustment transistor M2 transmits the bias adjustment signal DVH to the first electrode of the driving transistor M1, and then writes it to the second electrode and the gate of the driving transistor M1 in sequence. The gate voltage, the voltage of the first electrode and the voltage of the second electrode of the driving transistor M1 can be adjusted before the data signal Vdata is written into the gate of the driving transistor M1, thereby adjusting the bias state of the driving transistor M1, ensuring the consistency of the output characteristics of each driving transistor M1 in each pixel circuit 10, and ensuring that before entering the light emitting stage t4, the first electrode signal of the driving transistor M1 of each pixel circuit 10 is maintained as the bias adjustment signal DVH, preventing the accuracy of the driving current provided by the driving transistor M1 from being affected by the different written data signals Vdata, thereby facilitating the improvement of the light emitting accuracy of the light emitting module 11.

[0082] Continue to refer Figure 8 , Fig.12 and Fig.13, the first scan control signal includes the second effective level EP2 and the third effective level EP3 in the data refresh frame T1 so that N1 = 2. At this time, N2 = 3, that is, the first scan control signal S1 can output two effective levels in the data write frame T1, and N1 < N2 is satisfied at this time. Then, in the holding frame T2, in addition to the second bias adjustment stage t5 and the third bias adjustment stage t6, the fourth bias adjustment stage t7 may also be included, that is, the first scanning control signal S1 outputs a valid level in the second bias adjustment stage t5, the third bias adjustment stage t6 and the fourth bias adjustment stage t7, so that the bias adjustment transistor M2 can write the bias adjustment signal DVH to the driving transistor M1 in the second bias adjustment stage t5, the third bias adjustment stage t6 and the fourth bias adjustment stage t7, respectively, so that the driving transistor M1 is bias-adjusted three times in the holding frame T2 to improve the output characteristic offset of the driving transistor M1, and ensure that before entering the light-emitting stage t4, the first electrode signal of the driving transistor M1 of each pixel circuit 10 is maintained as the bias adjustment signal DVH, so as to prevent the accuracy of the driving current provided by the driving transistor M1 from being affected by the different written data signals Vdata, thereby facilitating the improvement of the light-emitting accuracy of the light-emitting module 11. Among them, the time interval between the fourth bias adjustment stage t7 and the light-emitting stage t4 in the frame T2 can be the same as the time interval between the data writing stage t3 and the light-emitting stage t4 in the data refresh frame T1, the time interval between the second bias adjustment stage t5 and the fourth bias adjustment stage t7 in the frame T2 is the same as the time interval between the first bias adjustment stage t1 and the data writing stage t3 in the data refresh frame T1, and the third bias adjustment stage t6 in the frame T2 is located between the fourth bias adjustment stage t7 and the light-emitting stage t4. In this way, the jump of the first scanning control signal S1 before the third bias adjustment stage t6 in the frame T2 stage can be the same as its jump in the same time period of the data refresh frame T1, which is conducive to simplifying the control process of the first scanning control signal S1.

[0083] Optional, reference Figure 6 , Figure 7 and Figures 9 to 13 In any of the figures, the data refresh frame T1 and the hold frame T2 both include a non-luminous phase t0 and a luminous phase t4; in the non-luminous phase t0, the first scan control signal S1 includes a valid level; in the luminous phase t4, the first scan control signal S1 remains at an invalid level.

[0084] Specifically, in the non-light-emitting stage t0, the light-emitting control signal EM is maintained at an invalid level to control the first light-emitting control transistor M6 and the second light-emitting control transistor M7 to be turned off, so that a current path cannot be formed between the first power signal VDD and the second power signal VSS, and the light-emitting module 11 does not emit light. In the light-emitting stage t4, the light-emitting control signal EM is maintained at an invalid level to control the first light-emitting control transistor M6 and the second light-emitting control transistor M7 to be turned on, so that a current path can be formed between the first power signal VDD and the second power signal VSS, and the driving transistor M1 generates a driving current according to the data signal written to the gate, and drives the light-emitting module 11 to emit light. By setting the first scanning control signal S1 to include a valid level in the non-luminous stage t0 and to remain at an invalid level in the luminous stage t4, for the data refresh frame T1, the data signal Vdata can be written to the driving transistor M in the non-luminous stage t0, or the data signal Vdata and the bias adjustment signal DVH can be written to the driving transistor M1 in the non-luminous stage t0, so as to avoid writing the data signal Vdata or the bias adjustment signal DVH in the luminous stage t0 to cause the light-emitting module 11 to flicker, thereby affecting the display effect; similarly, for the holding frame T2, the bias adjustment signal DVH can be written to the driving transistor M1 in the non-luminous stage t0, so as to avoid writing the bias adjustment signal DVH in the luminous stage t0 to cause the light-emitting module 11 to flicker, thereby affecting the display effect.

[0085] Based on the same inventive concept, the technical solution of the embodiment of the present invention further provides a display panel, Fig.14 is a schematic diagram of a display panel provided by an embodiment of the present invention, with reference to Fig.14 The display device includes the display panel provided by any of the above embodiments. The display device can be a mobile phone, a tablet, a display, a smart watch, an MP3, an MP4 or other wearable devices, etc., because it includes the pixel circuit provided by any embodiment of the present invention, and thus has the same beneficial effects, which will not be described in detail here.

[0086] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0087] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: Pixel circuits arranged in an array; The pixel circuit includes a light emitting module, a driving module and a bias adjustment module; The driving module is used to drive the light-emitting module to emit light; The driving module includes a driving transistor; The bias adjustment module is electrically connected to the driving module, and the bias adjustment module receives a bias adjustment signal and a first scanning control signal; The bias adjustment module is used for outputting the bias adjustment signal to the driving module when the first scanning control signal outputs a valid level; The driving cycle of the pixel circuit includes a data refresh frame and m holding frames; m ≥ 0, and m is an integer; The number of valid levels output by the first scanning control signal in the data refresh frame is N1; When m≥1, the number of valid level outputs of the first scanning control signal in the holding frame is N2; 1≤N1≤N2, and N1 and N2 are both integers.

2. The display panel according to claim 1, characterized in that: The data refresh frame at least includes a data writing phase; In the data refresh frame, after the data writing phase, the first scanning control number is maintained at an invalid level.

3. The display panel according to claim 1, characterized in that: N1<N2.

4. The display panel according to claim 1, characterized in that: N1=N2; The duration of the first scan control signal outputting a valid level in the data refresh frame is a first duration, and the duration of the first scan control signal outputting a valid level in the hold frame is a second duration; the first duration is shorter than the second duration.

5. The display panel according to claim 1, characterized in that: The data refresh frame and the hold frame both include a non-light-emitting phase and a light-emitting phase; In the non-light-emitting stage, the first scanning control signal includes a valid level; In the light emitting stage, the first scanning control signal is maintained at an inactive level.

6. The display panel according to claim 2, characterized in that: The pixel circuit also includes a data writing module; The data writing module receives a data signal and a second scanning control signal; the second scanning control signal outputs a valid level in the data writing phase, so that the data writing module outputs the data signal to the driving module; The first scanning control signal comprises a first effective level in the data writing frame, and the first effective level is located before the data writing phase.

7. The display panel according to claim 2, characterized in that: The bias adjustment module is multiplexed as a data writing module; The first scanning control signal comprises a second effective level in the data refresh frame; The second effective level is in the data writing phase.

8. The display panel according to claim 7, characterized in that: The first scanning control signal further comprises a third effective level in the data refresh frame; The third effective level is located before the second effective level.

9. The display panel according to claim 1, characterized in that: The pixel circuit also includes an initialization module, a threshold compensation module and a storage module; The initialization module is electrically connected to the driving module, and the initialization module receives an initialization signal and a third scanning control signal; the initialization module is used to output the initialization signal to the driving module when the third scanning control signal outputs a valid level; The threshold compensation module is electrically connected to the driving module, and the threshold compensation module receives a fourth scanning control signal; the threshold compensation module is used to provide a compensation voltage to the driving module when the fourth scanning control signal outputs a valid level; The storage module is electrically connected to the driving module, and the storage module is used to store data signals.

10. The display panel according to claim 1, characterized in that: The pixel circuit further includes a first light emitting control module, a second light emitting control module and a reset module; The first light-emitting control module, the driving module, the second light-emitting control module and the light-emitting module are electrically connected between the first power supply terminal and the second power supply terminal in sequence, and the first light-emitting control module and the second light-emitting control module both receive a light-emitting control signal; The reset module is electrically connected to the light emitting module, and receives a reset signal and a fifth scanning control signal; the reset module is used to output the reset signal to the light emitting module when the fifth scanning control signal outputs a valid level.

11. The display panel according to claim 10, characterized in that: The first scanning control signal is multiplexed into the fifth scanning control signal.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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