Partition display circuit, driving method thereof, display panel and display equipment

Abstract

The invention discloses a partition display circuit and a driving method thereof, a display panel and display equipment, and relates to the technical field of display, the circuit comprises a display driving module, a main display area and an auxiliary display area, the display driving module comprises a main display driving part and an auxiliary display driving part, the main display driving part is electrically connected with a plurality of pixel rows of the main display area, and the auxiliary display driving part is electrically connected with a plurality of pixel rows of the auxiliary display area. The auxiliary display driving part is electrically connected with a plurality of pixel rows of the auxiliary display area; the display driving module is set to acquire a partition display demand of a user, determine a target display area according to the partition display demand, and enable the main display driving piece to supply power to a plurality of pixel rows of the main display area according to a preset main driving time sequence for the main display area according to the target display area; or, according to the target display area, enabling an auxiliary display driving part to supply power to a plurality of pixel rows of the auxiliary display area according to a preset auxiliary driving time sequence for the auxiliary display area. Partitioned display of the display panel is realized, so that display power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a partition display circuit and a driving method thereof, a display panel and a display device. Background Art

[0002] In the current field of display technology, with the widespread application of display devices, reducing display power consumption has become an important technical development direction.

[0003] Although existing display panels have made significant progress in resolution and display effects, there are still many inconveniences in partitioned display. For example, traditional display panels usually use overall backlight control, which cannot accurately adjust the brightness according to the display requirements of different areas, resulting in high power consumption. In addition, when traditional display panels are partitioned, it is difficult to achieve independent driving and brightness adjustment of different areas, which affects the display effect and power consumption control, and thus seriously restricts the energy-saving development of display panels.

[0004] Therefore, how to realize partitioned display of a display panel to reduce display power consumption is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The main purpose of the present application is to provide a partition display circuit and a driving method thereof, a display panel and a display device, aiming to realize partition display of the display panel to reduce display power consumption.

[0006] To achieve the above-mentioned object, the present application provides a partition display circuit, the partition display circuit includes a display driving module, a main display area and a sub-display area, the display driving module includes a main display driving component and a sub-display driving component, the main display driving component is electrically connected to a plurality of pixel rows in the main display area, and the sub-display driving component is electrically connected to a plurality of pixel rows in the sub-display area; The display driver module is configured to obtain the user's partition display requirements, and determine the target display area based on the partition display requirements, and enable the main display driver to power multiple pixel rows in the main display area according to a preset main drive timing for the main display area according to the target display area; or, enable the secondary display driver to power multiple pixel rows in the secondary display area according to a preset secondary drive timing for the secondary display area according to the target display area.

[0007] In one embodiment, the main display driver includes a first main driving module, and the first main driving module includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor and a second capacitor; The gate terminal of the first thin film transistor and the first channel terminal of the first thin film transistor are both electrically connected to the main gate terminals of the first two stages of the current main gate terminal, the second channel terminal of the first thin film transistor is electrically connected to the first end of the first capacitor and the gate terminal of the second thin film transistor respectively, and the first channel terminal of the second thin film transistor is electrically connected to the main clock signal terminal of the current stage; The gate terminal of the third thin film transistor, the first channel terminal of the third thin film transistor, the second terminal of the first capacitor, and the second channel terminal of the second thin film transistor are all electrically connected to the current main gate terminal, the second channel terminal of the third thin film transistor is electrically connected to the second capacitor and the gate terminal of the fourth thin film transistor, respectively, the first channel terminal of the fourth thin film transistor is electrically connected to the latter two main clock terminals of the current main clock signal terminal, and the second channel terminal of the fourth thin film transistor is electrically connected to the latter two main gate terminals of the current main gate terminal.

[0008] In one embodiment, the main display driver further includes a second main driving module, and the second main driving module includes a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a third capacitor and a fourth capacitor; The gate terminal of the fifth thin film transistor and the first channel terminal of the fifth thin film transistor are both electrically connected to the main gate terminal of the previous stage of the current main gate terminal, the second channel terminal of the fifth thin film transistor is electrically connected to the first end of the third capacitor and the gate terminal of the sixth thin film transistor respectively, and the first channel terminal of the sixth thin film transistor is electrically connected to the main clock signal terminal of the next stage of the current main clock signal terminal; The gate terminal of the seventh thin film transistor, the first channel terminal of the seventh thin film transistor, the second end of the third capacitor, and the second channel terminal of the sixth thin film transistor are all electrically connected to the main gate terminal of the next level of the current main gate terminal, the second channel terminal of the seventh thin film transistor is electrically connected to the fourth capacitor and the gate terminal of the eighth thin film transistor respectively, the first channel terminal of the eighth thin film transistor is electrically connected to the next three main clock terminals of the current main clock signal terminal, and the second channel terminal of the eighth thin film transistor is electrically connected to the next three main gate terminals of the current main gate terminal.

[0009] In one embodiment, the auxiliary display area includes an upper display area and a lower display area, and the upper display area and the lower display area are respectively arranged on both sides of the main display area; wherein, The number of pixel rows in the upper display area is the same as the number of pixel rows in the lower display area, and the total number of pixel rows between the number of pixel rows in the upper display area and the number of pixel rows in the lower display area is less than the number of pixel rows in the main display area.

[0010] In one embodiment, the auxiliary display driver includes an upper display driver corresponding to the upper display area, and a lower display driver corresponding to the lower display area; The upper display driver is electrically connected to a plurality of pixel rows in the upper display area, and the lower display driver is electrically connected to a plurality of pixel rows in the lower display area.

[0011] In one embodiment, the upper display driving element includes a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a fifth capacitor and a sixth capacitor; The gate terminal of the ninth thin film transistor and the first channel terminal of the ninth thin film transistor are both electrically connected to the upper gate terminal of the previous stage of the current upper gate terminal, the second channel terminal of the ninth thin film transistor is electrically connected to the first end of the fifth capacitor and the gate terminal of the tenth thin film transistor respectively, and the first channel terminal of the tenth thin film transistor is electrically connected to the upper clock signal terminal of the current stage; The gate terminal of the eleventh thin film transistor, the first channel terminal of the eleventh thin film transistor, the second terminal of the fifth capacitor, and the second channel terminal of the tenth thin film transistor are all electrically connected to the current upper gate terminal, the second channel terminal of the eleventh thin film transistor is electrically connected to the sixth capacitor and the gate terminal of the twelfth thin film transistor, respectively, the first channel terminal of the twelfth thin film transistor is electrically connected to the clock terminal of the next level of the clock signal terminal of the current level, and the second channel terminal of the twelfth thin film transistor is electrically connected to the upper gate terminal of the next level of the current upper gate terminal.

[0012] In one embodiment, the lower display driving element includes a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventh capacitor and an eighth capacitor; The gate terminal of the thirteenth thin film transistor and the first channel terminal of the thirteenth thin film transistor are both electrically connected to the lower gate terminal of the previous stage of the current lower gate terminal, the second channel terminal of the thirteenth thin film transistor is electrically connected to the first end of the seventh capacitor and the gate terminal of the fourteenth thin film transistor respectively, and the first channel terminal of the fourteenth thin film transistor is electrically connected to the lower clock signal terminal of the current stage; The gate terminal of the fifteenth thin film transistor, the first channel terminal of the fifteenth thin film transistor, the second terminal of the seventh capacitor, and the second channel terminal of the fourteenth thin film transistor are all electrically connected to the current lower gate terminal, the second channel terminal of the fifteenth thin film transistor is electrically connected to the eighth capacitor and the gate terminal of the sixteenth thin film transistor, respectively, the first channel terminal of the sixteenth thin film transistor is electrically connected to the next level lower clock terminal of the current level lower clock signal terminal, and the second channel terminal of the sixteenth thin film transistor is electrically connected to the next level lower gate terminal of the current lower gate terminal.

[0013] In addition, to achieve the above-mentioned purpose, the present application also provides a driving method of a partition display circuit, the driving method is applied to any of the partition display circuits described above, and the driving method includes: Obtaining the user's partition display requirements through the display driver module, and determining the target display area according to the partition display requirements; According to the target display area being the main display area, the main display driver in the display driver module is enabled to power multiple pixel rows in the main display area according to a preset main drive timing; or, according to the target display area being the secondary display area, the secondary display driver in the display driver module is enabled to power multiple pixel rows in the secondary display area according to a preset secondary drive timing.

[0014] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the partition display circuit described in any one of the above items.

[0015] In addition, to achieve the above-mentioned purpose, the present application also provides a display device, the display device includes the above-mentioned display panel; or, The display device includes a processor, a memory, and a driver program stored in the memory and executable by the processor, wherein the driver program implements the steps of the above-mentioned driving method when executed by the processor.

[0016] The partition display circuit provided in the present application realizes the partition display of the display panel to reduce the display power consumption. The partition display circuit includes a display driver module, a main display area and a secondary display area, wherein the display driver module integrates a main display driver and a secondary display driver; the main display driver is electrically connected to multiple pixel rows in the main display area, and the secondary display driver is electrically connected to multiple pixel rows in the secondary display area, thereby realizing the partition independent drive of the main display area and the secondary display area. Specifically, the display driver module can accurately obtain the target display area according to the user's partition display requirements; next, the main display driver or the secondary display driver is selectively enabled according to the different target display areas, that is, when the target display area is the main display area, the main display driver is enabled to power multiple pixel rows in the main display area according to the preset main drive timing; when the target display area is the secondary display area, the secondary display driver is enabled to power multiple pixel rows in the secondary display area according to the preset secondary drive timing, thereby realizing the power supply of the pixel rows in the display area specified by the partition display requirements, thereby effectively avoiding the unnecessary power consumption waste of the traditional display panel under the overall backlight control, and significantly reducing the display power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 It is a structural block diagram of the first embodiment of the partition display circuit of the present application; Figure 2 It is a schematic diagram of a partition display circuit involved in an embodiment of the present application; Figure 3 It is a schematic diagram of a signal waveform of a partition display circuit involved in an embodiment of the present application; Figure 4 is a schematic diagram of an upper display area involved in an embodiment of the present application; Figure 5 It is a schematic diagram of the main display area involved in the embodiment of the present application; Figure 6 is a schematic diagram of the lower display area involved in the embodiment of the present application; Figure 7 It is a schematic diagram of the structure of the display device involved in the embodiment of the present application.

[0020] Explanation of the accompanying drawings: 10, main display driver; 20, auxiliary display driver; 11, first main driver module; T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; T4, fourth thin film transistor; C1, first capacitor; C2, second capacitor; 12, second main driver module; T5, fifth thin film transistor; T6, sixth thin film transistor; T7, seventh thin film transistor; T8, eighth thin film transistor; C3, third capacitor; C4, fourth capacitor; 21, upper display driver; T9, ninth thin film transistor; T10, tenth thin film transistor; T11, eleventh thin film transistor; T12, twelfth thin film transistor; C5, fifth capacitor; C6, sixth capacitor; 22, lower display driver; T13, thirteenth thin film transistor; T14, fourteenth thin film transistor; T15, fifteenth thin film transistor; T16, sixteenth thin film transistor; C7, seventh capacitor; C8, eighth capacitor.

[0021] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0024] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0025] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0026] In the current field of display technology, with the widespread application of display devices, reducing display power consumption has become an important technical development direction.

[0027] Although existing display panels have made significant progress in resolution and display effects, there are still many inconveniences in partitioned display. For example, traditional display panels usually use overall backlight control, which cannot accurately adjust the brightness according to the display requirements of different areas, resulting in high power consumption. In addition, when traditional display panels are partitioned, it is difficult to achieve independent driving and brightness adjustment of different areas, which affects the display effect and power consumption control, and thus seriously restricts the energy-saving development of display panels.

[0028] Therefore, how to realize partitioned display of a display panel to reduce display power consumption is a technical problem that needs to be solved urgently.

[0029] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art.

[0030] In order to solve the technical defects existing in the above content, the present application provides a partition display circuit and a driving method thereof, a display panel and a display device.

[0031] The present application embodiment provides a partition display circuit, referring to Figure 1 As shown, Figure 1 1 is a block diagram of the first embodiment of the partition display circuit of the present application. The partition display circuit includes a display driving module, a main display area and a secondary display area, wherein the display driving module includes a main display driving component 10 and a secondary display driving component 20, wherein the main display driving component 10 is electrically connected to a plurality of pixel rows in the main display area, and the secondary display driving component 20 is electrically connected to a plurality of pixel rows in the secondary display area.

[0032] In this embodiment, the partition display circuit provided in the present application divides the display panel into a main display area and a sub-display area, and is respectively equipped with a main display driver 10 and a sub-display driver 20, thereby realizing independent control of different display areas, thereby significantly improving the power consumption management capability and display flexibility of the display panel.

[0033] In a specific embodiment, the main display driver 10 is electrically connected to multiple pixel rows in the main display area, and can independently adjust its main drive timing and brightness output according to the display content requirements of the main display area; the auxiliary display driver 20 is electrically connected to multiple pixel rows in the auxiliary display area, and can also independently adjust its auxiliary drive timing and brightness output according to the display content requirements of the auxiliary display area, so that the display panel can flexibly adjust the display status of the main display area and the auxiliary display area according to the actual usage scenario.

[0034] The display driver module is configured to obtain the user's partition display requirements, and determine the target display area based on the partition display requirements, and enable the main display driver 10 to power multiple pixel rows in the main display area according to a preset main drive timing for the main display area according to the target display area; or, enable the auxiliary display driver 20 to power multiple pixel rows in the auxiliary display area according to a preset auxiliary drive timing for the auxiliary display area according to the target display area.

[0035] In this embodiment, after the display driver module receives the user's partition display demand based on the preset human-computer interaction interface, the partition display scene corresponding to the partition display demand is obtained, and when the partition display scene is the main display area usage scene, the target display area is determined to be the main display area; next, based on the response of the driver chip in the display driver module to the target display area as the main display area, the display drive state of the main display driver 10 is enabled to switch from the off state to the drive state, and a stable and reliable power supply is provided for the multiple pixel rows in the main display area for normal display according to the preset main drive timing; at the same time, the driver chip also responds to the target display area as the main display area, enabling the auxiliary display driver 20 to maintain the off state, thereby avoiding the auxiliary display area from consuming additional power consumption when displaying non-essentially.

[0036] In another implementation, when the partition display scenario is a sub-display area usage scenario, the target display area is determined to be the sub-display area; next, based on the response of the driver chip in the display driver module to the target display area being the sub-display area, the display drive state of the sub-display driver 20 is enabled to switch from the off state to the drive state, and a stable and reliable power supply is provided to the multiple pixel rows in the sub-display area for normal display according to the preset sub-drive timing; at the same time, the driver chip also responds to the target display area being the sub-display area, enabling the main display driver 10 to maintain the off state, thereby avoiding the main display area from consuming additional power consumption during non-essential display.

[0037] It should be noted that the use scenario of the main display area can be understood as a dynamic content display scenario, such as game screen display, movie screen display, and novel browsing screen display scenario, etc. The use scenario of the secondary display area can be understood as a static content display scenario, such as time interface display, phone interface display, and text message interface display scenario, etc.

[0038] The auxiliary display driver 20 includes an upper display driver 21 and a lower display driver 22; the preset auxiliary drive timing may include an upper drive timing and a lower drive timing; the auxiliary display area may include an upper display area and a lower display area; the upper display area may be used to display static information such as time, phone or text message notifications, and the lower display area may display other auxiliary content, such as system status, shortcut operation buttons or a typing keyboard. The above is only a feasible implementation method of the present application, and the functions of the upper display area and the lower display area can be interchangeable, and the present application does not impose any restrictions here.

[0039] For example, when the user's partition display requirement is to check the time and other basic interfaces or the display power of the display panel meets the preset single-zone display power threshold, the upper display driver 21 can provide a stable and reliable power supply for multiple pixel rows in the upper display area according to the upper drive timing for normal display, which not only meets the user's display needs by displaying the upper display area separately, but also effectively reduces power consumption.

[0040] Further, in some feasible embodiments, referring to Figure 2 , Figure 2 It is a schematic diagram of a partition display circuit involved in the embodiment of the present application. The main display driver 10 includes a first main driving module 11, and the first main driving module 11 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a first capacitor C1, and a second capacitor C2; the gate end of the first thin film transistor T1 and the first channel end of the first thin film transistor T1 are electrically connected to the first two main gate ends of the current main gate end, the second channel end of the first thin film transistor T1 is electrically connected to the first end of the first capacitor C1 and the gate end of the second thin film transistor T2, respectively, and the first channel end of the second thin film transistor T2 is electrically connected to the current level The main clock signal terminal is electrically connected; the gate terminal of the third thin film transistor T3, the first channel terminal of the third thin film transistor T3, the second end of the first capacitor C1, and the second channel terminal of the second thin film transistor T2 are all electrically connected to the current main gate terminal, the second channel terminal of the third thin film transistor T3 is electrically connected to the second capacitor C2 and the gate terminal of the fourth thin film transistor T4, respectively, the first channel terminal of the fourth thin film transistor T4 is electrically connected to the latter two stages of the main clock terminals of the current main clock signal terminal, and the second channel terminal of the fourth thin film transistor T4 is electrically connected to the latter two stages of the main gate terminals of the current main gate terminal.

[0041] In this embodiment, when the target display area is the main display area, the driving chip provides a signal STV2 to the current-stage main clock signal terminal in the first driving module and to the next two stages of main clock terminals of the current-stage main clock signal terminal.

[0042] It should be noted that the clock signal connected to the current master clock signal terminal can be used Figure 2 The signal clk3 shown in the figure represents the current master clock signal terminal; the next two master clock terminals can be used Figure 2 The signal clk5 shown in the figure represents the gate drive signal of the first two main gate terminals of the current main gate terminal. Figure 2 The signal Gn-2 shown in the figure represents the gate drive signal currently connected to the main gate terminal. Figure 2 The signal Gn shown in FIG. 1 represents the gate drive signal of the two main gate terminals after the current main gate terminal. Figure 2 The signal Gn+2 shown is representative.

[0043] For example, refer to Figures 2 to 3 The driver chip set in the present application responds to the target display area as the main display area, and the enable signal STV2 is Figure 3 The low potential shown is switched to a high potential; next, the signal STV2 is turned high to turn on the signal clk3 and the signal clk5, that is, the signal clk3 and the signal clk5 are switched from a low potential to a high potential respectively.

[0044] Further, in some other feasible embodiments, referring to Figure 2 The main display driver 10 further includes a second main driving module 12, which includes a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, a third capacitor C3 and a fourth capacitor C4; the gate terminal of the fifth thin film transistor T5 and the first channel terminal of the fifth thin film transistor T5 are both electrically connected to the main gate terminal of the previous stage of the current main gate terminal, the second channel terminal of the fifth thin film transistor T5 is respectively electrically connected to the first end of the third capacitor C3 and the gate terminal of the sixth thin film transistor T6, the first channel terminal of the sixth thin film transistor T6 is electrically connected to the rear end of the main clock signal terminal of the current stage a first-level master clock signal terminal is electrically connected; a gate terminal of the seventh thin film transistor T7, a first channel terminal of the seventh thin film transistor T7, a second end of the third capacitor C3, and a second channel terminal of the sixth thin film transistor T6 are all electrically connected to a main gate terminal of a subsequent level of the current main gate terminal, a second channel terminal of the seventh thin film transistor T7 is electrically connected to the fourth capacitor C4 and a gate terminal of the eighth thin film transistor T8, respectively, a first channel terminal of the eighth thin film transistor T8 is electrically connected to the subsequent three levels of main clock terminals of the current main clock signal terminal, and a second channel terminal of the eighth thin film transistor T8 is electrically connected to the subsequent three levels of main gate terminals of the current main gate terminal.

[0045] In this embodiment, the driving chip provides a signal STV2 to the current-level master clock signal terminal and the next two-level master clock terminals of the current-level master clock signal terminal in the first driving module based on the display situation of the target display area as the main display area, and also provides a signal STV2 to the next-level master clock signal terminal of the current-level master clock signal terminal and the next three-level master clock terminals of the current-level master clock signal terminal in the second driving module.

[0046] It should be noted that the clock signal connected to the next-level master clock signal terminal of the current-level master clock signal terminal can be used Figure 2 The signal clk4 shown in the figure represents the current master clock signal end; the next three master clock ends can be used Figure 2The signal clk6 shown in the figure represents the gate drive signal connected to the previous main gate terminal of the current main gate terminal. Figure 2 The signal Gn-1 shown in the figure represents the gate drive signal connected to the next-stage main gate terminal of the current main gate terminal. Figure 2 The signal Gn+1 shown in the figure represents the gate drive signal of the three main gate terminals after the current main gate terminal. Figure 2 The signal Gn+3 shown is representative.

[0047] For example, refer to Figures 2 to 3 The driver chip set in the present application responds to the target display area as the main display area, and the enable signal STV2 is Figure 3 The low potential shown is switched to a high potential; next, the signal STV2 is turned high to turn on the signal clk4 and the signal clk6, that is, the signal clk4 and the signal clk6 are connected to Figure 3 The corresponding signal waveform is shown.

[0048] In the specific example, refer to Figures 2 to 3 , the display of the main display area is sequentially turned on by signal STV2, signal clk3, signal clk4, signal clk5 and signal clk6 for 4clk repetitive cycles. Generally, the number of pixel rows set in the main display area is about 1500, that is, the number of cycles of 4clk repetitive cycles is 1500 / 4=375 times. In other words, the preset main driving timing is 4clk repetitive cycle drive, that is, signal clk3, signal clk4, signal clk5 and signal clk6 work in a cycle in turn, and drive 4 pixel rows in each cycle; illustratively, for the 1500 pixel row drive in the main display area, signal clk3 drives the first pixel row in each cycle (that is, the pixel row electrically connected to the signal Gn terminal), signal clk4 drives the second pixel row in each cycle (that is, the pixel row electrically connected to the signal Gn+1 terminal), signal clk5 drives the third pixel row in each cycle (that is, the pixel row electrically connected to the signal Gn+2 terminal), and signal clk6 drives the third pixel row in each cycle (that is, the pixel row electrically connected to the signal Gn+2 terminal).

[0049] Further, in some feasible embodiments, referring to Figure 2 , the secondary display area includes an upper display area and a lower display area, and the upper display area and the lower display area are respectively arranged on both sides of the main display area; wherein the number of pixel rows in the upper display area is the same as the number of pixel rows in the lower display area, and the total number of pixel rows between the number of pixel rows in the upper display area and the number of pixel rows in the lower display area is less than the number of pixel rows in the main display area.

[0050] In the present embodiment, the secondary display area is divided into an upper display area and a lower display area, and the upper display area and the lower display area are respectively arranged on both sides of the main display area. Specifically, the number of pixel rows in the upper display area and the lower display area is the same, and the total number of pixel rows between the number of pixel rows in the upper display area and the number of pixel rows in the lower display area is less than the number of pixel rows in the main display area. As a result, the main display area can occupy the central part of the display panel to display the main dynamic content, such as game screens, video playback, etc., while the upper display area and the lower display area can be used to display static or auxiliary information, such as time, notifications, status bars, etc. In other words, the present application provides an upper display area and a lower display area on both sides of the main display area, so that the display panel can flexibly adjust the display state and power consumption distribution of each area according to different display requirements, thereby significantly reducing the overall power consumption while optimizing the display effect and improving the energy efficiency performance of the display panel.

[0051] Further, in some other feasible embodiments, referring to Figure 2 The auxiliary display driver 20 includes an upper display driver 21 corresponding to the upper display area, and a lower display driver 22 corresponding to the lower display area; the upper display driver 21 is electrically connected to multiple pixel rows in the upper display area, and the lower display driver 22 is electrically connected to multiple pixel rows in the lower display area.

[0052] In this embodiment, the auxiliary display driver 20 is integrated with Figure 2 The upper display driver 21 and the lower display driver 22 shown correspond to the driving requirements of the upper display area and the lower display area respectively. The upper display driver 21 is electrically connected to multiple pixel rows in the upper display area and is responsible for controlling the display output of the upper display area; the lower display driver 22 is electrically connected to multiple pixel rows in the lower display area and is used to control the display output of the lower display area; thereby enabling the upper display area and the lower display area to be independently controlled from the main display area, achieving more flexible display functions and lower power consumption management. For example, the upper display area can be used to display static information such as time or notifications, while the lower display area can display other auxiliary content, such as system status, shortcut operation buttons or typing keyboards. Through the upper display driver 21 and the lower display driver 22 corresponding to the upper display area and the lower display area, the upper display area and the lower display area can adjust parameters such as brightness and refresh rate according to their respective display contents, further optimizing the display effect and power consumption performance.

[0053] Further, in some feasible embodiments, referring to Figure 2The upper display driving element 21 includes a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, a fifth capacitor C5 and a sixth capacitor C6; the gate terminal of the ninth thin film transistor T9 and the first channel terminal of the ninth thin film transistor T9 are both electrically connected to the previous stage upper gate terminal of the current upper gate terminal, the second channel terminal of the ninth thin film transistor T9 is electrically connected to the first end of the fifth capacitor C5 and the gate terminal of the tenth thin film transistor T10 respectively, the first channel terminal of the tenth thin film transistor T10 is electrically connected to the current stage upper clock signal terminal; the tenth The gate terminal of the first thin film transistor T11, the first channel terminal of the eleventh thin film transistor T11, the second terminal of the fifth capacitor C5, and the second channel terminal of the tenth thin film transistor T10 are all electrically connected to the current upper gate terminal, the second channel terminal of the eleventh thin film transistor T11 is electrically connected to the sixth capacitor C6 and the gate terminal of the twelfth thin film transistor T12 respectively, the first channel terminal of the twelfth thin film transistor T12 is electrically connected to the next-stage upper clock terminal of the current-stage upper clock signal terminal, and the second channel terminal of the twelfth thin film transistor T12 is electrically connected to the next-stage upper gate terminal of the current upper gate terminal.

[0054] In this embodiment, when the target display area is the upper display area in the auxiliary display area, the driving chip provides a signal STV1 to the current level upper clock signal terminal in the upper display area and to the next level upper clock terminal of the current level upper clock signal terminal.

[0055] It should be noted that the clock signal connected to the clock signal terminal of the current stage can be used Figure 2 The signal clk1 shown in the figure represents that the clock terminal of the next stage can be used when the clock signal terminal of the current stage is Figure 2 The signal clk2 shown in the figure represents the gate drive signal connected to the previous stage upper gate terminal of the current upper gate terminal. Figure 2 The signal gn-1 shown is representative; the current upper gate terminal can be Figure 2 The signal gn shown in the figure represents the gate drive signal connected to the next level upper gate terminal of the current upper gate terminal. Figure 2 The signal gn+1 shown represents: In addition, the preset auxiliary driving timing may include an up driving timing and a down driving timing.

[0056] For example, refer to Figures 2 to 3 The driver chip provided in the present application responds that the target display area is the upper display area in the auxiliary display area, and the enable signal STV1 is changed from Figure 3 The low potential shown is switched to a high potential; next, the signal STV1 is turned high to turn on the signal clk1 and the signal clk2, that is, the signal clk1 and the signal clk2 are connected to Figure 3 The corresponding signal waveform is shown.

[0057] In the specific example, refer to Figures 2 to 3 , the display of the upper display area is sequentially turned on by signal STV1, signal clk1 and signal clk2 are repeated for 2clk cycles. Generally, the number of pixel rows set in the upper display area is about 60, that is, the number of cycles of 2clk repeated cycles is 60 / 2=30 times. In other words, the upper drive timing is 2clk repeated cycle drive, that is, signal clk1 and signal clk2 work in sequence, and each cycle drives 2 rows of pixel rows; for example, for the 60 rows of pixel rows in the upper display area, signal clk1 drives the first pixel row in each cycle (that is, the pixel row electrically connected to the signal gn end), and signal clk2 drives the second pixel row in each cycle (that is, the pixel row electrically connected to the signal gn+1 end).

[0058] Further, in some other feasible embodiments, the lower display driving component 22 includes a thirteenth thin film transistor T13, a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, a sixteenth thin film transistor T16, a seventh capacitor C7 and an eighth capacitor C8; the gate terminal of the thirteenth thin film transistor T13 and the first channel terminal of the thirteenth thin film transistor T13 are both electrically connected to the previous stage lower gate terminal of the current lower gate terminal, the second channel terminal of the thirteenth thin film transistor T13 is respectively electrically connected to the first end of the seventh capacitor C7 and the gate terminal of the fourteenth thin film transistor T14, and the first channel terminal of the fourteenth thin film transistor T14 is electrically connected to the current stage lower gate terminal. the gate terminal of the fifteenth thin film transistor T15, the first channel terminal of the fifteenth thin film transistor T15, the second end of the seventh capacitor C7, and the second channel terminal of the fourteenth thin film transistor T14 are all electrically connected to the current lower gate terminal, the second channel terminal of the fifteenth thin film transistor T15 is respectively electrically connected to the eighth capacitor C8 and the gate terminal of the sixteenth thin film transistor T16, the first channel terminal of the sixteenth thin film transistor T16 is electrically connected to the next level lower clock terminal of the current level lower clock signal terminal, and the second channel terminal of the sixteenth thin film transistor T16 is electrically connected to the next level lower gate terminal of the current lower gate terminal.

[0059] In this embodiment, when the target display area is the lower display area in the auxiliary display area, the driving chip provides a signal STV3 to the current stage lower clock signal terminal in the lower display area and to the next stage lower clock terminal of the current stage lower clock signal terminal.

[0060] It should be noted that the clock signal connected to the clock signal terminal of the current stage can be used Figure 2 The signal clk7 shown in the figure represents that the next level clock terminal of the current level clock signal terminal can be used Figure 2The signal clk8 shown in the figure represents that the gate drive signal connected to the previous lower gate terminal of the current lower gate terminal can be used Figure 2 The signal Mn-1 shown is representative; the current lower gate terminal can be used Figure 2 The signal Mn shown in the figure represents the gate drive signal connected to the lower gate terminal of the next stage of the current lower gate terminal. Figure 2 The signal Mn+1 shown represents.

[0061] For example, refer to Figures 2 to 3 The driver chip provided in the present application responds that the target display area is the lower display area in the auxiliary display area, and the enable signal STV3 is Figure 3 The low potential shown is switched to a high potential; next, the signal STV3 is turned high to turn on the signal clk7 and the signal clk8, that is, the signal clk1 and the signal clk2 are connected to Figure 3 The corresponding signal waveform is shown.

[0062] In the specific example, refer to Figures 2 to 3 , the display of the lower display area is sequentially turned on by signal STV3, and signal clk7 and signal clk8 are repeatedly cycled for 2clk. Generally, the number of pixel rows set in the lower display area is about 60, that is, the number of cycles of 2clk repeated cycles is 60 / 2=30 times. In other words, the lower drive timing is 2clk repeated cycle drive, that is, signal clk7 and signal clk8 work in a cycle in turn, and each cycle drives 2 rows of pixel rows; for example, for the 60 rows of pixel rows in the lower display area, signal clk7 drives the first pixel row in each cycle (that is, the pixel row electrically connected to the signal Mn terminal), and signal clk8 drives the second pixel row in each cycle (that is, the pixel row electrically connected to the signal Mn+1 terminal).

[0063] In yet another embodiment, referring to Figure 4 , Figure 4 Schematic diagram of the upper display area involved in the embodiment of the present application. When the target display area is the upper display area, the signal STV1 switches from a low potential to a high potential to turn on the signal clk1 and the signal clk2 in turn, and Figure 4 The driving timing corresponding to the signal clk1 and the signal clk2 shown in the figure is repeated for 2clk to ensure the normal display of the upper display area; and the signal STV2 and the signal STV3 are both maintained at a low potential, so that the main display area and the lower display area are not displayed.

[0064] In another embodiment, referring to Figure 5 , Figure 5 Schematic diagram of the main display area involved in the embodiment of the present application. When the target display area is the main display area, the signal STV2 switches from a low potential to a high potential to turn on the signals clk3, clk4, clk5 and clk6 in sequence, and Figure 5 The driving timing corresponding to the signal clk3 to the signal clk4 shown in the figure is repeated for 4clk to ensure the normal display of the main display area; and the signal STV1 and the signal STV3 are both maintained at a low potential, so that the upper display area and the lower display area are not displayed.

[0065] In yet another embodiment, referring to Figure 6 , Figure 6 Schematic diagram of the lower display area involved in the embodiment of the present application. When the target display area is the lower display area, the signal STV3 is switched from low potential to high potential to turn on the signal clk7 and the signal clk8 in turn, and Figure 6 The driving timing corresponding to the signal clk7 to the signal clk8 shown in the figure is repeated for 2clk cycles to ensure the normal display of the lower display area; and the signal STV1 and the signal STV2 are both maintained at a low potential, so that the upper display area and the main display area are not displayed. In addition, when the user's partition display requirement is a typing display requirement, that is, there is no need to require picture quality, the frequency of the driving timing corresponding to the signal clk7 to the signal clk8 can be reduced, that is, the time for the signal clk7 and the signal clk8 to maintain a high level becomes longer, thereby reducing the refresh rate of the lower display area, so as to effectively reduce the display power consumption of the lower display area.

[0066] In summary, the partition display circuit provided in the present application realizes the partition display of the display panel to reduce the display power consumption. The partition display circuit includes a display driver module, a main display area and a sub-display area, wherein the display driver module integrates a main display driver 10 and a sub-display driver 20; the main display driver 10 is electrically connected to a plurality of pixel rows in the main display area, and the sub-display driver 20 is electrically connected to a plurality of pixel rows in the sub-display area, thereby realizing the partition independent driving of the main display area and the sub-display area. Specifically, the display driver module can accurately obtain the target display area according to the user's partition display requirements; next, the main display driver 10 or the auxiliary display driver 20 is selectively enabled according to the target display area, that is, when the target display area is the main display area, the main display driver 10 is enabled to power multiple pixel rows in the main display area according to a preset main drive timing; when the target display area is the auxiliary display area, the auxiliary display driver 20 is enabled to power multiple pixel rows in the auxiliary display area according to a preset auxiliary drive timing, thereby realizing power supply for the pixel rows in the display area specified by the partition display requirements, thereby effectively avoiding unnecessary power consumption waste of the traditional display panel under the overall backlight control, and significantly reducing the display power consumption of the display panel.

[0067] Furthermore, based on the first embodiment of the partition display circuit of the present application, a second embodiment of the driving method of the present application is proposed.

[0068] The driving method of the present application is applied to any of the above-mentioned partition display circuits. The driving method of the present application is executed by a terminal device that drives and controls the partition display circuit. The driving method of the present application includes the following implementation steps S10 to S20.

[0069] Step S10: obtaining the partition display requirement of the user through the display driving module, and determining the target display area according to the partition display requirement.

[0070] In this embodiment, after the display driving module receives the user's partition display demand based on the preset human-computer interaction interface, the partition display scene corresponding to the partition display demand is obtained. When the partition display scene is the main display area usage scene, the target display area is determined to be the main display area; when the partition display scene is the secondary display area usage scene, the target display area is determined to be the secondary display area.

[0071] Step S20: Based on the target display area being the main display area, the main display driver in the display driver module is enabled to power multiple pixel rows in the main display area according to a preset main drive timing; or, based on the target display area being the secondary display area, the secondary display driver in the display driver module is enabled to power multiple pixel rows in the secondary display area according to a preset secondary drive timing.

[0072] In this embodiment, according to the response of the driver chip in the display driver module that the target display area is the main display area, the display driving state of the main display driver is switched from the cut-off state to the driving state, and a stable and reliable power supply is provided for multiple pixel rows in the main display area according to the preset main driving timing for normal display; at the same time, the driver chip also responds to the target display area being the main display area, enabling the auxiliary display driver to maintain the cut-off state, thereby avoiding the auxiliary display area from consuming extra power when displaying non-essentially. Alternatively, according to the response of the driver chip in the display driver module that the target display area is the auxiliary display area, the display driving state of the auxiliary display driver is switched from the cut-off state to the driving state, and a stable and reliable power supply is provided for multiple pixel rows in the auxiliary display area according to the preset auxiliary driving timing for normal display; at the same time, the driver chip also responds to the target display area being the auxiliary display area, enabling the main display driver to maintain the cut-off state, thereby avoiding the main display area from consuming extra power when displaying non-essentially.

[0073] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the partition display circuit described in any one of the above items.

[0074] In addition, the present application also provides a display device. Figure 7, Figure 7 The structure diagram of the display device involved in the embodiment of the present application is shown in FIG. The display device in the embodiment of the present application may be a device for locally running the driving method.

[0075] like Figure 7 As shown, the display device of the embodiment of the present application may include: the above-mentioned partition display circuit; or, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0076] The memory 1005 is arranged on the display device body, and a program is stored in the memory 1005, and the program implements the corresponding operation when it is executed by the processor 1001. The memory 1005 is also used to store parameters for use by the display device. The memory 1005 can be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0077] Those skilled in the art will understand that Figure 7 The display device structure shown in the figure does not constitute a limitation on the display device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0078] like Figure 7 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a driver of a display device.

[0079] exist Figure 7 In the display device shown, the processor 1001 can be used to call a driver program of the display device stored in the memory 1005 and execute the steps of the driving method as described above.

[0080] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0081] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0082] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium such as ROM / RAM, a magnetic disk, or an optical disk as described above, and includes a number of instructions for enabling a display device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0083] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A partition display circuit, characterized in that: The partition display circuit comprises a display driving module, a main display area and a sub-display area, the display driving module comprises a main display driving component and a sub-display driving component, the main display driving component is electrically connected to a plurality of pixel rows in the main display area, and the sub-display driving component is electrically connected to a plurality of pixel rows in the sub-display area; The display driver module is configured to obtain the user's partition display requirements, and determine the target display area based on the partition display requirements, and enable the main display driver to power multiple pixel rows in the main display area according to a preset main drive timing for the main display area according to the target display area; or, enable the secondary display driver to power multiple pixel rows in the secondary display area according to a preset secondary drive timing for the secondary display area according to the target display area.

2. The partition display circuit according to claim 1, characterized in that: The main display driver comprises a first main driving module, and the first main driving module comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor and a second capacitor; The gate terminal of the first thin film transistor and the first channel terminal of the first thin film transistor are both electrically connected to the main gate terminals of the first two stages of the current main gate terminal, the second channel terminal of the first thin film transistor is electrically connected to the first end of the first capacitor and the gate terminal of the second thin film transistor respectively, and the first channel terminal of the second thin film transistor is electrically connected to the main clock signal terminal of the current stage; The gate terminal of the third thin film transistor, the first channel terminal of the third thin film transistor, the second terminal of the first capacitor, and the second channel terminal of the second thin film transistor are all electrically connected to the current main gate terminal, the second channel terminal of the third thin film transistor is electrically connected to the second capacitor and the gate terminal of the fourth thin film transistor, respectively, the first channel terminal of the fourth thin film transistor is electrically connected to the latter two main clock terminals of the current main clock signal terminal, and the second channel terminal of the fourth thin film transistor is electrically connected to the latter two main gate terminals of the current main gate terminal.

3. The partition display circuit according to claim 2, characterized in that: The main display driver also includes a second main driving module, and the second main driving module includes a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a third capacitor and a fourth capacitor; The gate terminal of the fifth thin film transistor and the first channel terminal of the fifth thin film transistor are both electrically connected to the main gate terminal of the previous stage of the current main gate terminal, the second channel terminal of the fifth thin film transistor is electrically connected to the first end of the third capacitor and the gate terminal of the sixth thin film transistor respectively, and the first channel terminal of the sixth thin film transistor is electrically connected to the main clock signal terminal of the next stage of the current main clock signal terminal; The gate terminal of the seventh thin film transistor, the first channel terminal of the seventh thin film transistor, the second end of the third capacitor, and the second channel terminal of the sixth thin film transistor are all electrically connected to the main gate terminal of the next level of the current main gate terminal, the second channel terminal of the seventh thin film transistor is electrically connected to the fourth capacitor and the gate terminal of the eighth thin film transistor respectively, the first channel terminal of the eighth thin film transistor is electrically connected to the next three main clock terminals of the current main clock signal terminal, and the second channel terminal of the eighth thin film transistor is electrically connected to the next three main gate terminals of the current main gate terminal.

4. The partition display circuit according to claim 1, characterized in that: The auxiliary display area includes an upper display area and a lower display area, and the upper display area and the lower display area are respectively arranged on both sides of the main display area; wherein, The number of pixel rows in the upper display area is the same as the number of pixel rows in the lower display area, and the total number of pixel rows between the number of pixel rows in the upper display area and the number of pixel rows in the lower display area is less than the number of pixel rows in the main display area.

5. The partition display circuit according to claim 4, characterized in that: The auxiliary display driver comprises an upper display driver corresponding to the upper display area, and a lower display driver corresponding to the lower display area; The upper display driver is electrically connected to a plurality of pixel rows in the upper display area, and the lower display driver is electrically connected to a plurality of pixel rows in the lower display area.

6. The partition display circuit according to claim 5, characterized in that: The upper display driving element includes a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a fifth capacitor and a sixth capacitor; The gate terminal of the ninth thin film transistor and the first channel terminal of the ninth thin film transistor are both electrically connected to the upper gate terminal of the previous stage of the current upper gate terminal, the second channel terminal of the ninth thin film transistor is electrically connected to the first end of the fifth capacitor and the gate terminal of the tenth thin film transistor respectively, and the first channel terminal of the tenth thin film transistor is electrically connected to the upper clock signal terminal of the current stage; The gate terminal of the eleventh thin film transistor, the first channel terminal of the eleventh thin film transistor, the second terminal of the fifth capacitor, and the second channel terminal of the tenth thin film transistor are all electrically connected to the current upper gate terminal, the second channel terminal of the eleventh thin film transistor is electrically connected to the sixth capacitor and the gate terminal of the twelfth thin film transistor, respectively, the first channel terminal of the twelfth thin film transistor is electrically connected to the clock terminal of the next level of the clock signal terminal of the current level, and the second channel terminal of the twelfth thin film transistor is electrically connected to the upper gate terminal of the next level of the current upper gate terminal.

7. The partition display circuit according to claim 5, characterized in that: The lower display driving element includes a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventh capacitor and an eighth capacitor; The gate terminal of the thirteenth thin film transistor and the first channel terminal of the thirteenth thin film transistor are both electrically connected to the lower gate terminal of the previous stage of the current lower gate terminal, the second channel terminal of the thirteenth thin film transistor is electrically connected to the first end of the seventh capacitor and the gate terminal of the fourteenth thin film transistor respectively, and the first channel terminal of the fourteenth thin film transistor is electrically connected to the lower clock signal terminal of the current stage; The gate terminal of the fifteenth thin film transistor, the first channel terminal of the fifteenth thin film transistor, the second terminal of the seventh capacitor, and the second channel terminal of the fourteenth thin film transistor are all electrically connected to the current lower gate terminal, the second channel terminal of the fifteenth thin film transistor is electrically connected to the eighth capacitor and the gate terminal of the sixteenth thin film transistor, respectively, the first channel terminal of the sixteenth thin film transistor is electrically connected to the next level lower clock terminal of the current level lower clock signal terminal, and the second channel terminal of the sixteenth thin film transistor is electrically connected to the next level lower gate terminal of the current lower gate terminal.

8. A driving method for a partition display circuit, characterized in that: The driving method of the partition display circuit is applied to the partition display circuit, and the driving method includes: Obtaining the user's partition display requirements through the display driver module, and determining the target display area according to the partition display requirements; According to the target display area being the main display area, the main display driver in the display driver module is enabled to power multiple pixel rows in the main display area according to a preset main drive timing; or, according to the target display area being the secondary display area, the secondary display driver in the display driver module is enabled to power multiple pixel rows in the secondary display area according to a preset secondary drive timing.

9. A display panel, characterized in that: The display panel includes a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the partition display circuit according to any one of claims 1 to 7.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9; or, The display device comprises a processor, a memory, and a driver program stored in the memory and executable by the processor, wherein the driver program, when executed by the processor, implements the steps of the driving method according to claim 8.

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