Defence hammer circuit based on rram double layer counting

Abstract

The application discloses a defense row hammer circuit based on RRAM double-layer counting, which comprises a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS tube. The group counter circuit and the four row counter circuits are realized based on RRAM devices. The decoder circuit is used for converting a 2-bit binary address signal into a 4-bit binary decoding signal and outputting the 4-bit binary decoding signal to the four row counter circuits in one-to-one correspondence. The group counter circuit is used for counting a high level of an external enable signal EN and generating a corresponding count signal R_EN according to a count value. The first PMOS tube is used for controlling the count signal R_EN to be output to the four row counter circuits. Each row counter is used for counting a high level of the decoding signal output to the row counter by the decoder circuit and outputting a warning signal with a low level when a count value does not reach an upper limit of counting, and outputting a warning signal with a high level when the count value reaches the upper limit of counting. The application has the advantages of small hardware overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to a defense hammering circuit, in particular to a defense hammering circuit based on RRAM double-layer counting. BACKGROUND

[0002] With the development of manufacturing technology, the storage density of dynamic random access memory is significantly improved. The interaction between circuit elements can cause the problem of coupling crosstalk. Researchers have found that dynamic random access memory is vulnerable to row hammer phenomenon: when a certain memory row (i.e. a bit output line in dynamic random access memory) in high-frequency activated dynamic random access memory is activated, it may induce bit flip in its physically adjacent memory row. Thus, attackers can use this phenomenon to perform attacks on dynamic random access memory on computer systems, i.e. row hammer attacks, to achieve privilege escalation and access data in any memory row of dynamic random access memory.

[0003] Currently, the defense hammering circuit based on row counter tracking strategy can effectively solve the problem of dynamic random access memory row hammer attack. The defense hammering circuit tracks the number of activations of each memory row in dynamic random access memory. Once the number of activations of a certain memory row reaches a preset threshold value that triggers a row hammer attack, the memory row is prevented from being activated continuously.

[0004] However, the existing defense hammering circuit requires a large number of counters to count a memory row, for example, when the threshold value that triggers a row hammer attack is 1000 times, a 10-bit static random access memory is required to count a memory row, which brings a large hardware overhead. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a defense hammering circuit based on RRAM double-layer counting with small hardware overhead.

[0006] The technical scheme adopted by the present application to solve the above technical problems is: a defense row hammer circuit based on RRAM double-layer counting, comprising a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS tube, the four row counter circuits are respectively referred to as a first row counter circuit, a second row counter circuit, a third row counter circuit and a fourth row counter circuit; the group counter circuit and the four row counter circuits are respectively realized based on RRAM devices; the decoder circuit is used to convert the 2-bit binary address signal output externally to it into a 4-bit binary decoding signal under the control of an external enable signal EN, and output it to the four row counter circuits one by one; the first PMOS tube is used to be turned on or turned off under the control of the signal input at its gate; when the signal input at the gate of the first PMOS tube is low, the first PMOS tube is turned on, and the group counter circuit is connected to the four row counter circuits through the first PMOS tube; the group counter circuit can output signals to the four row counter circuits; when the signal input at the gate of the first PMOS tube is high, the first PMOS tube is turned off, and the group counter circuit is disconnected from the four row counter circuits; the group counter circuit cannot output signals to the four row counter circuits, and cannot affect the working state of the four row counter circuits; the group counter circuit is used to count the high level of the external enable signal EN, and output the corresponding count signal R_EN to the drain of the first PMOS tube according to the count value; if the count value does not reach the upper limit of the group counter circuit, the count signal R_EN output by the group counter circuit is low; if the count value reaches the count upper limit of the group counter circuit, the count signal R_EN output by the group counter circuit is high at this time; the row counter circuit is used to count the high level of the signal output to it by the decoder circuit when the signal output to it by the decoder circuit is high, the count signal R_EN output by the group counter circuit is high, and the signal input at the gate of the first PMOS is low, and output a low-level warning signal Alert when the count value does not reach the count upper limit, and output a high-level warning signal Alert when the count value reaches the count upper limit.

[0007] The decoder circuit has three input terminals and four output terminals, and its three input terminals are respectively referred to as its first input terminal, second input terminal and third input terminal, and its four output terminals are respectively referred to as its first output terminal, second output terminal, third output terminal and fourth output terminal; the group counter circuit has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; each of the row counter circuits has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; the first input terminal of the decoder circuit is used to access the first bit A of the 2-bit binary address signal, and the second input terminal of the decoder circuit is used to access the second bit B of the 2-bit binary address signal; the first output terminal of the decoder circuit is used to output The first bit of the 4-bit binary decoded signal is outputted from the decoder circuit; the second output terminal of the decoder circuit is used to output the second bit of the 4-bit binary decoded signal; the third output terminal of the decoder circuit is used to output the third bit of the 4-bit binary decoded signal; the fourth output terminal of the decoder circuit is used to output the fourth bit of the 4-bit binary decoded signal; the third input terminal of the decoder circuit is connected to the first input terminal of the group counter circuit, and its connection terminal is the enable terminal of the defense hammer circuit, which is used to receive the external enable signal EN; the second input terminal of the group counter circuit is connected to the power supply VDD; the third input terminal of the group counter circuit is the first refresh terminal of the defense hammer circuit, which is used to receive the first refresh signal Ref1 that restarts the group counter circuit; the fourth input terminal of the group counter circuit is the first reference terminal of the defense hammer circuit, which is used to receive the first reference voltage V rfe1; the fifth input terminal of the group counter circuit is the first control terminal of the defense row hammer circuit, for inputting a first control signal SA1_CTL to control whether the output terminal of the group counter circuit outputs a signal; the first output terminal of the decoder circuit is connected with the first input terminal of the first row counter circuit, the second output terminal of the decoder circuit is connected with the first input terminal of the second row counter circuit, the third output terminal of the decoder circuit is connected with the first input terminal of the third row counter circuit, and the fourth output terminal of the decoder circuit is connected with the first input terminal of the fourth row counter circuit; the second input terminal of the first row counter circuit, the second input terminal of the second row counter circuit, the second input terminal of the third row counter circuit and the second input terminal of the fourth row counter circuit are connected, and the connection terminal thereof is the second control terminal of the defense row hammer circuit, for inputting a second control signal SA2_CTL to control whether the output terminal of the group counter circuit outputs a signal; the third input terminal of the first row counter circuit, the third input terminal of the second row counter circuit, the third input terminal of the third row counter circuit, the third input terminal of the fourth row counter circuit and the gate of the first PMOS transistor are connected, and the connection terminal thereof is the second refresh terminal of the defense row hammer circuit, for inputting a second refresh signal Ref2 to make the row counter circuit restart; the source of the first PMOS transistor is connected with the fourth input terminal of the first row counter circuit, the fourth input terminal of the second row counter circuit, the fourth input terminal of the third row counter circuit and the fourth input terminal of the fourth row counter circuit respectively, and the fifth input terminal of the first row counter circuit, the fifth input terminal of the second row counter circuit, the fifth input terminal of the third row counter circuit and the fifth input terminal of the fourth row counter circuit are connected, and the connection terminal thereof is the second reference terminal of the defense row hammer circuit, for inputting a second reference voltage V rfe2 .

[0008] The group counter circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second PMOS transistor, a first sensitive amplifier, a first memristor and a second memristor, the first sensitive amplifier has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal, the first memristor and the second memristor both have a top electrode and a bottom electrode, the initial resistance state of the first memristor is high resistance state, the initial resistance state of the second memristor is low resistance state, the drain of the first NMOS transistor and the drain of the fourth NMOS transistor are connected, and the connection end is the second input terminal of the group counter circuit, the gate of the first NMOS transistor, the gate of the fifth NMOS transistor and the enable terminal of the first sensitive amplifier are connected, and the connection end is the first input terminal of the group counter circuit, the source of the first NMOS transistor and the top electrode of the first memristor are connected, the bottom electrode of the first memristor, the source of the second PMOS transistor and the non-inverting input terminal of the first sensitive amplifier are connected, the inverting input terminal of the first sensitive amplifier is the fourth input terminal of the group counter circuit, the drain of the second PMOS transistor, the top electrode of the second memristor and the drain of the third NMOS transistor are connected, the gate of the third NMOS transistor, the gate of the second PMOS transistor and the gate of the fourth NMOS transistor are connected, and the connection end is the third input terminal of the group counter circuit, the source of the third NMOS transistor and the source of the fifth NMOS transistor are both grounded, the bottom electrode of the second memristor, the source of the fourth NMOS transistor and the drain of the fifth NMOS transistor are connected, the output terminal of the first sensitive amplifier and the drain of the second NMOS transistor are connected, the gate of the second NMOS transistor is the fifth input terminal of the group counter circuit, and the source of the second NMOS transistor is the output terminal of the group counter circuit.

[0009] Each of the row counter circuits includes a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a third PMOS tube, a fourth PMOS tube, a second sensitive amplifier, a third memristor and a fourth memristor. The second sensitive amplifier has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The third memristor and the fourth memristor both have a top electrode and a bottom electrode. The initial resistance state of the third memristor is a high resistance state, and the initial resistance state of the fourth memristor is a low resistance state. The top electrode of the third memristor, the gate of the eighth NMOS tube and the enable terminal of the second sensitive amplifier are connected, and the connection end thereof is the first input terminal of the row counter circuit. The source of the sixth NMOS tube is connected to the bottom electrode of the third memristor. The drain of the sixth NMOS tube, the source of the third PMOS tube and the non-inverting input terminal of the second sensitive amplifier are connected. The inverting input terminal of the second sensitive amplifier is the The fifth input terminal of the row counter circuit, the drain of the third PMOS tube, the top electrode of the fourth memristor and the drain of the eighth NMOS tube are connected, the gate of the ninth NMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube are connected, and their connection end is the third input terminal of the row counter circuit, the source of the eighth NMOS tube and the drain of the fourth PMOS tube are both grounded, the bottom electrode of the fourth memristor, the source of the fourth PMOS tube and the source of the ninth NMOS tube are connected, the drain of the ninth NMOS tube is connected to the power supply voltage, the output terminal of the second sensitive amplifier and the drain of the seventh NMOS tube are connected, the gate of the seventh NMOS tube is the second input terminal of the row counter circuit, the source of the seventh NMOS tube is the output terminal of the row counter circuit, and the gate of the sixth NMOS tube is the fourth input terminal of the row counter circuit.

[0010] The first sensitive amplifier includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube. The source of the fifth PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are all connected to the power supply voltage. The gate of the fifth PMOS tube, the gate of the eighth PMOS tube and the gate of the fourteenth NMOS tube are connected, and the connection end thereof is the enable end of the first sensitive amplifier. The drain of the fifth PMOS tube, the drain of the sixth PMOS tube, the drain of the tenth NMOS tube, the gate of the seventh PMOS tube and the gate of the eleventh NMOS tube are connected, and the connection end thereof is the enable end of the first sensitive amplifier. The output end of the sense amplifier, the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor, the drain of the eleventh NMOS transistor, the gate of the sixth PMOS transistor, and the gate of the tenth NMOS transistor are connected, the source of the tenth NMOS transistor and the drain of the twelfth NMOS transistor are connected, the gate of the twelfth NMOS transistor serves as the inverting input end of the first sense amplifier, the source of the eleventh NMOS transistor and the drain of the thirteenth NMOS transistor are connected, the gate of the thirteenth NMOS transistor serves as the non-inverting input end of the first sense amplifier, the source of the twelfth NMOS transistor, the source of the thirteenth NMOS transistor, and the drain of the fourteenth NMOS transistor are connected, and the source of the fourteenth NMOS transistor is grounded; the circuit structure of the second sense amplifier is the same as that of the first sense amplifier.

[0011] Compared with the prior art, the advantage of the present invention is that a row hammer defense circuit is formed by a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS transistor. The group counter circuit and the four row counter circuits are respectively implemented based on RRAM devices. Under the control of an enable signal EN, a 2-bit binary address signal externally output thereto is converted into a 4-bit binary decoding signal, which is output one-to-one to the four row counter circuits. The first PMOS transistor is used to be turned on or off under the control of a signal connected to its gate. When the signal connected to the gate of the first PMOS transistor is at a low level, the first PMOS transistor is turned on. The group counter circuit is connected to the four row counter circuits through the first PMOS transistor. The group counter circuit can output signals to the four row counter circuits. When the signal connected to the gate of the first PMOS transistor is at a high level, the first PMOS transistor is turned off, and the group counter circuit is disconnected from the four row counter circuits. The group counter circuit cannot output signals to the four row counter circuits, and the group counter circuit cannot affect the working state of the four row counter circuits. The group counter circuit is used to count the high level of the external enable signal EN and generate a corresponding counting signal R_EN based on the count value and output it to the first PMOS transistor. The drain of the S tube, if the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is low level; if the count value reaches the counting upper limit of the group counter circuit, the counting signal R_EN output by the group counter circuit is high level; the row counter circuit is used to count the high level output by the decoder circuit when the signal output to it by the decoder circuit is high level, the counting signal R_EN output by the group counter circuit is high level and the signal connected to the gate of the first PMOS is low level, and outputs a low level when the count value does not reach its counting upper limit When the count value reaches its upper count limit, the warning signal Alert of the high level is output. Therefore, the present invention only needs to use a one-bit group counter circuit and a four-bit row counter circuit to accurately complete the counting operation of the four-bit output lines in the dynamic random access memory and output the row hammer attack warning signal to achieve defense against the row hammer attack. Compared with the traditional defense row hammer circuit that needs to rely on multi-bit static random access memory and complex peripheral circuits to count the one-bit output line in the dynamic random access memory, the hardware overhead is significantly reduced, and the hardware overhead is relatively small. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 4 is a block diagram of a defensive hammer circuit based on RRAM double-layer counting according to the present invention.

[0013] Figure 2 FIG. 4 is a circuit diagram of a group counter circuit of a defense hammer circuit based on RRAM dual-layer counting according to the present invention.

[0014] Figure 3FIG. 4 is a circuit diagram of a row counter circuit of a row hammer defense circuit based on RRAM dual-layer counting according to the present invention.

[0015] Figure 4 A circuit diagram of a first sense amplifier of a hammer defense circuit based on RRAM dual-layer counting according to the present invention;

[0016] Figure 5 This is a test diagram of the counting and reset functions of the group counter circuit of the RRAM double-layer counting defense hammer circuit of the present invention;

[0017] Figure 6 This is a test diagram of the counting and reset functions of the row counter circuit of the row hammer defense circuit based on RRAM double-layer counting of the present invention. DETAILED DESCRIPTION

[0018] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0019] Example 1: Figure 1As shown, a defense row hammer circuit based on RRAM double-layer counting includes a decoder circuit, a group counter circuit, four row counter circuits, and a first PMOS tube P1. The four row counter circuits are respectively referred to as a first row counter circuit, a second row counter circuit, a third row counter circuit, and a fourth row counter circuit. The group counter circuit and the four row counter circuits are respectively implemented based on RRAM devices. The decoder circuit is used to convert a 2-bit binary address signal output externally to the decoder circuit into a 4-bit binary decoding signal under the control of an external enable signal EN, and output the 4-bit binary decoding signal to the four row counter circuits one by one. The first PMOS tube is used to be turned on or turned off under the control of a signal input to the gate of the first PMOS tube. When the signal input to the gate of the first PMOS tube is at a low level, the first PMOS tube is turned on, the group counter circuit is connected to the four row counter circuits through the first PMOS tube P1, and the group counter circuit can output a signal to the four row counter circuits. When the signal input to the gate of the first PMOS tube is at a high level, the first PMOS tube is turned off, the group counter circuit is disconnected from the four row counter circuits, the group counter circuit cannot output a signal to the four row counter circuits, and the group counter circuit cannot affect the working state of the four row counter circuits. The group counter circuit is used to count the high level of the external enable signal EN, and output a corresponding count signal R_EN to the drain of the first PMOS tube P1. If the count value does not reach the upper limit of the group counter counting circuit, the count signal R_EN output by the group counter circuit is at a low level. If the count value reaches the count upper limit of the group counter circuit, the count signal R_EN output by the group counter circuit is at a high level. The row counter circuit is used to count the high level of the signal output by the decoder circuit to the row counter circuit, the count signal R_EN output by the group counter circuit, and the signal input to the gate of the first PMOS tube when the signal is at a low level. When the count value does not reach the count upper limit, the row counter circuit outputs a warning signal Alert at a low level. When the count value reaches the count upper limit, the row counter circuit outputs a warning signal Alert at a high level.

[0020] In this embodiment, the working principle of the defense row hammer circuit based on RRAM double-layer counting is as follows:

[0021] When the count signal R_EN output by the group counter circuit is at a low level, and the signal input to the gate of the first PMOS tube P1 is at a low level, the first PMOS tube P1 is turned on. Although the group counter circuit outputs the count signal R_EN to the four row counter circuits, the four row counter circuits are not working.

[0022] When the external enable signal EN is at a low level, the decoder circuit, the group counter circuit, and the four row counter circuits are not working.

[0023] When the external enable signal EN is high, the signal connected to the gate of the first PMOS is low, and the 2-bit binary address signal connected to the decoder circuit is 00, the first PMOS transistor P1 is turned on, and the decoder circuit outputs a 4-bit binary decoding signal of 0001. At this time, the high level 1 in the 4-bit binary decoding signal is output to the first row counter circuit, and the three low levels 0 in the 4-bit binary decoding signal are output to the second row counter circuit, the third row counter circuit and the fourth row counter circuit respectively. The second row counter circuit, the third row counter circuit and the fourth row counter circuit are all not working, and the first row counter circuit enters the standby state. The group counter circuit counts the high level of the external enable signal EN and generates a corresponding counting signal R_EN according to the count value and outputs it to the drain of the first PMOS transistor P1. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is low. At this time, the first row counter circuit remains in the standby state. When the count value reaches the counting upper limit of the group counter circuit, the group counter circuit The counting signal R_EN output by the counter circuit is high, and the first row counter circuit starts to operate. The first row counter circuit counts the high level output by the decoder circuit. When the count value of the first row counter circuit does not reach the counting upper limit of the first row counter circuit, the first row counter circuit outputs a low level warning signal Alert. When the count value reaches the counting upper limit of the first row counter circuit, the first row counter circuit outputs a high level warning signal Alert. When the first row counter circuit outputs the high level warning signal Alert, the signal connected to the gate of the first PMOS becomes high, the first PMOS is turned off, and the counting signal R_EN output by the group counter circuit cannot be transmitted to the four row counter circuits. The second row counter circuit, the third row counter circuit, and the fourth row counter circuit remain inoperative. At this time, the first row counter circuit performs a reset operation. Afterwards, the external enable signal EN is high, the group counter circuit performs a reset operation, and the defensive row hammer circuit based on the RRAM dual-layer counting completes this operation.

[0024] When the external enable signal EN is high, the signal connected to the gate of the first PMOS is low, and the 2-bit binary address signal connected to the decoder circuit is 01, the first PMOS transistor P1 is turned on, and the decoder circuit outputs a 4-bit binary decoding signal of 0010. At this time, the high level 1 in the 4-bit binary decoding signal is output to the second row counter circuit, and the three low levels 0 in the 4-bit binary decoding signal are output to the first row counter circuit, the second row counter circuit and the third row counter circuit respectively. The first row counter circuit, the third row counter circuit and the fourth row counter circuit are all not working, and the second row counter circuit enters the standby state. The group counter circuit counts the high level of the external enable signal EN and generates a corresponding counting signal R_EN according to the count value and outputs it to the drain of the first PMOS transistor P1. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is low. At this time, the first row counter circuit remains in the standby state. When the count value reaches the counting upper limit of the group counter circuit, The count signal R_EN output by the group counter circuit is high, and the second row counter circuit starts operating. The second row counter circuit counts the high levels output by the decoder circuit. When the count value of the second row counter circuit does not reach the upper limit of the second row counter circuit, the second row counter circuit outputs a low-level warning signal Alert. When the count value reaches the upper limit of the second row counter circuit, the second row counter circuit outputs a high-level warning signal Alert. When the second row counter circuit outputs the high-level warning signal Alert, the signal connected to the gate of the first PMOS becomes high, the first PMOS is turned off, and the count signal R_EN output by the group counter circuit cannot be transmitted to the four row counter circuits. The second, third, and fourth row counter circuits remain inoperative, and the second row counter circuit performs a reset operation. Afterwards, the external enable signal EN is high, the group counter circuit performs a reset operation, and the defensive row hammer circuit based on the RRAM dual-layer counting completes this operation.

[0025] When the external enable signal EN is high, the signal connected to the gate of the first PMOS is low, and the 2-bit binary address signal connected to the decoder circuit is 10, the first PMOS transistor P1 is turned on, and the decoder circuit outputs a 4-bit binary decoding signal of 0100. At this time, the high level 1 in the 4-bit binary decoding signal is output to the third row counter circuit, and the three low levels 0 in the 4-bit binary decoding signal are output to the first row counter circuit, the second row counter circuit and the fourth row counter circuit respectively. The first row counter circuit, the second row counter circuit and the fourth row counter circuit are all not working, and the third row counter circuit enters the standby state. The group counter circuit counts the high level of the external enable signal EN and generates a corresponding counting signal R_EN according to the count value and outputs it to the drain of the first PMOS transistor P1. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is low. At this time, the third row counter circuit remains in the standby state. When the count value reaches the counting upper limit of the group counter circuit, the group counter circuit is turned off. The count signal R_EN output by the counter circuit is high, and the third row counter circuit starts operating. The third row counter circuit counts the high levels output by the decoder circuit. When the count value of the third row counter circuit does not reach the upper limit of the third row counter circuit, the third row counter circuit outputs a low-level warning signal Alert. When the count value reaches the upper limit of the third row counter circuit, the third row counter circuit outputs a high-level warning signal Alert. When the third row counter circuit outputs the high-level warning signal Alert, the signal connected to the gate of the first PMOS becomes high, and the first PMOS is turned off. The count signal R_EN output by the group counter circuit cannot be transmitted to the four row counter circuits. The first, second, and fourth row counter circuits remain inoperative, and the third row counter circuit performs a reset operation. Afterwards, the external enable signal EN is high, the group counter circuit performs a reset operation, and the RRAM dual-layer counting defense row hammer circuit completes this operation.

[0026] When the external enable signal EN is high, the signal connected to the gate of the first PMOS is low, and the 2-bit binary address signal connected to the decoder circuit is 11, the first PMOS transistor P1 is turned on, and the decoder circuit outputs a 4-bit binary decoding signal of 1000. At this time, the high level 1 in the 4-bit binary decoding signal is output to the fourth row counter circuit, and the three low levels 0 in the 4-bit binary decoding signal are output to the first row counter circuit, the second row counter circuit and the third row counter circuit respectively. The first row counter circuit, the second row counter circuit and the third row counter circuit do not work, and the fourth row counter circuit enters a standby state. The group counter circuit counts the high level of the external enable signal EN and generates a corresponding counting signal R_EN according to the count value and outputs it to the drain of the first PMOS transistor P1. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is low. At this time, the fourth row counter circuit remains in a standby state. When the count value reaches the upper limit of the group counter circuit, the group counter circuit When the count signal R_EN output by the decoder circuit is high, the fourth row counter circuit starts operating and counts the high-level signals output by the decoder circuit. When the count value of the fourth row counter circuit does not reach the upper limit of the fourth row counter circuit, the fourth row counter circuit outputs a low-level warning signal Alert. When the count value reaches the upper limit of the fourth row counter circuit, the fourth row counter circuit outputs a high-level warning signal Alert. When the fourth row counter circuit outputs the high-level warning signal Alert, the signal connected to the gate of the first PMOS becomes high, the first PMOS is turned off, and the count signal R_EN output by the group counter circuit cannot be transmitted to the four row counter circuits. The first, second, and third row counter circuits remain inoperative, and the fourth row counter circuit performs a reset operation. Afterwards, the external enable signal EN is high, the group counter circuit performs a reset operation, and the RRAM dual-layer counting defense row hammer circuit completes this operation.

[0027] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, the decoder circuit has three input terminals and four output terminals, and its three input terminals are respectively referred to as its first input terminal, second input terminal, and third input terminal, and its four output terminals are respectively referred to as its first output terminal, second output terminal, third output terminal, and fourth output terminal; the group counter circuit has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal, and fifth input terminal; each row counter circuit has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal, and fifth input terminal; the first input terminal of the decoder circuit is used to receive the first bit A of the 2-bit binary address signal, and the second input terminal of the decoder circuit is used to receive the 2-bit binary The second bit B of the address signal; the first output end of the decoder circuit is used to output the first bit of the 4-bit binary decoded signal, the second output end of the decoder circuit is used to output the second bit of the 4-bit binary decoded signal, the third output end of the decoder circuit is used to output the third bit of the 4-bit binary decoded signal, and the fourth output end of the decoder circuit is used to output the fourth bit of the 4-bit binary decoded signal. The third input end of the decoder circuit is connected to the first input end of the group counter circuit, and its connection end is the enable end of the defense hammer circuit, which is used to receive the external enable signal EN; the second input end of the group counter circuit is connected to the power supply VDD; the third input end of the group counter circuit is the first refresh end of the defense hammer circuit, which is used to receive the first refresh signal Ref1 that restarts the group counter circuit; the fourth input end of the group counter circuit is the first reference end of the defense hammer circuit, which is used to receive the first reference voltage V rfe1; The fifth input end of the group counter circuit is the first control end of the defense row hammer circuit, which is used to access the first control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal; the first output end of the decoder circuit is connected to the first input end of the first row counter circuit, the second output end of the decoder circuit is connected to the first input end of the second row counter circuit, the third output end of the decoder circuit is connected to the first input end of the third row counter circuit, the fourth output end of the decoder circuit is connected to the first input end of the fourth row counter circuit, the second input end of the first row counter circuit, the second input end of the second row counter circuit, the second input end of the third row counter circuit and the second input end of the fourth row counter circuit are connected, and the connection end is the second control end of the defense row hammer circuit, which is used to access the second control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal. 2_CTL; the third input terminal of the first row counter circuit, the third input terminal of the second row counter circuit, the third input terminal of the third row counter circuit, the third input terminal of the fourth row counter circuit and the gate of the first PMOS transistor P1 are connected, and the connection terminal thereof is the second refresh terminal of the defense row hammer circuit, which is used to receive the second refresh signal Ref2 for re-enabling the row counter circuit; the source of the first PMOS transistor P1 is respectively connected to the fourth input terminal of the first row counter circuit, the fourth input terminal of the second row counter circuit, the fourth input terminal of the third row counter circuit and the fourth input terminal of the fourth row counter circuit, and the fifth input terminal of the first row counter circuit, the fifth input terminal of the second row counter circuit, the fifth input terminal of the third row counter circuit and the fifth input terminal of the fourth row counter circuit, and the connection terminal thereof is the second reference terminal of the defense row hammer circuit, which is received the second reference voltage V rfe2 .

[0028] The working principle of the RRAM double-layer counting defense hammer circuit of this embodiment is as follows:

[0029] In the initial state, the count values ​​of the group counter circuit and the row counter circuit are both 0. When the external enable signal EN connected to the enable terminal of the defense row hammer circuit based on RRAM dual-layer counting is low, the decoder circuit, the group counter circuit and the four row counter circuits do not work; when the external enable signal EN connected to the enable terminal of the defense row hammer circuit based on RRAM dual-layer counting, the first control signal SA1_CTL connected to the first control terminal and the second control signal SA2_CTL connected to the second control terminal are all high, the first refresh signal Ref1 connected to the first refresh terminal and the second refresh signal Ref2 connected to the second refresh terminal are both low. When the first PMOS transistor P1 is turned on, the group counter circuit is enabled and counts the high level of the external enable signal EN. Based on the count value, a corresponding count signal R_EN is generated and output to the drain of the first PMOS transistor P1. If the count value does not reach the upper limit of the group counter circuit, the count signal R_EN output by the group counter circuit is low. If the count value reaches the upper limit of the group counter circuit, the count signal R_EN output by the group counter circuit is high. Although the group counter circuit outputs the count signal R_EN to the four row counter circuits, the four row counter circuits do not operate regardless of the signal output by the decoder circuit. When the count value reaches the upper limit of the group counter circuit and the count signal R_EN output by the group counter circuit is high, the external enable signal EN, the first control signal SA1_CTL, and the second control signal SA2_CTL remain high, and the first refresh signal Ref1 and the second refresh signal Ref2 remain low.At this time, if the 2-bit binary address signal connected to the decoder circuit is 00, the decoder circuit outputs a 4-bit binary decoding signal of 0001, the signal output by the decoder circuit to the first row counter circuit is high, and the signals output to the second row counter circuit, the third row counter circuit and the fourth row counter circuit are all low, the second row counter circuit, the third row counter circuit and the fourth row counter circuit are all not working, and the first row counter circuit starts working; if the 2-bit binary address signal connected to the decoder circuit is 01, the decoder circuit outputs a 4-bit binary decoding signal of 0010, the signal output by the decoder circuit to the second row counter circuit is high, and the signals output to the first row counter circuit, the third row counter circuit and the fourth row counter circuit are all low, the first row counter circuit, the third row counter circuit and the fourth row counter circuit are all not working, and the second row counter circuit starts working operation; if the 2-bit binary address signal connected to the decoder circuit is 10, the decoder circuit outputs a 4-bit binary decoding signal of 0100, the signal output by the decoder circuit to the third row counter circuit is high, the signals output to the first row counter circuit, the second row counter circuit and the fourth row counter circuit are all low, the first row counter circuit, the second row counter circuit and the fourth row counter circuit all do not work, and the third row counter circuit starts to work; if the 2-bit binary address signal connected to the decoder circuit is 11, the decoder circuit outputs a 4-bit binary decoding signal of 1000, the signal output by the decoder circuit to the fourth row counter circuit is high, the signals output to the first row counter circuit, the second row counter circuit and the third row counter circuit are all low, the first row counter circuit, the second row counter circuit and the third row counter circuit all do not work, and the fourth row counter circuit starts to work. When a row counter circuit starts working, the row counter circuit counts the high level outputted to it by the decoder circuit. When the count value of the row counter circuit does not reach its upper limit, the output end of the row counter circuit outputs a low-level warning signal Alert. When the count value reaches its upper limit, the output end of the row counter circuit outputs a high-level warning signal Alert. When the output end of the row counter circuit outputs the high-level warning signal Alert, the second refresh signal Ref2 becomes high, turning off the first PMOS. At this time, the count signal R_EN outputted by the group counter circuit cannot be transmitted to the four row counter circuits. The other three row counter circuits except the row counter circuit remain inoperative, and the row counter circuit performs a reset operation. Afterwards, the first refresh signal Ref1 becomes high, the group counter circuit performs a reset operation, and the defensive row hammer circuit based on the RRAM double-layer counting completes this operation.

[0030] Example 3: This example is basically the same as Example 2, except that: in this example, Figure 2As shown, the group counter circuit comprises a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a second PMOS transistor P2, a first sensitive amplifier SA1, a first memristor R1 and a second memristor R2. The first sensitive amplifier SA1 has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The first and second memristors R1 and R2 each has a top electrode and a bottom electrode. The first memristor R1 has an initial high resistance state, and the second memristor R2 has an initial low resistance state. The drain of the first NMOS transistor N1 is connected to the drain of the fourth NMOS transistor N4, and the connection terminal is the second input terminal of the group counter circuit. The gate of the first NMOS transistor N1, the gate of the fifth NMOS transistor N5 and the enable terminal of the first sensitive amplifier SA1 are connected, and the connection terminal is the first input terminal of the group counter circuit. The source of the first NMOS transistor N1 is connected to the top electrode of the first memristor R1. The bottom electrode of the first memristor R1, the source of the second PMOS transistor P2 and the non-inverting input terminal of the first sensitive amplifier SA1 are connected. The inverting input terminal of the first sensitive amplifier SA1 is the fourth input terminal of the group counter circuit. The drain of the second PMOS transistor P2, the top electrode of the second memristor R2 and the drain of the third NMOS transistor N3 are connected. The gate of the third NMOS transistor N3, the gate of the second PMOS transistor P2 and the gate of the fourth NMOS transistor N4 are connected, and the connection terminal is the third input terminal of the group counter circuit. The source of the third NMOS transistor N3 and the source of the fifth NMOS transistor N5 are grounded. The bottom electrode of the second memristor R2, the source of the fourth NMOS transistor N4 and the drain of the fifth NMOS transistor N5 are connected. The output terminal of the first sensitive amplifier SA1 is connected to the drain of the second NMOS transistor N2. The gate of the second NMOS transistor N2 is the fifth input terminal of the group counter circuit. The source of the second NMOS transistor N2 is the output terminal of the group counter circuit.

[0031] The working principle of the group counter circuit is as follows. When the external enable signal EN and the first control signal SA1_CTL are both high, and the first refresh signal Ref1 is low, the group counter circuit starts counting operation. The first NMOS transistor N1, the second NMOS transistor N2, the second PMOS transistor P2 and the fifth NMOS transistor N5 are all turned on. The third NMOS transistor N3 and the fourth NMOS transistor N4 are both turned off. At this time, the voltage of the top electrode of the second memristor R2 is higher than that of the bottom electrode. The resistance of the second memristor R2 gradually rises. When the counting number of the group counter circuit reaches the upper limit, the resistance state of the second memristor R2 changes from the low resistance state to the high resistance state. The voltage of the bottom electrode of the first memristor R1 rises to be higher than the first reference voltage V rfe1At this time, the signal output by the output terminal of the first sense amplifier SA1 is high. This signal is transmitted through the drain of the second NMOS transistor N2 to its source. This means that the R_EN signal output by the output terminal of the group counter circuit is high. Subsequently, when the first refresh signal Ref1 becomes high, the group counter circuit begins a reset operation. The first NMOS transistor N1, the second NMOS transistor N2, the fifth NMOS transistor N5, and the second PMOS transistor P2 are all turned off, while the third NMOS transistor N3 and the fourth NMOS transistor N4 are both turned on. The voltage at the top electrode of the second memristor R2 is lower than the voltage at its bottom electrode, and the second memristor R2 transitions from a high-resistance state to a low-resistance state, completing the reset operation.

[0032] Example 4: This example is basically the same as Example 3, except that: in this example, Figure 3 As shown, each row counter circuit includes a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a third PMOS transistor P3, a fourth PMOS transistor P4, a second sensitive amplifier SA2, a third memristor R3 and a fourth memristor R4. The second sensitive amplifier SA2 has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The third memristor R3 and the fourth memristor R4 both have a top electrode and a bottom electrode. The initial resistance state of the third memristor R3 is a high resistance state, and the initial resistance state of the fourth memristor R4 is a low resistance state. The top electrode of the third memristor R3, the gate of the eighth NMOS transistor N8 and the enable terminal of the second sensitive amplifier SA2 are connected, and the connection terminal thereof is the first input terminal of the row counter circuit. The source of the sixth NMOS transistor N6 is connected to the bottom electrode of the third memristor R3. The drain of the sixth NMOS transistor N6, the source of the third PMOS transistor P3 and the non-inverting input terminal of the second sensitive amplifier SA2 are connected. The inverting input terminal of the second sense amplifier SA2 is the fifth input terminal of the row counter circuit. The drain of the third PMOS transistor P3, the top electrode of the fourth memristor R4, and the drain of the eighth NMOS transistor N8 are connected. The gate of the ninth NMOS transistor N9, the gate of the third PMOS transistor P3, and the gate of the fourth PMOS transistor P4 are connected, and their connection terminal is the third input terminal of the row counter circuit. The source of the eighth NMOS transistor N8 and the drain of the fourth PMOS transistor P4 are both grounded. The bottom electrode of the fourth memristor R4, the source of the fourth PMOS transistor P4, and the source of the ninth NMOS transistor N9 are connected. The drain of the ninth NMOS transistor N9 is connected to the power supply voltage. The output terminal of the second sense amplifier SA2 is connected to the drain of the seventh NMOS transistor N7. The gate of the seventh NMOS transistor N7 is the second input terminal of the row counter circuit. The source of the seventh NMOS transistor N7 is the output terminal of the row counter circuit. The gate of the sixth NMOS transistor N6 is the fourth input terminal of the row counter circuit.

[0033] The working principle of the row counter circuit of the embodiment is as follows: when the signal input into the first input end of the row counter circuit, the second control signal SA2_CTL input into the second input end, and the count signal RC_EN input into the fourth input end are all high level, and the second refresh signal Ref2 input into the third input end is low level, the row counter circuit starts the counting operation, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the third PMOS transistor P3 and the fourth PMOS transistor P4 are all turned on, the eighth NMOS transistor N8 and the ninth NMOS transistor N9 are all turned off, the voltage at the top electrode of the fourth memristor R4 is higher than the voltage at the bottom electrode of the fourth memristor R4, and the resistance of the fourth memristor R4 gradually rises. When the counting number of the row counter circuit reaches the upper limit, the resistance state of the fourth memristor R4 changes from the low resistance state to the high resistance state, at this time, the voltage at the non-inverting input end of the second sensitive amplifier SA2 rises to be higher than the second reference voltage V rfe2 , the signal output from the output end of the second sensitive amplifier SA2 is high level, the signal output from the output end of the second sensitive amplifier SA2 is transmitted to the source electrode of the seventh NMOS transistor N7 through the drain electrode of the seventh NMOS transistor N7, that is, the Alert signal output from the output end of the row counter circuit becomes high level. When the warning signal Alert output from the row counter circuit is high level, the second refresh signal Ref2 becomes high level, and the row counter circuit starts the reset operation, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the third PMOS transistor P3 and the fourth PMOS transistor P4 are all turned off, the eighth NMOS transistor N8 and the ninth NMOS transistor N9 are all turned on, the voltage at the top electrode of the fourth memristor R4 is lower than the voltage at the bottom electrode of the fourth memristor R4, the fourth memristor R4 changes from the high resistance state to the low resistance state, and the reset operation is completed.

[0034] Embodiment five: the embodiment five is basically the same as the embodiment four, the difference is that, in the embodiment five, as shown in FIG. 5, the first reference voltage V Figure 4As shown, the first sense amplifier SA1 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13 and a fourteenth NMOS transistor N14. The source of the fifth PMOS transistor P5, the source of the sixth PMOS transistor P6, the source of the seventh PMOS transistor P7 and the source of the eighth PMOS transistor P8 are all connected to the power supply voltage. The gate of the fifth PMOS transistor P5, the gate of the eighth PMOS transistor P8 and the gate of the fourteenth NMOS transistor N14 are connected, and the connection end thereof serves as the enable end of the first sense amplifier SA1. The drain of the fifth PMOS transistor P5, the drain of the sixth PMOS transistor P6, the drain of the tenth NMOS transistor N10, the gate of the seventh PMOS transistor P7 and the gate of the eleventh NMOS transistor N11 are connected. , and its connection end is the output end of the first sense amplifier SA1, the drain of the seventh PMOS transistor P7, the drain of the eighth PMOS transistor P8, the drain of the eleventh NMOS transistor N11, the gate of the sixth PMOS transistor P6 and the gate of the tenth NMOS transistor N10 are connected, the source of the tenth NMOS transistor N10 and the drain of the twelfth NMOS transistor N12 are connected, the gate of the twelfth NMOS transistor N12 is the inverting input end of the first sense amplifier SA1, the source of the eleventh NMOS transistor N11 and the drain of the thirteenth NMOS transistor N13 are connected, the gate of the thirteenth NMOS transistor N13 is the non-inverting input end of the first sense amplifier SA1, the source of the twelfth NMOS transistor N12, the source of the thirteenth NMOS transistor N13 and the drain of the fourteenth NMOS transistor are connected, and the source of the fourteenth NMOS transistor N14 is grounded; the circuit structure of the second sense amplifier SA2 is the same as that of the first sense amplifier SA1.

[0035] The working principle of the first sense amplifier SA1 of this embodiment is as follows: when the external enable signal EN is at a low level, the first sense amplifier SA1 starts a reset operation, the fifth PMOS transistor P5 and the eighth PMOS transistor P8 are all turned on, the drains of the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, and the eighth PMOS transistor P8 are charged to the power supply voltage VDD, the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are all turned off, the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 are both turned on, and the reset operation is completed. When the external enable signal EN is at a high level, the first sensitive amplifier SA1 starts to work, the fifth PMOS transistor P5 and the eighth PMOS transistor P8 are both turned off, and the fourteenth NMOS transistor N14 is turned on. When the gate voltage of the twelfth NMOS transistor N12 is higher than the gate voltage of the thirteenth NMOS transistor N13, the conduction degree of the twelfth NMOS transistor N12 is higher than the conduction degree of the thirteenth NMOS transistor N13, resulting in the discharge speed of the drain of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 being faster than the drain discharge speed of the seventh PMOS transistor P7 and the eighth PMOS transistor P8, and the drain voltage of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 will be lower than that of the seventh PMOS transistor P7 and the eighth PMOS transistor P8. 8, the drain voltage of the seventh PMOS transistor P7 is increased, so that the conduction degree of the seventh PMOS transistor P7 is higher than that of the sixth PMOS transistor P6, the conduction degree of the tenth NMOS transistor N10 is higher than that of the eleventh NMOS transistor N11, and the discharge speed of the drains of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 through the twelfth NMOS transistor N12 and the fourteenth NMOS transistor N14 is further accelerated, and the power supply voltage VDD is charged to the drains of the seventh PMOS transistor P7 and the eighth PMOS transistor P8 through the seventh PMOS transistor P7, until the drain voltage of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 drops to the ground GND, and the source voltage of the seventh PMOS transistor P7 and the eighth PMOS transistor P8 rises to be equal to the power supply voltage VDD.

[0036] To verify the performance of the RRAM double-layer counting defense row hammer circuit of the present invention, Spectre was used to perform functional simulation of the RRAM double-layer counting defense row hammer circuit of the present invention at TSMC 28nm process voltage of 1V. The upper limit of the count of the group counter circuit was set to 800, and the upper limit of the count of each row counter was set to 200. Thus, defense was performed when the row hammer attack threshold was 1000 times. The counting and reset function tests of the group counter circuit are as follows: Figure 5 As shown, the counting and reset function test of the row counter circuit is as follows Figure 6 Analysis Figure 5It can be seen that the group counter circuit in the RRAM dual-layer counting defense hammer circuit of the present invention can realize 800 counting operations for the high level of the external enable signal EN, and when the number of counts reaches 800, the counting signal R_EN output by the group counter circuit is high, and then the group counter circuit is refreshed and the count value is reset. Figure 6 It can be seen that the row counter circuit in the RRAM double-layer counting defense row hammer circuit of the present invention can realize 200 counting operations for the high level of the first input terminal, and when the number of counts reaches 200 times, the warning signal Alert output by the row counter circuit is high, and then the row counter circuit is refreshed and the count value is reset.

Claims

1. A hammer protection circuit based on RRAM double-layer counting, characterized in that The invention comprises a decoder circuit, a group counter circuit, four row counter circuits and a first PMOS transistor. The four row counter circuits are respectively referred to as a first row counter circuit, a second row counter circuit, a third row counter circuit and a fourth row counter circuit. The group counter circuit and the four row counter circuits are respectively implemented based on RRAM devices. The decoder circuit is used to convert a 2-bit binary address signal outputted externally thereto into a 4-bit binary decoding signal under the control of an external enable signal EN and output the signal to the four row counter circuits in a one-to-one correspondence. The first PMOS transistor is used to be turned on or off under the control of a signal connected to its gate. When the signal connected to the gate of the first PMOS transistor is at a low level, the first PMOS transistor is turned on. The group counter circuit is connected to the four row counter circuits through the first PMOS transistor. The group counter circuit can output signals to the four row counter circuits. When the signal connected to the gate of the first PMOS transistor is at a high level, the first PMOS transistor is turned off, the group counter circuit and the four row counter circuits are all disconnected, and the group counter circuit is turned on. The counter circuit cannot output signals to the four row counter circuits, and the group counter circuit cannot affect the working states of the four row counter circuits. The group counter circuit is used to count the high level of the external enable signal EN and generate a corresponding counting signal R_EN based on the count value and output it to the drain of the first PMOS transistor. If the count value does not reach the upper limit of the group counter counting circuit, the counting signal R_EN output by the group counter circuit is low. If the count value reaches the upper limit of the group counter circuit, the counting signal R_EN output by the group counter circuit is high. The row counter circuit is used to count the high level output by the decoder circuit when the signal output by the decoder circuit is high, the counting signal R_EN output by the group counter circuit is high, and the signal connected to the gate of the first PMOS is low. If the count value does not reach its upper limit, it outputs a low-level warning signal Alert; if the count value reaches its upper limit, it outputs a high-level warning signal Alert.

2. The RRAM double-layer counting-based anti-hammer circuit according to claim 1, characterized in that The decoder circuit has three input terminals and four output terminals, and its three input terminals are respectively referred to as its first input terminal, second input terminal and third input terminal, and its four output terminals are respectively referred to as its first output terminal, second output terminal, third output terminal and fourth output terminal; the group counter circuit has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; each of the row counter circuits has five input terminals and one output terminal, and its five input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; the first input terminal of the decoder circuit is used to access the first bit A of the 2-bit binary address signal, and the second input terminal of the decoder circuit is used to access the second bit B of the 2-bit binary address signal; the first output terminal of the decoder circuit is used to output The first bit of the 4-bit binary decoded signal is outputted from the decoder circuit; the second output terminal of the decoder circuit is used to output the second bit of the 4-bit binary decoded signal; the third output terminal of the decoder circuit is used to output the third bit of the 4-bit binary decoded signal; the fourth output terminal of the decoder circuit is used to output the fourth bit of the 4-bit binary decoded signal; the third input terminal of the decoder circuit is connected to the first input terminal of the group counter circuit, and its connection terminal is the enable terminal of the defense hammer circuit, which is used to receive the external enable signal EN; the second input terminal of the group counter circuit is connected to the power supply VDD; the third input terminal of the group counter circuit is the first refresh terminal of the defense hammer circuit, which is used to receive the first refresh signal Ref1 that restarts the group counter circuit; the fourth input terminal of the group counter circuit is the first reference terminal of the defense hammer circuit, which is used to receive the first reference voltage V rfe1 ; The fifth input end of the group counter circuit is the first control end of the defense hammer circuit, which is used to access the first control signal SA1_CTL for controlling whether the output end of the group counter circuit outputs a signal; the first output end of the decoder circuit is connected to the first input end of the first row counter circuit, the second output end of the decoder circuit is connected to the first input end of the second row counter circuit, the third output end of the decoder circuit is connected to the first input end of the third row counter circuit, the fourth output end of the decoder circuit is connected to the first input end of the fourth row counter circuit, the second input end of the first row counter circuit, the second input end of the second row counter circuit, the second input end of the third row counter circuit and the second input end of the fourth row counter circuit are connected, and the connection end is the second control end of the defense hammer circuit, which is used to access the second control signal for controlling whether the output end of the group counter circuit outputs a signal. SA2_CTL; the third input terminal of the first row counter circuit, the third input terminal of the second row counter circuit, the third input terminal of the third row counter circuit, the third input terminal of the fourth row counter circuit and the gate of the first PMOS tube are connected, and the connection terminal is the second refresh terminal of the defense row hammer circuit, which is used to access the second refresh signal Ref2 that restarts the row counter circuit; the source of the first PMOS tube is respectively connected to the fourth input terminal of the first row counter circuit, the fourth input terminal of the second row counter circuit, the fourth input terminal of the third row counter circuit and the fourth input terminal of the fourth row counter circuit, the fifth input terminal of the first row counter circuit, the fifth input terminal of the second row counter circuit, the fifth input terminal of the third row counter circuit and the fifth input terminal of the fourth row counter circuit are connected, and the connection terminal is the second reference terminal of the defense row hammer circuit, which is connected to the second reference voltage V rfe2 .

3. The RRAM double-layer counting-based anti-hammer circuit according to claim 2, characterized in that The group counter circuit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second PMOS tube, a first sensitive amplifier, a first memristor and a second memristor. The first sensitive amplifier has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The first memristor and the second memristor both have a top electrode and a bottom electrode. The initial resistance state of the first memristor is a high resistance state, and the initial resistance state of the second memristor is a low resistance state. The drain of the first NMOS tube is connected to the drain of the fourth NMOS tube, and the connection end thereof is the second input terminal of the group counter circuit. The gate of the first NMOS tube and the gate of the fifth NMOS tube are connected to the enable terminal of the first sensitive amplifier, and the connection end thereof is the first input terminal of the group counter circuit. The source of the first NMOS tube is connected to the top electrode of the first memristor. The bottom electrode of the first memristor, the The source of the second PMOS tube is connected to the non-inverting input of the first sensitive amplifier, the inverting input of the first sensitive amplifier is the fourth input of the group counter circuit, the drain of the second PMOS tube, the top electrode of the second memristor and the drain of the third NMOS tube are connected, the gate of the third NMOS tube, the gate of the second PMOS tube and the gate of the fourth NMOS tube are connected, and their connection end is the third input of the group counter circuit, the source of the third NMOS tube and the source of the fifth NMOS tube are both grounded, the bottom electrode of the second memristor, the source of the fourth NMOS tube and the drain of the fifth NMOS tube are connected, the output of the first sensitive amplifier is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is the fifth input of the group counter circuit, and the source of the second NMOS tube is the output of the group counter circuit.

4. The RRAM double-layer counting-based anti-hammer circuit according to claim 3, characterized in that Each of the row counter circuits includes a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a third PMOS tube, a fourth PMOS tube, a second sensitive amplifier, a third memristor and a fourth memristor. The second sensitive amplifier has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The third memristor and the fourth memristor both have a top electrode and a bottom electrode. The initial resistance state of the third memristor is a high resistance state, and the initial resistance state of the fourth memristor is a low resistance state. The top electrode of the third memristor, the gate of the eighth NMOS tube and the enable terminal of the second sensitive amplifier are connected, and the connection end thereof is the first input terminal of the row counter circuit. The source of the sixth NMOS tube is connected to the bottom electrode of the third memristor. The drain of the sixth NMOS tube, the source of the third PMOS tube and the non-inverting input terminal of the second sensitive amplifier are connected. The inverting input terminal of the second sensitive amplifier is the The fifth input terminal of the row counter circuit, the drain of the third PMOS tube, the top electrode of the fourth memristor and the drain of the eighth NMOS tube are connected, the gate of the ninth NMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube are connected, and the connection end is the third input terminal of the row counter circuit, the source of the eighth NMOS tube and the drain of the fourth PMOS tube are both grounded, the bottom electrode of the fourth memristor, the source of the fourth PMOS tube and the source of the ninth NMOS tube are connected, the drain of the ninth NMOS tube is connected to the power supply voltage, the output terminal of the second sensitive amplifier and the drain of the seventh NMOS tube are connected, the gate of the seventh NMOS tube is the second input terminal of the row counter circuit, the source of the seventh NMOS tube is the output terminal of the row counter circuit, and the gate of the sixth NMOS tube is the fourth input terminal of the row counter circuit.

5. The RRAM double-layer counting-based anti-hammer circuit according to claim 4, characterized in that The first sensitive amplifier includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube. The source of the fifth PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are all connected to the power supply voltage. The gate of the fifth PMOS tube, the gate of the eighth PMOS tube and the gate of the fourteenth NMOS tube are connected, and the connection end thereof is the enable end of the first sensitive amplifier. The drain of the fifth PMOS tube, the drain of the sixth PMOS tube, the drain of the tenth NMOS tube, the gate of the seventh PMOS tube and the gate of the eleventh NMOS tube are connected, and the connection end thereof is the enable end of the first sensitive amplifier. The output end of the sense amplifier, the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor, the drain of the eleventh NMOS transistor, the gate of the sixth PMOS transistor, and the gate of the tenth NMOS transistor are connected, the source of the tenth NMOS transistor and the drain of the twelfth NMOS transistor are connected, the gate of the twelfth NMOS transistor serves as the inverting input end of the first sense amplifier, the source of the eleventh NMOS transistor and the drain of the thirteenth NMOS transistor are connected, the gate of the thirteenth NMOS transistor serves as the non-inverting input end of the first sense amplifier, the source of the twelfth NMOS transistor, the source of the thirteenth NMOS transistor, and the drain of the fourteenth NMOS transistor are connected, and the source of the fourteenth NMOS transistor is grounded; the circuit structure of the second sense amplifier is the same as that of the first sense amplifier.

Images