Preparation method of semiconductor device
By opening a step structure on the gate dielectric layer of the gallium nitride semiconductor device, depositing and peeling the metal layer, the problem of difficulty in forming a good interface state in the dry etching process is solved, and the reliability and dynamic performance of the device are improved.
Patent Information
- Application Number
- CN202411901109.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-05-13
AI Technical Summary
In the dry etching process, it is difficult for existing gallium nitride semiconductor devices to form a good interface state, resulting in the impact of the reliability and dynamic performance of the device.
By opening a gate step on one side of the gate dielectric layer and preparing a gate photoresist layer outside it, after depositing the gate metal layer, the photoresist layer is peeled off to retain the required metal layer, thereby forming a gate field plate structure to avoid a dry etching process.
This method effectively forms a good interface state, improves the reliability and dynamic performance of semiconductor devices, and avoids the defects of dry etching process.
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Figure CN119993831A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the field of semiconductor technology, and in particular relates to a method for preparing a semiconductor device. Background Art
[0002] Semiconductor devices are electronic devices that use the special electrical properties of semiconductor materials to perform specific functions.
[0003] In the related technology, gallium nitride semiconductor devices are relatively common, which include an epitaxial layer, a gate dielectric layer, and a gate field plate structure arranged on one side of the gate dielectric layer. Among them, the gate field plate structure is based on the dielectric layer. When preparing the gate field plate structure, a dry etching process is required to etch the dielectric layer. The dry etching process is to etch and remove the dielectric layer through plasma bombardment.
[0004] However, due to the characteristics of plasma bombardment, it is difficult to form a good interface state at the interface after the dielectric layer is etched, which affects the reliability and dynamic performance of semiconductor devices. Summary of the invention
[0005] The embodiment of the present disclosure provides a method for preparing a semiconductor device, which can improve the reliability and dynamic performance of the semiconductor device. The technical solution is as follows:
[0006] The present disclosure provides a method for preparing a semiconductor device, the method comprising:
[0007] preparing a gate dielectric layer;
[0008] A gate step is provided on one side of the gate dielectric layer;
[0009] Prepare a gate photoresist layer, wherein the gate photoresist layer is located on one side of the gate dielectric layer and outside the gate step;
[0010] Depositing a gate metal layer, wherein the gate metal layer is located on one side of the gate dielectric layer, one side of the gate photoresist layer, and within the gate step;
[0011] The gate photoresist layer is stripped off to retain the gate metal layer located on one side of the gate dielectric layer and the gate metal layer located in the gate step, thereby obtaining a gate field plate structure.
[0012] In one implementation of the present disclosure, depositing a gate metal layer includes:
[0013] depositing a first sublayer, wherein the first sublayer is titanium or titanium nitride;
[0014] depositing a second sublayer, wherein the second sublayer is an aluminum-silicon alloy or an aluminum-copper alloy;
[0015] A third sublayer is deposited, wherein the third sublayer is titanium or titanium nitride.
[0016] In one implementation of the present disclosure, depositing a gate metal layer includes:
[0017] Depositing a first sublayer, wherein the first sublayer is aluminum, aluminum-silicon alloy or aluminum-copper alloy;
[0018] A second sublayer is deposited, the second sublayer being titanium or titanium nitride.
[0019] In another implementation of the present disclosure, the thickness of the first sublayer is set to 20 nm to 200 nm;
[0020] The thickness of the second sublayer is set to 200 nm to 2000 nm;
[0021] The thickness of the third sublayer is set to be 20 nm to 200 nm.
[0022] In another implementation of the present disclosure, stripping the gate photoresist layer includes:
[0023] Adhere an adhesive film to the gate metal layer on one side of the gate photoresist layer;
[0024] The adhesive film is peeled off to peel off the gate photoresist layer and the gate metal layer located on one side of the gate photoresist layer together.
[0025] In another implementation of the present disclosure, stripping the gate photoresist layer includes:
[0026] The gate photoresist layer is dissolved by a photoresist dissolving solution, so that the gate photoresist layer and the gate metal layer located on one side of the gate photoresist layer are peeled off together.
[0027] In another implementation of the present disclosure, a gate step is provided on one side of the gate dielectric layer, including:
[0028] Multiple dielectric layers are sequentially prepared on one side of the gate dielectric layer, each of the dielectric layers has holes, and the size of each hole gradually increases in a direction away from the gate dielectric layer, and the holes are arranged relatively to form the gate step.
[0029] In another implementation of the present disclosure, a dielectric layer is prepared on one side of the gate dielectric layer, including:
[0030] preparing a dielectric photoresist layer;
[0031] Depositing a dielectric layer, the dielectric layer being located on one side of the gate dielectric layer and one side of the dielectric photoresist layer;
[0032] The dielectric photoresist layer is stripped off to retain the dielectric layer located on one side of the gate dielectric layer.
[0033] In yet another implementation of the present disclosure, depositing a dielectric layer includes:
[0034] The thickness of the dielectric layer is set to 20 nm to 1000 nm;
[0035] Deposit silicon nitride or silicon dioxide film layers.
[0036] In another implementation of the present disclosure, stripping the dielectric photoresist layer includes:
[0037] Adhere an adhesive film to the dielectric layer on one side of the dielectric photoresist layer;
[0038] The adhesive film is peeled off to peel off the dielectric photoresist layer and the dielectric layer located on one side of the dielectric photoresist layer together.
[0039] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0040] In the process of preparing a semiconductor device by the preparation method provided by the embodiment of the present disclosure, a gate step is provided on one side of the gate dielectric layer, which serves as the basis for preparing the gate metal layer. Then, a gate photoresist layer is prepared on one side of the gate dielectric layer, so that the gate photoresist layer is located outside the gate step. Then, the gate metal layer is directly deposited, so that the gate metal layer is located on one side of the gate dielectric layer, one side of the gate photoresist layer, and inside the gate step. Finally, the gate photoresist layer is stripped off. Since part of the gate metal layer is located on one side of the gate photoresist layer, after the gate photoresist layer is stripped off, this part of the gate metal layer will be stripped off together, thereby retaining the gate metal layer on one side of the gate dielectric layer and the gate metal layer located in the gate step, thereby obtaining a gate field plate structure.
[0041] That is to say, in the process of preparing semiconductor devices, the required gate metal layer is retained by stripping off the redundant gate metal layer to obtain the gate field plate structure. In the process of stripping off, no dry etching process is involved, which can effectively form a good interface state, so that the reliability and dynamic performance of the semiconductor device can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0043] Figure 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present disclosure;
[0044] Figure 2 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present disclosure;
[0045] Figure 3 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0046] Figure 4 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0047] Figure 5 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0048] Figure 6 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0049] Figure 7 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0050] Figure 8 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0051] Fig. 9 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0052] Fig.10 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0053] Fig.11 It is a schematic diagram of the steps of the preparation method provided by the embodiment of the present disclosure;
[0054] Fig.12 It is a schematic diagram of the steps of the preparation method provided in an embodiment of the present disclosure.
[0055] The symbols in the figure mean the following:
[0056] 10. Gate dielectric layer;
[0057] 20. Gate ladder;
[0058] 30. Gate photoresist layer;
[0059] 40. Gate metal layer;
[0060] 50. Dielectric layer;
[0061] 60. Dielectric photoresist layer;
[0062] 70. Epitaxial layer.
[0063] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0064] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0065] The present disclosure provides a method for preparing a semiconductor device. Figure 1 For a flow chart of the preparation method, see Figure 1 In this embodiment, the preparation method comprises:
[0066] Step 101: preparing a gate dielectric layer 10 .
[0067] Step 102 : forming a gate step 20 on one side of the gate dielectric layer 10 .
[0068] Step 103 : preparing a gate photoresist layer 30 . The gate photoresist layer 30 is located on one side of the gate dielectric layer 10 and outside the gate step 20 .
[0069] Step 104 : depositing a gate metal layer 40 , where the gate metal layer 40 is located on one side of the gate dielectric layer 10 , one side of the gate photoresist layer 30 , and within the gate step 20 .
[0070] Step 105 : stripping off the gate photoresist layer 30 to retain the gate metal layer 40 located on one side of the gate dielectric layer 10 and the gate metal layer 40 located in the gate step 20 , thereby obtaining a gate field plate structure.
[0071] In the process of preparing a semiconductor device by the preparation method provided by the embodiment of the present disclosure, a gate dielectric layer 10 is first prepared, and a gate step 20 is opened on one side of the gate dielectric layer 10, which serves as a preparation basis for the gate metal layer 40. Then, a gate photoresist layer 30 is prepared on one side of the gate dielectric layer 10, so that the gate photoresist layer 30 is located outside the gate step 20. Then, the gate metal layer 40 is directly deposited, so that the gate metal layer 40 is located on one side of the gate dielectric layer 10, one side of the gate photoresist layer 30, and inside the gate step 20. Finally, the gate photoresist layer 30 is stripped off. Since part of the gate metal layer 40 is located on one side of the gate photoresist layer 30, after the gate photoresist layer 30 is stripped off, this part of the gate metal layer 40 will be stripped off together, thereby retaining the gate metal layer 40 on one side of the gate dielectric layer 10 and the gate metal layer 40 located in the gate step 20, and then obtaining a gate field plate structure.
[0072] That is, in the process of preparing the semiconductor device, the required gate metal layer 40 is retained by stripping off the redundant gate metal layer 40 to obtain the gate field plate structure. In the stripping process, no dry etching process is involved, and a good interface state can be effectively formed, so that the reliability and dynamic performance of the semiconductor device can be guaranteed.
[0073] Figure 2 A flowchart of another method for preparing a semiconductor device provided in an embodiment of the present disclosure is provided in Figure 2 In this embodiment, the preparation method comprises:
[0074] Step 201: Provide a substrate.
[0075] Exemplarily, the substrate is a sapphire-based substrate, or other silicon-based substrates, which is not limited in the present disclosure.
[0076] Step 202: growing an epitaxial layer 70 on one side of the substrate (see Figure 3 ).
[0077] Exemplarily, the epitaxial layer 70 includes a nucleation layer, a buffer layer, a channel layer and a barrier layer grown in sequence. The channel layer is an AlN layer, the thickness of the channel layer is 20nm to 1000nm, the buffer layer is an AlGaN layer, the thickness of the buffer layer is 20nm to 1000nm, the channel layer is a GaN layer, the thickness of the channel layer is 100nm to 400nm, and the barrier is an AlGaN layer, the thickness of the barrier layer is 10nm to 30nm.
[0078] Step 203 : growing a gate dielectric layer 10 on one side of the epitaxial layer 70 .
[0079] Exemplarily, the gate dielectric layer 10 is a silicon nitride layer, and the growth thickness is 10 nm to 80 nm.
[0080] Exemplarily, the gate dielectric layer 10 is prepared by LPCVD (low pressure chemical vapor deposition) equipment, or by MOCVD (metal-organic chemical vapor deposition) equipment.
[0081] Step 204 : forming a gate step 20 on one side of the gate dielectric layer 10 .
[0082] Exemplarily, multiple dielectric layers 50 are sequentially prepared on one side of the gate dielectric layer 10 , each dielectric layer 50 has holes, the holes are arranged opposite to each other, and the size of each hole gradually increases in a direction away from the gate dielectric layer 10 .
[0083] It can be seen that in step 204, the gate step 20 has a multi-layer structure, and each layer structure is prepared in sequence to form the gate step 20. The preparation method of the gate step 20 is described below by taking a two-layer structure as an example.
[0084] For the first layer structure:
[0085] Step 2041: Prepare a dielectric photoresist layer 60 (see Figure 4 ).
[0086] Exemplarily, a negative photoresist is coated on one side of the gate dielectric layer 10 , and then exposed, developed and stripped to retain a dielectric photoresist layer 60 on one side of the gate dielectric layer 10 at a position corresponding to the first gate step 20 .
[0087] Step 2042: Deposit dielectric layer 50 (see Figure 5 ).
[0088] Since one side of the gate dielectric layer 10 has the dielectric photoresist layer 60, the dielectric layer 50 is located on one side of the gate dielectric layer 10 and one side of the dielectric photoresist layer 60.
[0089] Exemplarily, in step 2042 , the thickness of the dielectric layer 50 is set to 20 nm to 1000 nm, and a silicon nitride or silicon dioxide film layer is deposited to form the dielectric layer 50 .
[0090] For example, the deposition method of the dielectric layer 50 may be PECVD (plasma enhanced chemical vapor deposition) or LPCVD. The temperature of PECVD is less than 500 degrees Celsius, and the film forming speed is fast, while the temperature of LPCVD is 500 to 1200 degrees Celsius, and the film forming speed is slow, but the film quality is better than that of PECVD. The present disclosure does not limit this.
[0091] Step 2043: Strip the dielectric photoresist layer 60 to retain the dielectric layer 50 located on one side of the gate dielectric layer 10 (see Figure 6 ).
[0092] There are two ways to strip the dielectric photoresist layer 60. In some examples, first, an adhesive film is adhered to the dielectric layer 50 on one side of the dielectric photoresist layer 60, and then the adhesive film is stripped to strip the dielectric photoresist layer 60 and the dielectric layer 50 on one side of the dielectric photoresist layer 60 together.
[0093] Exemplarily, the adhesive film is a blue film, which is made of materials such as polyolefin or polycarbonate, and has high tensile strength and chemical corrosion resistance. During the mechanical stripping process, the blue film is bonded to the wafer surface and is torn off after the wafer processing is completed. This process requires the blue film to have good adhesion and easy stripping properties.
[0094] The above-mentioned stripping method for the dielectric photoresist layer 60 is physical stripping.
[0095] In other examples, first, a sufficient amount of photoresist dissolving solution is provided, and then the entire semiconductor device is placed in the photoresist dissolving solution to dissolve the dielectric photoresist layer 60, so that the dielectric photoresist layer 60 and the dielectric layer 50 located on one side of the dielectric photoresist layer 60 are peeled off together.
[0096] Illustratively, the photoresist dissolving solution is a solvent-based stripping agent, such as acetone, NMP (1-methyl-2-pyrrolidone), NEP (nitroethylpyrrolidone), and DMSO (dimethyl sulfoxide).
[0097] Exemplarily, the entire semiconductor device is placed in a photoresist dissolving solution for 2 to 20 minutes to ensure full dissolution.
[0098] In this embodiment, if the photoresist removal is difficult during the stripping process using the photoresist dissolving solution, ultrasonic or megasonic cleaning may be used.
[0099] The above-mentioned stripping method for the dielectric photoresist layer 60 is chemical stripping.
[0100] Whether physical stripping or chemical stripping is used, a good stripping effect on the dielectric photoresist layer 60 can be achieved.
[0101] Through steps 2041 to 2043 , the first layer of gate steps 20 can be formed.
[0102] For the second layer structure:
[0103] Step 2044: Prepare a dielectric photoresist layer 60 (see Figure 7 ).
[0104] Exemplarily, a negative photoresist is coated on one side of the gate dielectric layer 10 , and then exposed, developed and stripped to retain the dielectric photoresist layer 60 on one side of the gate dielectric layer 10 and in the first gate step 20 .
[0105] Step 2045: Deposit dielectric layer 50 (see Figure 8 ).
[0106] Since one side of the gate dielectric layer 10 has the dielectric photoresist layer 60, the dielectric layer 50 is located on one side of the gate dielectric layer 10 and one side of the dielectric photoresist layer 60.
[0107] Exemplarily, in step 2045 , the thickness of the dielectric layer 50 is set to 20 nm to 1000 nm, and a silicon nitride or silicon dioxide film layer is deposited to form the dielectric layer 50 .
[0108] Exemplarily, the dielectric layer 50 may be deposited by chemical vapor deposition or furnace deposition.
[0109] Step 2046: Strip the dielectric photoresist layer 60 to retain the dielectric layer 50 located on one side of the gate dielectric layer 10 (see Fig. 9 ).
[0110] The method of stripping the dielectric photoresist layer 60 is the same as the stripping method mentioned in step 2043 , which can be stripped physically or chemically, and will not be described in detail here.
[0111] Through steps 2044 to 2046 , the first layer of gate steps 20 can be formed.
[0112] It is easy to understand that if the gate step 20 is a three-layer structure, a four-layer structure, etc., it can be prepared by referring to the first layer structure and the second layer structure mentioned above, and no further details will be given here.
[0113] Step 205: Prepare a gate photoresist layer 30 (see Fig.10 , in order to indicate that the two dielectric layers 50 are a whole, and the two gate steps 20 are a whole, Fig.10 The solid line between the two dielectric layers 50 is omitted).
[0114] The gate photoresist layer 30 is located on one side of the gate dielectric layer 10 and outside the gate step 20 .
[0115] A negative photoresist is coated on one side of the gate dielectric layer 10 , and then exposed, developed and stripped to retain a dielectric photoresist layer 60 on one side of the gate dielectric layer 10 at a position outside the gate step 20 .
[0116] Step 206: Deposit gate metal layer 40 (see Fig.11 ).
[0117] Exemplarily, step 206 includes the following steps:
[0118] Step 2061: depositing a first sub-layer, the first sub-layer being titanium or titanium nitride.
[0119] Exemplarily, the thickness of the first sublayer is set to be 20 nm to 200 nm.
[0120] Step 2062: depositing a second sub-layer, wherein the second sub-layer is an aluminum-silicon alloy or an aluminum-copper alloy.
[0121] Exemplarily, the thickness of the second sublayer is set to be 200 nm to 2000 nm.
[0122] Step 2063: depositing a third sub-layer, wherein the third sub-layer is titanium or titanium nitride.
[0123] Exemplarily, the thickness of the third sublayer is set to be 20 nm to 200 nm.
[0124] In the above implementation, benefiting from the material properties of the first sublayer and the third sublayer, the first sublayer and the third sublayer are relatively hard, and can block the diffusion of the aluminum-silicon alloy or aluminum-copper alloy in the second sublayer, and can also serve as a barrier layer for subsequent contact hole etching to the gate metal layer 40.
[0125] In other embodiments, step 206 may also replace the above steps 2061 to 2063 with the following steps:
[0126] Step 2061: depositing a first sub-layer, wherein the first sub-layer is aluminum, aluminum-silicon alloy or aluminum-copper alloy.
[0127] Step 2062: Deposit a second sub-layer, the second sub-layer is titanium or titanium nitride.
[0128] In this case, the gate metal layer 40 is a two-layer structure, and its preparation efficiency is higher than that of the three-layer structure mentioned above.
[0129] Step 207: stripping the gate photoresist layer 30 to retain the gate metal layer 40 on one side of the gate dielectric layer 10 and the gate metal layer 40 in the gate step 20, thereby obtaining a gate field plate structure (see Fig.12 ).
[0130] There are two ways to strip the gate photoresist layer 30. In some examples, first, an adhesive film is adhered to the gate metal layer 40 located on one side of the gate photoresist layer 30, and then the adhesive film is stripped to strip the gate photoresist layer 30 and the gate metal layer 40 located on one side of the gate photoresist layer 30 together.
[0131] The stripping method for the gate photoresist layer 30 is physical stripping.
[0132] In other examples, first, a sufficient amount of photoresist dissolving solution is provided, and then the entire semiconductor device is placed in the photoresist dissolving solution to dissolve the gate photoresist layer 30, so that the gate photoresist layer 30 and the gate metal layer 40 located on one side of the gate photoresist layer 30 are peeled off together.
[0133] The stripping method for the gate photoresist layer 30 is chemical stripping.
[0134] Whether physical stripping or chemical stripping is used, a good stripping effect on the dielectric photoresist layer 60 can be achieved.
[0135] In the process of preparing a semiconductor device by the preparation method provided by the embodiment of the present disclosure, a gate dielectric layer 10 is first prepared, and a gate step 20 is opened on one side of the gate dielectric layer 10, which serves as a preparation basis for the gate metal layer 40. Then, a gate photoresist layer 30 is prepared on one side of the gate dielectric layer 10, so that the gate photoresist layer 30 is located outside the gate step 20. Then, the gate metal layer 40 is directly deposited, so that the gate metal layer 40 is located on one side of the gate dielectric layer 10, one side of the gate photoresist layer 30, and inside the gate step 20. Finally, the gate photoresist layer 30 is stripped off. Since part of the gate metal layer 40 is located on one side of the gate photoresist layer 30, after the gate photoresist layer 30 is stripped off, this part of the gate metal layer 40 will be stripped off together, thereby retaining the gate metal layer 40 on one side of the gate dielectric layer 10 and the gate metal layer 40 located in the gate step 20, and then obtaining a gate field plate structure.
[0136] That is, in the process of preparing the semiconductor device, the required gate metal layer 40 is retained by stripping off the redundant gate metal layer 40 to obtain the gate field plate structure. In the stripping process, no dry etching process is involved, and a good interface state can be effectively formed, so that the reliability and dynamic performance of the semiconductor device can be guaranteed.
[0137] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0138] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: preparing a gate dielectric layer (10); A gate step (20) is provided on one side of the gate dielectric layer (10); Preparing a gate photoresist layer (30), wherein the gate photoresist layer (30) is located on one side of the gate dielectric layer (10) and outside the gate step (20); Depositing a gate metal layer (40), wherein the gate metal layer (40) is located on one side of the gate dielectric layer (10), one side of the gate photoresist layer (30), and within the gate step (20); The gate photoresist layer (30) is stripped off to retain the gate metal layer (40) located on one side of the gate dielectric layer (10) and the gate metal layer (40) located in the gate step (20), thereby obtaining a gate field plate structure.
2. The preparation method according to claim 1, characterized in that: Depositing a gate metal layer (40), comprising: depositing a first sublayer, wherein the first sublayer is titanium or titanium nitride; depositing a second sublayer, wherein the second sublayer is an aluminum-silicon alloy or an aluminum-copper alloy; A third sublayer is deposited, wherein the third sublayer is titanium or titanium nitride.
3. The preparation method according to claim 1, characterized in that: Depositing a gate metal layer (40), comprising: Depositing a first sublayer, wherein the first sublayer is aluminum, aluminum-silicon alloy or aluminum-copper alloy; A second sublayer is deposited, the second sublayer being titanium or titanium nitride.
4. The preparation method according to claim 2, characterized in that: The thickness of the first sublayer is set to 20 nm to 200 nm; The thickness of the second sublayer is set to 200 nm to 2000 nm; The thickness of the third sublayer is set to be 20 nm to 200 nm.
5. The preparation method according to claim 1, characterized in that: Stripping the gate photoresist layer (30) comprises: Adhere an adhesive film to the gate metal layer (40) located on one side of the gate photoresist layer (30); The adhesive film is peeled off to peel off the gate photoresist layer (30) and the gate metal layer (40) located on one side of the gate photoresist layer (30) together.
6. The preparation method according to claim 1, characterized in that: Stripping the gate photoresist layer (30) comprises: The gate photoresist layer (30) is dissolved by a photoresist dissolving solution, so that the gate photoresist layer (30) and the gate metal layer (40) located on one side of the gate photoresist layer (30) are peeled off together.
7. The preparation method according to claim 1, characterized in that: A gate step (20) is provided on one side of the gate dielectric layer (10), comprising: A plurality of dielectric layers (50) are sequentially prepared on one side of the gate dielectric layer (10), each of the dielectric layers (50) having a hole, and the size of each of the holes gradually increases in a direction away from the gate dielectric layer (10), and the holes are arranged relative to each other to form the gate step (20).
8. The preparation method according to claim 7, characterized in that: A dielectric layer (50) is prepared on one side of the gate dielectric layer (10), comprising: preparing a dielectric photoresist layer (60); Depositing a dielectric layer (50), wherein the dielectric layer (50) is located on one side of the gate dielectric layer (10) and one side of the dielectric photoresist layer (60); The dielectric photoresist layer (60) is stripped off to retain the dielectric layer (50) located on one side of the gate dielectric layer (10).
9. The preparation method according to claim 7, characterized in that: Depositing a dielectric layer (50), comprising: The thickness of the dielectric layer (50) is set to be 20 nm to 1000 nm; Deposit silicon nitride or silicon dioxide film layers.
10. The preparation method according to claim 7, characterized in that: Stripping the dielectric photoresist layer (60) comprises: Adhere an adhesive film to the dielectric layer (50) located on one side of the dielectric photoresist layer (60); The adhesive film is peeled off to peel off the dielectric photoresist layer (60) and the dielectric layer (50) located on one side of the dielectric photoresist layer (60) together.