Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a lead frame structure which comprises a first surface and a second surface which are opposite to each other, and the lead frame structure comprises a plurality of sub-base islands which are arranged at intervals; the plurality of chips are arranged on the first surfaces of the corresponding sub-base islands; the pin is arranged on the outer side of the lead frame structure and is electrically connected with the chip; the full plastic packaging layer is configured to be formed on the first surface of the lead frame structure, wrap the chip and fix the pins; and the local plastic packaging layer is at least formed on part of the surface of the full plastic packaging layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices generally include a base island, a chip disposed on the base island, and pins connected to the chip through bonding wires. In particular, high-voltage or high-power semiconductor devices often include multiple base islands, which are spaced apart from each other.

[0003] In order to meet the creepage distance requirements, the spacing between adjacent islands must meet the regulations. For example, in existing semiconductor devices, the minimum spacing requirement between islands is 1.2 mm. When the island spacing increases, the area of ​​the circuit board occupied will also increase accordingly, which is not conducive to the miniaturization of the circuit board size.

[0004] As a result, the layout of the base island is limited and cannot meet the flexible design requirements of semiconductor devices. Summary of the invention

[0005] The present application provides a semiconductor device that can solve the technical problem that the protection performance and heat dissipation performance of existing semiconductor devices are insufficient.

[0006] A semiconductor device, comprising: A lead frame structure, the lead frame structure comprising a first surface and a second surface facing each other, the lead frame structure comprising a plurality of spaced-apart sub-islands; A plurality of chips are disposed on the first surface of the corresponding sub-base island; A pin, disposed outside the lead frame structure and electrically connected to the chip; A full plastic encapsulation layer is configured to be formed on the first surface of the lead frame structure and wrap the chip and fix the pins; and The partial plastic sealing layer is formed on at least a portion of the surface of the full plastic sealing layer.

[0007] In one embodiment, the partial plastic encapsulation layer is also formed on the surface of the pin or the surface of the sub-base island.

[0008] In one embodiment, the sub-base island includes a first base island and a second base island in the thickness direction, the forward projection of the second base island falls completely within the plane where the first base island is located, the chip is arranged on the surface of the first base island facing away from the second base island, and the edge of the second base island is at a distance ranging from 0.20-0.30 mm from the edge of the first base island.

[0009] In one embodiment, the first base island and the second base island are integrally formed, and the distance between the second base island and the edge of the first base island is formed by etching.

[0010] In one embodiment, each of the sub-base islands includes a base island body and an extension pin connected to the base island body, and the extension pin and the lead are embedded in the full plastic packaging layer and located on the side of the full plastic packaging layer; or Each of the sub-base islands includes a base island body and an extension pin connected to the base island body. The extension pin is embedded in the full plastic sealing layer and the bending position extends from the inside of the full plastic sealing layer to the bottom surface of the full plastic sealing layer. The bottom surface of the full plastic sealing layer is correspondingly provided with a recess, and the extension pin is located in the recess.

[0011] In one embodiment, the pin or the extension pin includes a recess; or the second surface of the sub-base island is convexly provided with a micro-adjustment structure, and the height of the micro-adjustment structure is between 0.05 mm and 0.1 mm.

[0012] In one embodiment, the thickness of the full plastic sealing layer is greater than the thickness of the partial plastic sealing layer, and the forward projection of the partial plastic sealing layer completely falls within the plane where the full plastic sealing layer is located.

[0013] A method for manufacturing a semiconductor device, comprising: Providing a lead frame structure, the lead frame structure comprising a first surface and a second surface opposite to each other, the lead frame structure comprising a plurality of sub-base islands arranged at intervals; Providing a plurality of chips, arranged on the first surface of the corresponding sub-base island; Providing pins, which are arranged on one side of the lead frame structure, and the pins and the chip are arranged at a preset position so that the pins and the chip form a first packaged body; Providing a mold, the mold comprising a first cavity, placing the first body to be packaged into the first cavity, injecting molten resin into the first surface of the lead frame structure in the first cavity to form a full plastic sealing layer that wraps the chip and fixes the pins to obtain a second body to be packaged; and The mold further comprises a second cavity, and the second object to be packaged is placed in the second cavity to form a partial plastic sealing layer at least on the surface of the full plastic sealing layer.

[0014] In one embodiment, the size of the second cavity is adjustable.

[0015] In one embodiment, the mold provided includes a mold body, an insert and a locking member, the locking member includes a covering cap, a screw rod and an elastic member, the mold body is provided with a through hole for the screw rod to pass through, a step hole located on one side of the through hole and connected to the through hole, and a receiving groove located on the other side of the through hole and connected to the through hole, the elastic member passes through the screw rod and one end of the elastic member is fixed to the insert, and the other end of the elastic member is abutted against the bottom of the receiving groove, the elastic member is in a compressed state, the covering cap can be selectively located at the upper or lower part of the step hole to control the position of the insert, and when the insert is in the first position, the insert can be flush with the inner surface of the mold body; when the insert is in the second position, the insert is located in the receiving groove to adjust the size of the second cavity.

[0016] The present application provides a semiconductor device and a method for manufacturing the same, which can achieve the following technical effects: 1. In the related art, the creepage distance requirement for safety of adjacent chip components leads to excessive spacing between adjacent chip components, which results in the size of the sub-base island arranged on the same area being limited. If the size of the sub-base island is limited, the size of the chip arranged on the surface of the sub-base island is also reduced accordingly, which cannot meet the power requirement of the semiconductor device. In the present application, a local plastic encapsulation layer is formed on part of the surface of the full plastic encapsulation layer and between adjacent chip components. Therefore, the distance required for the shortest path along the surface of the insulating material between two conductive parts can be increased due to the thickness of the local plastic encapsulation layer. In other words, the local plastic encapsulation layer can be used to reduce the spacing between adjacent chip components, so that high-voltage or high-power chips can be arranged. In other words, more sub-base islands can be arranged within the same layout area, thereby arranging more chips, which means that there is no limit to the spacing requirement of the chip components and only a single layout method, thereby improving the flexibility of product layout.

[0017] 2. The creepage distance of adjacent chip components includes the creepage distance between sub-islands and between sub-islands and between sub-islands and pins. When a local plastic encapsulation layer is formed on the surface of the pins, the pins can be enhanced for protection.

[0018] 3. The position and size of the partial plastic sealing layer can be adjusted, thus achieving flexibility in the design of semiconductor device products. Furthermore, since the partial plastic sealing layer does not completely cover the sub-base island, the heat dissipation performance is ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic structural diagram of a semiconductor device provided in the first embodiment of the present application; Figure 2 yes Figure 1A schematic diagram of the electrical connection between a chip assembly and a lead frame structure included in the provided semiconductor device; Figure 3 yes Figure 2 The structural schematic diagram of the perspective flipping 180 degrees shown; Figure 4 yes Figure 2 A schematic diagram of the position of a chip component and a lead frame structure included in the provided semiconductor device; Figure 5 yes Figure 4 The structural schematic diagram of the perspective flipping 180 degrees shown; Figure 6 It is a schematic diagram of the structure of a semiconductor device array formed during mass production of semiconductor devices; Figure 7 It is a structural schematic diagram of the mold provided in the first embodiment of the present application; Figure 8 yes Figure 7 The structural diagram of the provided mold in use; Fig. 9 is a schematic structural diagram of a semiconductor device provided in the second embodiment of the present application; Fig.10 is a schematic structural diagram of a semiconductor device provided in the third embodiment of the present application; Fig.11 It is a structural schematic diagram of another semiconductor device provided in the third embodiment of the present application.

[0020] Explanation of the accompanying drawings: 100, semiconductor device; 1, lead frame structure; 2, chip assembly; 3, full plastic sealing layer; 4, partial plastic sealing layer; 10, sub-base island; 101, first surface; 102, second surface; 12, first base island; 14, second base island; 110, base island body; 112, extended pin; 30, bottom surface; 302, recess; 114, fine-adjustment structure; 5, mold; 501, second cavity; 50, mold body; 52, inlay; 54, locking part; 56, control system; 510, through hole; 512, receiving groove; 514, step hole; 540, limit plate; 542, screw; 20, chip; 22, pin; 40, partial plastic sealing layer one; 42, partial plastic sealing layer two. DETAILED DESCRIPTION

[0021] The following is combined with Figure 1-10 The semiconductor device provided by the present application is described in further detail.

[0022] See also Figure 1-5 , Figure 1-5A semiconductor device 100 is provided in the first embodiment of the present application. The semiconductor device 100 includes a lead frame structure 1, a chip component 2, a full plastic packaging layer 3 and a partial plastic packaging layer 4.

[0023] The lead frame structure 1 includes a first surface 101 and a second surface 102 facing each other, and the lead frame structure 1 includes a plurality of spaced-apart sub-base islands 10. The sub-base islands 10 are metal copper sheets that can dissipate heat and provide electrical conduction when communicating with external signals. The number of sub-base islands 10 is not limited. In this embodiment, three sub-base islands 10 are shown. It can be understood that the number of sub-base islands 10 can be set according to actual needs.

[0024] The chip assembly 2 includes a chip 20 disposed on the first surface 101 of the sub-base island 10 and a pin 22 bonded to the chip 20. The chip 20 is disposed on the first surface 101 of the corresponding sub-base island 10, and the chip 20 and the pin 22 are connected by a bonding wire. In this embodiment, the type of chip 20 is not limited, for example, it can be a power chip, such as a power MOSFET chip; or a control chip, a logic chip, a light-emitting chip, etc. Each sub-base island 10 can be placed with one or more chips 20, or a chip 20 can be placed on one and / or two sub-base islands, while no chip 20 is placed on the other sub-base island. This application does not limit the arrangement of the chip 20.

[0025] The pins 22 are arranged outside the lead frame structure 1 and are electrically connected to the chip 20 through bonding wires. The pins 22 are flush with the surface of the lead frame structure 1. The pins 22 can be independent pins or a pin strip formed by a plurality of pins.

[0026] The full plastic packaging layer 3 is formed on the first surface 101 of the lead frame structure 1 and wraps the chip 20 and fixes the lead 22 .

[0027] The partial plastic encapsulation layer 4 is formed on at least part of the surface of the full plastic encapsulation layer 3, and is used to increase the creepage distance between adjacent lead frame structures 1 and / or between the lead frame structure 1 and the pin 22. The full plastic encapsulation layer 3 and the partial plastic encapsulation layer 4 are formed by separate injection molding. In the present embodiment, the partial plastic encapsulation layer 4 is formed on part of the surface of the full plastic encapsulation layer 3 and is located between adjacent lead frame structures 1 and / or between the lead frame structure 1 and the pin 22, the thickness of the full plastic encapsulation layer 3 is greater than the thickness of the partial plastic encapsulation layer 4, and the forward projection of the partial plastic encapsulation layer 4 completely falls within the plane where the full plastic encapsulation layer 3 is located.

[0028] The partial plastic encapsulation layer 4 is in a straight line, concave or corrugated shape. The specific shape of the partial plastic encapsulation layer 4 is selected according to actual needs. In the present embodiment, only the partial plastic encapsulation layer 1 40 and the partial plastic encapsulation layer 2 42 are illustrated, wherein the partial plastic encapsulation layer 1 40 is in a straight line, and the opposite sides of the partial plastic encapsulation layer 1 40 at least contact the conductors on both sides respectively, and the partial plastic encapsulation layer 2 42 is concave. It can be understood that the partial plastic encapsulation layer 4 can also be formed in the space between adjacent sub-base islands 10 to solve the creepage distance between adjacent sub-base islands 10.

[0029] The structure of the traditional semiconductor device 100 is mainly divided into two categories, a fully encapsulated structure and a semi-encapsulated structure. Full encapsulation provides comprehensive protection for the product, but the cost is high and the heat dissipation performance may be limited. Semi-encapsulation partially exposes the product, which can reduce costs because less plastic packaging materials are required, and improve heat dissipation because the product is not fully encapsulated. However, semi-encapsulation sacrifices certain protection performance because the conductor parts are exposed. The semiconductor device 100 provided in the present application can solve the problems of heat dissipation, protection, and increase the flexibility of product layout while achieving semi-encapsulation.

[0030] The present application forms a local plastic encapsulation layer 4 on part of the surface of the full plastic encapsulation layer 3 and between adjacent chip components 2. Therefore, the distance required for the shortest path along the surface of the insulating material between two conductors can be increased due to the thickness of the local plastic encapsulation layer 4, thereby the local plastic encapsulation layer 4 can increase the creepage distance.

[0031] That is to say, due to the existence of the partial plastic encapsulation layer 1 40 and the partial plastic encapsulation layer 2 42, the creepage distance between the lead frame structure 1 and the pin 22 is increased from the previous straight-line distance between the two to the sum of the straight-line distance of the partial plastic encapsulation layer 1 40 or the partial plastic encapsulation layer 2 42 and twice the thickness of the partial plastic encapsulation layer 1 40 or the partial plastic encapsulation layer 2 42, so the creepage distance is improved. In addition, the partial plastic encapsulation layer 1 40 and the partial plastic encapsulation layer 2 42 can solve the technical problem of the stress of the pin 22 while solving the creepage distance. Because in the actual mass production process, please refer to Figure 6 , semiconductor devices 100 are usually collectively plastic-sealed in a mold and then cut to obtain a number of independent semiconductor devices 100. The intervals between adjacent semiconductor devices 100 are small. If there is no local plastic-sealing layer 4, the pins 22 located at the edge will often break due to stress during cutting, which affects the yield of the product. In addition, when the semiconductor device 100 is placed on the PCB board, it will also be subject to internal stress due to reflow soldering, and the internal stress will inevitably affect the position of the pin 22. Therefore, if the local plastic-sealing layer 4 can be formed on the surface of the pin 22, it can provide support for the pin 22 to prevent the internal stress from affecting its position during reflow soldering heating.

[0032] Thus, the local plastic encapsulation layer 4 can be used to reduce the spacing between adjacent chip components 2, so that high-voltage or high-power chips 20 can be arranged; or in other words, more sub-islands 10 can be arranged within the same layout area, thereby arranging more chips 20, that is, they will not be limited by the spacing requirements of the chip components 2 and can only have a single layout method, thereby improving the flexibility of product layout.

[0033] In this embodiment, the creepage distance between adjacent chip components 2 includes the creepage distance between sub-base islands 10 and sub-base islands 10 and the creepage distance between the sub-base islands 10 and the pins 22 .

[0034] In one of the embodiments, the sub-island 10 includes a first island 12 and a second island 14 in the thickness direction, the forward projection of the second island 14 completely falls within the plane where the first island 12 is located, the chip 20 is arranged on the surface of the first island 12 away from the second island 14, and the distance between the edge of the second island 14 and the edge of the first island 12 is in the range of 0.20-0.30mm.

[0035] In this embodiment, the first base island 12 and the second base island 14 are integrally formed, and the distance between the second base island 14 and the edge of the first base island 12 is formed by etching. That is, the distance between the second base island 14 and the edge of the first base island 12 is called an etching groove. The etching groove facilitates the flow of the molten plastic encapsulation resin.

[0036] In this embodiment, each sub-island 10 includes an island body 110 and an extension pin 112 connected to the island body 110. The extension pin 112 and the lead 22 are embedded in the full plastic packaging layer 3 and are located on the side of the full plastic packaging layer 3. The extension pin 112 is used to realize the interconnection between the chip 20 and the circuit board.

[0037] Please also read Figure 7-8 The present application also relates to a method for manufacturing a semiconductor device 100, comprising: S1: providing a lead frame structure 1, wherein the lead frame structure 1 comprises a first surface 101 and a second surface 102 opposite to each other, and the lead frame structure 1 comprises a plurality of sub-base islands 10 arranged at intervals; S2: providing a plurality of chips 20, and disposing them on the first surface 101 of the corresponding sub-base island 10; S3: providing a pin 22, which is disposed on one side of the lead frame structure 1, and the pin 22 and the chip 20 are arranged at a preset position so that the pin 22 and the chip 20 form a first package body; S4: providing a mold 5, wherein the mold 5 includes a first cavity (not shown) formed by an upper mold and a lower mold, placing the first body to be packaged into the first cavity, and injecting molten resin into the first surface 101 of the lead frame structure 1 in the first cavity to form a full plastic packaging layer 3 that wraps the chip 20 and fixes the pins 22 to obtain a second body to be packaged; and The mold 5 further includes a second cavity 501 , and the second object to be packaged is placed in the second cavity 501 to form a partial plastic sealing layer 4 at least on the surface of the full plastic sealing layer 3 .

[0038] In one embodiment, the size of the second cavity 501 is adjustable.

[0039] In one embodiment, the provided mold 5 includes a mold body 50 (which may be referred to as an upper mold), an insert 52 , a locking member 54 and a control system 56 .

[0040] The locking component 54 includes a limit plate 540 and a screw rod 542. The mold body 50 is provided with a through hole 510 for the screw rod 542 to pass through, a step hole 514 located on one side of the through hole 510 and connected to the through hole 510, and a receiving groove 512 located on the other side of the through hole 510 and connected to the through hole 510. One end of the screw rod 542 is fixed to the inlay 52, and the other end of the screw rod 542 is connected to the inlay 52. ​​The control system 56 can control the position of the limit plate 540 so that the limit plate 540 can be selectively located at the upper or lower part of the step hole 514 to control the position of the inlay 52. ​​When the inlay 52 is in the first position, the inlay 52 can be flush with the inner surface of the mold body 50; when the inlay 52 is in the second position, the inlay 52 is located in the receiving groove 512 to adjust the size of the second cavity 501. The size of the second cavity 501 determines the thickness or shape of the local plastic sealing layer 4. It can be understood that the control system 56 can be a motor, and the control system 56 controls the movement of the screw rod 542. Only one inlay 52 is shown in the figure. In fact, there are multiple inlays 52 matching the mold 5. The shape of each inlay 52 may be different, and each can be independently controlled. Each inlay 52 corresponds to a certain area on the surface of the full plastic sealing layer 3, so that the corresponding local plastic sealing layer 4 can be controlled at a preset position on the surface of the full plastic sealing layer 3 according to actual conditions. Example 2

[0041] See also Fig. 9The structure of the semiconductor device 100 provided in Example 2 is basically the same as that of the first embodiment, except that the extension pin 112 is embedded in the full plastic packaging layer 3 and the bending position extends from the inside of the full plastic packaging layer 3 to the bottom surface 30 of the full plastic packaging layer 3, and the bottom surface 30 of the full plastic packaging layer 3 is correspondingly provided with a recess 302, and the extension pin 112 is located in the recess 302.

[0042] In this embodiment, by adjusting the position of the extension pin 112 , the design of the recess 302 and the bending layout of the extension pin 112 , the overall volume of the package can be reduced while meeting the creepage distance. Example 3

[0043] See also Figure 10-11 The structure of the semiconductor device 100 provided in Example 3 is substantially the same as that of the semiconductor device 100 provided in the first embodiment, except that, in this embodiment, the two sides of the local plastic encapsulation layer 40 in contact with the sub-base island 10 and the lead 22 are corrugated.

[0044] The second surface 102 of the sub-base island 10 is integrally formed with a micro-adjustment structure 114, which may be a raised dot array ( Fig.10 ) or multiple spaced sheets ( Fig.11 ). The height of the fine adjustment structure 114 is between 0.05 mm and 0.1 mm. When the fine adjustment structure 114 is a raised dot array, it is preferably in a conical or truncated cone shape.

[0045] The partial plastic encapsulation layer 4 covers the surface of the micro-adjustment structure 114 . The thickness of the partial plastic encapsulation layer 4 is smaller than the height of the micro-adjustment structure 114 .

[0046] With such arrangement, firstly, the micro-adjustment structure 114 can increase the surface area of ​​the sub-base island 10, which helps to improve the heat conduction path and enhance the heat dissipation efficiency. Moreover, due to the existence of the micro-adjustment structure 114, there are a number of sheet-like micro-adjustment structures 114 between the local plastic encapsulation layer 40 from the pin 22 to the sub-base island 10, which can increase the surface area of ​​the local plastic encapsulation layer 40, which is equivalent to further increasing the creepage distance between the pin 22 and the sub-base island 10.

[0047] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: A lead frame structure (1), the lead frame structure (1) comprising a first surface (101) and a second surface (102) facing each other, the lead frame structure (1) comprising a plurality of sub-base islands (10) arranged at intervals; A chip assembly (2), comprising a chip (20) disposed on the first surface (101) of the sub-base island (10) and a lead (22) bonded to the chip (20); A full plastic encapsulation layer (3) is configured to be formed on the first surface (101) of the lead frame structure (1) and wrap the chip (20); as well as The partial plastic encapsulation layer (4) is formed on a portion of the surface of the full plastic encapsulation layer (3) and is located 50 between adjacent lead frame structures (1) and / or between the lead frame structure (1) and the pins (22).

2. A semiconductor device according to claim 1, characterized in that: The thickness of the full plastic sealing layer (3) is greater than the thickness of the partial plastic sealing layer (4), and the forward projection of the partial plastic sealing layer (4) completely falls within the plane where the full plastic sealing layer (3) is located.

3. A semiconductor device according to claim 2, characterized in that: The partial plastic sealing layer (4) is in a straight line shape, a concave shape or a corrugated shape; the two opposite sides of the partial plastic sealing layer (4) at least respectively contact the conductors on the two sides.

4. A semiconductor device according to claim 1, characterized in that: The sub-island (10) includes a first island (12) and a second island (14) in the thickness direction, the forward projection of the second island (14) completely falls within the plane where the first island (12) is located, the chip (20) is arranged on the surface of the first island (12) facing away from the second island (14), and the distance between the edge of the second island (14) and the edge of the first island (12) is in the range of 0.20-0.30 mm.

5. A semiconductor device according to claim 4, characterized in that: The first base island (12) and the second base island (14) are integrally formed, and the distance between the second base island (14) and the edge of the first base island (12) is formed by etching.

6. A semiconductor device according to claim 1, characterized in that: Each of the sub-base islands (10) comprises a base island body (110) and an extension pin (112) connected to the base island body (110), wherein the extension pin (112) and the lead pin (22) are both embedded in the full plastic packaging layer (3) and located on the side of the full plastic packaging layer (3); or Each of the sub-base islands (10) comprises a base island body (110) and an extension pin (112) connected to the base island body (110); the extension pin (112) is embedded in the full plastic sealing layer (3) and extends from the inside of the full plastic sealing layer (3) to the bottom surface (30) of the full plastic sealing layer (3) at a bent position; and a recess (302) is correspondingly provided on the bottom surface (30) of the full plastic sealing layer (3), and the extension pin (112) is located in the recess (302).

7. A semiconductor device according to claim 6, characterized in that: The pin (22) or the extension pin (112) includes a recess (302); or the second surface (102) of the sub-base island (10) is convexly provided with a micro-adjustment structure (114), and the height of the micro-adjustment structure (114) is between 0.05mm and 0.1mm.

8. A method for manufacturing a semiconductor device, characterized in that: include: A lead frame structure (1) is provided, wherein the lead frame structure (1) comprises a first surface (101) and a second surface (102) facing each other, and the lead frame structure (1) comprises a plurality of sub-base islands (10) arranged at intervals; Providing a plurality of chips (20), arranged on the first surface (101) of the corresponding sub-base island (10); Providing a lead (22) disposed on one side of the lead frame structure (1), wherein the lead (22) and the chip (20) are arranged at a preset position so that the lead (22) and the chip (20) form a first body to be packaged; A mold (5) is provided, the mold (5) comprising a first cavity, the first body to be packaged is placed in the first cavity, molten resin is injected into the first cavity onto the first surface (101) of the lead frame structure (1) to form a full plastic encapsulation layer (3) that wraps the chip (20) and fixes the lead (22) to obtain a second body to be packaged; and The mold (5) further comprises a second mold cavity (501), and the second object to be packaged is placed in the second mold cavity (501) to form a partial plastic sealing layer (4) at least on the surface of the full plastic sealing layer (3).

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that: The size of the second cavity (501) is adjustable.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that: The mold (5) provided comprises a mold body (50), an inlay piece (52), a locking piece (54) and a control system (56); the locking piece (54) comprises a limit plate (540) and a screw rod (542); the mold body (50) is provided with a through hole (510) for the screw rod (542) to pass through, a step hole (514) located on one side of the through hole (510) and connected to the through hole (510), and a receiving groove (512) located on the other side of the through hole (510) and connected to the through hole (510); one end of the screw rod (542) is connected to the limit plate (540) and the step hole (514) is located on one side of the through hole (510) and connected to the through hole (510). The positioning plate (540) is fixed, and the other end of the screw rod (542) is connected to the inlay (52). The control system (56) can control the position of the limiting plate (540) so that the limiting plate (540) can be selectively located at the upper part or the lower part of the step hole (514) to control the position of the inlay (52). When the inlay (52) is in the first position, the inlay (52) can be flush with the inner surface of the mold body (50); when the inlay (52) is in the second position, the inlay (52) is located in the accommodating groove (512) to adjust the size of the second cavity (501).

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