Semiconductor package

Abstract

A semiconductor package includes semiconductor chips each including at least one of a front insulating layer or a rear insulating layer, the semiconductor chips being bonded to each other by a direct bond between the front insulating layer and the rear insulating layer. At least one of the semiconductor chips includes: a device layer including an interconnect structure; and a conductive pattern on the front surface of the device layer. The conductive pattern includes: a pad pattern electrically connected to the interconnect structure; and a dummy pattern spaced apart from the pad pattern. The dummy patterns include: a first dummy pattern between the pad patterns to overlap the pad patterns in the first direction; and a second dummy pattern between the first dummy patterns to overlap the pad pattern in the second direction. The second dummy pattern is spaced apart from the first dummy pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0156542 filed in the Korean Intellectual Property Office on November 13, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor packaging. Background Art

[0004] According to the trend of miniaturization of semiconductor packages and the realization of high performance, it is necessary to develop a system-in-package (SiP) technology for embedding multiple semiconductor chips performing different functions in a single package. In order to form fine interconnections that connect semiconductor chips to each other within the package, a technology for forming through silicon vias (TSVs) and bonding semiconductor chips to each other through bonding pads has been used. Summary of the invention

[0005] One or more embodiments provide a semiconductor package that may have improved electrical characteristics and / or reliability of a front surface of a semiconductor chip.

[0006] According to one aspect of an example embodiment, a semiconductor package includes: a plurality of semiconductor chips, each of the plurality of semiconductor chips includes at least one of a front insulating layer and a rear insulating layer, and adjacent semiconductor chips among the plurality of semiconductor chips are bonded to each other by direct bonding between the front insulating layer of a first semiconductor chip among the adjacent semiconductor chips and the rear insulating layer of a second semiconductor chip among the adjacent semiconductor chips. At least one semiconductor chip among the plurality of semiconductor chips includes: a device layer including an interconnect structure; and a conductive pattern on a front surface of the device layer. The conductive pattern includes: a plurality of pad patterns electrically connected to the interconnect structure; and a dummy pattern spaced apart from the plurality of pad patterns. The dummy pattern includes: a plurality of first dummy patterns between the plurality of pad patterns, and overlapping with the plurality of pad patterns in a first direction and not in a second direction; and a plurality of second dummy patterns between the plurality of first dummy patterns, and overlapping with the plurality of pad patterns in a second direction and not in the first direction, wherein the plurality of second dummy patterns are spaced apart from the plurality of first dummy patterns.

[0007] According to one aspect of an example embodiment, a semiconductor package includes: a plurality of semiconductor chips, each of the plurality of semiconductor chips includes at least one of a front insulating layer and a rear insulating layer, and adjacent semiconductor chips in the plurality of semiconductor chips are bonded to each other by direct bonding between the front insulating layer of a first semiconductor chip in the adjacent semiconductor chips and the rear insulating layer of a second semiconductor chip in the adjacent semiconductor chips. At least one semiconductor chip in the plurality of semiconductor chips includes: a plurality of front pads; a front insulating layer around each of the plurality of front pads; a device layer on a rear surface of the front insulating layer, the device layer including an interconnect structure electrically connected to the plurality of front pads; a supporting insulating layer between the device layer and the front insulating layer; and a conductive pattern between the interconnect structure and the plurality of front pads, and around the conductive pattern. The conductive pattern includes: a plurality of pad patterns electrically connected between the interconnect structure and the plurality of front pads; and a dummy pattern spaced apart from the plurality of front pads and the plurality of pad patterns. The dummy pattern includes a plurality of first dummy patterns extending along a second direction between the plurality of pad patterns, and the plurality of first dummy patterns overlap with the plurality of pad patterns in the first direction. The plurality of first dummy patterns are spaced apart from each other along the first direction between two adjacent pad patterns among the plurality of pad patterns.

[0008] According to one aspect of an example embodiment, a semiconductor package includes: a semiconductor chip, including: a front insulating layer; a plurality of front pads, surrounded by the front insulating layer; a device layer, on the rear surface of the front insulating layer, and including an interconnect structure electrically connected to the plurality of front pads; a conductive pattern, between the interconnect structure and the plurality of front pads; a supporting insulating layer, between the device layer and the front insulating layer, and around the conductive pattern; a semiconductor substrate, on the rear surface of the device layer; a through electrode, passing through the semiconductor substrate; and a rear insulating layer, on the rear surface of the semiconductor substrate. The conductive pattern includes: a plurality of pad patterns, electrically connected between the interconnect structure and the plurality of front pads; and a dummy pattern, spaced apart from the plurality of front pads and the plurality of pad patterns. The dummy pattern includes a plurality of dummy patterns arranged around each of the plurality of pad patterns, and each of the plurality of dummy patterns extends in an unbent extension direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view of a semiconductor package according to one or more example embodiments of the present disclosure;

[0011] Figure 2A yes Figure 1 an enlarged view of a portion A of a semiconductor package;

[0012] Figure 2B yes Figure 1 an enlarged view of a portion B of a semiconductor package;

[0013] Figure 3A is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0014] Figure 3B is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0015] Figure 3C is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0016] Figure 3D is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0017] Figure 3E is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0018] Figure 3F is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0019] Figure 4A is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0020] Figure 4B is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0021] Figure 4C is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0022] Figure 4D is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0023] Figure 4E is a plan view of a semiconductor package and a conductive pattern according to one or more example embodiments of the present disclosure;

[0024] Figure 5A is an enlarged view of a semiconductor package according to one or more example embodiments of the present disclosure;

[0025] Figure 5B is an enlarged view of a semiconductor package according to one or more example embodiments of the present disclosure;

[0026] Fig. 6Ais a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0027] Figure 6B is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0028] Figure 6C is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0029] Fig.6D is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0030] Fig. 6E is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0031] Fig. 6F is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0032] Figure 6G is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0033] Fig. 7A is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0034] Figure 7B is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure;

[0035] Figure 7C is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure; and

[0036] Fig.7D is a cross-sectional view of a method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] The detailed description of the disclosure to be described later refers to the accompanying drawings, which show, by way of example, specific embodiments in which the disclosure can be practiced. These example embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. It should be understood that the various embodiments of the disclosure are different from each other, but not necessarily mutually exclusive. For example, one or more example embodiments of the specific shapes, structures, and characteristics described herein may be implemented in another embodiment without departing from the spirit and scope of the disclosure. In addition, it should be understood that the position or arrangement of the various components within each disclosed embodiment may be changed without departing from the spirit and scope of the disclosure. Therefore, the detailed description set forth below is not intended to be considered restrictive, and the scope of the disclosure is limited only by the appended claims and all equivalents claimed by these claims. Similar reference numerals in the drawings indicate the same or similar functions in various aspects.

[0038] The expressions "at least one of A and B" and "at least one of A or B" should be interpreted as meaning any one of "A" or "B" or "A and B". As another example, "perform at least one of step 1 and step 2" or "perform at least one of step 1 or step 2" means the following three juxtapositions: (1) perform step 1; (2) perform step 2; (3) perform both step 1 and step 2.

[0039] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure.

[0040] Figure 1 Shown along Figure 3A An XZ cross section of the semiconductor package taken along line II-II'. Figure 3A Shown along Figure 1 An XY cross section of the semiconductor package taken along line II'. Figure 2A yes Figure 1 An enlarged view of part A of FIG. Figure 2B yes Figure 1 An enlarged view of part B.

[0041] refer to Figure 1 , Figure 2A , Figure 2B and Figure 3A, the semiconductor packages 500 and 500A according to one or more example embodiments of the present disclosure may include at least one of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C, and may further include a substrate structure 300 disposed at the lower side of each of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C. Each of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C may include a front insulating layer 162b, a plurality of front pads 152, a device layer 120, semiconductor substrates 110 and 110', a conductive pattern 147, and a supporting insulating layer 162a. Each of the plurality of semiconductor chips 100A1, 100A2, and 100A3 may include a through electrode 130, a rear insulating layer 164, and a plurality of rear pads 154. Figure 1 A structure in which the number of the semiconductor chips 100A1 , 100A2 , 100A3 , and 100C is four is shown, but the number of the semiconductor chips 100A1 , 100A2 , 100A3 , and 100C is not particularly limited.

[0042] Each of the plurality of semiconductor chips 100A1, 100A2, 100A3 and 100C can be a memory chip. For example, the memory chip can be a volatile memory chip (e.g., a dynamic random access memory (DRAM) or a static random access memory (SRAM)) or a non-volatile memory chip (e.g., a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM) or a resistance random access memory (RRAM)). Alternatively, some of the semiconductor chips among the plurality of semiconductor chips 100A1, 100A2, 100A3 and 100C can each be a memory chip, and each of the other semiconductor chips can be a logic chip. The logic chip can be, for example, a microprocessor, an analog element or a digital signal processor, and can control the operation of the memory chip. For example, the combination of the plurality of semiconductor chips 100A1, 100A2, 100A3 and 100C can be a high bandwidth memory (HBM) DRAM.

[0043] The substrate structure 300 may include a lower connection pad 352 disposed on the lower surface of the substrate structure 300 and an upper connection pad 354 disposed on the upper surface of the substrate structure 300. For example, the substrate structure 300 may have a width (i.e., area) wider than the widths W1a and W1b (i.e., area) of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C. The substrate structure 300 may include a substrate body 310 and an interconnection circuit that connects the lower connection pad 352 and the upper connection pad 354 to each other within the substrate body 310. A connection bump 370 may be attached to the lower connection pad 352 of the substrate structure 300. The connection bump 370 may be, for example, a solder ball or a conductive bump. The connection bump 370 may be electrically connected to the semiconductor package 500 and a printed circuit board (e.g., a mainboard). Alternatively, the connection bump 370 may be electrically connected to an interposer for redistribution on the lower side. The substrate structure 300 may be implemented as a semiconductor chip, but the embodiments of the present disclosure are not limited thereto. For example, the substrate structure 300 may be implemented as an interposer according to design.

[0044] The semiconductor substrates 110 and 110' may include a semiconductor such as silicon. For example, the semiconductor substrate 110 may include various impurity regions for individual elements, and an element isolation structure such as a shallow trench isolation (STI) structure. The semiconductor is not limited to silicon, and may include at least one of germanium, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). For example, the element includes a planar metal oxide semiconductor FET (MOSFET), a FinFET having a fin structure in an active region, a multi-bridge channel FET (MBCFET), and a MOSFET. TM ), or a full-surround gate transistor or vertical FET (VFET) including multiple channels vertically stacked on an active area, but the embodiments of the present disclosure are not limited thereto.

[0045] Each through electrode 130 may have a column structure passing through the semiconductor substrate 110. The through electrode 130 may not pass through the semiconductor substrate 110'. The upper end of the through electrode 130 may be connected to the plurality of rear pads 154, and the lower end of the through electrode 130 may be electrically connected to the plurality of front pads 152 through the interconnect structure 140. The through electrode 130 may include a via plug 135 and an insulating liner 131 surrounding the via plug 135 (disposed around the via plug 135). The insulating liner 131 may electrically isolate the via plug 135 from the semiconductor substrate 110. The through electrode 330, the insulating liner 331, and the via plug 335 of the base structure 300 may be implemented in substantially the same manner as the through electrode 130, the insulating liner 131, and the via plug 135.

[0046] The device layer 120 may include an interconnection structure 140 connected to a plurality of individual elements formed on the front surface (lower surface) of the semiconductor substrates 110 and 110'. The interconnection structure 140 may include an interconnection layer 142 and an interconnection via 145. For example, the interconnection structure 140 may have a structure in which a plurality of interconnection layers 142 are stacked in the Z direction, and may include a plurality of interconnection vias 145 that electrically connect the plurality of interconnection layers 142 to each other in the Z direction. The interconnection structure 140 may be electrically connected to a plurality of front pads 152 disposed on the lower side of the device layer 120. The interconnection layer 142 and the interconnection via 145 may include at least one metal material of copper (Cu), copper alloy, aluminum (Al), and aluminum alloy. The metal material is not limited thereto, and may be implemented as at least one of nickel (Ni), gold (Au), cobalt (Co), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), and alloys thereof (e.g., TiN and TaN). The space of the device layer 120 where the interconnection structure 140 is not disposed may be filled with an insulating layer. For example, the insulating layer may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon carbonitride (SiCN). The device layer 320 of the substrate structure 300 may be implemented in substantially the same manner as the device layer 120 .

[0047] A plurality of front pads 152 may be arranged on the front surface (lower surface) of each of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C, and may provide an electrical path for the exterior of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C. The exterior of the semiconductor chips 100A2, 100A3, and 100C may be a plurality of rear pads 154 of the semiconductor chips 100A1, 100A2, and 100A3 immediately below the semiconductor chips 100A2, 100A3, and 100C. That is, a plurality of front pads 152 may be connected to a plurality of rear pads 154, thereby providing an electrical connection path between the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C. The plurality of rear pads 154 may be arranged on a rear surface (upper surface) of each of the plurality of semiconductor chips 100A1 , 100A2 , and 100A3 , and may be connected between the plurality of front pads 152 and the through-electrodes 130 .

[0048] The front surface (lower surface) and the rear surface (upper surface) of each of the plurality of front pads 152 and the plurality of rear pads 154 may have a polygonal or circular shape, and may have a width wider than the line width of the interconnection of the interconnection layer 142. Each of the plurality of front pads 152 and the plurality of rear pads 154 may include a metal material capable of being coupled to each other while having high conductivity, for example, copper (Cu) or a copper alloy. The metal material is not limited to copper, and may also be implemented as at least one of aluminum (Al), nickel (Ni), gold (Au), cobalt (Co), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W) and an alloy thereof. For example, the plurality of front pads 152 and the plurality of rear pads 154 may be temporarily bonded to each other to be in direct contact with each other, and then may be firmly coupled to each other using a high temperature annealing process, by mutual diffusion of copper.

[0049] The front insulating layer 162b may surround the plurality of front pads 152 (disposed around the plurality of front pads 152), and the rear insulating layer 164 may surround the plurality of rear pads 154 (disposed around the plurality of rear pads 154). The front insulating layer 162b and the front surfaces (lower surfaces) and the rear surfaces (upper surfaces) of the plurality of front pads 152 may be coplanar with each other, respectively, and the rear insulating layer 164 and the front surfaces (lower surfaces) and the rear surfaces (upper surfaces) of the plurality of rear pads 154 may be coplanar with each other, respectively.

[0050] Each of the front insulating layer 162b and the rear insulating layer 164 may include SiO 2 When the front insulating layer 162b and the rear insulating layer 164 are bonded to each other, SiO 2 The oxygen in the front insulating layer 162b can form a covalent bond with silicon. Therefore, the front insulating layer 162b and the rear insulating layer 164 can have a strong bonding strength. The insulating material included in the front insulating layer 162b and the rear insulating layer 164 is not limited to silicon oxide, and can be implemented as at least one of SiN, SiCN and tetraethoxysilane (TEOS).

[0051] For example, the rear insulating layer 164 may include a first insulating film 164a and a second insulating film 164b. The first insulating film 164a may prevent undesired electrical connection between the plurality of rear pads 154 and the semiconductor substrate 110. In addition, the plurality of rear pads 154 may be buried in the second insulating film 164b so that the rear surface (upper surface) of the plurality of rear pads 154 is exposed. The plurality of rear pads 154 may have an exposed rear surface (upper surface) substantially flat with the rear surface (upper surface) of the second insulating film 164b. In some example embodiments, the first insulating film 164a and the second insulating film 164b may be formed of the same material, but the embodiments of the present disclosure are not limited thereto and may be formed of different materials. For example, the first insulating film 164a may include silicon nitride or silicon oxynitride, and the second insulating film 164b may include silicon oxide.

[0052] Adjacent semiconductor chips among the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C may be bonded to each other through direct bonding DB2 between the front insulating layer 162b and the rear insulating layer 164. In addition, adjacent semiconductor chips among the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C may be electrically connected to each other through direct bonding DB1 between the plurality of front pads 152 and the plurality of rear pads 154. The direct bonding DB1 may be a metal-to-metal bonding, and the direct bonding DB2 may be a dielectric-to-dielectric bonding. The combination of the direct bonding DB1 and the direct bonding DB2 may be a hybrid bonding.

[0053] The bottom semiconductor chip 100A1 among the plurality of semiconductor chips 100A1, 100A2 and 100A3 can be directly bonded to the substrate structure 300 in a manner similar to the above-mentioned direct bonding DB1 and direct bonding DB2. Specifically, the plurality of front pads 152 of the semiconductor chip 100A1 adjacent to the substrate structure 300 can be directly bonded to the upper connection pad 354 to form a direct bonding DB1. The direct bonding DB1 can ensure electrical connection while bonding the substrate structure 300 and the semiconductor chip 100A1 to each other. An upper bonding insulating layer 364 can be formed on the upper surface of the substrate structure 300 according to the present example embodiment, and the upper bonding insulating layer 364 can have an upper surface substantially flat with the upper connection pad 354. The upper bonding insulating layer 364 of the substrate structure 300 and the front insulating layer 162 of the bottom semiconductor chip 100A1 can be directly bonded to each other to form a direct bonding DB2. Therefore, the substrate structure 300 and the bottom semiconductor chip 100A1 can be hybrid bonded to each other. For example, the upper bonding insulating layer 364 may include a first insulating film 364 a and a second insulating film 364 b , and the first insulating film 364 a and the second insulating film 364 b may be formed in substantially the same manner as the first insulating film 164 a and the second insulating film 164 b .

[0054] Due to at least one of the direct bonding DB1 and the direct bonding DB2, a conductive structure (e.g., a bump or solder) having a relatively low melting point may not be disposed between the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C. Typically, the conductive structure (e.g., a bump or solder) may be formed using a reflow process or a thermal compression bonding (TCB) process, but a minimum width or spacing (e.g., a bump or solder) may be required to ensure reliability.

[0055] Due to at least one of direct bonding DB1 and direct bonding DB2, multiple semiconductor chips 100A1, 100A2, 100A3 and 100C can be bonded to each other without using a conductive structure (e.g., a bump or solder), so that it is possible to reduce the width or spacing of each of the multiple front pads 152 and the multiple rear pads 154. Therefore, the multiple semiconductor chips 100A1, 100A2, 100A3 and 100C can effectively increase the integration of the multiple front pads 152 and the multiple rear pads 154. Since the integration of the multiple front pads 152 and the multiple rear pads 154 increases, the electrical paths (e.g., the paths through which at least one of the data signal, the control signal, the power supply signal and the ground signal passes) of the multiple semiconductor chips 100A1, 100A2, 100A3 and 100C can be increased. Therefore, semiconductor packages 500 and 500A can be more conducive to miniaturization and high performance. Alternatively, due to at least one of direct bonding DB1 and direct bonding DB2, electrical reliability (eg, impedance stability, reduction of equivalent series resistance, signal integrity, power integrity, etc.) between the plurality of front pads 152 and the plurality of rear pads 154 may be further improved.

[0056] Due to at least one of direct bonding DB1 and direct bonding DB2, the front and rear surfaces of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C can be in direct contact with each other, so that it may be more important to flatten the front and rear surfaces. Since the front and rear surfaces have a high flatness, the reliability between the plurality of front pads 152 and the plurality of rear pads 154 (e.g., poor contact or electrical short circuit prevention performance) and the reliability between the front insulating layer 162b and the rear insulating layer 164 (e.g., pore or crack prevention performance) can be improved.

[0057] The conductive pattern 147 may be disposed between the interconnect structure 140 and the plurality of front pads 152. The supporting insulating layer 162a may be disposed between the device layer 120 and the front insulating layer 162b to surround the conductive pattern 147 (disposed around the conductive pattern 147). The front surface (lower surface) and the rear surface (upper surface) of the conductive pattern 147 and the supporting insulating layer 162a may be coplanar with each other, respectively. The conductive pattern 347 and the supporting insulating layer 362 of the substrate structure 300 may be implemented in substantially the same manner as the conductive pattern 147 and the supporting insulating layer 162a.

[0058] When multiple front pads 152 are coupled to multiple rear pads 154 using an annealing process, not only multiple front pads 152 can be thermally expanded, but also conductive pattern 147 can be thermally expanded. The thermal expansion of conductive pattern 147 can support the thermal expansion of multiple front pads 152 relative to multiple rear pads 154. Therefore, multiple front pads 152 and multiple rear pads 154 can be more effectively coupled to each other. Since the coupling efficiency between multiple front pads 152 and multiple rear pads 154 becomes higher, the minimum volume required for multiple front pads 152 and multiple rear pads 154 can be further reduced. Therefore, the width or spacing of each of multiple front pads 152 and multiple rear pads 154 can be further refined, and the integration of the electrical paths of multiple semiconductor chips 100A1, 100A2, 100A3 and 100C can also be further increased.

[0059] The supporting insulating layer 162a may be implemented in the same manner as the front insulating layer 162b. For example, the supporting insulating layer 162a may include SiO 2 , SiN, SiCN, and tetraethoxysilane (TEOS). The conductive pattern 147 may be implemented in the same manner (using the same material and the same process) as the interconnection layer 142 of the interconnection structure 140. Therefore, the conductive pattern 147 may be the lowermost interconnection layer of the interconnection structure 140. For example, the conductive pattern 147 may include at least one of copper, a copper alloy, aluminum, and an aluminum alloy.

[0060] The thickness of the conductive pattern 147 may be greater than the thickness of each of the plurality of interconnection layers 142. The conductive pattern 147 having a thickness greater than the thickness of each of the plurality of interconnection layers 142 may have a relatively large volume. Since the conductive pattern 147 has a large volume, the thermal expansion of the plurality of front pads 152 relative to the plurality of rear pads 154 may be effectively and stably supported.

[0061] According to the design, the conductive pattern 147 may include a conductive material (e.g., aluminum) having a higher thermal expansion coefficient than the conductive material (e.g., copper) of the plurality of front pads 152. The thermal expansion coefficient of aluminum may be higher than the thermal expansion coefficient of copper, and thus, the conductive pattern 147 including aluminum may more effectively support the thermal expansion of the plurality of front pads 152 including copper.

[0062] The efficiency of the conductive pattern 147 in supporting the thermal expansion coupling between the plurality of front pads 152 and the plurality of rear pads 154 may be a trade-off with the flatness (or the importance of the flatness) of the front surfaces of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C. The semiconductor package 500 or 500A according to one or more example embodiments of the present disclosure may ensure one of the thermal expansion coupling support efficiency and the flatness (or the importance of the flatness) while improving the other.

[0063] refer to Figure 1 and Figure 3A , the conductive pattern 147 may include a plurality of pad patterns 147a electrically connected between the interconnection structure 140 and the plurality of front pads 152, and dummy patterns 147b and 147c spaced apart from the plurality of front pads 152 and the plurality of pad patterns 147a.

[0064] For example, the front surface (lower surface) and the rear surface (upper surface) of each of the plurality of pad patterns 147a may have a polygonal shape or a circular shape. The width (X1 or Y1) of each of the plurality of pad patterns 147a may be wider than the width of each of the plurality of front pads 152. Therefore, the plurality of pad patterns 147a may support the plurality of front pads 152 more stably.

[0065] For example, a portion (e.g., a central portion) of the front surface (lower surface) of the plurality of pad patterns 147a may be in direct contact with the plurality of front pads 152, and the other portion (e.g., an edge portion) of the front surface of the plurality of pad patterns 147a may be in direct contact with the front insulating layer 162b. Thus, the overall stacking stability of the combination 162 of the supporting insulating layer 162a and the front insulating layer 162b may be improved, thereby stably preventing delamination of the combination 162 from occurring.

[0066] The dummy patterns 147b and 147c can fill a portion of the peripheral space of the plurality of pad patterns 147a to prevent the metal material from being concentrated at a specific point (e.g., a plurality of pad patterns 147a) of the combination of the conductive pattern 147 and the supporting insulating layer 162a. Therefore, even when the conductive pattern 147 is thicker than the interconnect layer 142, the combination of the conductive pattern 147 and the supporting insulating layer 162a can be stably stacked on the front surface (lower surface) of the device layer 120, and the delamination of the combination can be stably prevented from occurring. That is, the dummy patterns 147b and 147c can improve the structural stability of the conductive pattern 147 and its periphery.

[0067] The dummy patterns 147b and 147c may be spaced apart from the plurality of pad patterns 147a and may not be connected to the plurality of front pads 152 and / or the interconnect structure 140. For example, the plurality of pad patterns 147a may be configured to send signals to or receive signals from the interconnect structure 140, and the dummy patterns 147b and 147c may have a ground or DC voltage. The dummy patterns 147b and 147c may surround the plurality of pad patterns 147a (arranged around the plurality of pad patterns 147a), thereby electromagnetically shielding the plurality of pad patterns 147a. In addition, the relatively large volume of the dummy patterns 147b and 147c may improve the electrical stability of the DC voltage or ground.

[0068] The total area of ​​the dummy patterns 147b and 147c (e.g., the area based on X1, X3, and Y3) may be greater than the total area of ​​the plurality of pad patterns 147a (e.g., the area based on X1 and Y1). Since the total area of ​​the dummy patterns 147b and 147c is increased, the dummy patterns 147b and 147c may further improve the structural stability of the conductive pattern 147 and its periphery (e.g., prevent delamination).

[0069] Generally, since the connectivity between a portion of the dummy patterns 147b and 147c (or the total number of dummy patterns relative to a unit area) increases, the total area of ​​the dummy patterns 147b and 147c can be increased more effectively. However, since the connectivity between a portion of the dummy patterns 147b and 147c (or the total number of dummy patterns relative to a unit area) increases, the impact of the thermal expansion of the dummy patterns 147b and 147c on the flatness (or the importance of flatness) of the front surfaces of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C may increase. Therefore, the structural stability (e.g., preventing delamination) of the conductive pattern 147 and its periphery may be a trade-off with flatness (or the importance of flatness). The semiconductor packages 500 and 500A according to one or more example embodiments of the present disclosure can ensure one of structural stability and flatness while improving the other.

[0070] refer to Figure 3A The dummy patterns 147b and 147c may include a plurality of first dummy patterns 147c and a plurality of second dummy patterns 147b, the plurality of first dummy patterns 147c being disposed between the plurality of pad patterns 147a to extend in a first direction (eg, Figure 3A in the horizontal X direction) but not in the second direction (e.g., Figure 3A The plurality of second dummy patterns 147b overlap with the plurality of pad patterns 147a in the vertical Y direction in the second direction (eg, Figure 3A ) but not in the first direction (e.g., Figure 3A The front surface ( X direction) of each of the plurality of first dummy patterns 147c overlaps with the plurality of pad patterns 147a. Figure 1 The center of the lower surface of the second dummy pattern 147b may be in direct contact with the front insulating layer 162b or the rear insulating layer 164, and the front surface ( Figure 1 The center of the lower surface in the middle may be in direct contact with the front insulating layer 162b or the rear insulating layer 164.

[0071] The plurality of first dummy patterns 147c and the plurality of second dummy patterns 147b may overlap the plurality of pad patterns 147a in the first direction and the second direction, respectively, so that the dummy patterns 147b and 147c may effectively prevent the metal material from being concentrated at a specific point (e.g., the plurality of pad patterns 147a) of the combination of the conductive pattern 147 and the supporting insulating layer 162a. Therefore, the structural stability of the conductive pattern 147 and its periphery may be effectively improved (e.g., preventing delamination).

[0072] The plurality of first dummy patterns 147c may thermally expand in the first direction, and the plurality of second dummy patterns 147b may thermally expand in the first direction and the second direction. In this case, the thermal expansion of the plurality of first dummy patterns 147c in the first direction and the thermal expansion of the plurality of second dummy patterns 147b in the first direction may converge between the plurality of first dummy patterns 147c and the plurality of second dummy patterns 147b. This convergence of thermal expansion may be from a direction perpendicular to the first direction and the second direction (e.g., Figure 1 The thermal expansion phenomenon in the vertical Z direction (in the vertical Z direction) is derived and may be a factor that disturbs the flatness of the front surfaces of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C.

[0073] The plurality of second dummy patterns 147b may be spaced apart from the plurality of first dummy patterns 147c. Therefore, the space between the plurality of first dummy patterns 147c and the plurality of second dummy patterns 147b may be a spare space for preventing the convergence of thermal expansion as a factor interfering with the flatness. Therefore, the flatness of the front surfaces of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C may be stably ensured.

[0074] Alternatively, the plurality of first dummy patterns 147c may be arranged in the second direction (eg, Figure 3A , and may extend in a first direction (eg, a vertical Y direction) between two adjacent pad patterns among the plurality of pad patterns 147a. Figure 3A For example, when the first direction (e.g., Figure 3A When six pad patterns 147a are arranged in the horizontal X direction (in the horizontal X direction), two or more first dummy patterns 147c may be provided in each space between the six pad patterns 147a, and a total of ten or more dummy patterns 147c may be provided.

[0075] The space SL1 between the plurality of first dummy patterns 147c in the space between two adjacent pad patterns among the plurality of pad patterns 147a may be a spare space to prevent the convergence of thermal expansion as a factor disturbing the flatness. Therefore, the flatness of the front surfaces of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C may be stably ensured.

[0076] Alternatively, the dummy patterns 147b and 147c may include each having an extension direction (eg, Figure 3A A plurality of dummy patterns 147b and 147c are provided in a form that is not bent or extended (in the vertical Y direction), and the plurality of dummy patterns 147b and 147c are arranged to surround each of the plurality of pad patterns 147a (arranged around each of the plurality of pad patterns 147a).

[0077] A plurality of dummy patterns 147b and 147c may surround each of the plurality of pad patterns 147a (be disposed around each of the plurality of pad patterns 147a) so that a portion of the space around the plurality of pad patterns 147a may be effectively filled, thereby effectively improving the structural stability of the conductive pattern 147 and its periphery (e.g., preventing delamination).

[0078] Extension direction (e.g. Figure 3A The bending form in the vertical Y direction) can be in the extension direction (for example, Figure 3A The thermal expansion convergence is caused at the point of bending (in the vertical Y direction in the first direction), and the thermal expansion convergence can be from a direction perpendicular to the first direction and the second direction (for example, Figure 1 Each of the plurality of dummy patterns 147b and 147c may have an extension direction (eg, Figure 3A The vertical Y direction in the middle (in the vertical Y direction) is not bent or extended, thereby preventing the thermal expansion from converging at the point where the extension direction is bent. Therefore, the flatness of the front surfaces of the plurality of semiconductor chips 100A1, 100A2, 100A3 and 100C can be stably ensured.

[0079] For example, each of the plurality of first dummy patterns 147c may be arranged in the second direction (eg, Figure 3A , and a portion of each of the plurality of first dummy patterns 147c may extend in the first direction (eg, the vertical Y direction). Figure 3AThe conductive pattern 147a is overlapped with the plurality of second dummy patterns 147b in the horizontal X direction ...

[0080] For example, each of the plurality of second dummy patterns 147b may have the same shape as that of each of the plurality of pad patterns 147a, and n second dummy patterns 147b and n pad patterns 147a (eg, n=1) may be arranged in the second direction (eg, Figure 3A Therefore, the structural stability of the space in which the plurality of second dummy patterns 147b and the plurality of pad patterns 147a are alternately arranged can be effectively improved.

[0081] In terms of the entire dummy patterns 147b and 147c, the plurality of first dummy patterns 147c may have a continental shape, and the plurality of second dummy patterns 147b may have an island shape. For example, the gap X2 between the plurality of first dummy patterns 147c and the plurality of second dummy patterns 147b may be longer than the gap Y2 between the plurality of second dummy patterns 147b and the plurality of pad patterns 147a, and may be longer than the gap X4 between the plurality of first dummy patterns 147c. For example, the width X3 of each of the plurality of first dummy patterns 147c may be longer than the gaps X2 and X4. For example, the width X1 and Y3 of each of the plurality of second dummy patterns 147b and the width X1 and Y1 of each of the plurality of pad patterns 147a may be longer than the width X3 of each of the plurality of first dummy patterns 147c. Here, the widths X1, Y1, and Y3 may be measured in the first direction or the second direction relative to the center of each corresponding pattern.

[0082] Each of X1, X2, X3, X4, Y1, Y2, and Y3 may be measured as an average value in a horizontal cross section of the semiconductor package and may be applied to analysis using at least one of a transmission electron microscope (TEM), an atomic force microscope (AFM), a scanning electron microscope (SEM), an optical microscope, and a surface profiler. Each of X1, X2, X3, X4, Y1, Y2, and Y3 may be measured using visual inspection or image processing (e.g., identifying pixels based on their color or brightness, filtering pixel values ​​for pixel identification efficiency, integrating distances between identified pixels, etc.).

[0083] The structure of the conductive pattern 147 of the semiconductor package 500 according to one or more example embodiments of the present disclosure is not limited to Figure 3AThe structure of the conductive pattern 147 is shown and may be FIG. 3B to FIG. 4E One or a combination of various structures of the conductive pattern 147 shown. Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 4A and Figure 4E The dummy patterns 147b and 147c may include a plurality of first dummy patterns 147c and a plurality of second dummy patterns 147b, the plurality of first dummy patterns 147c being disposed between the plurality of pad patterns 147a to extend in a first direction (eg, Figure 3A in the horizontal X direction) but not in the second direction (e.g., Figure 3A The plurality of second dummy patterns 147b overlap with the plurality of pad patterns 147a in the vertical Y direction in the second direction (eg, Figure 3A ) but not in the first direction (e.g., Figure 3A The plurality of second dummy patterns 147b may overlap with the plurality of pad patterns 147a in the horizontal X direction (in the horizontal X direction). The plurality of second dummy patterns 147b may be spaced apart from the plurality of first dummy patterns 147c.

[0084] In addition, reference Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 4B , Figure 4C , Figure 4D and Figure 4E , the plurality of first dummy patterns 147c may be arranged in the second direction (eg, Figure 3A , and may extend in a first direction (eg, a vertical Y direction) between two adjacent pad patterns among the plurality of pad patterns 147a. Figure 3A The horizontal X direction in the figure is spaced apart from each other. Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 4A and Figure 4E , the dummy patterns 147b and 147c may include each having an extension direction (eg, Figure 3A A plurality of dummy patterns 147b and 147c are provided in a form that is not bent or extended (in the vertical Y direction), and the plurality of dummy patterns 147b and 147c are arranged to surround each of the plurality of pad patterns 147a (arranged around each of the plurality of pad patterns 147a).

[0085] refer to Figure 3B , the semiconductor package 500B according to one or more example embodiments of the present disclosure may have a structure in which some of the plurality of first dummy patterns 147c overlap each other in the second direction (e.g., the vertical direction). The plurality of first dummy patterns 147c may together have a space SL1 in the first direction and a space SL2 in the second direction. The number of spaces SL2 in the second direction is not limited to Figure 3B The structure shown in FIG. 1 , and the area of ​​each of the plurality of first dummy patterns 147 c may be adjusted by adjusting the number of spaces SL2 in the second direction.

[0086] refer to FIG. 3C to FIG. 3F , the semiconductor packages 500C, 500D, 500E, and 500F according to one or more example embodiments of the present disclosure may have a structure in which the shape of each of the plurality of second dummy patterns 147b is different from the shape of each of the plurality of pad patterns 147a (eg, a polygonal shape). Figure 3C , the shape of each of the plurality of second dummy patterns 147 b may be a circular shape.

[0087] refer to Figures 3D to 3F , the semiconductor packages 500D, 500E, and 500F according to one or more example embodiments of the present disclosure may have a structure in which the area of ​​each of the plurality of second dummy patterns 147b is smaller than the area of ​​each of the plurality of pad patterns 147a, and a structure in which some of the plurality of second dummy patterns 147b are spaced apart from each other between two adjacent pad patterns among the plurality of pad patterns 147a. Figure 3D , the plurality of second dummy patterns 147b may be spaced apart from each other in the first direction (eg, horizontal direction), may extend in the second direction (eg, vertical direction), and may have a space SL3 between the plurality of second dummy patterns 147b. Figure 3E , the plurality of second dummy patterns 147b may be spaced apart from each other in the second direction (eg, vertical direction), may extend in the first direction (eg, horizontal direction), and may have a space SL4 between the plurality of second dummy patterns 147b. Figure 3F , the plurality of second dummy patterns 147 b may be spaced apart from each other in the first direction and the second direction (eg, the horizontal direction and the vertical direction), and may have spaces SL3 and SL4 therebetween.

[0088] refer to Figure 4A, the plurality of first dummy patterns 147c of the semiconductor package 500G according to one or more example embodiments of the present disclosure may extend in the second direction (e.g., the vertical direction), and may be implemented as one pad pattern between two adjacent pad patterns among the plurality of pad patterns 147a. Therefore, the plurality of first dummy patterns 147c may each have a wider width X5, but may be spaced apart from the plurality of second dummy patterns 147b in the first direction (e.g., the horizontal direction).

[0089] refer to FIG. 4B to FIG. 4D , the plurality of first dummy patterns 147c of the semiconductor packages 500H, 500I, and 500J according to one or more example embodiments of the present disclosure may overlap with the plurality of pad patterns 147a in the first direction and the second direction (e.g., the horizontal direction and the vertical direction). Here, the plurality of first dummy patterns 147c may extend in the second direction (e.g., the vertical direction), and may be spaced apart from each other along the first direction (e.g., the horizontal direction) between two adjacent pad patterns among the plurality of pad patterns 147a. The space SL1 between the plurality of first dummy patterns 147c may be a spare space for reducing the influence of the thermal expansion of the conductive pattern 147 on the flatness of the front surface of the plurality of semiconductor chips.

[0090] refer to Figure 4B and Figure 4C , the plurality of second dummy patterns 147b may overlap the plurality of pad patterns 147a in the first direction (eg, horizontal direction) but not in the second direction (eg, vertical direction). Figure 4D , the conductive pattern 147 may not include a plurality of second dummy patterns.

[0091] refer to Figure 4E , the plurality of second dummy patterns 147b of the semiconductor package 500K according to one or more example embodiments of the present disclosure may have different shapes. For example, as the distance from the center of the semiconductor package 500K decreases, the plurality of second dummy patterns 147b may have a more finely divided structure, and as the distance from the edge of the semiconductor package 500K decreases, each of the plurality of second dummy patterns 147b may have a larger area.

[0092] Figure 5A and Figure 5B An enlarged portion of semiconductor packages 500L and 500M according to one or more example embodiments of the present disclosure is shown, and the portion may correspond to Figure 1 Part B, but can also be implemented in Figure 1 in section A.

[0093] refer to Figure 5A, the semiconductor package 500L according to one or more example embodiments of the present disclosure may have a structure in which the Figure 2B The rear pad 154 may have a structure in which the front pad 152 and the through electrode 130 are in direct contact with each other. FIG. 3A to FIG. 4E The illustrated conductive pattern 147 may support a direct bond DB1 between the front pad 152 and the through electrode 130 , and may ensure flatness between the front pad 152 and the through electrode 130 .

[0094] refer to Figure 5B , the semiconductor package 500M according to one or more example embodiments of the present disclosure may have the Figure 2B The structure of the front pad 152 may be formed by the plurality of pad patterns 147a of the conductive pattern 147, and the plurality of rear pads 154 may be in direct contact with each other. For example, the areas of the plurality of pad patterns 147a may be adjusted to correspond to the areas of the plurality of rear pads 154, and the conductive material (e.g., copper) included in the plurality of pad patterns 147a may also correspond to the conductive material (e.g., copper) included in the plurality of rear pads 154. The plurality of pad patterns 147a may be surrounded by a combination 162 of a supporting insulating layer and a front insulating layer, and the supporting insulating layer may be omitted from the combination 162. FIG. 3A to FIG. 4E The conductive pattern 147 shown may improve the stability of the direct bonding DB1 between the plurality of pad patterns 147 a and the plurality of rear pads 154 , and may ensure the flatness between the plurality of pad patterns 147 a and the plurality of rear pads 154 .

[0095] refer to Figure 1 , a semiconductor package 500 according to one or more example embodiments of the present disclosure may include an upper dummy chip 200 disposed on a rear surface (upper surface) of a semiconductor chip 100C. For example, the upper dummy chip 200 may include a semiconductor such as silicon or a substrate such as metal. In some example embodiments, the upper dummy chip 200 may provide a heat dissipation function and / or an identification mark display area.

[0096] The upper dummy chip 200 may have a thickness T2 greater than the thickness T1a of the plurality of semiconductor chips 100A1, 100A2, and 100A3 and the thickness T1b of the semiconductor chip 100C. For example, the thickness T2 of the upper dummy chip 200 may be 200 μm or more, and the thicknesses T1a and T1b may be 100 μm or less.

[0097] The upper dummy chip 200 may include a lower bonding insulating layer 210 disposed on the lower surface of the upper dummy chip 200, and the semiconductor chip 100C may include a rear insulating layer 174 disposed on the upper surface of the semiconductor chip 100C. The lower bonding insulating layer 210 and the rear insulating layer 174 may be directly bonded to each other so that the upper dummy chip 200 may be bonded to the rear surface (upper surface) of the semiconductor chip 100C. Therefore, the upper dummy chip 200 and the semiconductor chip 100C may be bonded to each other through the dielectric inter-bonding between the lower bonding insulating layer 210 and the rear insulating layer 174. At least one of the lower bonding insulating layer 210 and the rear insulating layer 174 may include a dielectric layer formed using a deposition process. Alternatively, at least one of the lower bonding insulating layer 210 and the rear insulating layer 174 may include a natural oxide film formed using a high temperature annealing process.

[0098] The width W2 (ie, area) of the upper dummy chip 200 may be the same as the width W1a (ie, area) of the plurality of semiconductor chips 100A1 , 100A2 , and 100A3 , and may be the same as the width W1b (ie, area) of the semiconductor chip 100C, but the present disclosure is not limited thereto.

[0099] refer to Figure 1 , a semiconductor package 500 according to one or more example embodiments of the present disclosure may include a molding portion 180 that seals a plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C and an upper dummy chip 200. For example, the molding portion 180 may include an epoxy molding compound (EMC) or the like.

[0100] The upper surface 200T of the upper dummy chip 200 may be exposed to the upper surface 180T of the molding portion 180. The exposed upper surface 200T of the upper dummy chip 200 may be substantially coplanar with the upper surface 180T of the molding portion 180. The coplanar upper surfaces may be understood as upper surfaces obtained using a polishing process. In addition, the side surface of the molding portion 180 may be substantially coplanar with the side surface of the substrate structure 300. The coplanar side surfaces may be understood as side surfaces obtained using the same cutting process.

[0101] refer to FIG. 6A to FIG. 6E The method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure may include operations of forming a device layer 120 , a semiconductor substrate 110 , a rear insulating layer 164 , and a plurality of rear pads 154 .

[0102] refer to Fig. 6A, a semiconductor substrate 110 for a plurality of semiconductor chips 100A may be bonded to a carrier substrate 600. For ease of description, the semiconductor substrate 110 is shown as a wafer including three semiconductor chips 100A. Individual elements may form a plurality of semiconductor chips on the active surface of the semiconductor substrate 110. In addition, the through electrode 130 extends into the semiconductor substrate 110, and the device layer 120 is connected to the through electrode 130 and formed on the active surface of the semiconductor substrate 110. Therefore, it can be understood that the semiconductor substrate 110 is in a state where the back process is not performed after the front process of the semiconductor chip is completed. That is, the semiconductor substrate 110 may be in a state where the grinding process is not applied, and therefore, the semiconductor substrate 110 may have a relatively large first thickness T0. The front surface (lower surface) of the semiconductor substrate 110 (i.e., the surface where the device layer is formed) may be bonded to be opposite to the carrier substrate 600. Such bonding may be achieved using an adhesive layer 610 such as a UV curable film.

[0103] refer to Figure 6B , a grinding process may be applied to the non-active surface of the semiconductor substrate 110 so that the thickness of the semiconductor substrate 110 is reduced from T0 to Ta. In the grinding process, the upper end 130T of the through electrode 130 may be exposed from the ground surface of the semiconductor wafer. Due to the difference in etching rate, the semiconductor wafer 100 may protrude from the surface. The thickness of the semiconductor chip 100A may be reduced to a desired thickness Ta using this process. This thickness reduction process may be performed using a post-etching process other than a grinding process such as a chemical mechanical polishing (CMP) process or a combination thereof. In some example embodiments, a grinding process may be performed to reduce the thickness of the semiconductor substrate 110, and the post-etching process may be performed under appropriate conditions to fully expose the through electrode 130.

[0104] refer to Figure 6C , a first insulating film 164a may be formed on the semiconductor substrate 110 to cover the exposed upper end 130T of the through electrode 130. The first insulating film 164a may serve as a passivation layer. For example, the first insulating film 164a may include silicon nitride or silicon nitride oxide.

[0105] refer to Fig.6D , the first insulating film 164a may be ground to expose the through electrode 130. The grinding process may be performed up to the predetermined line GL so that the first insulating film 164a is partially removed and the through electrode 130 is sufficiently exposed. Using the grinding process, the first insulating film 164a may have an upper surface substantially flat with an upper surface of the through electrode 130. In addition, a damaged portion of the upper end 130T of the through electrode 130 may also be removed.

[0106] refer to Fig. 6E, a plurality of rear pads 154 and a second insulating film 164b surrounding the plurality of rear pads 154 (arranged around the plurality of rear pads 154) may be formed on the first insulating film 164a. In a manner similar to the above process, a plurality of rear pads 154 may be formed on the first insulating film 164a, and the second insulating film 164b may be formed to cover the plurality of rear pads 154. Subsequently, a grinding process may be performed so that the second insulating film 164b is partially removed to expose the rear surface (upper surface) of the plurality of rear pads 154. Using the grinding process, the second insulating film 164b may have a rear surface (upper surface) that is substantially flat with the rear surface (upper surface) of the plurality of rear pads 154. For example, the second insulating film 164b may include silicon oxide. As used herein, the first insulating film 164a and the second insulating film 164b are collectively referred to as the rear insulating layer 164.

[0107] refer to Fig. 6F The method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure may include an operation of forming a conductive pattern 147 on a front surface (lower surface) of a device layer 120 of at least one semiconductor chip 100A1 among a plurality of semiconductor chips. For example, the conductive pattern 147 may be formed using photolithography. Fig. 6F The conductive pattern 147 is shown to be formed after forming the semiconductor substrate 110, the rear insulating layer 164, and the plurality of rear pads 154. However, according to the design, the conductive pattern 147 may also be formed together with the device layer 120. This is because the conductive pattern 147 may be a part of the interconnect structure 140 of the device layer 120. That is, the operation of forming the conductive pattern 147 on the front surface (lower surface) of the device layer 120 of at least one semiconductor chip 100A1 among the plurality of semiconductor chips may be a part of the operation of forming the device layer 120.

[0108] refer to Figure 6G , the method of manufacturing a semiconductor package according to one or more example embodiments of the present disclosure may include an operation of forming a plurality of front pads 152 by forming a combination 162 of a supporting insulating layer 162a and a front insulating layer 162b. For example, the operation may also include an operation of planarizing the front surface (lower surface) of the supporting insulating layer 162a after forming the supporting insulating layer 162a, and the front insulating layer 162b may be formed after planarizing the supporting insulating layer 162a. For example, the operation may also include an operation of forming a hole in the front insulating layer 162b, and the plurality of front pads 152 may be formed to fill the hole. Depending on the design, the operation may also be performed before forming the semiconductor substrate 110, the rear insulating layer 164, and the plurality of rear pads 154.

[0109] refer to FIG. 7A to FIG. 7D, a method for manufacturing a semiconductor package according to one or more example embodiments of the present disclosure may include the following operations: directly bonding a combination 162 of a supporting insulating layer 162a and a front insulating layer 162b of one of a plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C to a rear insulating layer 164 of another of the plurality of semiconductor chips 100A1, 100A2, 100A3, and 100C.

[0110] refer to Fig. 7A , a substrate structure 300 having an upper connection pad 354 and a lower connection pad 352 can be prepared. For ease of description, the substrate structure 300 is shown to be in the form of a three-semiconductor package. The substrate structure 300 may include an upper bonding insulating layer 364 surrounding the upper connection pad 354 (arranged around the upper connection pad 354) on the upper surface of the substrate structure 300. The upper bonding insulating layer 364 may have an upper surface substantially coplanar with the upper surface of the upper connection pad 354. A connection bump 370 such as a solder ball may be formed on the lower connection pad 352 of the substrate structure 300. In addition, in the present exemplary embodiment, the substrate structure 300 is shown to be in the form of a logic chip or a memory chip that electrically connects the upper connection pad 354 and the lower connection pad 352. However, according to the design, the substrate structure 300 may be an interposer with an internal circuit.

[0111] refer to Figure 7B , individualized semiconductor chips 100A1 may be disposed on the substrate structure 300. The semiconductor chips 100A1 may be Figure 6G The semiconductor chip obtained in the operation shown. In this stacking process, pre-bonding can be performed by applying a specific pressure using a bonding tool BT. Specifically, each of the plurality of front pads 152 of the first semiconductor chip 100A1 can be directly pre-bonded to the upper connection pad 354 of the substrate structure 300. Similarly, the front insulating layer 162 of the semiconductor chip 100A1 can be directly pre-bonded to the upper bonding insulating layer 364 of the substrate structure 300.

[0112] refer to Figure 7C, additional semiconductor chips 100A2 and 100A3 may be sequentially stacked, and a semiconductor chip 100C may be disposed on the uppermost semiconductor chip 100A3. A plurality of semiconductor chips 100A2, 100A3, and 100C may be pre-bonded to other semiconductor chips 100A1, 100A2, and 100A3 located therebelow. Specifically, a plurality of front pads 152 and a front insulating layer 162 of each of the semiconductor chips 100A2, 100A3, and 100C may be pre-bonded directly to a plurality of rear pads 154 and a rear insulating layer 164 of each of the other semiconductor chips 100A1, 100A2, and 100A3 stacked immediately before them, respectively. Thereafter, an annealing process may be performed, the front insulating layer 162 and the rear insulating layer 164 may be directly bonded to each other, and a plurality of front pads 152 and a plurality of rear pads 154 may be directly bonded to each other. Thereafter, the upper dummy chip 200 may be disposed on the rear surface (upper surface) of the semiconductor chip 100C, and the rear surface (upper surface) of the upper dummy chip 200 may be polished.

[0113] refer to Fig.7D , can cut in vertical direction Figure 7C The semiconductor package shown. Therefore, a plurality of semiconductor packages may be formed. According to the design, the rear surface (upper surface) of the upper dummy chip 200 may include an identification mark or provide a space for arranging a heat sink.

[0114] As described above, the semiconductor package according to one or more example embodiments of the present disclosure can improve the electrical characteristics and / or reliability of the front surface of the semiconductor chip. For example, the semiconductor package can increase the integration of the electrical connection path (e.g., pad) between multiple semiconductor chips or can improve the electrical characteristics (e.g., signal integrity) of the electrical connection path (e.g., pad), and can improve the reliability (e.g., surface flatness, structural stability of the layer, and delamination prevention performance) between multiple semiconductor chips.

[0115] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: a plurality of semiconductor chips, each of the plurality of semiconductor chips comprising at least one of a front insulating layer and a rear insulating layer, adjacent semiconductor chips of the plurality of semiconductor chips being bonded to each other by direct bonding between the front insulating layer of a first semiconductor chip of the adjacent semiconductor chips and the rear insulating layer of a second semiconductor chip of the adjacent semiconductor chips, Wherein, at least one semiconductor chip among the plurality of semiconductor chips comprises: device layers, including interconnect structures; and a conductive pattern, on the front surface of the device layer, Wherein, the conductive pattern comprises: a plurality of pad patterns electrically connected to the interconnect structure; and a dummy pattern spaced apart from the plurality of pad patterns, Wherein, the dummy pattern includes: a plurality of first dummy patterns between the plurality of pad patterns and not overlapping the plurality of pad patterns in the first direction and in the second direction; and A plurality of second dummy patterns are between the plurality of first dummy patterns and do not overlap the plurality of pad patterns in the second direction and in the first direction, wherein the plurality of second dummy patterns are spaced apart from the plurality of first dummy patterns.

2. The semiconductor package according to claim 1, wherein The at least one semiconductor chip among the plurality of semiconductor chips further comprises: a plurality of front pads connected to the front surfaces of the plurality of pad patterns; the front insulating layer surrounding the plurality of front pads; and A supporting insulating layer is between the device layer and the front insulating layer and around the conductive pattern.

3. The semiconductor package according to claim 2, wherein: The at least one semiconductor chip among the plurality of semiconductor chips further comprises: Semiconductor substrate; A through electrode passing through the semiconductor substrate; The rear insulating layer is disposed on the rear surface of the semiconductor substrate; and a plurality of rear pads electrically connected to the through-electrodes, the rear insulating layer surrounding the plurality of rear pads, and Wherein, adjacent semiconductor chips among the plurality of semiconductor chips are electrically connected to each other through direct bonding between a plurality of front pads of a first semiconductor chip among the adjacent semiconductor chips and a plurality of rear pads of a second semiconductor chip among the adjacent semiconductor chips.

4. The semiconductor package according to claim 3, wherein: Each of the front insulating layer, the supporting insulating layer, and the rear insulating layer includes at least one of SiO 2 , SiN, SiCN, or tetraethoxysilane TEOS.

5. The semiconductor package according to claim 4, in, Each of the plurality of front pads includes copper or a copper alloy, and Wherein, the conductive pattern includes at least one of copper, copper alloy, aluminum or aluminum alloy.

6. The semiconductor package according to claim 5, wherein: Central portions of the front surfaces of the plurality of pad patterns directly contact the plurality of front pads, and Wherein, edge portions of the front surfaces of the plurality of pad patterns directly contact the front insulating layer.

7. The semiconductor package according to claim 2, wherein: The conductive pattern includes a first conductive material having a first thermal expansion coefficient, and each of the plurality of front pads includes a conductive material having a second thermal expansion coefficient lower than the first thermal expansion coefficient.

8. The semiconductor package according to claim 1, wherein The interconnect structure includes at least one interconnect layer and interconnect vias, and Wherein, the thickness of the conductive pattern is greater than the thickness of each of the at least one interconnection layer.

9. The semiconductor package according to claim 1, wherein: A total area of ​​the dummy patterns is greater than a total area of ​​the plurality of pad patterns.

10. The semiconductor package according to claim 1, wherein A center of a front surface of each of the plurality of first dummy patterns directly contacts the front insulating layer or the rear insulating layer, and Wherein, a center of a front surface of each of the plurality of second dummy patterns directly contacts the front insulating layer or the rear insulating layer.

11. The semiconductor package according to claim 1, wherein Each of the plurality of first dummy patterns extends in the second direction, and A portion of each of the plurality of first dummy patterns overlaps with the plurality of second dummy patterns in the first direction.

12. A semiconductor package, comprising: a plurality of semiconductor chips, each of the plurality of semiconductor chips comprising at least one of a front insulating layer and a rear insulating layer, adjacent semiconductor chips of the plurality of semiconductor chips being bonded to each other by direct bonding between the front insulating layer of a first semiconductor chip of the adjacent semiconductor chips and the rear insulating layer of a second semiconductor chip of the adjacent semiconductor chips, Wherein, at least one semiconductor chip among the plurality of semiconductor chips comprises: Multiple front pads; the front insulating layer around each of the plurality of front pads; a device layer, on a rear surface of the front insulating layer, the device layer comprising an interconnect structure electrically connected to the plurality of front pads; a supporting insulating layer between the device layer and the front insulating layer; and a conductive pattern between the interconnect structure and the plurality of front pads and around the conductive pattern, Wherein, the conductive pattern comprises: a plurality of pad patterns electrically connected between the interconnect structure and the plurality of front pads; and a dummy pattern spaced apart from the plurality of front pads and the plurality of pad patterns, wherein the dummy pattern comprises a plurality of first dummy patterns extending along the second direction between the plurality of pad patterns, and the plurality of first dummy patterns overlap the plurality of pad patterns in the first direction, and The plurality of first dummy patterns are spaced apart from each other along the first direction between two adjacent pad patterns among the plurality of pad patterns.

13. The semiconductor package according to claim 12, wherein: The plurality of front pads are connected to front surfaces of the plurality of pad patterns, Wherein, the at least one semiconductor chip among the plurality of semiconductor chips further comprises: Semiconductor substrate; A through electrode passing through the semiconductor substrate; The rear insulating layer is on the rear surface of the semiconductor substrate; and a plurality of rear pads electrically connected to the through-electrodes, the rear insulating layer surrounding the plurality of rear pads, and Wherein, the adjacent semiconductor chips are electrically connected to each other through direct bonding between the plurality of front pads and the plurality of rear pads.

14. The semiconductor package according to claim 12, wherein: A center of a front surface of each of the plurality of first dummy patterns directly contacts the front insulating layer or the rear insulating layer, wherein the plurality of pad patterns are configured to send signals to or receive signals from the interconnect structure, and The plurality of first dummy patterns are configured to have a ground or DC voltage.

15. The semiconductor package according to claim 12, wherein: The interconnect structure comprises at least one interconnect layer and interconnect vias, wherein the thickness of the conductive pattern is greater than the thickness of the at least one interconnect layer, and Wherein, the total area of ​​the dummy patterns is greater than the total area of ​​the plurality of pad patterns.

16. A semiconductor package, comprising: Semiconductor chips, including: front insulation layer; A plurality of front pads surrounded by the front insulating layer; a device layer on the rear surface of the front insulating layer and comprising an interconnect structure electrically connected to the plurality of front pads; a conductive pattern between the interconnect structure and the plurality of front pads; a supporting insulating layer between the device layer and the front insulating layer and around the conductive pattern; A semiconductor substrate, on the rear surface of the device layer; a through electrode passing through the semiconductor substrate; and a rear insulating layer, on the rear surface of the semiconductor substrate, Wherein, the conductive pattern comprises: a plurality of pad patterns electrically connected between the interconnect structure and the plurality of front pads; and a dummy pattern spaced apart from the plurality of front pads and the plurality of pad patterns, and The dummy pattern includes a plurality of dummy patterns arranged around the plurality of pad patterns, and each of the plurality of dummy patterns extends in a non-bending extending direction.

17. The semiconductor package according to claim 16, wherein: a first dummy pattern among the plurality of dummy patterns overlaps the plurality of pad patterns in a first direction, wherein a second dummy pattern among the plurality of dummy patterns overlaps the plurality of pad patterns in a second direction different from the first direction, and Wherein, the second dummy pattern is spaced apart from the first dummy pattern.

18. The semiconductor package according to claim 17, wherein: Each of the first dummy patterns extends in the second direction, wherein a portion of each of the first dummy patterns overlaps with the second dummy pattern in the first direction, wherein each of the second dummy patterns has the same shape as that of each of the plurality of pad patterns, and Wherein, the second dummy patterns and the plurality of pad patterns are alternately arranged in the second direction.

19. The semiconductor package according to claim 16, wherein: The interconnect structure comprises at least one interconnect layer and interconnect vias, wherein the thickness of the conductive pattern is greater than the thickness of each of the at least one interconnect layer, and Wherein, the total area of ​​the dummy patterns is greater than the total area of ​​the plurality of pad patterns.

20. The semiconductor package according to claim 16, wherein Each of the front insulating layer, the supporting insulating layer and the rear insulating layer comprises at least one of SiO2, SiN, SiCN or tetraethoxysilane TEOS, wherein the plurality of front pads comprise copper or a copper alloy, and Wherein, the conductive pattern includes at least one of copper, copper alloy, aluminum or aluminum alloy.

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