Semiconductor packaging structure with improved heat dissipation performance and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor packaging structure capable of improving heat dissipation performance and a manufacturing method of the semiconductor packaging structure, and belongs to the technical field of semiconductor packaging. The semiconductor packaging structure comprises a lead frame, a conductive bonding layer and a semiconductor chip, the first surface of the lead frame is provided with a groove, and the conductive bonding layer is located on the bottom surface of the groove and the side wall of the groove; the semiconductor chip is located in the groove, and the bottom surface of the semiconductor chip and the side wall of the semiconductor chip are connected with the lead frame through the conductive bonding layer. According to the embodiment of the invention, the heat dissipation performance of the semiconductor packaging structure can be improved, and the reliability of the semiconductor packaging structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure with improved heat dissipation performance and a manufacturing method thereof. Background Art

[0002] With the development of electronic technology, consumers have higher and higher requirements for electronic products, and more and more functions are integrated into electronic products. In order to meet the development requirements of high integration and miniaturization, semiconductor chips are packaged to form semiconductor packaging structures.

[0003] In the related art, a semiconductor packaging structure includes a lead frame, a conductive adhesive layer and a semiconductor chip, wherein the surface of the lead frame is a plane, the conductive adhesive layer is located on the surface of the lead frame, and the bottom surface of the semiconductor chip is connected to the lead frame through the conductive adhesive layer.

[0004] However, during the use of the semiconductor packaging structure, the semiconductor chip will continuously generate heat. In the semiconductor packaging structure, only the bottom surface of the semiconductor chip is connected to the lead frame through the conductive adhesive layer. The contact area between the semiconductor chip and the conductive adhesive layer is small. The heat of the semiconductor chip will be difficult to dissipate to the outside. The heat dissipation performance of the semiconductor packaging structure is poor, which affects the reliability of the semiconductor packaging structure. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor packaging structure with improved heat dissipation performance and a manufacturing method thereof, which can improve the heat dissipation performance of the semiconductor packaging structure and improve the reliability of the semiconductor packaging structure. The technical solution is as follows:

[0006] On the one hand, a semiconductor packaging structure is provided, including a lead frame, a conductive adhesive layer and a semiconductor chip, wherein the first surface of the lead frame has a groove, and the conductive adhesive layer is located on the bottom surface and the side wall of the groove; the semiconductor chip is located in the groove, and the bottom surface and the side wall of the semiconductor chip are connected to the lead frame through the conductive adhesive layer.

[0007] Optionally, in a direction perpendicular to the first surface, a depth of the groove is less than a sum of a thickness of the conductive adhesive layer and a thickness of the semiconductor chip.

[0008] Optionally, a ratio of the depth of the groove to the maximum thickness of the lead frame is 0.5 to 0.75.

[0009] Optionally, the conductive adhesive layer has a first portion, which is located between the side wall of the groove and the side wall of the semiconductor chip, and in a direction perpendicular to the first surface, the distance between the surface of the first portion away from the bottom surface of the groove and the bottom surface of the semiconductor chip is in a ratio of 0.5 to 0.75 to the thickness of the semiconductor chip.

[0010] Optionally, the semiconductor packaging structure further includes an insulating thermally conductive layer, which is located at least on a surface of the semiconductor chip away from the lead frame and a side wall of the semiconductor chip, and contacts at least one of the conductive adhesive layer and the first surface of the lead frame.

[0011] Optionally, the insulating heat-conducting layer is also located on the first surface of the periphery of the semiconductor chip.

[0012] Optionally, the conductive adhesive layer is made of metal solder or conductive glue.

[0013] Optionally, the semiconductor packaging structure further includes a packaging layer, wherein the packaging layer is located at least on the first surface of the lead frame, the surface of the semiconductor chip away from the lead frame, and the sidewall of the semiconductor chip, and covers the semiconductor chip.

[0014] Optionally, the lead frame includes a base island and a plurality of pins, the first surface includes the surface of the base island, and the plurality of pins are arranged at intervals on the periphery of the base island; the semiconductor packaging structure also includes a plurality of connecting wires, the semiconductor chip is electrically connected to the pins through the connecting wires, and each of the pins is connected to at least one of the connecting wires.

[0015] On the other hand, a method for manufacturing a semiconductor packaging structure is provided, comprising: providing a lead frame and a semiconductor chip, wherein the first surface of the lead frame has a groove; connecting the lead frame and the semiconductor chip through a conductive adhesive layer to obtain the semiconductor packaging structure, wherein the conductive adhesive layer is located on the bottom surface of the groove and the side wall of the groove, the semiconductor chip is located in the groove, and the bottom surface of the semiconductor chip and the side wall of the semiconductor chip are both connected to the lead frame through the conductive adhesive layer.

[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0017] In the disclosed embodiment, a groove is provided on the first surface of the lead frame, and a conductive adhesive layer is provided on the bottom surface and the side wall of the groove, the semiconductor chip is located in the groove, and the bottom surface and the side wall of the semiconductor chip are connected to the lead frame through the conductive adhesive layer. In this way, compared with only the bottom surface of the semiconductor chip being connected to the lead frame through the conductive adhesive layer, the contact area between the semiconductor chip and the conductive adhesive layer is increased. During the use of the semiconductor packaging structure, the heat generated by the semiconductor chip can be conducted to the lead frame through the conductive adhesive layer located on the bottom surface and the side wall of the groove and then dissipated to the outside, thereby improving the heat dissipation performance of the semiconductor packaging structure and improving the reliability of the semiconductor packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a structural schematic diagram of a semiconductor packaging structure in the related art;

[0020] Figure 2 is a structural schematic diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0021] Figure 3 is a structural schematic diagram of another semiconductor packaging structure provided by an embodiment of the present disclosure;

[0022] Figure 4 is a top view of a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0023] Figure 5 is a flow chart of a method for manufacturing a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0024] Figure 6 It is a flow chart of another method for manufacturing a semiconductor packaging structure provided by an embodiment of the present disclosure.

[0025] Reference numerals:

[0026] 10: lead frame; 10a: first surface; 101: groove; 102: first groove; 103: second groove; 11: base island; 12: pin; 20: conductive adhesive layer; 201: first part; 30: semiconductor chip; 40: insulating thermal conductive layer; 50: packaging layer; 60: connecting wire. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0028] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0029] Figure 1 Schematic diagram of a semiconductor packaging structure in the related art. Figure 1 As shown, the semiconductor packaging structure includes a lead frame 10', a conductive adhesive layer 20' and a semiconductor chip 30'. The surface of the lead frame 10' is a plane, the conductive adhesive layer 20' is located on the surface of the lead frame 10', the semiconductor chip 30' is located on the surface of the conductive adhesive layer 20' away from the lead frame 10', and the bottom surface of the semiconductor chip 30' is connected to the lead frame 10' through the conductive adhesive layer 20'. During the use of the semiconductor packaging structure, the semiconductor chip 30' will continuously generate heat. In the semiconductor packaging structure, only the bottom surface of the semiconductor chip 30' is connected to the lead frame 10' through the conductive adhesive layer 20'. The contact area between the semiconductor chip 30' and the conductive adhesive layer 20' is small, and the heat of the semiconductor chip 30' will be difficult to dissipate to the outside. The heat dissipation performance of the semiconductor packaging structure is poor, thereby affecting the reliability of the semiconductor packaging structure.

[0030] Figure 2 Schematic diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 2As shown, the semiconductor package structure includes a lead frame 10, a conductive adhesive layer 20 and a semiconductor chip 30. The first surface 10a of the lead frame 10 has a groove 101, and the conductive adhesive layer 20 is located on the bottom surface and side walls of the groove 101. The semiconductor chip 30 is located in the groove 101, and the bottom surface and side walls of the semiconductor chip 30 are connected to the lead frame 10 through the conductive adhesive layer 20.

[0031] In the embodiment of the present disclosure, a groove 101 is provided on the first surface 10a of the lead frame 10, and a conductive adhesive layer 20 is provided on the bottom surface of the groove 101 and the side wall of the groove 101. The semiconductor chip 30 is located in the groove 101, and the bottom surface of the semiconductor chip 30 and the side wall of the semiconductor chip 30 are connected to the lead frame 10 through the conductive adhesive layer 20. In this way, compared with only the bottom surface of the semiconductor chip 30 being connected to the lead frame 10 through the conductive adhesive layer 20, the contact area between the semiconductor chip 30 and the conductive adhesive layer 20 is increased. During the use of the semiconductor packaging structure, the heat generated by the semiconductor chip 30 can be conducted to the lead frame 10 through the conductive adhesive layer 20 located on the bottom surface of the groove 101 and the side wall of the groove 101 and then dissipated to the outside, thereby improving the heat dissipation performance of the semiconductor packaging structure and improving the reliability of the semiconductor packaging structure.

[0032] It should be noted that, in the semiconductor packaging structure, the lead frame 10 is used to be welded with external wires, etc., so as to lead out the internal circuit of the semiconductor chip 30 .

[0033] Optionally, the semiconductor chip 30 may be a power semiconductor chip. Exemplarily, the power semiconductor chip may be a Schottky diode chip, a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) chip, or a High Electron Mobility Transistor (HEMT) chip.

[0034] In other embodiments, the type of the semiconductor chip 30 may be adjusted according to actual needs, and the present disclosure does not limit this.

[0035] In the embodiment of the present disclosure, the semiconductor chip 30 is taken as a HEMT chip as an example for illustrative description.

[0036] like Figure 2As shown, in the direction perpendicular to the first surface 10a, the depth H1 of the groove 101 is less than the sum of the thickness H2 of the conductive adhesive layer 20 and the thickness H3 of the semiconductor chip 30. That is, the surface of the semiconductor chip 30 away from the lead frame 10 protrudes above the first surface 10a. This makes it easy to electrically connect the electrodes on the surface of the semiconductor chip 30 away from the lead frame 10 to the lead frame 10 through the packaging process.

[0037] Optionally, the thickness H3 of the semiconductor chip 30 is 100 μm to 300 μm.

[0038] By way of example, the thickness H3 of the semiconductor chip 30 may be 100 μm, 200 μm, 300 μm, or the like.

[0039] like Figure 2 As shown, the ratio of the depth H1 of the groove 101 to the maximum thickness H4 of the lead frame 10 is 0.5 to 0.75. Since the groove 101 is provided on the first surface 10a of the lead frame 10, the thickness of different parts of the lead frame 10 may be different. Here, the maximum thickness H4 of the lead frame 10 refers to the maximum value of the thickness of the lead frame 10 in the direction perpendicular to the first surface 10a. Figure 2 In the embodiment, the maximum thickness H4 of the lead frame 10 is the distance between the bottom surface of the lead frame and the first surface 10a. If the ratio of H1 to H4 is too small, the contact area between the semiconductor chip 30 and the conductive adhesive layer 20 may be small, affecting the heat dissipation performance of the semiconductor packaging structure; if the ratio of H1 to H4 is too large, the thickness of the lead frame 10 below the groove 101 may be too small, resulting in a low strength of the semiconductor packaging structure, thereby affecting the reliability of the semiconductor packaging structure. When the ratio of H1 to H4 is within this range, the heat dissipation performance of the semiconductor packaging structure can be ensured to be good while ensuring the strength of the semiconductor packaging structure to be high.

[0040] For example, the ratio of the depth H1 of the groove 101 to the maximum thickness H4 of the lead frame 10 may be 0.5, 0.65, 0.75, or the like.

[0041] Optionally, the maximum thickness H4 of the lead frame 10 is 100 μm to 300 μm.

[0042] For example, the maximum thickness H4 of the lead frame 10 may be 100 μm, 200 μm, 300 μm, or the like.

[0043] like Figure 2As shown, the conductive adhesive layer 20 has a first portion 201, and the first portion 201 is located between the side wall of the groove 101 and the side wall of the semiconductor chip 30. In the direction perpendicular to the first surface 10a, the distance H5 between the surface of the first portion 201 away from the bottom surface of the groove 101 and the bottom surface of the semiconductor chip 30 is 0.5 to 0.75 with respect to the thickness H3 of the semiconductor chip 30. If the ratio of H5 to H3 is too small, the contact area between the semiconductor chip 30 and the conductive adhesive layer 20 may be small, affecting the heat dissipation performance of the semiconductor packaging structure; if the ratio of H5 to H3 is too large, the conductive adhesive layer 20 may contact the electrode located on the surface of the semiconductor chip 30 away from the lead frame 10, causing a short circuit failure, affecting the reliability of the semiconductor packaging structure. When the ratio of H5 to H3 is within this range, a larger contact area between the semiconductor chip 30 and the conductive adhesive layer 20 can be ensured, the heat dissipation performance of the semiconductor packaging structure is better, and the probability of short circuit failure caused by the conductive adhesive layer 20 contacting the electrode on the surface of the semiconductor chip 30 away from the lead frame 10 can be reduced, which is beneficial to improving the reliability of the semiconductor packaging structure.

[0044] For example, the ratio of the distance H5 between the surface of the first portion 201 away from the bottom surface of the groove 101 and the bottom surface of the semiconductor chip 30 to the thickness H3 of the semiconductor chip 30 may be 0.5, 0.65, 0.75, etc.

[0045] For example, in a direction perpendicular to the first surface 10a, the height of the surface of the first portion 201 away from the bottom surface of the groove 101 is lower than the height of the bottom surface of the epitaxial layer in the semiconductor chip 30. That is, the first portion 201 will not contact the epitaxial layer in the semiconductor chip 30, thereby reducing the probability of short circuit failure. For example, the first portion 201 may only contact the substrate in the semiconductor chip 30, etc.

[0046] Exemplarily, the distance H6 between the surface of the first portion 201 away from the bottom surface of the groove 101 and the surface of the semiconductor chip 30 away from the lead frame 10 is greater than 30 μm. For example, the distance H6 between the surface of the first portion 201 away from the bottom surface of the groove 101 and the surface of the semiconductor chip 30 away from the lead frame 10 may be 40 μm, 50 μm, or 60 μm, etc.

[0047] Figure 3 It is a structural schematic diagram of another semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 3 Part (a) of FIG. 1 may represent a schematic diagram of a structure on a cross section perpendicular to the first surface 10a. Figure 3 Part (b) of FIG. 1 may represent a schematic diagram of a structure on a cross section perpendicular to the first surface 10a and perpendicular to the cross section of part (a). Figure 3As shown, the semiconductor package structure further includes an insulating heat-conducting layer 40, which is at least located on the surface of the semiconductor chip 30 away from the lead frame 10 and the side wall of the semiconductor chip 30, and is in contact with at least one of the conductive adhesive layer 20 and the first surface 10a of the lead frame 10. In this way, during the use of the semiconductor package structure, the heat generated by the semiconductor chip 30 can be conducted to the conductive adhesive layer 20 through the insulating heat-conducting layer 40, and then indirectly conducted to the first surface 10a of the lead frame 10 through the conductive adhesive layer 20, or directly conducted to the first surface 10a of the lead frame 10 through the insulating heat-conducting layer 40, and then dissipated to the outside, thereby further increasing the heat dissipation area of ​​the semiconductor chip 30, and can effectively improve the heat dissipation performance of the semiconductor package structure.

[0048] In one possible embodiment, the orthographic projection of the insulating heat-conducting layer 40 on the lead frame 10 is located inside the orthographic projection of the conductive adhesive layer 20 on the lead frame 10, and the insulating heat-conducting layer 40 on the side wall of the semiconductor chip 30 contacts the interface between the first surface 10a and the conductive adhesive layer 20, so that the insulating heat-conducting layer 40 contacts the first surface 10a of the lead frame 10.

[0049] Exemplarily, the insulating heat-conducting layer 40 is also located on the first surface 10a of the periphery of the semiconductor chip 30. That is, the insulating heat-conducting layer 40 can extend from the side wall of the semiconductor chip 30 to the first surface 10a of the periphery thereof. In this way, the contact area between the insulating heat-conducting layer 40 and the lead frame 10 can be increased, which is beneficial for heat conduction to the lead frame 10 and improves the heat dissipation performance.

[0050] In the embodiment of the present disclosure, the insulating thermal conductive layer 40 contacts both the conductive adhesive layer 20 and the lead frame 10. In other embodiments, the insulating thermal conductive layer 40 may only contact the conductive adhesive layer 20 but not the lead frame 10, and the present disclosure does not limit this.

[0051] Figure 4 It is a top view of a semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 3 Part (a) can be Figure 4 Schematic diagram of the cross-section structure at the AA line. Figure 3 Part (b) can be Figure 4 Schematic diagram of the cross-sectional structure at the BB line. Figures 2 to 4 As shown, the orthographic projection of the semiconductor chip 30 on the first surface 10 a is located inside the orthographic projection of the groove 101 on the first surface 10 a .

[0052] Optionally, the center of the orthographic projection of the semiconductor chip 30 on the first surface 10a coincides with the center of the orthographic projection of the groove 101 on the first surface 10a. This ensures that the thickness of the conductive adhesive layer 20 between the sidewall of the semiconductor chip 30 and the sidewall of the groove 101 is relatively uniform, thereby improving the uniformity of heat dissipation of the semiconductor packaging structure.

[0053] Exemplarily, the orthographic projection of the semiconductor chip 30 on the first surface 10a and the outer contour of the orthographic projection of the groove 101 on the first surface 10a have the same shape. For example, the outer contour of the orthographic projection of the groove 101 on the first surface 10a is a rectangle, and the groove 101 is a rectangular groove. The outer contour of the orthographic projection of the semiconductor chip 30 on the first surface 10a is also a rectangle, and the semiconductor chip 30 is a cube or a cuboid chip.

[0054] like Figures 2 to 4 As shown, the semiconductor package structure further includes a packaging layer 50, which is located at least on the first surface 10a of the lead frame 10, the surface of the semiconductor chip 30 away from the lead frame 10, and the sidewall of the semiconductor chip 30, and covers the semiconductor chip 30. Here, covering means that the packaging layer 50 can cover the surfaces of the semiconductor chip 30 that may be exposed. The packaging layer 50 can seal, protect and fix the semiconductor chip 30, thereby improving the reliability of the semiconductor package structure. Figure 3 An insulating heat-conducting layer 40 is disposed in the structure, and the encapsulation layer 50 is also located on the surface of the insulating heat-conducting layer 40 and covers the insulating heat-conducting layer 40 .

[0055] Optionally, the lead frame 10 includes a base island 11 and a plurality of pins 12, the first surface 10a includes the surface of the base island 11, and the plurality of pins 12 are arranged at intervals on the periphery of the base island 11. The semiconductor package structure also includes a plurality of connecting wires 60, the semiconductor chip 30 is electrically connected to the pins 12 through the connecting wires 60, and each pin 12 is connected to at least one connecting wire 60. In this way, the internal circuit of the semiconductor chip 30 is conveniently led out through the pins 12 and the connecting wires 60, and is convenient for connection with external wires, etc., and the plurality of pins 12 are arranged at intervals to reduce the probability of short circuits between the internal circuits of the semiconductor chip 30.

[0056] Exemplarily, there is a through groove between the base island 11 and the plurality of pins 12, and the through groove includes a first groove 102 and a second groove 103, the first groove 102 and the second groove 103 are correspondingly arranged and interconnected, and the second groove 103 is located on a side of the first groove 102 away from the first surface 10a.

[0057] Exemplarily, the orthographic projection of the first groove 102 on the bottom surface of the lead frame 10 is located inside the orthographic projection of the second groove 103 on the bottom surface of the lead frame 10. Figure 2 and Figure 3 As shown, the shape of the through groove on the cross section perpendicular to the first surface 10a can be an inverted T-shape, the shape of the base island 11 on the cross section perpendicular to the first surface 10a can be similar to a T-shape, and the shape of the pin 12 on the cross section perpendicular to the first surface 10a can be a "7" shape or a "7" shape mirrored along the left and right sides. This makes it easy to fill and form the packaging layer 50 between the base island 11 and the pin 12, which is beneficial to improving the strength of the semiconductor packaging structure.

[0058] Exemplarily, the encapsulation layer 50 is also located between the base island 11 and the pins 12 , that is, filled in the through grooves. The surface of the pins 12 away from the connection wires 60 is exposed to the surface of the encapsulation layer 50 , and the encapsulation layer 50 covers the plurality of connection wires 60 .

[0059] In the embodiment of the present disclosure, the semiconductor chip 30 is a HEMT chip, the lead frame 10 includes a base island 11 and two pins 12, the two pins 12 are arranged at intervals on both sides of the periphery of the base island 11, the substrate of the HEMT chip is electrically connected to the base island 11 through a conductive adhesive layer 20, and the source of the HEMT chip can be electrically connected to the base island 11 through a connecting line (not shown), and the gate and drain of the HEMT chip are respectively connected to a pin 12 through a connecting line 60. Figure 2 , Figure 3 Part (a) and Figure 4 As shown, the gate of the HEMT chip can be connected to a pin 12 on the left side of the base island 11 through a connecting line 60 , and the drain of the HEMT chip can be connected to a pin 12 on the right side of the base island 11 through a connecting line 60 .

[0060] It should be noted that Figures 2 to 4 The substrate, source, gate and drain of the HEMT chip are not shown separately. The specific structure of the HEMT chip can be found in the related art, and the present disclosure will not elaborate on it here.

[0061] In other embodiments, each pin 12 may be connected to a plurality of connection lines 60 , which is not limited in the present disclosure.

[0062] Figure 3 and Figure 4 In the embodiment, the insulating heat-conducting layer 40 is located on two opposite side walls of the semiconductor chip 30 and the first surface 10 a on two opposite sides of the periphery of the semiconductor chip 30 .

[0063] Exemplarily, the orthographic projection of the insulating heat-conducting layer 40 on the first surface 10 a has no overlapping portion with the orthographic projection of the gate of the HEMT chip on the first surface 10 a and the orthographic projection of the drain of the HEMT chip on the first surface 10 a. In this way, the insulating heat-conducting layer 40 will not affect the connecting wire 60.

[0064] In other embodiments, the number of pins 12 in the lead frame 10 and the connection method between the pins 12 and the semiconductor chip 30 can be adjusted according to actual needs, and the present disclosure does not limit this.

[0065] Optionally, the lead frame 10 is made of Cu.

[0066] Exemplarily, the lead frame 10 may be a lead frame with a main body of Cu and a surface plated with Ag and NiPdAu.

[0067] Optionally, the conductive adhesive layer 20 is made of metal solder or conductive glue. These materials are convenient for fixing the semiconductor chip 30 and the lead frame 10, and these materials have good thermal conductivity, which is conducive to improving the heat dissipation performance of the semiconductor packaging structure. For example, the metal solder can be solder paste, silver paste or Au, and the conductive glue can be epoxy resin containing silver particles.

[0068] Exemplarily, the insulating heat-conducting layer 40 may be made of a thermally conductive adhesive.

[0069] Optionally, the encapsulation layer 50 may be made of a polymer material. For example, the encapsulation layer 50 may be a molding compound, such as epoxy resin.

[0070] Optionally, the connection wire 60 may be a gold wire, an aluminum wire, a copper wire, a palladium-plated copper wire, or the like.

[0071] Figure 5 FIG. 1 is a flow chart of a method for manufacturing a semiconductor packaging structure provided by an embodiment of the present disclosure. Figure 5 As shown, the manufacturing method includes:

[0072] In step S1001 , a lead frame and a semiconductor chip are provided.

[0073] The first surface of the lead frame has a groove.

[0074] In step S1002 , the lead frame and the semiconductor chip are connected via a conductive adhesive layer to obtain a semiconductor packaging structure.

[0075] The conductive adhesive layer is located on the bottom surface and the side wall of the groove, the semiconductor chip is located in the groove, and the bottom surface and the side wall of the semiconductor chip are connected to the lead frame through the conductive adhesive layer.

[0076] In the disclosed embodiment, a groove is provided on the first surface of the lead frame, and a conductive adhesive layer is provided on the bottom surface and the side wall of the groove, the semiconductor chip is located in the groove, and the bottom surface and the side wall of the semiconductor chip are connected to the lead frame through the conductive adhesive layer. In this way, compared with only the bottom surface of the semiconductor chip being connected to the lead frame through the conductive adhesive layer, the contact area between the semiconductor chip and the conductive adhesive layer is increased. During the use of the semiconductor packaging structure, the heat generated by the semiconductor chip can be conducted to the lead frame through the conductive adhesive layer located on the bottom surface and the side wall of the groove and then dissipated to the outside, thereby improving the heat dissipation performance of the semiconductor packaging structure and improving the reliability of the semiconductor packaging structure.

[0077] Figure 6 It is a flow chart of another method for manufacturing a semiconductor packaging structure provided by an embodiment of the present disclosure.

[0078] like Figure 6 As shown, the manufacturing method includes:

[0079] In step S2001, a lead frame and a semiconductor chip are provided.

[0080] Optionally, the semiconductor chip is a HEMT chip.

[0081] Exemplarily, the HEMT chip includes a drain, a source, and a gate.

[0082] Optionally, the lead frame includes a base island and a plurality of leads, the plurality of leads are arranged at intervals on the periphery of the base island, the first surface of the lead frame has a groove, and the first surface includes a surface of the base island.

[0083] In step S2002 , the lead frame and the semiconductor chip are connected via a conductive adhesive layer.

[0084] Exemplarily, a conductive adhesive material can be formed in the groove, and then the semiconductor chip is bonded to the groove and a certain pressure is applied to form a conductive adhesive layer, the conductive adhesive layer is located on the bottom surface and side walls of the groove, the semiconductor chip is located in the groove, and the bottom surface and side walls of the semiconductor chip are connected to the lead frame through the conductive adhesive layer.

[0085] Optionally, after completing the above step S2002, the manufacturing method may further include:

[0086] In step S2003, an insulating heat-conducting layer is formed on the semiconductor chip.

[0087] Exemplarily, the insulating heat-conducting layer is located at least on a surface of the semiconductor chip away from the lead frame and a side wall of the semiconductor chip, and is in contact with at least one of the conductive adhesive layer and the first surface of the lead frame.

[0088] In step S2004, at least one connecting line is formed on each pin.

[0089] Exemplarily, at least one connection wire may be formed on each pin by a wire bonding process, and the semiconductor chip is electrically connected to the pin via the connection wire.

[0090] In step S2005, the lead frame, the conductive adhesive layer, the semiconductor chip, the insulating thermal conductive layer and the plurality of connecting wires are packaged by a packaging layer.

[0091] Exemplarily, the packaging layer is located between the base island and the pin, the first surface of the lead frame, the surface of the semiconductor chip away from the lead frame, the side wall of the semiconductor chip, and the surface of the insulating thermal conductive layer, and covers the semiconductor chip, the insulating thermal conductive layer and multiple connecting wires, and the surface of the pin away from the connecting wires is exposed to the surface of the packaging layer.

[0092] Optionally, the structure, material, shape and thickness of each layer can be found in Figures 2 to 4 The detailed description of the related embodiments is omitted here.

[0093] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: It comprises a lead frame (10), a conductive adhesive layer (20) and a semiconductor chip (30), The first surface (10a) of the lead frame (10) has a groove (101), and the conductive adhesive layer (20) is located on the bottom surface of the groove (101) and the side wall of the groove (101); The semiconductor chip (30) is located in the groove (101), and the bottom surface of the semiconductor chip (30) and the side wall of the semiconductor chip (30) are connected to the lead frame (10) via the conductive adhesive layer (20).

2. The semiconductor package structure according to claim 1, wherein: In a direction perpendicular to the first surface (10a), the depth of the groove (101) is less than the sum of the thickness of the conductive adhesive layer (20) and the thickness of the semiconductor chip (30).

3. The semiconductor package structure according to claim 2, characterized in that: The ratio of the depth of the groove (101) to the maximum thickness of the lead frame (10) is 0.5 to 0.

75.

4. The semiconductor package structure according to claim 2, wherein: The conductive adhesive layer (20) has a first portion (201), the first portion (201) is located between the side wall of the groove (101) and the side wall of the semiconductor chip (30), and in a direction perpendicular to the first surface (10a), the ratio of the distance between the surface of the first portion (201) away from the bottom surface of the groove (101) and the bottom surface of the semiconductor chip (30) to the thickness of the semiconductor chip (30) is 0.5 to 0.

75.

5. The semiconductor package structure according to any one of claims 1 to 4, characterized in that: The semiconductor packaging structure further comprises an insulating heat-conducting layer (40), The insulating heat-conducting layer (40) is located at least on a surface of the semiconductor chip (30) away from the lead frame (10) and a side wall of the semiconductor chip (30), and is in contact with at least one of the conductive adhesive layer (20) and a first surface (11) of the lead frame (10).

6. The semiconductor package structure according to claim 5, characterized in that: The insulating heat-conducting layer (40) is also located on the first surface (10a) at the periphery of the semiconductor chip (30).

7. The semiconductor package structure according to any one of claims 1 to 4 and claim 6, characterized in that: The conductive adhesive layer (20) is made of metal solder or conductive glue.

8. The semiconductor package structure according to any one of claims 1 to 4 and claim 6, characterized in that: The semiconductor packaging structure further comprises a packaging layer (50), wherein the packaging layer (50) is located at least on a first surface (10a) of the lead frame (10), a surface of the semiconductor chip (30) away from the lead frame (10), and a side wall of the semiconductor chip (30), and covers the semiconductor chip (30).

9. The semiconductor package structure according to any one of claims 1 to 4 and claim 6, characterized in that: The lead frame (10) comprises a base island (11) and a plurality of pins (12), the first surface (10a) comprises a surface of the base island (11), and the plurality of pins (12) are arranged at intervals on the periphery of the base island (11); The semiconductor packaging structure also includes a plurality of connection wires (60), the semiconductor chip (30) is electrically connected to the pins (12) via the connection wires (60), and each of the pins (12) is connected to at least one of the connection wires (60).

10. A method for manufacturing a semiconductor packaging structure, characterized in that: include: A lead frame (10) and a semiconductor chip (30) are provided, wherein a first surface (10a) of the lead frame (10) has a groove (101); The lead frame (10) and the semiconductor chip (30) are connected via a conductive adhesive layer (20) to obtain the semiconductor packaging structure, wherein the conductive adhesive layer (20) is located on the bottom surface of the groove (101) and the side wall of the groove (101), the semiconductor chip (30) is located in the groove (101), and the bottom surface of the semiconductor chip (30) and the side wall of the semiconductor chip (30) are both connected to the lead frame (10) via the conductive adhesive layer (20).

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