Semiconductor package

Abstract

The semiconductor package includes: an upper package including a first package substrate, a first semiconductor chip mounted on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a printed circuit board (PCB) on the PCB, the upper package being mounted in the central region; and a stiffener on the top surface of the PCB and including an opening. The top surface of the PCB contacts the bottom surface of the stiffener in at least a portion of the edge region of the PCB. In a central region of the PCB and in an edge region other than at least a portion of the edge region of the PCB, a top surface of the PCB is spaced apart from a bottom surface of the stiffener in a vertical direction, and an opening of the stiffener overlaps the upper package in the vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the priority of Singapore patent application No. 10202303199U filed with the Intellectual Property Office of Singapore on November 10, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a reinforcement. Background Art

[0004] A semiconductor package may include a semiconductor chip implemented in a form suitable for use in an electronic product. Typically, in a semiconductor package, the semiconductor chip is mounted on a printed circuit board (PCB) and electrically connected to the PCB by using bonding wires or bumps. As semiconductor packages become faster and have higher capacitance, the power consumption of semiconductor packages is increasing. Therefore, the importance of a PCB / package structure that meets the size / performance requirements of a semiconductor package and provides a stable power supply to the semiconductor package is increasing. Summary of the invention

[0005] The present disclosure relates to semiconductor packages having improved heat dissipation performance.

[0006] The present disclosure relates to a semiconductor package capable of suppressing a warpage phenomenon.

[0007] The present disclosure relates to a miniaturized semiconductor package with a reduced signal distance between passive components and a semiconductor chip.

[0008] Problems to be solved by the technical idea of ​​the present inventive concept are not limited to the above-mentioned problems, and other problems may be clearly understood by those skilled in the art from the following description.

[0009] Some example embodiments of the present inventive concept provide a semiconductor package, the semiconductor package comprising: an upper package, which includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a printed circuit board (PCB), the upper package is located in a central area of ​​the PCB; and a reinforcement member, which is located on a top surface of the PCB, the reinforcement member including an opening. The top surface of the PCB contacts the bottom surface of the reinforcement member in at least a portion of an edge area of ​​the PCB. In the central area of ​​the PCB and in the edge area other than at least a portion of the edge area of ​​the PCB that contacts the reinforcement member, the top surface of the PCB is spaced apart from the bottom surface of the reinforcement member in a vertical direction. The opening of the reinforcement member overlaps with the upper package in a vertical direction.

[0010] Some example embodiments of the present inventive concept also provide a semiconductor package, which includes: a first upper package, which includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a plurality of second upper packages, each of which includes a second package substrate, a second semiconductor chip on the second package substrate, and a second molding layer surrounding the second semiconductor chip; a printed circuit board (PCB), the first upper package is mounted on a central area of ​​the PCB, and the PCB electrically connects the first upper package to the plurality of second upper packages; and a reinforcement member, which is located on a top surface of the PCB, the reinforcement member including an opening. At least some portions of an edge area of ​​the PCB contact the reinforcement member. The central area of ​​the PCB and the edge area other than at least some portions of the edge area of ​​the PCB contacting the reinforcement member are spaced apart from the reinforcement member in the vertical direction. The opening of the reinforcement member overlaps with the first upper package in the vertical direction.

[0011] Some example embodiments of the present inventive concept further provide a semiconductor package, the semiconductor package comprising: a first upper package, which includes a first package substrate, a first semiconductor chip on the first package substrate, and a first mold layer surrounding a side surface of the first semiconductor chip, the first semiconductor chip having a horizontal area smaller than that of the first package substrate; a printed circuit board (PCB), the upper package is located on a central area of ​​the PCB, and the PCB has a horizontal area larger than that of the first upper package; and a stiffener attached to a top surface of the PCB through an adhesive layer, the stiffener including an opening. A pitch between each two of a plurality of lower connection pads of the first semiconductor chip is smaller than a pitch between each two of a plurality of lower connection terminals of the first package substrate. A pitch between each two of a plurality of lower connection terminals of the first package substrate is smaller than a pitch between each two of a plurality of lower connection terminals of the PCB. The top surface of the PCB contacts the bottom surface of the stiffener in at least a portion of an edge area of ​​the PCB. In the central area of ​​the PCB and in an edge area other than at least a portion of the edge area of ​​the PCB that contacts the stiffener, the top surface of the PCB is spaced apart from the bottom surface of the stiffener in a vertical direction. The opening of the reinforcement member overlaps with the first upper package member in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Some example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a perspective view schematically illustrating a semiconductor package according to some example embodiments;

[0014] Figure 2 It is schematically shown Figure 1A plan view of a semiconductor package;

[0015] Figure 3 It is schematically shown Figure 2 a plan view of a printed circuit board (PCB) of a semiconductor package;

[0016] Figure 4 is schematically shown along Figure 2 The line A1-A1' is intercepted Figure 2 A cross-sectional view of a semiconductor package;

[0017] Figure 5 is schematically shown along Figure 2 The line B1-B1' intercepts Figure 2 A cross-sectional view of a semiconductor package;

[0018] Figure 6 is a plan view schematically illustrating a semiconductor package according to some example embodiments;

[0019] Figure 7 is schematically shown along Figure 6 The line A2-A2' intercepts Figure 6 A cross-sectional view of a semiconductor package;

[0020] Figure 8 is schematically shown along Figure 6 The line B2-B2' intercepts Figure 6 A cross-sectional view of a semiconductor package;

[0021] Fig. 9 is a plan view schematically illustrating a semiconductor package according to some example embodiments;

[0022] Fig.10 is schematically shown along Fig. 9 The line A3-A3' is intercepted Fig. 9 A cross-sectional view of a semiconductor package;

[0023] Fig.11 is schematically shown along Fig. 9 The line B3-B3' is intercepted Fig. 9 A cross-sectional view of a semiconductor package;

[0024] Fig.12 is a plan view schematically illustrating a semiconductor package according to some example embodiments;

[0025] Fig.13 is schematically shown along Fig.12 The line A4-A4' is intercepted Fig.12 A cross-sectional view of a semiconductor package;

[0026] Fig.14 is a perspective view schematically illustrating a semiconductor package according to some example embodiments;

[0027] Fig.15 It is schematically shown Fig.14 A plan view of a semiconductor package;

[0028] Fig.16 is schematically shown along Fig.15 The line C-C' intercepts Fig.15 A cross-sectional view of a semiconductor package;

[0029] Fig.17 is schematically shown along Fig.15 The line D-D' intercepts Fig.15 A cross-sectional view of a semiconductor package;

[0030] Fig.18 , Fig.19 and Fig. 20 It is a schematic diagram showing the respective Fig.15 A cross-sectional view of a semiconductor package according to some example embodiments taken along line CC';

[0031] as well as Fig.21 and Fig. 22 It is a schematic diagram showing the respective Fig.15 1 is a cross-sectional view of a semiconductor package according to some example embodiments, taken along line CC′. DETAILED DESCRIPTION

[0032] Since the current example embodiments may undergo various changes and have various forms, some example embodiments will be shown in the drawings and described in detail. However, the example embodiments are not limited to a specific disclosed form.

[0033] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing tolerance or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the freedom of the shape is within the scope of the present disclosure. In addition, whether or not a numerical value or shape is modified as "approximately" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing tolerance or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0034] In addition, for example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C (such as ABC, AB, BC, and AC for example).

[0035] Figure 1 is a perspective view schematically illustrating a semiconductor package 1000 according to some example embodiments. Figure 2 It is schematically shown Figure 1 1 is a plan view of a semiconductor package 1000.

[0036] Figure 3 It is schematically shown Figure 2 FIG. 1 is a plan view of a printed circuit board (PCB) 200 of a semiconductor package 1000 . Figure 4 is schematically shown along Figure 2 The line A1-A1' is intercepted Figure 2 1 is a cross-sectional view of a semiconductor package 1000 . Figure 5 is schematically shown along Figure 2 The line B1-B1' intercepts Figure 2 A cross-sectional view of a semiconductor package 1000 .

[0037] Reference Figures 1 to 5 , the semiconductor package 1000 may include a PCB 200 , a first upper package 100 , and a stiffener 300 . In some example embodiments, the semiconductor package 1000 may further include a plurality of passive elements 500 .

[0038] The PCB 200 of the semiconductor package 1000 may include, for example, a module board on which the package is mounted. For example, the PCB 200 may correspond to a thin core high density interconnect (HDI) PCB.

[0039] The PCB 200 may generally have a flat plate or panel shape. The PCB 200 may include a top surface and a bottom surface opposite to each other, and the top surface and the bottom surface may be flat surfaces, respectively. Hereinafter, a horizontal direction (e.g., an X direction and / or a Y direction) may be defined as a direction parallel to the top surface of the PCB 200, and a vertical direction (e.g., a Z direction) may be defined as a direction perpendicular to the top surface of the PCB 200.

[0040] The PCB 200 may include a core insulating layer, a plurality of upper connecting pads 207 , and a plurality of lower connecting pads 208 .

[0041] The core insulating layer may include at least one material selected from phenolic resin, epoxy resin and polyimide. For example, the core insulating layer may include at least one material selected from polyimide, flame retardant (FR)-4, tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene oxide, bismaleimide triazine (BT), (Non-woven aramid fiber reinforced substrate for printed wiring boards), at least one material selected from cyanate esters and liquid crystal polymers.

[0042] A plurality of upper connection pads 207 may be disposed on the top surface of the core insulating layer, and conductive connection members for electrical and physical connection between the PCB 200 and mounting components mounted on the PCB 200 may be attached to the plurality of upper connection pads 207 .

[0043] A plurality of lower connection pads 208 may be disposed on the bottom surface of the core insulating layer. External connection terminals 209 may be attached to the plurality of lower connection pads 208. The external connection terminals 209 may electrically and physically connect the PCB 200 to an external device on which the PCB 200 is mounted. The external connection terminals 209 may include, for example, solder balls or solder bumps. The plurality of upper connection pads 207 may be electrically connected to the plurality of lower connection pads 208 through a metal wiring structure disposed in the core insulating layer.

[0044] For example, the plurality of upper connecting pads 207 and the plurality of lower connecting pads 208 may include a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga) or ruthenium (Ru) or alloys thereof.

[0045] like Figure 3 As shown in , the PCB 200 may include a central area 200_C and an edge area 200_E. The central area 200_C may include a central point 200_CP of the top surface of the printed circuit board 200, and the edge area 200_E may be an area surrounding the central area 200_C. The edge area 200_E may include first to fourth vertices 200_P1, 200_P2, 200_P3, and 200_P4 of the top surface of the PCB 200. That is, the edge area 200_E may extend from one end of the central area 200_C to one end of the PCB 200.

[0046] The edge region 200_E of the PCB 200 may include a corner region 200_EC and a middle region 200_EB between adjacent corner regions.

[0047] For example, the edge region 200_E may include first to fourth corner regions 200_EC1, 200_EC2, 200_EC3, and 200_EC4 corresponding to first to fourth vertices 200_P1, 200_P2, 200_P3, and 200_P4 of the top surface of the PCB 200. The first corner region 200_EC1 may be spaced apart from the second corner region 200_EC2 in the first horizontal direction (X direction), the second corner region 200_EC2 may be spaced apart from the third corner region 200_EC3 in the second horizontal direction (Y direction), the third corner region 200_EC3 may be spaced apart from the fourth corner region 200_EC4 in the first horizontal direction (X direction), and the fourth corner region 200_EC4 may be spaced apart from the first corner region 200_EC1 in the second horizontal direction (Y direction).

[0048] The intermediate region 200_EB may include a first intermediate region 200_EB1 between the first angular region 200_EC1 and the second angular region 200_EC2, a second intermediate region 200_EB2 between the second angular region 200_EC2 and the third angular region 200_EC3, a third intermediate region 200_EB3 between the third angular region 200_EC3 and the fourth angular region 200_EC4, and a fourth intermediate region 200_EB4 between the fourth angular region 200_EC4 and the first angular region 200_EC1.

[0049] The first upper package 100 of the semiconductor package 1000 may include a first package substrate 120 , a first semiconductor chip 110 , and a first mold layer 130 .

[0050] The first upper package 100 may be mounted on the PCB 200. The horizontal area of ​​the first upper package 100 may be smaller than the horizontal area of ​​the PCB 200. For example, the first upper package 100 may be mounted in the central area 200_C of the PCB 200. In some example embodiments, the center point 200_CP of the top surface of the PCB 200 and the center point of the top surface of the first upper package 100 may be in a straight line in the vertical direction (Z direction). For example, the center point 200_CP may be aligned with the center point of the top surface of the first upper package 100 along the vertical direction (Z direction).

[0051] Like the PCB 200, the first package substrate 120 of the first upper package 100 may include a core insulating layer, a plurality of upper connecting pads 127, and a plurality of lower connecting pads 128. According to some example embodiments, the first package substrate 120 may be thinner than the PCB 200. The plurality of upper connecting pads 127 may be electrically connected to the plurality of lower connecting pads 128 through a metal wiring structure disposed in the core insulating layer.

[0052] A plurality of upper connection pads 127 may be disposed on the top surface of the core insulating layer. The plurality of upper connection pads 127 may be electrically and physically connected to a plurality of lower connection pads 118 of the first semiconductor chip 110 mounted on the first package substrate 120. For example, the plurality of upper connection pads 127 of the first package substrate 120 may correspond one-to-one to the plurality of lower connection pads 118 of the first semiconductor chip 110.

[0053] A plurality of lower connection pads 128 may be disposed on the bottom surface of the core insulating layer. The plurality of lower connection pads 128 may be electrically and physically connected to a plurality of upper connection pads 207 of the PCB 200 through a conductive connection member 129. The conductive connection member 129 may include, for example, a solder ball or a solder bump. For example, the plurality of lower connection pads 128 of the first package substrate 120 may correspond one-to-one to the plurality of upper connection pads 207 of the PCB 200. The bottom filler UF may be filled between the first package substrate 120 and the PCB 200 and between the conductive connection members 129.

[0054] Hereinafter, “pitch” means a distance between centers of pads adjacent to each other in a horizontal direction.

[0055] In some example embodiments, a pitch P_208 between every two lower connecting pads 208 among the plurality of lower connecting pads 208 of the PCB 200, a pitch P_128 between every two lower connecting pads 128 among the plurality of lower connecting pads 128 of the first packaging substrate 120, and a pitch P_118 between every two lower connecting pads 118 among the plurality of lower connecting pads 118 of the first semiconductor chip 110 may be different from each other. For example, the pitch P_208 between every two lower connecting pads 208 among the multiple lower connecting pads 208 of the PCB 200 may be greater than the pitch P_128 between every two lower connecting pads 128 among the multiple lower connecting pads 128 of the first packaging substrate 120, and the pitch P_128 between every two lower connecting pads 128 among the multiple lower connecting pads 128 of the first packaging substrate 120 may be greater than the pitch P_118 between every two lower connecting pads 118 among the multiple lower connecting pads 118 of the first semiconductor chip 110. In some example embodiments, a pitch P_208 between every two lower connecting pads 208 of the plurality of lower connecting pads 208 of the PCB 200 may be 0.8 mm to 1.3 mm, a pitch P_128 between every two lower connecting pads 128 of the first packaging substrate 120 may be 0.3 mm to 0.6 mm, and a pitch P_118 between every two lower connecting pads 118 of the plurality of lower connecting pads 118 of the first semiconductor chip 110 may be 0.1 mm to 0.2 mm.

[0056] The first semiconductor chip 110 of the first upper package 100 may be mounted on the first package substrate 120. A horizontal area of ​​the first semiconductor chip 110 may be smaller than a horizontal area of ​​the first package substrate 120.

[0057] In some example embodiments, the first semiconductor chip 110 may be mounted on the first package substrate 120 by a flip chip method. For example, the plurality of lower connection pads 118 of the first semiconductor chip 110 may be electrically connected to the plurality of upper connection pads 127 of the first package substrate 120, respectively.

[0058] In some example embodiments, the first semiconductor chip 110 may include a system on chip (SOC) or a logic chip. Here, the logic chip may include an application processor (AP), a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a controller, or an application specific integrated circuit (ASIC).

[0059] For example, the first semiconductor chip 110 as an advanced RISC machine (ARM) server SOC may include a dynamic random access memory (DRAM) interface (I / F) for a dual in-line memory module (DIMM), a peripheral component interconnect express (PCIe) I / F used as a switch, and a CPU.

[0060] The first mold layer 130 of the first upper package 100 may surround the side surface of the first semiconductor chip 110 and may cover the top surface of the first package substrate 120. The sidewalls of the first mold layer 130 may be aligned in the vertical direction (Z direction) with the sidewalls of the first package substrate 120 to be coplanar. The first mold layer 130 may include, for example, epoxy mold compound (EMC).

[0061] The first mold layer 130 may protect the first semiconductor chip 110 from external influences. However, the first mold layer 130 may not cover the top surface 110_U of the first semiconductor chip 110. The top surface 110_U of the first semiconductor chip 110 may be exposed to the outside so that the heat generated by the first semiconductor chip 110 can be easily dissipated. In some example embodiments, the top surface 110_U of the first semiconductor chip 110 may be aligned with the top surface 130_U of the first mold layer 130 in the horizontal direction to be coplanar. That is, the vertical level of the first semiconductor chip 110 may be the same as the vertical level of the first mold layer 130. In the current specification, "vertical level" means the distance from the bottom surface of the PCB 200.

[0062] The reinforcement member 300 of the semiconductor package 1000 may be located on the PCB 200. The reinforcement member 300 may have a curved shape, for example, may include regions having different vertical levels. In some example embodiments, the reinforcement member 300 may include a contact unit (e.g., a member) 300_A2, a separation unit (e.g., a member) 300_A1, and an extension (e.g., a member) 300_A3. At the contact unit 300_A2, the bottom surface of the reinforcement member 300 contacts the top surface of the PCB 200, at the separation unit 300_A1, the bottom surface of the reinforcement member 300 is spaced apart from the top surface of the PCB 200, and at the extension unit 300_A3, the contact unit 300_A2 is connected to the separation unit 300_A1.

[0063] For example, the contact unit 300_A2 and the separation unit 300_A1 may be parallel to the top surface of the PCB 200, and the vertical level of each of the contact units 300_A2 may be different from the vertical level of each of the separation units 300_A1. For example, the vertical level of each of the contact units 300_A2 may be lower than the vertical level of each of the separation units 300_A1.

[0064] The extension unit 300_A3 may be inclined in a vertical direction (Z direction) with respect to the top surface of the PCB 200 to connect the contact unit 300_A2 and the separation unit 300_A1 having different vertical levels. Figure 5 , as the extension units 300_A3 located in the same middle area among the first to fourth middle areas 200_EB1, 200_EB2, 200_EB3, and 200_EB4 and spaced apart from each other in the horizontal direction are farther from the PCB 200, the distance D_300_A3 between the extension units 300_A3 may decrease. However, when the extension units 300_A3 extend in the vertical direction (Z direction), the distance D_300_A3 between the extension units 300_A3 located in the same middle area and spaced apart from each other in the horizontal direction may be constant.

[0065] The shape of the reinforcement member 300 will be described in detail based on a contact position between the PCB 200 and the reinforcement member 300 .

[0066] In at least a portion (e.g., some) of the edge region 200_E of the PCB 200, the top surface of the PCB 200 may contact the bottom surface of the stiffener 300. In the rest of the edge region 200_E and the center region 200_C of the PCB 200, the top surface of the PCB 200 may be spaced apart from the bottom surface of the stiffener 300 in the vertical direction.

[0067] In some example embodiments, the area where the top surface of the PCB 200 contacts the bottom surface of the stiffener 300 may be point-symmetrical with respect to the center point 200_CP of the top surface of the PCB 200. That is, the stiffener 300 contacts the PCB 200 to be symmetrical with respect to the center point 200_CP of the top surface of the PCB 200, so that a phenomenon in which some areas of the stiffener 300 are subjected to greater stress than other areas may be suppressed.

[0068] In some example embodiments, the contact unit 300_A2 of the reinforcement member 300 may be located on the corner region 200_EC of the edge region 200_E of the PCB 200. That is, the reinforcement member 300 may contact the top surface of the PCB 200 near the first to fourth vertices 200_P1, 200_P2, 200_P3, and 200_P4 of the top surface of the PCB 200.

[0069] The separation unit 300_A1 and the extension unit 300_A3 of the reinforcement member 300 may be located on the middle region 200_EB of the edge region 200_E of the PCB 200. That is, the reinforcement member 300 may be spaced apart from the PCB 200 in the vertical direction in the middle region 200_EB of the edge region 200_E of the PCB 200.

[0070] For example, the separation unit 300_A1 and the extension unit 300_A3 of the reinforcement member 300 may be arranged in a “+” shape in a plan view, and the contact unit 300_A2 of the reinforcement member 300 may include a square having first to fourth vertices 200_P1, 200_P2, 200_P3 and 200_P4 of the top surface of the PCB 200, respectively.

[0071] In some example embodiments, the contact units 300_A2 may be spaced apart from each other by a first distance D_X in a first horizontal direction (X direction). The contact units 300_A2 may be spaced apart from each other by a second distance D_Y in a second horizontal direction (Y direction). For example, the first distance D_X may be different from the second distance D_Y.

[0072] In some example embodiments, the contact unit 300_A2 located on the first corner region 200_EC1 may be spaced apart from the contact unit 300_A2 located on the second corner region 200_EC2 by a first distance D_X, and the contact unit 300_A2 located on the second corner region 200_EC2 may be spaced apart from the contact unit 300_A2 located on the third corner region 200_EC3 by a second distance D_Y different from the first distance D_X.

[0073] Therefore, the horizontal area of ​​the space between the first corner region 200_EC1 and the second corner region 200_EC2 of the PCB 200 and the stiffener 300 is different from the horizontal area of ​​the space between the second corner region 200_EC2 and the third corner region 200_EC3 of the PCB 200 and the stiffener 300, so that the components mounted in the space between the first corner region 200_EC1 and the second corner region 200_EC2 of the PCB 200 and the stiffener 300 may be different from the components mounted in the space between the second corner region 200_EC2 and the third corner region 200_EC3 of the PCB 200 and the stiffener 300. For example, the mounted components may include the components to be described later. Fig.14 A plurality of passive components 500 or a second upper package 400 .

[0074] For example, the number of components mounted between the contact unit 300_A2 located on the first corner area 200_EC1 and the contact unit 300_A2 located on the second corner area 200_EC2 may be different from the number of components mounted between the contact unit 300_A2 located on the second corner area 200_EC2 and the contact unit 300_A2 located on the third corner area 200_EC3.

[0075] The reinforcement member 300 may include an opening 300_O extending from a top surface thereof to a bottom surface thereof. The upper portion of the PCB 200 may be covered by the reinforcement member 300 except for the region where the opening 300_O is located. That is, the reinforcement member 300 may be located above the region of the PCB 200 except for the region where the opening 300_O is located. The reinforcement member 300 may be located above the PCB 200 in the region except for the opening 300_O to suppress the warping phenomenon of the PCB 200.

[0076] The first upper package 100 may be located in the opening 300_O of the reinforcement member 300. For example, the first upper package 100 may be mounted on a region of the PCB 200 where the opening 300_O is located.

[0077] In some example embodiments, the horizontal area of ​​the opening 300_O may be greater than the horizontal area of ​​the first upper package 100. The side surface of the reinforcement member 300 defining the opening 300_O may be spaced apart in the horizontal direction from the side surface of the first upper package 100. For example, a distance D_300 between each of the side surfaces of the reinforcement member 300 defining the opening 300_O and each of the side surfaces of the first upper package 100 may be 2 mm to 5 mm.

[0078] The top surface of the first upper package 100 may be exposed to the outside through the opening 300_O of the reinforcement 300. Therefore, heat generated by the first semiconductor chip 110 of the first upper package 100 may be easily dissipated to the outside.

[0079] The reinforcement member 300 may include a metal such as steel or copper (Cu). However, the material of the reinforcement member 300 is not limited thereto. The reinforcement member 300 may be adhered and fixed to the PCB 200 by the adhesive layer 309 .

[0080] A plurality of passive components 500 of the semiconductor package 1000 may be mounted on the PCB 200. The plurality of passive components 500 may be located below the separation unit 300_A1 and the extension unit 300_A3 of the reinforcement 300. For example, the plurality of passive components 500 may be located on the top surface of the PCB 200 in an area where the PCB 200 is spaced apart from the reinforcement 300 in the vertical direction. In some example embodiments, an air gap may be formed between the plurality of passive components 500 and the bottom surface of the reinforcement 300. The plurality of passive components 500 may include, for example, one of an inductor, a resistor, and a capacitor. Figure 2 1 and 2 show that four passive components 500 are arranged on each side of the first upper package 100. However, the number and position of the passive components 500 are not limited thereto.

[0081] Figure 6 is a plan view schematically illustrating a semiconductor package 1000 a according to some example embodiments. Figure 7 is schematically shown along Figure 6 The line A2-A2' intercepts Figure 6 1 is a cross-sectional view of a semiconductor package 1000 a. Figure 8 is a schematic diagram showing the Figure 6 Line B2-B2' intercepted Figure 6 1 is a cross-sectional view of a semiconductor package 1000 a.

[0082] Most of the components and materials forming the semiconductor package 1000a described below are similar to those previously described. Figure 1 Therefore, for convenience, the following description will be mainly Figure 6 The semiconductor package 1000a is similar to the semiconductor package 1000a described above. Figure 1 The differences between the semiconductor packages 1000 are shown in FIG.

[0083] The reinforcement member 300a of the semiconductor package 1000a may be located on the PCB 200. The reinforcement member 300a may have a curved shape, for example, may include regions having different vertical levels. In some example embodiments, the reinforcement member 300a may include a contact unit 300a_A2, a separation unit 300a_A1, and an extension unit 300a_A3. In the contact unit 300a_A2, the bottom surface of the reinforcement member 300a contacts the top surface of the PCB 200, in the separation unit 300a_A1, the bottom surface of the reinforcement member 300a is spaced apart from the top surface of the PCB 200, and in the extension unit 300a_A3, the contact unit 300a_A2 is connected to the separation unit 300a_A1.

[0084] The separation unit 300a_A1 and the extension unit 300a_A3 of the reinforcement member 300a may be located on the corner region 200_EC of the edge region 200_E of the PCB 200. That is, the reinforcement member 300a may be spaced apart from the PCB 200 near the first to fourth vertices 200_P1, 200_P2, 200_P3, and 200_P4 of the top surface of the PCB 200.

[0085] The contact unit 300a_A2 of the reinforcement member 300a may be located on the middle region 200_EB of the edge region 200_E of the PCB 200. That is, the reinforcement member 300a may contact the PCB 200 in the middle region 200_EB of the edge region 200_E of the PCB 200.

[0086] For example, the reinforcement 300a may contact the PCB 200 in a square shape near the center of each side of the top surface of the PCB 200 and may be spaced apart from the PCB 200 in the vertical direction (Z direction) in other areas. The separation unit 300a_A1 and the extension unit 300a_A3 may be arranged in an "X" shape.

[0087] Fig. 9 is a plan view schematically illustrating a semiconductor package 1000 b according to some example embodiments. Fig.10 is schematically shown along Fig. 9 The line A3-A3' is intercepted Fig. 9 1 is a cross-sectional view of a semiconductor package 1000 b. Fig.11 is schematically shown along Fig. 9 The line B3-B3' is intercepted Fig. 9 1 is a cross-sectional view of a semiconductor package 1000 b.

[0088] Most of the components and materials forming the semiconductor package 1000b described below are similar to those previously described in Figure 1Therefore, for convenience, the following description will be mainly Fig. 9 The semiconductor package 1000b is similar to the semiconductor package 1000b described above. Figure 1 The differences between the semiconductor packages 1000 are shown in FIG.

[0089] The reinforcement member 300b of the semiconductor package 1000b may be located on the PCB 200. The reinforcement member 300b may have a curved shape, for example, may include regions having different vertical levels. In some example embodiments, the reinforcement member 300b may include a contact unit 300b_A2, a separation unit 300b_A1, and an extension unit 300b_A3.

[0090] The contact unit 300b_A2 of the reinforcement member 300b may be located on the edge region 200_E of the PCB 200. The contact unit 300b_A2 may extend along the edge of the top surface of the PCB 200. For example, the contact unit 300b_A2 may have a square ring shape. That is, the reinforcement member 300b may contact the PCB 200 near the edge of the top surface of the PCB 200.

[0091] The separation unit 300b_A1 and the extension unit 300b_A3 of the reinforcement member 300b may be located on the central area 200_C of the PCB 200. That is, in the central area 200_C of the PCB 200, the reinforcement member 300b may be spaced apart from the PCB 200 in the vertical direction (Z direction). The separation unit 300b_A1 and the extension unit 300b_A3 may be arranged in a square shape. The passive element 500 may be arranged in the central area 200_C of the PCB 200, for example, below the extension unit 300b_A3.

[0092] Fig.12 is a plan view schematically illustrating a semiconductor package 1000 c according to some example embodiments. Fig.13 is schematically shown along Fig.12 The line A4-A4' is intercepted Fig.12 1 is a cross-sectional view of a semiconductor package 1000 c.

[0093] Most of the components and materials forming the semiconductor package 1000c described below are similar to those previously described. Figure 1 Therefore, for convenience, the following description will be mainly Fig.12 The semiconductor package 1000c is similar to the semiconductor package 1000c described above. Figure 1 The differences between the semiconductor packages 1000 are shown in FIG.

[0094] The semiconductor package 1000c may further include a plurality of passive elements 500c. The plurality of passive elements 500c may include, for example, one of an inductor, a resistor, and a capacitor.

[0095] The plurality of passive elements 500c may be arranged on at least one of the bottom surface of the first package substrate 120 of the first upper package 100 and the bottom surface of the PCB 200. That is, top surfaces of the plurality of passive elements 500c may contact the bottom surface of the first package substrate 120 or the bottom surface of the PCB 200.

[0096] The plurality of passive components 500c may include a first passive component 501 and a second passive component 502, respectively. The first passive component 501 may be mounted on the bottom surface of the PCB 200, and the second passive component 502 may be mounted on the bottom surface of the first package substrate 120. For example, the component may not be mounted on an area of ​​the top surface of the PCB 200 where the stiffener 300c is spaced apart from the PCB 200 in the vertical direction. That is, the component may not be mounted between the separation unit 300c_A1 and the extension unit 300c_A3 of the stiffener 300c and the PCB 200.

[0097] The first passive element 501 may be surrounded by the external connection terminals 209. The external connection terminals 209 located on the bottom surface of the PCB 200 may be arranged in a grid structure while surrounding the first passive element 501. The first passive element 501 is arranged on the bottom surface of the PCB 200, so that the number of components mounted on the top surface of the PCB 200 is reduced. Therefore, the contact area between the reinforcement 300c and the PCB 200 can be increased. That is, the area of ​​the contact unit 300c_A2 of the reinforcement 300c is increased, so that the warping phenomenon of the semiconductor package 1000c can be suppressed.

[0098] The second passive element 502 may be located between the first package substrate 120 and the PCB 200. For example, the second passive element 502 may contact the bottom surface of the first package substrate 120. The second passive element 502 may be surrounded by a conductive connection member 129. The conductive connection member 129 located on the bottom surface of the first package substrate 120 may be arranged in a grid structure while surrounding the second passive element 502. The first semiconductor chip 110 may be electrically connected to the second passive element 502 through the first package substrate 120. The signal distance between the first semiconductor chip 110 and the second passive element 502 is reduced, so that signal integrity (SI) and power integrity (PI) may be improved.

[0099] Fig.14 is a perspective view schematically illustrating a semiconductor package 2000 according to some example embodiments. Fig.15 It is schematically shown Fig.14 FIG. 2 is a plan view of a semiconductor package 2000 . Fig.16 is schematically shown along Fig.15 The line C-C' intercepts Fig.15 2 is a cross-sectional view of a semiconductor package 2000. Fig.17 is schematically shown along Fig.15 The line D-D' intercepts Fig.15 2 is a cross-sectional view of a semiconductor package 2000.

[0100] Reference Figures 14 to 17 , the semiconductor package 2000 may include a PCB 200 , a first upper package 100 , a plurality of second upper packages 400 , and a reinforcement member 300 .

[0101] Most of the components and materials forming the semiconductor package 2000 described below are similar to those previously described in Figure 1 Therefore, for convenience, the following description will be mainly Fig.14 The semiconductor package 2000 described above Figure 1 The differences between the semiconductor packages 1000 are shown in FIG.

[0102] Fig.14 The semiconductor package 2000 may further include a plurality of second upper packages 400. The plurality of second upper packages 400 may be mounted on the PCB 200. The plurality of second upper packages 400 may be spaced apart from the first upper package 100 in a horizontal direction. In some example embodiments, the plurality of second upper packages 400 may be thinner than the first upper package 100.

[0103] Each of the plurality of second upper packages 400 may include a second package substrate 420 , a second semiconductor chip 410 , and a second mold layer 430 .

[0104] Like the first packaging substrate 120, the second packaging substrate 420 may include a core insulating layer, a plurality of upper connection pads 427, and a plurality of lower connection pads 428. For example, a pitch between every two lower connection pads 428 of the plurality of lower connection pads 428 of the second packaging substrate 420 may be the same as or substantially the same as a pitch between every two lower connection pads 128 of the plurality of lower connection pads 128 of the first packaging substrate 120.

[0105] The plurality of lower connection pads 428 may be electrically and physically connected to the plurality of upper connection pads 207 of the PCB 200 through the conductive connection members 429. An underfill UF may be filled between the second package substrate 420 and the PCB 200 and between the conductive connection members 429.

[0106] The second semiconductor chip 410 may be mounted on the second package substrate 420. In some example embodiments, the second semiconductor chip 410 may be mounted on the second package substrate 420 by a flip chip method. For example, the plurality of lower connection pads 418 of the second semiconductor chip 410 may be electrically connected to the plurality of upper connection pads 427 of the second package substrate 420, respectively.

[0107] In some example embodiments, the second semiconductor chip 410 may include a memory chip. For example, the memory chip may include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, an electrically erasable programmable read-only memory (EEPROM) device, a phase change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, or a resistive random access memory (RRAM) device.

[0108] In some example embodiments, the plurality of second upper packages 400 may include different types of second semiconductor chips. For example, some of the plurality of second upper packages 400 may include memory chips, and other second upper packages 400 may include a power management integrated circuit (PMIC).

[0109] The horizontal area of ​​the second semiconductor chip 410 may be smaller than that of the second package substrate 420 . The second mold layer 430 may cover the top surface of the second package substrate 420 , and may surround the second semiconductor chip 410 .

[0110] In some example embodiments, the second mold layer 430 may cover a top surface of the second semiconductor chip 410. The second semiconductor chip 410 may be located in the second mold layer 430. For example, the second semiconductor chip 410 may be buried in the second mold layer 430.

[0111] The plurality of second upper packages 400 may be attached to the bottom surface of the stiffener 300 through an adhesive layer 409. In some example embodiments, the adhesive layer 409 may be located on the second mold layer 430 of each of the plurality of second upper packages 400 so that the second mold layer 430 may be attached to the bottom surface of the stiffener 300. By fixing the plurality of second upper packages 400 to the stiffener 300, a warping phenomenon of the semiconductor package 2000 may be suppressed, and a phenomenon in which the plurality of second upper packages 400 are damaged by external force may be suppressed.

[0112] The plurality of second upper packages 400 and the first upper package 100 may include semiconductor chips of different types. The first upper package 100 exposed to the outside through the opening 300_O of the reinforcement member 300 may generate more heat than each of the plurality of second upper packages 400. For example, the plurality of second upper packages 400 may include memory chips and PMICs, and the first upper package 100 may include logic chips (e.g., SOC chips).

[0113] exist Fig.15 200. The same number of second upper packages 400 are shown facing each edge of the top surface of the PCB 200. However, the arrangement of the plurality of second upper packages 400 is not limited thereto. For example, two or more second upper packages 400 face one edge of the top surface of the PCB 200, and one second upper package 400 faces each of the other edges of the top surface of the PCB 200.

[0114] In some example embodiments, when the number of the second upper package 400 facing each edge of the top surface of the PCB 200 changes, the distance D_X or D_Y between the contact units 300_A2 of the stiffener 300 near each edge may change.

[0115] The reinforcement member 300 of the semiconductor package 2000 may include the above Figure 2 Reinforcement 300, Figure 6 300a, or Fig. 9 That is, the shape of the reinforcing member 300 of the semiconductor package 2000 may be as described above. Figure 2 Reinforcement 300, Figure 6 300a, or Fig. 9 The plurality of second upper packages 400 may be mounted on an area of ​​the top surface of the PCB 200 where the reinforcement 300 is spaced apart from the PCB 200 in the vertical direction. The first upper package 100 may be located in the opening 300_O of the reinforcement 300. The separation unit 300_A1 or the extension unit 300_A3 of the reinforcement 300 may be located on the plurality of second upper packages 400, and the upper portion of the first upper package 100 may be exposed to the outside.

[0116] In some example embodiments, the uppermost surface 300_A1_U of the reinforcement member 300 may be located at a vertical level different from the vertical level of the top surface 100_U of the first upper package 100. The uppermost surface 300_A1_U of the reinforcement member 300 is located at the highest vertical level among the top surfaces 300_U of the reinforcement member 300. For example, the uppermost surface 300_A1_U of the reinforcement member 300 may be located at the separation unit 300_A1 of the top surface 300_U of the reinforcement member 300.

[0117] In some example embodiments, the uppermost surface 300_A1_U of the reinforcement member 300 may be located at a vertical level lower than that of the top surface 100_U of the first upper package 100. The upper end of the side surface of the first upper package 100 may protrude from the uppermost surface 300_A1_U of the reinforcement member 300 through the opening 300_O in the vertical direction (Z direction).

[0118] Figures 18 to 20 is a schematic diagram showing the respective Fig.15 2 is a cross-sectional view of semiconductor packages 2000 a , 2000 b , and 2000 c according to some example embodiments, taken along line CC′.

[0119] Most of the components and materials forming the semiconductor packages 2000a, 2000b, and 2000c described below are similar to those previously described in Fig.14 Therefore, for convenience, the following description will be mainly Figures 18 to 20 The semiconductor packages 2000a, 2000b and 2000c are similar to those described above. Fig.14 The differences between the semiconductor packages 2000 are shown in FIG.

[0120] Reference Fig.18 The semiconductor package 2000a may further include a plurality of passive elements 500. The plurality of passive elements 500 may include, for example, one of an inductor, a resistor, and a capacitor.

[0121] A plurality of passive components 500 may be mounted on the PCB 200. The plurality of passive components 500 may be located below the separation unit 300_A1 and the extension unit 300_A3 of the reinforcement member 300. For example, the plurality of passive components 500 may be located in a space of the PCB 200 that is vertically spaced apart from the reinforcement member 300. In some example embodiments, an air gap may be formed between the plurality of passive components 500 and the bottom surface of the reinforcement member 300.

[0122] The plurality of passive components 500 may be spaced apart from the first upper package 100 and the plurality of second upper packages 400 in a horizontal direction. In some example embodiments, the plurality of passive components 500 may be closer to the plurality of second upper packages 400 than the first upper package 100. In some example embodiments, the plurality of passive components 500 may be located around the plurality of second upper packages 400. In some example embodiments, the plurality of passive components 500 may be located between the first upper package 100 and the plurality of second upper packages 400. However, the positions of the plurality of passive components 500 are not limited thereto.

[0123] Reference Fig.19, the semiconductor package 2000b may further include a plurality of passive components 500c. The plurality of passive components 500c may include reference Fig.13 A plurality of passive components 500c are depicted.

[0124] The plurality of passive elements 500c may be arranged on at least one of the bottom surface of the first package substrate 120 of the first upper package 100 and the bottom surface of the PCB 200. That is, top surfaces of the plurality of passive elements 500c may contact the bottom surface of the first package substrate 120 or the bottom surface of the PCB 200.

[0125] The plurality of passive components 500c may respectively include a first passive component 501 and a second passive component 502. The first passive component 501 may be mounted on the bottom surface of the PCB 200, and the second passive component 502 may be mounted on the bottom surface of the first package substrate 120. For example, the plurality of passive components 500c may not be mounted on an area of ​​the top surface of the PCB 200 where the stiffener 300 is spaced apart from the PCB 200 in the vertical direction.

[0126] The contact area between the reinforcement member 300 and the PCB 200 is increased due to the first passive element 501, so that the warpage phenomenon of the semiconductor package 2000b can be suppressed. The first semiconductor chip 110 can be electrically connected to the second passive element 502 through the first package substrate 120. The signal distance between the first semiconductor chip 110 and the second passive element 502 is reduced, so that the signal integrity (SI) and the power integrity (PI) can be improved.

[0127] Reference Fig. 20 The semiconductor package 2000 c may further include a heat sink 600 .

[0128] The heat sink 600 can dissipate the heat generated by the semiconductor chip. The heat sink 600 may include a thermally conductive material having high thermal conductivity. For example, the heat sink 600 may include a metal such as copper (Cu) or aluminum (Al), or a carbonaceous material such as graphene, graphite and / or carbon nanotubes. However, the material of the heat sink 600 is not limited thereto. In some example embodiments, the heat sink 600 may include a single metal layer or a plurality of stacked metal layers.

[0129] The heat sink 600 may be attached to the first upper package 100. For example, the heat sink 600 may be attached to the top surface of the first upper package 100 through a thermal interface material (TIM) layer 610. The heat sink 600 directly contacts the first upper package 100 through the TIM layer 610, so that heat dissipation characteristics may be improved.

[0130] The TIM layer 610 may include a thermally conductive and electrically insulating material. For example, the TIM layer 610 may include a polymer containing metal powder such as silver (Ag) or Cu, thermal grease, white grease, or a combination thereof.

[0131] In some example embodiments, the heat sink 600 may have a flat plate shape. Therefore, the heat sink 600 may be spaced apart from the stiffener 300 in the vertical direction (Z direction). For example, when the vertical level of the top surface 100_U of the first upper package 100 is higher than the vertical level of the uppermost surface 300_A1_U of the stiffener 300, the bottom surface 600_B of the heat sink 600 attached to the top surface 100_U of the first upper package 100 may be spaced apart from the stiffener 300. In some example embodiments, an air gap may be located in a space between the bottom surface 600_B of the heat sink 600 and the top surface 300_U of the stiffener 300.

[0132] Fig.21 and Fig. 22 is a schematic diagram showing the respective Fig.15 2 is a cross-sectional view of semiconductor packages 2000d and 2000e according to some example embodiments, taken along line CC′.

[0133] Most of the components and materials forming the semiconductor packages 2000d and 2000e described below are similar to those previously described. Fig.14 Therefore, for convenience, the following description will be mainly Fig.21 and Fig. 22 The semiconductor packages 2000d and 2000e are similar to those described above. Fig.14 The differences between the semiconductor packages 2000 are shown in FIG.

[0134] Reference Fig.21 , the uppermost surface 300d_A1_U of the reinforcement 300d of the semiconductor package 2000d may be located at a vertical level different from that of the top surface 100_U of the first upper package 100. The uppermost surface 300d_A1_U of the reinforcement 300d indicates a region where the separation unit 300d_A1 of the top surface 300d_U of the reinforcement 300d is located.

[0135] The uppermost surface 300d_A1_U of the reinforcement 300d may be located at a vertical level higher than the vertical level of the top surface 100_U of the first upper package 100. That is, the first upper package 100 may not protrude from the top surface 300d_U of the reinforcement 300d in the vertical direction. However, because the first upper package 100 is located in the opening 300d_O of the reinforcement 300d, the top surface 100_U of the first upper package 100 may be exposed to the outside.

[0136] In some example embodiments, the vertical level of the top surface 100_U of the first upper package 100 may be lower than the vertical level of the uppermost surface 300d_A1_U of the stiffener 300d, and may be higher than the vertical level of the top surface of each of the plurality of second upper packages 400. However, the inventive concept is not limited thereto, and the vertical level of the top surface 100_U of the first upper package 100 may be lower than the vertical level of the top surface of each of the plurality of second upper packages 400.

[0137] Reference Fig. 22 , the semiconductor package 2000e may further include a heat sink 600a. The heat sink 600a may dissipate heat generated by the semiconductor chip. The heat sink 600a may include a thermally conductive material having high thermal conductivity.

[0138] The heat sink 600a may be attached to the first upper package 100. For example, the heat sink 600a may be attached to the top surface 100_U of the first upper package 100 through the TIM layer 610. In some example embodiments, the heat sink 600a may be attached to the separation unit 300d_A1 of the stiffener 300d through the TIM layer 610. The heat sink 600a directly contacts the first upper package 100 through the TIM layer 610, so that heat dissipation characteristics may be improved.

[0139] The heat sink 600a may include a protrusion unit (eg, member) 600a_P. The protrusion unit 600a_P of the heat sink 600a may protrude outward from a portion of the bottom surface 600a_B of the heat sink 600a. The protrusion unit 600a_P of the heat sink 600a may correspond to the opening 300d_O of the reinforcement 300d.

[0140] For example, when the vertical level of the uppermost surface 300d_A1_U of the reinforcement 300d is higher than the vertical level of the top surface 100_U of the first upper package 100, the protrusion unit 600a_P may be located in the opening 300d_O of the reinforcement 300d. Therefore, the protrusion unit 600a_P of the heat sink 600a may contact the first upper package 100. For example, the TIM layer 610 may be located on the bottom surface of the protrusion unit 600a_P of the heat sink 600a so that the heat sink 600a may be attached to the first upper package 100.

[0141] While the inventive concept has been particularly shown and described with reference to certain example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: an upper package comprising a first package substrate, a first semiconductor chip on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a printed circuit board, the upper package being located in a central region of the printed circuit board; as well as a reinforcement member located on a top surface of the printed circuit board, the reinforcement member including an opening, wherein the top surface of the printed circuit board contacts the bottom surface of the reinforcement in at least a portion of an edge region of the printed circuit board, wherein, in a central region of the printed circuit board and in an edge region other than the at least a portion of the edge region of the printed circuit board contacting the stiffener, a top surface of the printed circuit board is spaced apart from a bottom surface of the stiffener in a vertical direction, and Wherein, the opening of the reinforcement member overlaps with the upper packaging member in the vertical direction.

2. The semiconductor package according to claim 1, wherein: In a corner region of an edge region of the printed circuit board, a top surface of the printed circuit board contacts a bottom surface of the stiffener.

3. The semiconductor package according to claim 1, wherein: The top surface of the printed circuit board contacts the bottom surface of the stiffener between corner regions of the edge region of the printed circuit board.

4. The semiconductor package according to claim 1, wherein: An area where the bottom surface of the reinforcement contacts the top surface of the printed circuit board is point-symmetrical with respect to a center point of the top surface of the printed circuit board.

5. The semiconductor package according to claim 1, in, The reinforcement includes a contact member contacting a top surface of the printed circuit board, a separation member spaced apart from the top surface of the printed circuit board, and an extension member connecting the contact member to the separation member, and Wherein, the contact member and the separation member of the reinforcement are parallel to the top surface of the printed circuit board.

6. The semiconductor package according to claim 5, wherein: The extending member is inclined in the vertical direction with respect to a top surface of the printed circuit board.

7. The semiconductor package according to claim 5, wherein: The reinforcement member includes a plurality of contact members including the contact member, and A distance between contact members of the reinforcement in a first horizontal direction is different from a distance between contact members of the reinforcement in a second horizontal direction perpendicular to the first horizontal direction.

8. The semiconductor package according to claim 1, in, The first molding layer of the upper package covers the top surface of the first package substrate of the upper package and surrounds the side surface of the first semiconductor chip of the upper package, and Wherein, a top surface of the first semiconductor chip of the upper package and a top surface of the first molding layer are coplanar.

9. The semiconductor package according to claim 1, wherein: The area of ​​the opening defined by the reinforcement member is larger than the area of ​​the upper packaging member.

10. The semiconductor package according to claim 9, wherein: A side of the reinforcement member defining the opening is spaced apart from a side of the upper packaging member by 2 mm to 5 mm in a horizontal direction.

11. The semiconductor package according to claim 1, in, A pitch between each two of the plurality of lower connection pads of the first semiconductor chip is smaller than a pitch between each two of the plurality of lower connection terminals of the first package substrate, and Wherein, a pitch between every two lower connection terminals among the plurality of lower connection terminals of the first packaging substrate is smaller than a pitch between every two lower connection terminals among the plurality of lower connection terminals of the printed circuit board.

12. The semiconductor package according to claim 1, Also included are a plurality of passive components on the printed circuit board, in, The plurality of passive elements are located in a region where the top surface of the printed circuit board is spaced apart from the bottom surface of the stiffener in the vertical direction.

13. The semiconductor package according to claim 1, Also includes a number of passive components, in, The plurality of passive elements are located on at least one of a bottom surface of the first package substrate of the upper package and a bottom surface of the printed circuit board.

14. A semiconductor package, comprising: A first upper package including a first package substrate, a first semiconductor chip on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a plurality of second upper packages, each of which includes a second package substrate, a second semiconductor chip on the second package substrate, and a second molding layer surrounding the second semiconductor chip; a printed circuit board, the first upper package being located on a central area of ​​the printed circuit board, and the printed circuit board electrically connecting the first upper package to the plurality of second upper packages; as well as a reinforcement member located on a top surface of the printed circuit board, the reinforcement member including an opening, wherein at least some portions of the edge region of the printed circuit board contact the reinforcement, wherein a central region of the printed circuit board and edge regions other than the at least some portions of the edge regions of the printed circuit board contacting the reinforcing member are spaced apart from the reinforcing member in a vertical direction, and Wherein, the opening of the reinforcement member overlaps with the first upper packaging member in the vertical direction.

15. The semiconductor package according to claim 14, in, A top surface of the first molding layer of the first upper package is coplanar with a top surface of the first semiconductor chip, and The second molding layer of each of the plurality of second upper packages covers the top surface of the second semiconductor chip.

16. The semiconductor package according to claim 14, wherein: The plurality of second upper packages are spaced apart from the first upper packages in a horizontal direction, and are located on an area of ​​a top surface of the printed circuit board spaced apart from the stiffener in the vertical direction.

17. The semiconductor package according to claim 14, Also includes a radiator, in, The vertical level of the top surface of the first upper packaging member is higher than the vertical level of the uppermost surface of the reinforcing member, and The heat sink contacts a top surface of the first upper package and is spaced apart from an uppermost surface of the reinforcement in the vertical direction.

18. The semiconductor package according to claim 14, Also included is a heat sink having a protruding member, in, The vertical level of the top surface of the first upper packaging member is lower than the vertical level of the uppermost surface of the reinforcing member, and The protruding member of the heat sink protrudes toward the opening of the reinforcement member and contacts the first upper package.

19. A semiconductor package, comprising: a first upper package including a first package substrate, a first semiconductor chip on the first package substrate, and a first molding layer surrounding a side surface of the first semiconductor chip, the first semiconductor chip having a horizontal area smaller than a horizontal area of ​​the first package substrate; a printed circuit board, the first upper package being located on a central area of ​​the printed circuit board, and the printed circuit board having a horizontal area larger than a horizontal area of ​​the first upper package; as well as a reinforcement member attached to the top surface of the printed circuit board by an adhesive layer, the reinforcement member including an opening, wherein a pitch between each two of the plurality of lower connection pads of the first semiconductor chip is smaller than a pitch between each two of the plurality of lower connection terminals of the first packaging substrate, wherein a pitch between each two of the plurality of lower connection terminals of the first packaging substrate is smaller than a pitch between each two of the plurality of lower connection terminals of the printed circuit board, wherein the top surface of the printed circuit board contacts the bottom surface of the reinforcement in at least a portion of an edge region of the printed circuit board, wherein, in a central region of the printed circuit board and in an edge region other than the at least a portion of the edge region of the printed circuit board contacting the stiffener, a top surface of the printed circuit board is spaced apart from a bottom surface of the stiffener in a vertical direction, and Wherein, the opening of the reinforcement member overlaps with the first upper packaging member in the vertical direction.

20. The semiconductor package according to claim 19, further comprising: a plurality of second upper packages, each of which includes a second package substrate on the printed circuit board, a second semiconductor chip on the second package substrate, and a second molding layer surrounding the second semiconductor chip, the second semiconductor having a horizontal area smaller than that of the second package substrate; as well as a plurality of passive components located on the printed circuit board, the plurality of passive components being electrically connected to the first upper package, Wherein, each of the plurality of second upper packages and the plurality of passive components is located on an area of ​​the top surface of the printed circuit board spaced apart from the stiffener.

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